最新美国发明专利第2016-11-22期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09503148B2	Combination mobile phone protective case and portable safe system, apparatus and method An integrated mobile phone protective case and carrier drawer system for securely containing small personal items, comprising: a regular mobile phone protective case portion; a drawer space integrally contained inside a rear part of the integrated mobile phone protective case; a drawer cover separate from the integrated mobile phone protective case, configured to mate onto the rear part of the integrated mobile phone protective case; a latching extension integrally affixed with the drawer cover; a latch integrally affixed with the integrated mobile phone protective case and configured to latch together with the latching extension; and a release actuator for releasing the latching extension from the latch; wherein: after the drawer cover has been slid onto the integrated mobile phone protective case, the latching extension simultaneously becomes latched together with the latch thereby preventing any personal items contained within the personal item carriage drawer from being removed from the drawer.
US09503147B2	Protective enclosure for an electronic device A protective enclosure for an electronic device includes a cushioning layer and a structural layer. The cushioning layer covers the back surface and side surfaces of the installed electronic device. The structural layer is disposed over the cushioning layer and includes a back portion, a right side portion, and a left side portion. The structural layer includes a thinner region on the back portion. The thinner region has a thickness that is less than the thickness of the remainder of the back portion of the structural layer. The thinner region of the structural layer allows a section of the protective enclosure to bend away from the back surface of the electronic device during installation and removal of the electronic device from the protective enclosure.
US09503142B2	Method of providing antenna by using component in electronic device and the electronic device therefor An electronic device is provided. The electronic device includes a control signal generation unit configured to generate a control signal corresponding to a user input, a signal transmission unit configured to transmit the generated control signal to a signal processing unit, the signal processing unit configured to process the transmitted control signal, and a ground connection unit configured to connect a ground plate of the signal transmission unit and a ground plate of the signal processing unit, wherein the ground plate of the signal transmission unit and the ground plate of the signal processing unit are spaced from each other and the ground plate of the signal transmission unit is used as a radiator.
US09503141B2	Socket device A socket device is provided. The socket device includes a substrate, at least one structure, and a socket. The at least one structure is disposed on the substrate, and includes an upper surface. The upper surface includes an opening separated with a predetermined interval from a surface of the substrate. The socket is disposed so that at least a portion of the socket is stacked on an upper portion of the structure. The socket is electrically connected to the substrate via the opening. The number of parts is reduced, so that the number of assembly processes is reduced and assembling is convenient, and manufacturing costs is reduced and slimness of an electronic device is achieved.
US09503140B2	Methods reducing antenna port interference for EPDCCH and related systems, devices, and networks A method of operating a base station in a radio access network may include configuring first and second control channel sets with respective first and second antenna port configurations for a wireless terminal using control channel signaling transmitted to the wireless terminal. First reference signals may be transmitted to the wireless terminal according to the first antenna port configuration, and second reference signals may be transmitted to the wireless terminal according to the second antenna port configuration.
US09503139B2	Very low intermediate frequency (VLIF) receiver and method of controlling VLIF receiver A very-low intermediate frequency (VLIF) receiver and a method of controlling a VLIF receiver. The method comprises receiving a first signal, the first signal including a first adjacent channel interferer, and detecting first interference from the first adjacent channel interferer. The method further comprises, subsequent to receiving the first signal, receiving a second signal, the second signal including a second adjacent channel interferer, and detecting second interference from the second adjacent channel interferer. Furthermore, subsequent to detecting the second interference, the VLIF receiver is configured to avoid the first interference while receiving a third signal.
US09503138B2	Interference cancellation A circuit comprises a vector separator circuit to generate a first extracted signal according to (i) a first correlation signal, (ii) a second correlation signal, and (iii) a relative response signal. The first correlation signal corresponds to a first correlation between an input signal and a first test signal. The first test signal has a first frequency, and the input signal includes a first spur having the first frequency. The second correlation signal corresponds to a second correlation between the input signal and a second test signal. The second test signal has a second frequency. The relative response signal corresponds to a relative response of the second frequency in the first correlation signal.
US09503136B2	Receiver and receiving method of receiver It is determined, on the basis of a signal component of a low frequency band and a signal component of a desired channel band of an intermediate frequency signal, whether an interfering wave is a far-off interfering wave which exists out of a low frequency band, an out-of-channel-band interfering wave which exists out of a channel band, or an in-channel-band interfering wave which exists in the channel band. When the interfering wave is determined to be the far-off interfering wave, the operation current of a circuit in the receiver is made lower than those in a case where the interfering wave is the out-of-channel-band or in-channel-band interfering wave.
US09503132B2	Wireless communication apparatus, communication control method, and computer-readable recording medium A wireless communication apparatus includes an amplifying unit that amplifies an input signal that includes signals with different frequencies of a first frequency and the second frequency; a measuring unit that measures a level of inter modulation distortion generated in a signal obtained by the input signal being amplified by the amplifying unit; a determining unit that determines whether the level of the inter modulation distortion measured by the measuring unit is equal to or greater than a regulation value that is previously stored; and a control unit that decreases, when a result of the determination obtained by the determining unit indicates that the level of the inter modulation distortion is equal to or greater than the regulation value, a level of a signal input to the amplifying unit.
US09503130B2	Signal transmitter, message generating system and signal power adjusting method A signal transmitter with adjustable signal power includes a housing, a first adjustable metal shielding layer and a circuit board. The first adjustable metal shielding layer is disposed within the housing. The area of the first adjustable metal shielding layer consists of a first shielding area and a first un-shielding area. The first shielding area and the first un-shielding area are adjustable. The circuit board is disposed within the housing, and is located below the first adjustable metal shielding layer. The circuit board is electrically connected with the first adjustable metal shielding layer, and includes a signal emission chip. The signal emission chip is configured for adjusting signal emission power to emit a signal according to the first un-shielding area of the first adjustable metal shielding layer. A message generating system and a signal power adjusting method are disclosed herein as well.
US09503126B2	ECC polar coding and list decoding methods and codecs A method of decoding data encoded with a polar code and devices that encode data with a polar code. A received word of polar encoded data is decoded following several distinct decoding paths to generate a list of codeword candidates. The decoding paths are successively duplicated and selectively pruned to generate a list of potential decoding paths. A single decoding path among the list of potential decoding paths is selected as the output and a single candidate codeword is thereby identified. In another preferred embodiment, the polar encoded data includes redundancy values in its unfrozen bits. The redundancy values aid the selection of the single decoding path. A preferred device of the invention is a cellular network device, (e.g., a handset) that conducts decoding in accordance with the methods of the invention.
US09503125B2	Modified trellis-based min-max decoder for non-binary low-density parity-check error-correcting codes A decoder includes a syndrome value calculator configured to generate multiple syndrome values. The decoder further includes a check node to variable node message generator that is coupled to the syndrome value calculator. The check node to variable node message generator is configured to generate multiple check node to variable node messages in a single clock cycle based on the multiple syndrome values.
US09503123B1	Random access to compressed data using bitwise indices Methods and apparatus are provided for random access to compressed data using bitwise indices, enabling interaction with compressed data as if interaction were with an uncompressed version thereof. A compressed file is decompressed using an index table comprising a bitwise mapping between individual bits in the compressed file and corresponding portions of an uncompressed version of the compressed file; and decompressing at least a portion of the compressed file using the index table. Different data types within a file are optionally managed by separate index tables. A block-based file system can process index tables to provide transparent access to the compressed file. The index tables support dynamic index granularities, without decompressing the compressed file and recompressing it. The decompressed portion of the compressed file is optionally stored in a cache, possibly with neighbor portions pre-fetched using the index tables. Multi-resolution compression and quality-based decompression are also provided without space overhead.
US09503122B1	Hardware data compressor that sorts hash chains based on node string match probabilities A hardware data compressor. A first hardware engine scans an input block of characters and uses a plurality of lists of nodes to produce back pointers to matching strings in the input block to compress the input block. Each node points to a character in the input block previously scanned and has an associated probability that a back pointer to a matching string that begins with the pointed-to character will be produced by the first hardware engine. A second hardware engine, for each list of nodes of the plurality of lists, sorts the list according to the probabilities of the nodes in the list so that higher probability nodes appear earlier in the list for use by the first hardware engine to search for matching strings during the scan of the input block of characters.
US09503117B2	Semiconductor device comprising analog to digital converters sharing reference capacitor and system on chip comprising the same Provided are a semiconductor device and a System on Chip (SoC). The semiconductor device includes a reference capacitor that receives a reference voltage from a reference voltage generator, a first successive approximation register analog-to-digital converter (SAR ADC), for converting a first analog signal into a first digital signal, using a first sampling capacitor that has a first capacitance and is connected to the reference capacitor through a first switching element, and a second sampling capacitor that has a second capacitance that is less than that of the first sampling capacitor, connected to the reference capacitor through a second switching element, a second SAR ADC, for converting a second analog signal into a second digital signal, using a third sampling capacitor that has a third capacitance, connected to the reference capacitor through a third switching element, and a fourth sampling capacitor that has a fourth capacitance that is less than that of the third sampling capacitance connected to the reference capacitor through a fourth switching element, and a controller configured to connect the first switching element and the third switching element to the reference capacitor at different times.
US09503116B2	Efficient calibration of errors in multi-stage analog-to-digital converter Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.
US09503115B1	Circuit for and method of implementing a time-interleaved analog-to-digital converter A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a reference clock signal having a first frequency. The sampling clock generator has a first stage sampling clock generator configured to generate a first plurality of clock signals based upon the reference clock signal and having a second frequency, and a second stage sampling clock generator configured to generate, for each clock signal of the first plurality of clock signals, a second plurality of clock signals having a third frequency; a first stage having a plurality of switches configured to receive an analog input signal, wherein each switch of the plurality of switches is controlled by a corresponding clock signal of the first plurality of clock signals; and a second stage having a plurality of analog-to-digital converter banks, each analog-to-digital converter bank having a plurality of analog-to-digital converters and configured to receive the analog input signal by way of a corresponding switch of the plurality of switches.
US09503110B2	Gas cell, quantum interference device, atomic oscillator, electronic device, and moving object A gas cell includes an internal space in which metal atoms and a buffer gas are sealed, the buffer gas includes nitrogen gas, and the partial pressure of the nitrogen gas in the internal space is equal to or higher than 30 Torr. The gas cell includes a pair of window portions and a body portion, the length of the internal space along a direction in which the pair of window portions are arranged is equal to or less than 10 mm, and the width of the internal space along a direction perpendicular to the direction in which the pair of window portions are arranged is equal to or less than 10 mm.
US09503109B2	Apparatus and methods for synchronizing phase-locked loops Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.
US09503108B2	Oscillation circuit, oscillator, electronic device, and moving object An oscillation circuit, an oscillator, an electronic device, and a moving object which are capable of adjusting an output frequency in a high modulation bandwidth with a high level of accuracy and adjusting a timing at which the output frequency is changed are provided. The oscillation circuit generates an oscillation signal by oscillating an oscillation element and includes a communication unit that receives frequency setting data for setting a frequency of the oscillation signal and frequency change data which is given a timing at which the frequency of the oscillation signal is changed on the basis of the frequency setting data, by serial transfer, and registers in which the frequency setting data and the frequency change data received by the communication unit are stored, respectively. An address of the register storing the frequency setting data is continuous with an address of the register storing the frequency change data.
US09503107B1	Closed loop bank selection for temperature compensation in wireless systems The disclosure is directed to compensating for frequency drift in a voltage-controlled oscillator (VCO). Example methods and systems are described which may detect a signal edge associated with a transceiver, and determine whether one or more lock quality signals indicate that the VCO frequency is outside of an specified range, indicating an unacceptable amount of frequency drift. A frequency tuning setting of the VCO may be adjusted based on the one or more lock quality signals, and a determination may be made whether or not the one or more lock quality signals indicate that the VCO frequency has returned to the specified range. The adjustment of the frequency tuning setting of the VCO may be repeated until the VCO frequency returns to the specified range.
US09503105B2	Phase frequency detector (PFD) circuit with improved lock time Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.
US09503103B2	Phase locked loop with a frequency multiplier and method of configuring the phase locked loop A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.
US09503097B2	Analog circuits incorporating magnetic logic units A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on a first analog input to the circuit. Each MTJ is electrically connected to a first and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of the MTJs varies based on the magnetic field. The circuit is configured to mix the first analog input and a second analog input to generate an analog output based on the output of the second output terminal.
US09503096B1	Multiple-layer configuration storage for runtime reconfigurable systems The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.
US09503095B2	Space-multiplexing DRAM-based reconfigurable logic According to one general aspect, an apparatus may include a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may include memory cells configured to simultaneously store a plurality of look-up tables, wherein each look-up table is associated with a respective logic function. The reconfigurable look-up table may include a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The reconfigurable look-up table may be configured to perform one logic function at a time, and wherein the logic function is dynamically selected. The plurality of look up tables stored in the memory cells may be configured to be dynamically altered via a write operation to the random access memory array.
US09503093B2	Virtualization of programmable integrated circuits A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.
US09503092B2	Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same An integrated circuit comprising a plurality of logic tiles, wherein each logic tile includes a plurality of (i) computing elements and (ii) switch matrices. The plurality of switch matrices are arranged in stages including (i) a first stage, configured in a hierarchical network (for example, a radix-4 network), wherein, each switch matrix of the first stage is connected to at least one associated computing element, (ii) a second stage configured in a hierarchical network (for example, a radix-2 or radix-3 network) and coupled to switches of the first stage, and (iii) a third stage configured in a mesh network and coupled to switches of the first and/or second stages. In one embodiment, the third stage of switch matrices is located between the first stage and second stage of switch matrices; in another embodiment, the third stage is the highest stage.
US09503089B2	Integrated circuit having multiple identified identical blocks An integrated circuit comprising N adjacent identical blocks indexed by index j, a current block connected to preceding and following blocks, each comprising identification circuits comprises: N ordered inputs indexed i, connected to N outputs of the preceding block of same index; and N ordered outputs indexed i, connected to N inputs of the following block of same index; each input for i≠N of the current block connected by routing line indexed to output i+1 of the current block; last input N of the current block not connected to output of the current block; and first output 1 of the current block not connected to input of the current block; each block comprising: a connection pad; and N logic gates indexed i, each gate comprising first and second inputs and an output, N buses indexed i comprising a line through N blocks, and connected to output of a logic gate.
US09503088B2	Method and control device for recovering NBTI/PBTI related parameter degradation in MOSFET devices The invention provides a method for recovering NBTI/PBTI related parameter degradation in MOSFET devices. The method includes operating the at least one MOSFET device in a standby mode, exiting the at least one MOSFET device from the standby mode, holding the at least one MOSFET device in an active state for a predetermined time span after exiting the standby mode, and operating the at least one MOSFET device in an operational mode after the predetermined time span has elapsed.
US09503085B1	Exclusive-OR gate using magneto-electric tunnel junctions A magneto-electric (ME) magnetic tunnel junction (MTJ) Exclusive-OR (XOR) gate is provided. The ME MTJ XOR gate includes an insulator separating a top ferromagnetic (FM) layer and a bottom FM layer, a top ME layer on the top FM layer, and a bottom ME layer on the bottom FM layer. The ME MTJ XOR gate also includes a top electrode coupled to the top ME layer and a bottom electrode coupled to the bottom ME layer where a voltage between the top electrode and the top FM layer is a first input, a voltage between the bottom electrode and the bottom FM layer is a second input, and a resistance between the top FM layer and the bottom FM layer is indicative of the XOR of the first input and the second input. The ME MTJ XOR has reduced energy consumption, smaller area, faster switching times, and is non-volatile.
US09503081B2	Radio frequency antenna switch A radio frequency antenna switch is provided that includes an antenna port, a radio frequency signal port, and at least one branch connected to the antenna port or the radio frequency signal port, where each branch includes multiple transistors which are connected in a stack manner; channel width to length ratios of a preset number of transistors in the multiple transistors progressively decrease in a direction away from the antenna port, where the preset number is less than or equal to the total number of the multiple transistors. With the radio frequency antenna switch, capacitances of the preset number of transistors close to the antenna port increase, and distributed voltages that these transistors close to an antenna end in an off state need to bear are reduced.
US09503079B1	Method and apparatus for current/power balancing Aspects of the disclosure provide a power circuit that includes a first switch module and a second switch module in parallel. The first switch module has a first gate terminal, a first drain terminal and a first source terminal, and the second switch module has a second gate terminal, a second drain terminal and a second source terminal. A drain interconnection module coupled to the first drain terminal and a gate interconnection module coupled to the second gate terminal are inductively coupled to balance current flowing through the first switch module and the second switch module.
US09503075B2	Delay line system and switching apparatus with embedded attenuators A monolithically integrated switch configured to operate at an input signal frequency ranging from 0 Hz to 80 GHz. The switch has an input port and two output ports. A first conduction path is provided from the input port to the first output port. A second conduction path is provided from the input port to the second output port. In addition, a first shunting path is provided between the first output port and a reference and a second shunting path is provided between the second output and the reference. In a first mode, the first conduction path and the second shunting path have a low impedance. The second conduction path and the first shunting path have a high impedance. In a second mode, the first conduction path and the second shunting path have a high impedance. The second conduction path and the first shunting path have a low impedance.
US09503074B2	RF circuit with switch transistor with body connection In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.
US09503069B1	Self resetting latch An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.
US09503063B1	Mechanically tunable superconducting qubit A system for adjusting qubit frequency includes a qubit device having a Josephson junction and a shunt capacitor coupled to electrodes of the Josephson junction. A cantilevered conductor is separated from the shunt capacitor by a spacing. An adjustment mechanism is configured to deflect the cantilevered conductor to tune a qubit frequency for the qubit device.
US09503062B2	Semiconductor circuit and semiconductor system An example embodiment discloses a flip-flop including a first inverter configured to invert first data, first and second transistors connected to each other in series and configured to receive the inverted first data and a first clock, respectively, a third transistor and a first gate configured to perform a logic operation on the first data and the first clock, the third transistor configured to receive an output of the logic operation. The second transistor and the third transistor are connected to a first node.
US09503061B2	System and method for calibrating chips in a 3D chip stack architecture A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal.
US09503057B1	Clock grid for integrated circuit Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.
US09503056B2	Frequency-adaptive notch filter One apparatus includes a notch filter that has a state observer unit and a parameter adaptation unit. The state observer unit is configured to receive a sampled noisy electrical signal and a sampled filtered electrical signal, the state observer unit having an estimated noise signal output, the estimated noise signal output carrying an estimated noise signal to be subtracted from the sampled noisy electrical signal, resulting in the filtered electrical signal. The parameter adaptation unit is configured to receive the estimated noise signal and an error signal from the state observer unit. The parameter adaptation unit is also configured to determine, based on the estimated noise signal and the error signal, an updated estimated noise frequency, thereby causing the state observer unit to generate an updated estimated noise signal to be provided on the estimated noise signal output.
US09503054B2	Linear phase FIR biorthogonal wavelet filters with complementarity for image noise reduction In described embodiments, Linear Phase, Finite Impulse Response, filters incorporate a power complementarity property into a perfect reconstruction filter bank. Non-linear constraints for type A and type B filters are included in the Sequential Quadratic Programming design of the filters. An initial Quadrature Mirror Filter includes perfect reconstruction constraints, which might be optimized through iterative design techniques. Embodiments might be employed in noise reduction applications related to, for example, signal processing of images.
US09503052B1	Frequency selective circuit A frequency selective circuit includes a first transistor, an impedance element, a first capacitive element, a second capacitive element, a second capacitive and a second transistor. The first transistor includes a first terminal, a second terminal and a control terminal. The impedance element is coupled between the first terminal and the control terminal of the first transistor. The first capacitive element is coupled to the first terminal of the first transistor. The second capacitive element is coupled to the control terminal of the first transistor. The second transistor includes a first terminal, a second terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the control terminal of the first transistor.
US09503045B2	Resonator element, resonator, oscillator, electronic apparatus, and moving object A resonator element includes a thick section, a middle section and a thin section, in which at least the thick section performs thickness shear vibration, in which a first step difference is provided at a boundary between the thick section and the middle section, and a second step difference is provided at a boundary between the middle section and the thin section, on one side of a direction of the thickness shear vibration, in which a first antinode of flexural vibration is located between the first step difference and the second step difference, and in which, a distance between the first antinode and the first step difference is indicated by d1, a distance between the first antinode and the second step difference is indicated by d2, and a wavelength of the flexural vibration is indicated by λ, a relationship of 0≦d1≦λ/8 and 0≦d2≦λ/8 is satisfied.
US09503043B2	Duplexer, circuit structure thereof and RF transceiver apparatus comprising the duplexer A duplexer is provided, which includes a first, a second and a third signal ports; a first filter and a second filter. The first filter has first, second, and third resonant circuits that have first, second and third inductors, respectively. The first, second and third inductors are mutually inductive. The first and third resonant circuits are electrically connected to the first and second signal ports, respectively. The second filter has fourth, fifth and sixth resonant circuits that have fourth, fifth and sixth inductors, respectively. The fourth resonant circuit is connected in series with the first resonant circuit. The fifth inductor and the fourth inductor are mutually inductive. The sixth resonant circuit is electrically connected to the third signal port. The second filter further has a main capacitor connected in series with the fifth and sixth resonant circuits respectively and located therebetween.
US09503040B1	Method and apparatus for changing the gain of a radio frequency signal A method and electronic circuit for changing the gain of a radio frequency signal. The apparatus is an electronic circuit comprising one or more variable gain electronic elements, and one or more adjustable phase shifting elements. The method comprises the steps of receiving a radio frequency signal, varying the gain of the variable gain electronic element while the variable gain electronic element changes the amplitude of the radio frequency signal, and adjusting an adjustable phase shifting element to generate a reverse phase shift in the radio frequency signal in response to the associated phase shift from the step of varying the gain.
US09503039B2	Trimming method for current sense amplifiers A method for adjusting common mode rejection ratio (CMRR) and gain error of a current sense (CS) amplifier, comprising: measuring a first referred to input (RTI) offset voltage while presenting a given common mode (CM) input voltage; adding a first trim resistor of a plurality of selectable trim resistors within an adjustable feedback resistor chain to a feedback electrical path; measuring a second RTI offset voltage while presenting the given CM input voltage; estimating, based upon the first and second RTI offset voltages, a third RTI offset voltage value that would result by adding a second trim resistor of the plurality of selectable trim resistors to the feedback electrical path; using the first, second and third RTI offset voltage values to identify the combination of selectable trim resistors that achieves an RTI offset voltage closest to zero volts; and adding the identified selectable trim resistors to the feedback electrical path.
US09503029B2	Transmitting amplifier and transmitter The present invention is applied to a transmitting amplifier including one of a carrier amplifier and a peak amplifier as a first amplifier and the other as a second amplifier. A transmitting amplifier according to the present invention includes a transmission line transformer with a ¼ wavelength, dual-coaxial structure such that a center conductor, an inner conductor, and an outer conductor are formed in that order from the center toward the outside. The center conductor and the inner conductor constitute a first coaxial line, and the inner conductor and the outer conductor constitute a second coaxial line. The output of the first amplifier is connected to one end of the first and the second coaxial lines, and an output terminal is connected to the other end of the first and second coaxial lines. The other end of the first coaxial line, the output of the second amplifier, and the other end of the second coaxial line are connected.
US09503026B2	Dynamic error vector magnitude duty cycle correction Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.
US09503020B2	Oscillator, electronic apparatus, and moving object An oscillator includes a first VCXO and a second VCXO which are capable of changing an output frequency by application of a control voltage, and a control voltage terminal to which the control voltage is applied, the first VCXO includes a variable-capacitance diode (first variable-capacitance diode) and a resistor (first resistor), the second VCXO includes a variable-capacitance diode (second variable-capacitance diode) and a resistor (second resistor), the cutoff frequency of the first variable-capacitance diode, the second variable-capacitance diode, the first resistor, and the second resistor is equal to the cutoff frequency of the first variable-capacitance diode and the first resistor, and the cutoff frequency of the second variable-capacitance diode and the second resistor.
US09503018B2	Semiconductor device A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage. The reference resistor is formed of a plurality of resistors, which extend in a first (Y) direction orthogonal to a first side, inside a first region (RG1, RG2, RG3, and RG4) surrounded by the first side (S1, S2, S3, and S4) of a main surface of the semiconductor chip (CP1), a first line (42, 43, 44, and 45) connecting between one end of the first side and the center (CT1) of the main surface of the semiconductor chip, and a second line (42, 43, 44, and 45) connecting between the other end of the first side and the center of the main surface of the semiconductor chip.
US09503017B1	Infrastructure-grade integrated voltage controlled oscillator (VCO) with linear tuning characteristics and low phase noise The described devices, systems and methods include a voltage controlled oscillator. The voltage controlled oscillator includes a fine-tuning varactor network, a switch capacitor array having a first plurality of binary capacitor array elements and a second plurality of thermometer code capacitor array elements, and a tank inductor network including a first inductor in parallel with a second inductor.
US09503016B2	Solar panel unit A solar panel unit (10) includes a control unit (73) which operates an actuator (41) such that an angle of a solar panel (20) coincides with a predetermined command angle. The control unit (73) performs reset control for resetting the angle of the solar panel (20) misaligned due to strong wind. In the reset control, the actuator (41) is not operated until a predetermined time has passed since the angle of the solar panel (20) was misaligned to wait for the strong wind to stop, and then the actuator (41) is operated to reset the angle of the solar panel (20).
US09503014B2	Geared motor unit having function for limiting thrust load A compact geared motor unit, capable of properly protecting an electric motor without disengaging gears or suspending the unit, even when a thrust force larger than an allowable value is generated. The geared motor unit 10 has an electric motor and a gear configured to generate a thrust force applied to the electric motor when transmitting a torque, and a control section for controlling the electric motor. The control section has a thrust load obtaining part which obtains a thrust load of the electric motor at predetermined timings or time intervals; a critical thrust load storing part which stores a critical thrust load of the electric motor; and a torque limiting part which electrically limits the torque of the electric motor when the obtained thrust load exceeds the stored critical thrust load.
US09503013B2	Motor drive voltage control device and method for controlling motor drive voltage To suppress a decline in the control accuracy of an applied voltage associated with an increase in quantum noise, and to increase the control accuracy of a motor speed. When generating a driving voltage signal supplied to a motor from a driving command signal, a motor-driving voltage control device reduces the gradation level and performs noise-shaping modulation before performing PWM modulation. Reducing the gradation level allows the degree of gradation of the driving voltage signal to be within the resolution range of the PWM modulation, and thus PWM modulation can be performed even when the driving voltage signal has a high frequency. Noise-shaping modulation reduces the level of quantum noise near the low frequency range by causing the quantum noise due to digitization, included in the driving voltage signal, to be biased toward the high frequency range side. Of modulation signals with the reduced-gradation level, the components near the high frequency band are cut, while the components near the low frequency range are used to suppress quantum noise and control the driving voltage applied to the motor with a high accuracy.
US09503011B2	Motor driving method, motor driving device, and hard disk device The present invention is intended to reduce noise and vibration of a motor. A first duty correction circuit generates a first corrected duty instruction value which changes with an increment same as an increment of a duty instruction value and in which an offset value as a constant is reflected. A second duty correction circuit generates a second corrected duty instruction value which changes with an increment different from an increment of the duty instruction value. A selector outputs, as the corrected duty instruction value, either one of the first corrected duty instruction value and the second corrected duty instruction value in accordance with a magnitude relation between the duty instruction value and a duty reference value.
US09503002B2	Image forming apparatus, motor control apparatus, and method of controlling motor An image forming apparatus includes an engine portion configured to perform image forming, a direct current (DC) motor configured to mechanically operate the engine portion, a driver including a resistor to measure current that flows to the DC motor according to the measured current and configured to provide a predetermined voltage to the DC motor, and a drive controller configured to measure a driving speed of the DC motor based on a voltage value of the resistor and to control the driver to provide a voltage that corresponds to the measured driving speed to the driver.
US09502992B2	Diode substitute with low drop and minimal loading A voltage rectifier circuit having a storage element and a switching stage that is switchable to enable the storage element to capture a peak voltage of an alternating power source. The switching stage includes transistors arranged in a back-to-back configuration. In one example, the storage element is a capacitor and the transistors are PNP bipolar junction transistors. The configuration of the circuit enables reduced loading on the power source, as well as reduced sensitivity to temperature.
US09502989B2	Energy storage device, system with energy storage device and method for generating a supply voltage of an energy storage device The invention relates to an energy storage device for generating an n-phase supply voltage for an electrical machine, where n≧1, or for an inverter, with n energy supply branches connected in parallel, each of which can be connected to one of n phase lines, each of the energy supply branches comprising a plurality of series-connected energy storage modules, each comprising: an energy storage cell module and a coupling device configured to selectively connect the energy storage cell module into the respective energy supply branch or to bypass said module, the energy storage cell modules of respective first energy storage modules of an energy supply branch each comprising at least one first energy storage cell, the energy storage cell modules of respective second energy storage modules of an energy supply branch each comprising at least one second energy storage cell, and the first energy storage cells having a lower internal resistance than the second energy storage cells below a predetermined temperature threshold.
US09502984B2	Switching parameter based discontinuous mode-critical conduction mode transition An electronic system includes a controller to provide at least dual-mode conduction control of a switching power converter. In at least one embodiment, the controller is capable to control transitions between discontinuous conduction mode (DCM) and critical conduction mode (CRM) of the switching power converter using a measured switching time parameter having a value corresponding with an approximately peak voltage of a time-varying supply voltage supplied to the switching power converter. In at least one embodiment, the controller dynamically compensates for changing parameters of the electronic system by dynamically determining a minimum non-conductive time of the control switch of the switching power converter using the measured switching time parameter value at approximately the peak of the supply voltage of the supply voltage.
US09502978B2	Switched power stage and a method for controlling the latter The disclosure relates to a method of generating an output voltage, comprising: generating a regulated output voltage from a high voltage source; providing an inductor having a first terminal and a second terminal linked to a low voltage source by a capacitor, the second inductor terminal supplying the output voltage to a load; connecting the first inductor terminal exclusively either to the high voltage source or to the low voltage source or to the second inductor terminal, as a function of command signals to reduce a difference between the output voltage and a reference voltage lower than a high voltage supplied by the high voltage source; and generating a square binary control signal having a duty cycle substantially adjusted to the ratio of the output voltage to the high voltage; the first inductor terminal being connected to the high voltage source or to the low voltage source as a function of a binary state of the control signal.
US09502977B2	Control apparatus for voltage converting apparatus A control apparatus (30) for a voltage converting apparatus controls a voltage converting apparatus (12) configured to realize one-arm drive by alternatively switching on first and second switching elements (Q1, Q2). The control apparatus for the voltage converting apparatus is provided with: a switching control signal generating device configured to generate switching control signals (PWI1, PWI2) for changing on and off the respective first and second switching elements; a current detecting device configured to detect a current value (IL) of a drive current flowing through the first or second switching element, at rise timing of the switching control signal, when the one-arm drive is changed between one-arm drive using the first arm and one-arm driving using the second arm; a current estimating device configured to estimate an average value of the drive current by using the detected current value; and a current controlling device configured to control the drive current on the basis of the estimated average value.
US09502976B2	Power supply circuit and control method for the same According to an embodiment, a power supply circuit is provided. The power supply circuit includes a switching transistor which is controlled to be ON/OFF by a PWM signal, and a mode switching control circuit configured to switch a control mode between peak current mode control and valley current mode control depending on the length of an ON time of the PWM signal which drives the switching transistor.
US09502975B2	Switch control circuit, switch control method and converter using the same Provided is a switch control circuit for controlling a current control switch of a power supply, the power supply including a load, an inductor and the current control switch that are series-coupled to an input power. The switch control circuit includes a current measuring unit configured to measure a current flowing into the load, a current integral unit configured to integrate the measured current, a comparison unit configured to compare the integrated current value and a reference value and a control unit coupled to the current control switch, the control unit being configured to turn off the current control switch when the integrated current is substantially the same as the reference value and turn on the current control switch when a predefined off-time elapses from a time when the current control switch is turned off. The switch control circuit may quickly and accurately control an average current.
US09502973B2	Buck converter with III-nitride switch for substantially increased input-to-output voltage ratio According to one exemplary embodiment, a buck converter for converting a high voltage at an input of the buck converter to a low voltage at an output of the buck converter includes a III-nitride switch interposed between the input and the output of the buck converter and a low resistance switch interposed between the output of the buck converter and a ground. The buck converter further includes a control circuit configured to control a duty cycle of the III-nitride switch. The III-nitride switch has a sufficiently high switching speed so as to allow a ratio of the input high voltage to the output low voltage of the buck converter to be substantially greater than 10.
US09502971B2	Charge pump circuit, integrated circuit, electronic device and method therefor A charge pump circuit for generating a negative voltage has: a clock generator arranged to output at least one clock signal; a switched capacitor voltage inverter circuit including capacitive elements wherein the switched capacitor voltage inverter circuit receives the at least one clock signal and generates a negative voltage therefrom. The charge pump circuit further has a regulation control loop providing a feedback path from an output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, and an output arranged to output a generated negative voltage. The feedback path has an operational amplifier configured to generate a maximum charging supply voltage from a fed back level-shifted negative voltage and apply the maximum charging supply voltage to the input supply of the switched capacitor voltage inverter to charge at least one of the capacitive elements during a loop start up.
US09502969B2	Negative reference voltage generating circuit A negative reference voltage generating circuit includes a switched capacitor circuit having a capacitor connected to a first and a second nodes, a first and a second switches connected to the first node, a third and a fourth switches connected to the second node; and a control circuit, generating a first to a fourth control signals to control the first to the fourth switches respectively. The control circuit applies a preset positive reference voltage to the first node to charge the capacitor during a first period, and outputs a negative voltage from the second node based on the voltage charged to the capacitor during a second period different from the first period. By repeating the first and the second periods, an inverting negative voltage of the positive reference voltage that is outputted from the second node is used as a negative reference voltage.
US09502968B2	Switched-capacitor converters with low-voltage gate drivers An apparatus for converting voltage includes terminals coupled to external circuits at corresponding voltages and a switching network having driving circuits and semiconductor switches that interconnect capacitors in successive states to one another and to the terminals. The switches interconnect some capacitors to one another through a series of switches when an activation pattern causes them to be activated. Each driving circuit has power connections, a control input, and a drive output coupled to and controlling at least one switch. A drive output of one of them couples to and drives each switch. Some of the driving circuits are powered via corresponding power connections from at least one of the capacitors such that a voltage across the corresponding power connections is less than a highest of the corresponding voltages. The terminals and the switching network are constituents of a switched capacitor converter.
US09502959B2	Detection of islanding state in electricity network An exemplary method for detecting a three-phase islanding state in a three-phase electricity network includes supplying power to a three-phase electricity network via a power supply assembly, controlling an output frequency of the power supply assembly with a frequency reference signal adapted to deviate the output frequency of the power supply assembly from a grid frequency representing a frequency of a common electricity network whose portion of the three-phase electricity network is in normal operating conditions. The method also includes detecting a three-phase islanding state in the electricity network if the output frequency of the power supply assembly is outside an allowable value range. During a normal operating state of the electricity network, the frequency reference signal depends on an active output current of the power supply assembly.
US09502954B2	Signal transmission circuit and power conversion device equipped with same A signal transmission circuit includes, in each of a first circuit connected to a first coil of an insulating transformer and a second circuit connected to a second coil of the insulating transformer, a transmitting circuit, a receiving circuit, a coil-side switching circuit, an input/output-side switching circuit, an abnormality detection circuit, a delay circuit, and a direction control section. In the signal transmission circuit, the direction control section controls the switching circuit to switch a signal direction between input and output, and the switching circuit switches between transmission and reception. The delay circuit delays a received signal and returns the resultant signal to the transmitting side, and the abnormality detection circuit detects abnormality to perform self-diagnosis.
US09502952B2	Hybrid motor A multi-phase motor including a rotor and a stator including at least one core. The stator includes a plurality of phase sections. Each phase section is configured to provide a phase of the multi-phase motor. Each phase section includes at least one of the core(s), at least two ring magnets having polarity facing in a substantially same direction, and a winding between the at least two ring magnets. The winding is configured to be energized to direct flux through the at least one core at a first portion associated with a first one of the ring magnets, and to be differently energized to direct flux through the at least one core at a second portion associated with a second one of the ring magnets.
US09502951B2	Electrical machine An electrical machine including a stator and a rotor rotatable relative to the stator with an air gap therebetween. The stator includes a first plurality of sources of magnetic field, which is equally spaced in a circumferential configuration over the stator. The rotor includes a second plurality of sources of magnetic field, which is equally spaced in a circumferential configuration over the rotor. The magnetic sources of at least one plurality are electromagnets and electromagnet includes at least one magnet coil resting on a magnet conductor. The magnetic conductor includes at least one member made of magnetically isotropic and/or anisotropic materials.
US09502950B2	Method of manufacturing rotor for rotating electrical machine A method of manufacturing a rotor for rotating electrical machines, notably an alternator, the rotor including two magnet wheels defining between them at least one interpole space arranged to receive at least one magnet. At least one angular indexing mark is produced on at least one of the magnet wheels. At least one groove partially delimiting the interpole space is formed, by machining, on the magnet wheel while maintaining the magnet wheel in an angular position dependent on the angular indexing mark.
US09502947B2	Generator for vehicle Provided is an AC generator for a vehicle, which is improved in heat-radiation performance and vibration resistance with a simple configuration. The AC generator for a vehicle includes a rectifier which is mounted to a rear bracket (2) and is electrically connected to a stator, for rectifying an alternating current generated in the stator into a direct current. The rear bracket (2) includes a bracket main body (30) having intake windows (32) and exhaust windows (34) partitioned by ribs (33), and a bearing housing portion (41) for housing a bearing therein, a mounting leg portion (31) extending radially outward from the bracket main body (30) so as to be mounted to a mounting target member, and an expanded portion (37) expanding radially from the mounting leg portion (31) toward a circumferential edge portion of the bracket main body (30).
US09502939B2	Method for manufacturing an armature core A method for manufacturing a stator configured to ensure insulation properties between a conductor and an armature core while preventing a manufacturing cost from increasing and preventing a space factor from lowering. In an edge-removing step, a plurality of independent edge-removing punches, which correspond to one slot S or two or more slots S, press and chamfer a corner portion of an axial opening edge of the slot in an axial end core sheet of the armature core.
US09502935B2	Hub shell for bicycle generator hub A hub shell is used as a part of a bicycle generator hub. The hub shell comprises a main body and a magnet arrangement section. The main body has a tubular shape with an internal circumferential surface. The magnet arrangement section is provided on the internal circumferential surface of the main body to arrange a magnet formed therein by injection molding. The magnet arrangement section includes an even section and a non-even section, the non-even section being configured as one of a recess and a protrusion with respect to the even section.
US09502931B2	Brushless motor A brushless motor includes a first rotor core, a second rotor core, and a field magnet member. The first rotor core includes primary projecting pieces arranged along a circumferential direction at equal intervals. The second rotor core has the same shape as the first rotor core, and includes secondary projecting pieces arranged along the circumferential direction at equal intervals. The secondary projecting pieces are positioned between the primary projecting pieces that are adjacent to one another in the circumferential direction. The field magnet member is arranged between the first rotor core and the second rotor core. The field magnet member is magnetized along an axial direction to generate primary magnetic poles in the primary projecting pieces, and generate secondary magnetic poles in the secondary projecting pieces. A rotor includes the first rotor core, the second rotor core, and the field magnet member.
US09502930B2	Motor rotor and motor having same A motor rotor includes an iron core and permanent magnets provided inside the iron core. The iron core is provided with sets of mounting grooves on the iron core in the peripheral direction of the iron core, each set of mounting grooves having two or more mounting grooves provided intermittently in the radial direction of the iron core. There are sets of permanent magnets, the individual permanent magnet of each set of permanent magnets correspondingly being embedded into the individual mounting grooves of each set of mounting grooves; there is an island region between the outermost layer of mounting grooves and the periphery of the iron core, and an enhancing hole is provided in the island region, an enhancing rod being provided in the enhancing hole. A motor includes a motor stator and the motor rotor, with the motor rotor provided inside the motor stator.
US09502929B2	Rotor and motor A rotor with a first rotor core, a second rotor core, a field magnet, and an interpole magnet is provided. The first rotor core has a first core base and a plurality of first nail-shaped magnetic pole parts that extend in the axis direction from the outer circumference section of the first core base. The second rotor core has a second core base and a plurality of second nail-shaped magnetic pole parts that extend in the axis direction from the outer circumference section of the second core base. The field magnet is magnetized along the axis direction and makes the first nail-shaped magnetic parts function as first magnetic poles and the second nail-shaped magnetic parts function as second magnetic poles. The interpole magnet is arranged between the first nail-shaped magnetic parts and the second nail-shaped magnetic parts. The interpole magnet has the same polarity as the first and second nail-shaped magnetic pole parts, in the sections where same face the first and second nail-shaped magnetic pole parts.
US09502927B2	Linear generator with tangential induction Embodiments of the invention relate to an electricity generator system. The system comprises: a conductor; a magnet; and conversion means. The magnet is configured such that motion of the conductor relative to the magnet induces a current in the conductor and the induced current in the conductor causes motion of the magnet. The conversion means are configured to convert motion of the magnet to electricity.
US09502926B2	Differential load detecting method for detecting a wireless power receiver in wireless power network and wireless power transmitter A differential load detection apparatus and method are provided for detecting a wireless power receiver in a wireless power network. The differential load detection method includes transmitting first detection power for detecting the wireless power receiver, transmitting second detection power when an impedance variation greater than a first predetermined threshold value and equal to or less than a second threshold value is detected, and waiting for a reception of an advertisement signal according to the transmission of the second detection power from the wireless power receiver.
US09502923B2	Wireless power transmission apparatus and method and wireless power reception apparatus A wireless power transmission apparatus includes a measurer configured to measure a value of a current flowing in a source resonator, a communication unit configured to receive a value of a charging current of a battery from a wireless power reception apparatus, and a power controller configured to control an amount of power to be transmitted by the source resonator based on either one or both of the value of the current measured by the measurer and the value of the charging current received by the communication unit. The value of the charging current of the battery varies as the battery is charged.
US09502918B2	Battery pulse charging method and apparatus Disclosed herein are some embodiments for safely charging a mobile system battery pack, even when the power source (e.g., adapter) voltage is at a relatively high level that would otherwise result in excessive charge current.
US09502917B2	Charging method of electronic cigarettes and electronic cigarette box The present invention relates to a charging method of an electronic cigarette and an electronic cigarette box. The charging method of the electronic cigarette comprising: presetting first voltage and current, and second voltage and current, charging the electronic cigarette with the first voltage and current for a preset length of time, detecting actual charging current or charging voltage to the electronic cigarette, comparing the actual charging current or charging voltage with the second current or voltage separately, selecting different charging modes to the electronic cigarette according to a comparing result. The electronic cigarette box is enabled to be compatible with different charging management modes for charging the electronic cigarettes, and the charging modes can be automatically selected according to the different charging management modes of the electronic cigarette.
US09502910B2	Power charging apparatus and battery apparatus A power charging apparatus and a battery apparatus quickly charge a battery with power by separately charging each battery cell with power. The power charging apparatus includes: a power supplier supplying power; and a charging part having at least two chargers corresponding one-to-one to at least two battery cells connected to each other in parallel, each of the at least two chargers charging the corresponding battery cell with power transmitted from the power supplying unit. The battery apparatus includes: a battery having at least two battery cells connected to each other in parallel; and a charging part having at least two chargers corresponding one-to-one to the at least two battery cells and charging the at least two chargers with power received.
US09502907B2	Power supplies for pool and spa equipment Power supplies for pool and spa equipment are disclosed. In one embodiment, the power supply includes a buoyant housing, a peripheral float, at least one solar cell positioned on the buoyant housing for collecting sunlight and converting same to electrical energy, and a power cable for interconnecting the power supply and pool/spa equipment. In other embodiments, first and second inductive power couplings are provided for powering pool and spa equipment. The power couplings can also be installed using existing plumbing features of the pool or spa.
US09502906B2	Relay unit and producing method thereof A relay unit electrically opens and closes between a power supply and a power-consuming device. The relay unit includes electronic components in a housing including a case and a cover, the electronic components including a resistor, a first relay connected in series with the resistor, and a second relay, the second relay connecting the power supply and the power-consuming device through an external connection terminal and being connected in parallel with the resistor and the first relay.
US09502903B2	Energy management systems and methods Example energy management systems and methods are described. In one implementation, a system includes an inverter and a combiner module coupled to the inverter. The combiner module receives DC signals from multiple DC sources and delivers a DC output signal. A control module manages a voltage and a current associated with the DC output signal delivered by the combiner module.
US09502900B2	Monitoring voltage stability of a transmission corridor A voltage stability monitoring apparatus monitors the voltage stability of a transmission corridor through which power flows between different parts of a power system. The apparatus monitors an equivalent load impedance at an interface between the transmission corridor and a part of the power system designated as generating the power. This equivalent load impedance at the interface comprises a ratio of a voltage phasor at the interface to a current phasor at the interface. The apparatus tracks a Thevenin equivalent voltage and impedance of the designated part by separately updating that voltage and impedance. Notably, the apparatus updates the Thevenin equivalent voltage to reflect the magnitude of any changes in the voltage phasor that are associated with large variations in the magnitude of the equivalent load impedance at the interface. The apparatus computes an index indicating the voltage stability as a function of this tracked Thevenin equivalent voltage and impedance.
US09502898B2	Systems and methods for managing a power distribution system A system and method of determining priorities for restoration of power in a power distribution system includes collecting customer prioritization data for a set of customers. An inconvenience factor is determined from the customer prioritization data for each customer. A zone restoration factor is then determined from the inconvenience factor for each customer. The inconvenience factor takes into account the estimated outage time, the customer's back-up time, the willingness of the customer to use back-up devices, and customer's priority for the estimated outage time.
US09502891B2	ESD protection device Provided is an ESD protection device that can suppress degradation of discharge characteristics caused by repeated discharge. The ESD protection device comprises (a) a ceramic multilayer substrate 12 in which a plurality of ceramic layers are stacked, (b) a cavity 13 formed inside the ceramic multilayer substrate 12, (c) at least one pair of discharge electrodes 14, 15 including opposing portions 14t, 15t that are formed along an inner surface of the cavity 13 and that face each other with a spacing held therebetween, and (d) outer electrodes formed on a surface of the ceramic multilayer substrate 12 and connected to the discharge electrodes 14, 15. At least one of the opposing portions 14t, 15t of the discharge electrodes 14, 15 is connected to one end portion of a via conductor 22, 23 penetrating through the ceramic layer of the ceramic multilayer substrate 12.
US09502884B2	Methods and systems for protecting DC circuits Methods and systems for protecting DC circuits are provided. In an aspect, a method for controlling at least one protection circuit is disclosed. The method can monitor one or more parameters of the at least one protection circuit. One or more control signals can be selectively provided to a plurality of switches in the at least one protection circuit based on one or more parameters of the at least one protection circuit, in order to implement the appropriate protective topology based on one or more parameters of the at least one protection circuit. The method can be used to control a plurality of switches in the protection circuit and protect the DC circuit against short circuit, instabilities, and bus outages, and the like.
US09502883B2	Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.
US09502879B2	Insulation waterproof member and insulation waterproofing method An insulating waterproof member for insulating and waterproofing a connector of a cable, the insulating waterproof member including: a sealing material for covering the connector, and a protective sheet for covering the connecting portion with the sealing material interposed therebetween, the protective sheet having an adhesive layer on a surface on a sealing material side, wherein the protective sheet includes a body portion for covering the connector and an extending portion that extends in a first direction from the body portion, and the extending portion allows pressure to be imparted to the sealing material and the body portion that cover the connector in a first region at a first end side of the body portion in a second direction that intersects the first direction, in a second region at a second end side of the body portion, and in a third region between the first region and the second region.
US09502877B2	Inlet funnel for cable terminal The present invention provides an inlet funnel (100) for cable terminal, which comprises a funnel body part (10) and a fixation part (20). The funnel body part (10) has one end with a smaller opening and the other end with a larger opening, said funnel body (10) having a gradually increasing diameter (D) from said one end with the smaller opening to said other end with the larger opening, and the funnel body (10) is suitably to be installed over an electrical cable (C). The fixation part (20) is provided at said other end with the larger opening of said funnel body part (10) and adapted for the attachment of said inlet funnel (100). The inlet funnel (100) further comprises a pretreated mounting part (30) extending from said one end side with the smaller opening towards said the other end side with the larger opening. Accordingly, the inlet funnel for cable terminal according to the present invention may reduce workload, save time, and simplify the mounting process.
US09502875B2	In-wall extension apparatus Various embodiments of the apparatus and/or methods are described for routing power to a wall-mounted appliance, particularly for routing electrical wiring and audio/video cabling up through a wall to power and communicate with a wall-mounted presentation device. The apparatus and systems include input and output enclosures with wiring therebetween and mechanisms for mounting the input and output enclosures adjacent to pre-cut wall openings. There exists at least one electrical input connector, disposed within the input enclosure, configured to electrically couple with a power source, and at least one electrical output connector, disposed within the output enclosure, configured to electrically couple with a wall-mounted appliance.
US09502868B2	Gas-insulated switchgear A circuit breaker is accommodated in a circuit breaker compartment such that a contacting/separating direction of a contact of the circuit breaker is along a vertical direction, a cable terminal of a first cable connected to one terminal of the circuit breaker via a first disconnector is accommodated in a first connection compartment such that a central conductor of the cable terminal is along the vertical direction, and a disconnector compartment which accommodates the first disconnector such that a contacting/separating direction of a contact of the first disconnector is along the vertical direction, is joined so as to be disposed between the circuit breaker compartment and the first connection compartment.
US09502863B2	Surface-emitting semiconductor laser, surface-emitting semiconductor laser device, optical transmission device, and information processing device Provided is a surface-emitting semiconductor laser including a substrate; a first semiconductor multilayer reflector of a first conductivity type formed on the substrate, the first semiconductor multilayer reflector including plural pairs of a low-refractive-index layer and a high-refractive-index layer; a cavity region formed on the first semiconductor multilayer reflector; a second semiconductor multilayer reflector of a second conductivity type formed on the cavity region, the second semiconductor multilayer reflector including plural pairs of a low-refractive-index layer and a high-refractive-index layer; a columnar structure extending from the second semiconductor multilayer reflector to the cavity region; and a current confinement layer formed inside the columnar structure by selective oxidation of a semiconductor layer containing Al. The cavity region includes an active region; and a cavity extension region interposed between the active region and the first semiconductor multilayer reflector.
US09502862B2	Light emitting elements drive control device, droplets-deposited layer drying device, and image forming apparatus A light emitting elements drive control device includes: a detection unit that detects drive voltages and drive currents of a plurality of respective semiconductor light emitting elements arranged in a width direction of a recording medium; a calculation unit that calculates generated heat amounts of the respective semiconductor light emitting elements from heating-raised temperatures of the respective semiconductor light emitting elements determined based on the drive voltages and the drive currents detected by the detection unit, and calculates actual emission light quantities of the semiconductor light emitting elements from differences between the generated heat amounts of the semiconductor light emitting elements and input heat amounts corresponding to powers supplied to the semiconductor light emitting elements, respectively; and a correction unit that corrects differences between the actual emission light quantities of the semiconductor light emitting elements calculated by the calculation unit and required emission light quantities, respectively.
US09502853B2	Gas laser device having function for discriminating type of alarm A gas laser device having a function for properly controlling the gas pressure of a laser oscillator after an alarm is generated. A controller of the laser device has an alarm monitoring part which monitors as to whether an alarm is generated in the oscillator, by which discharge in the oscillator should be stopped; an alarm judging part which discriminates a type of the alarm generated in the oscillator; a gas pressure controlling part which controls a pressure of laser gas within a discharge tube of the oscillator; and a power supply controlling part which controls a power supply of the oscillator. The gas pressure controlling part controls the pressure of the laser gas within the discharge tube to an appropriate value, after the alarm is generated, based on one of a plurality of control patterns predetermined corresponding to the respective types of the alarm.
US09502851B1	Waveguide amplification switch An apparatus includes a polymer waveguide having a doped region, with amplifying dopant, separating a first un-doped region and a second un-doped region. The doped region being doped with an amplifying dopant. An optical pump source illuminates the doped region to allow light to transmit from the first un-doped region to the second un-doped region.
US09502849B2	Commutator A commutator includes a first body and a second body which are separately made of electrically insulating material, a plurality of commutator segments fixed on an outer surface of the first body and a plurality of commutator terminals. The first body is a hollow cylinder with two opposite ends. Each terminal has a contact area for contacting a corresponding one of the commutator segments. The second body has a base and a ring wall extending from the base, and one end of the first body is received in a space defined by the base and the ring wall, with the contact area of each terminal being in tight contact with the corresponding commutator segment at the inner side of the ring wall.
US09502842B2	Network interface connector with proximity compensation A network interface connector includes a plurality of first and second alternating elongate contacts having contact portions situated in a common plane. The first and second contacts have rearward portions situated in respective first and second spaced parallel planes defining a proximity gap between them. A proximity insert having a particular electrical construction suited for a particular application is situated, preferably in a replaceable manner, in the proximity gap to provide the connector with desired transmission properties.
US09502841B2	Flippable electrical connector A plug for provision of power includes a housing forming a receiving cavity with two opposite sites in a vertical direction which is compatible with a standard plug connector with twelve contacts on each site and a first and second rows of contacts on the sides while in diagonally symmetrical manner. Each contact includes a contacting section, and a connecting section for directly connecting to a corresponding wire. Each row of contacts is categorized with a pair of power contacts, a pair of grounding contacts and a specific contact without any high speed differential pair. Two pair of power contacts of both two rows are electrically connected together either via direct mechanical connection via vertical extensions or via indirect electrical connection via the latch which has a pair of side arms extending into the receiving cavity at two opposite transverse ends.
US09502839B2	Electrical receptacle connector An electrical receptacle connector includes an insulated housing, a plurality of upper-row receptacle terminals, and a plurality of lower-row receptacle terminals. The insulated housing includes a base portion. Each of the upper-row receptacle terminals includes a tail portion protruded from the base portion. Each of the lower-row receptacle terminals includes a tail portion protruded from the base portion. The tail portions of the upper-row receptacle terminals and the tail portions of the lower-row receptacle terminals are protruded from the base portion, aligned into a line, and spaced from each other.
US09502836B2	Socket contact, inter-connector and connector device A socket contact is connectable with a first terminal and a second terminal at opposite ends thereof in an axial direction, respectively. The socket contact comprises a first portion, a second portion and a coupling portion. The first portion has a first end, a second end and a first spring portion. The first end includes a first contact point which is to be connected to the first terminal. The second end includes a second contact point which is to be connected to the second terminal. The first spring portion is positioned between the first contact point and the second contact point. The second portion has a third end, a fourth end and a second spring portion. The third end includes a third contact point which is to be connected to the first terminal. The fourth end includes a fourth contact point which is to be connected to the second terminal. The second spring portion is positioned between the third contact point and the fourth contact point. The coupling portion couples the first end with the fourth end.
US09502835B2	Electrical connector having a movable terminal and a static terminal An electrical connector includes: an insulative housing including a first insulative base with a first contact-receiving slot and a second contact-receiving slot and a second insulative base mounted to the first insulative base; an insulative cap attached to the insulative housing; a metal shell covering the insulative housing and the insulative cap; a static terminal received in the first contact-receiving slot; and a movable terminal received in the second contact-receiving slot. The movable terminal includes a resisting portion connecting and a pair of extension arms extending from the resisting portion. The second contact-receiving slot includes an engaging groove and a holding groove crossing with the engaging groove, the engaging groove defines a bottom wall inclining upwardly from a middle thereof to outer ends thereof to support the free ends of the extension arms. And the resisting portion is operable to be in touch with the bottom wall.
US09502832B1	Duplex receptacle having a plurality of LEDs to illuminate the sockets An illuminated duplex receptacle allows a small amount of light to escape from both the upper and lower sets of receiving sockets. The present invention adds to a standard duplex outlet by placing two light emitting diodes (“LEDs”) inside the plastic housing. One LED is placed behind the electrodes for the upper set of sockets. One LED is placed behind the electrodes for the lower set of sockets. The electrodes are interposed between the LEDs and the receiving sockets. In this way, only a small amount of indirect light filters out of the receiving sockets. In one embodiment, the LEDs run at one-quarter watt or less of continuous power. In an alternative embodiment, the housing is translucent, and the LEDs run at one watt or more of continuous power.
US09502830B2	Multimedia faceplates having ethernet conversion circuitry A multimedia faceplate includes a frame having a front face and a rear face and at least one connector mounting aperture therein, a non-Ethernet connector mounted in the connector mounting aperture, an Ethernet conversion unit that is electrically connected to the non-Ethernet connector and a plurality of wire connection contacts that are electrically connected to the Ethernet conversion unit. The Ethernet conversion unit is configured to draw an electrical power signal from either an AC to DC power conversion unit or from a Power-over-Ethernet power signal received from an Ethernet cable that is connected to the wire connection contacts.
US09502829B2	Modular jack having transformer with winding wires and method of making the same An electrical connector (500) includes a transformer (100) including a magnetic core (3), a first wire group (1), and a second wire group (2). The magnetic core has a left half (31), a right half (32), and an opening (30). The first and second wire groups each have four wires with different colors. Each wire has a first end, a second end, and a central portion. The central portion of the first wire group is only wound around the left half. The central portion of the second wire group is only wound around the right half.
US09502828B2	Insulation body of a plug-in connector The invention relates to an insulation body of a plug-in connector that consists of a plug body (10), in which contact elements (11) are provided, and which consists of a connection body (20), which in turn has connection elements (21) that can be electrically connected to conductor tracks of a circuit board and/or to individual wires of a multi-wired cable to be connected, wherein the plug body (10) and the connection body (20) can be mated together, as a result of which the contact elements (11) can be electrically contacted with the connection elements (21) of the connection body (20).
US09502827B2	Electrical connector with improved metal shell An electrical connector includes an insulative housing, at least one contact module, an inner metal shell, and a tubular outer metal shell. The insulative housing has a top wall, a bottom wall, a pair of side walls, and a receiving chamber. The contact module includes an insulator and a set of contacts retained in the insulator. Each contact has a contact portion protruding into the receiving chamber. The inner metal shell has a main frame surrounding the insulative housing by 360 degrees. The outer metal shell surrounds the inner metal shell and contacts with the inner metal shell.
US09502825B2	Shunt for electrical connector A shunt for an electrical connector that comprises a conductive body which has two resilient leg extensions connecting at a hinge, each of the leg extensions terminating at a tail end opposite the hinge. Each of the leg extensions has at least one contact point on an outer surface thereof for engaging a contact of the electrical connector. The leg extensions curve such that they diverge from one another at at least one portion of the conductive body. The at least one contact point is located at this at least one portion.
US09502824B2	Electrical connector An electrical connector for terminating an electrical cable and for engaging with a mating electrical connector comprises a body, resilient member, and a collar. The body has an engagement portion including a sleeve which extends in a longitudinal direction for engaging with the mating electrical connector. The sleeve comprises a keyway configured to receive a keyed mating connector. The resilient member is arranged on the sleeve and can deform in a transverse direction perpendicular to the direction and provide a reaction force for maintaining the engagement of the connector with the mating connector. The collar is configured to rotate about the sleeve, and comprises a radially inwardly protruding pin which extends into the sleeve and can be moved between two positions. One position is within the keyway between the key of the mating connector and the keyway opening such that the pin prevents axial disengagement of the connector.
US09502821B2	Flippable electrical connector An electrical connector includes an insulative housing defining a forwardly extending mating tongue, a plurality of contacts with contacting sections exposed upon the mating tongue and a metallic shield enclosing the insulative housing to define a mating cavity. A metallic shielding plate is embedded within the mating tongue and forms a pair of locking notches in two opposite lateral sides. The mating tongue further includes in two opposite lateral sides a pair of recesses aligned with and intimately located inside of the pair of locking notches, respectively, in the transverse direction. The housing and the corresponding contacts commonly form the terminal module which is composed of an upper terminal module, a lower terminal module commonly sandwiching a shielding plate module therebetween in the vertical direction. The metallic shield optionally defines a clip structure by folding an extension on a rear lower edge thereof.
US09502820B2	Connector assembly A connector assembly including a first connector, a second connector and a latch for connecting the first and second connectors. A securing lock is rotatable between a release position and a securing position securing the latch in a latching position. Optionally, the assembly includes a sliding guide and a resilient element forcing the securing lock to slide via the sliding guide into the securing position.
US09502819B2	Methods and apparatus for connecting devices with stacked magnetic connectors There is disclosed magnetic connectors and electronic devices including such connectors. A connector may include a magnet rotatable about at least one axis of the magnet; wherein the magnet rotates to magnetically engage a magnet of another connector to form an electrical connection between the two magnets. A connector may also include a cylindrical magnet to magnetically engage a magnet of another connector; and a sleeve wrapped around at least part of the magnet, the sleeve comprising a contact for forming an electrical connection with a contact on the other connector. A connector may be adapted for selective connection with other connectors. A connector may be adapted such that a moveable magnet may move between an engaged position proximate a contacting surface of the connector and a disengaged position recessed from a contacting surface, wherein the moveable magnet is biased to the disengaged position.
US09502818B2	USB plug without a metallic shell A USB plug includes a first housing piece having a base portion and a tongue portion extending forwards from the base portion, a second housing piece, a plurality of contacts and a cable. Each contact comprises a contacting portion, a retaining portion fixed in the first housing piece and a tail portion, the contacting portions exposed on the tongue portion for mating with a USB receptacle connector. The cable is soldering with tail portions of the contacts. The first housing piece defines a depression on a bottom surface thereof, the second housing piece is received in the depression and ultrasonic welding with the first housing piece.
US09502814B2	Connector cover and connector connecting apparatus A connector cover holds altogether a plurality of insertion connectors, the insertion connectors being provided at corresponding ends of cables and inserted into reception connectors. The connector cover includes a cover part in which a plurality of holding openings that hold the insertion connectors with ends thereof being exposed are formed so that the insertion connectors can be inserted into the reception connectors. The cover part can be divided along a dividing surface including the holding openings. The cover part is formed with a lock-lever pressing part that presses a lock lever of corresponding one of the insertion connectors held by the holding openings to fix the insertion connectors in an unlocked state for each of the holding openings.
US09502813B2	Supporting frame construction for modular connectors A supporting frame construction for modular connectors comprises a main structural element associated by sliding engagement means with a linear element; said main structural element including a linear portion having a plurality of seats for engaging therein a plurality of corresponding projections formed on modules to be mounted in the supporting frame construction; said linear element including a plurality of linear element seats, corresponding to the seats of the linear portion of the main structural element, for engaging therein corresponding projections formed on said modules.
US09502811B1	Process connector design to reduce or eliminate hoop stress in dielectric components An apparatus includes a conductor configured to transport a signal, a male connector surrounding at least a portion of the conductor, and a load ring configured to secure the conductor. The apparatus also includes a female connector including an annular end forming a cavity configured to receive the load ring in a first portion of the cavity and at least a portion of the male connector in a second portion of the cavity. Sidewalls of the first portion of the cavity are configured to create a compressive radial force on an outer surface of the load ring to reduce hoop stress resulting from radially-offset longitudinal forces on the load ring.
US09502807B2	Tamper resistant receptacle A tamper resistant electrical receptacle comprising a slide housing disposed beneath the hot and neutral blade openings in the receptacle. The slide housing includes a neutral slide body and a hot slide body having slide pads and tabs for reducing friction when the bodies slide against each other as the spring bias of the bodies in the slide housing is overcome by simultaneous insertion of the tines of an electrical plug contact ramp surfaces and camming past the slide bodies causing them to slide against each other and spreading a gap area a distance sufficient for receiving the lateral neutral prong of a 20 A electrical plug.
US09502803B2	Terminal and electrical connector A terminal and an electrical connector are shown and the terminal has a tail, an elastic arm, a contact and a front guiding member. The elastic arm is connected to the tail. The contact is positioned at a distal end of the elastic arm. The contact has a front guiding surface extending forwards and downwards. The front guiding member extends forwards from the elastic arm. The front guiding member has a front guiding portion that extends forwards and downwards. An extending direction of the elastic arm and an extending direction of the front guiding member intersected at an angle. The front guiding portion is positioned in front of the front guiding surface of the contact.
US09502800B2	Double-mated edge finger connector A double-mated edge finger connector that is configured to double the connector density without resorting to a reduction in pitch. A first connector defines a first slot configured to receive and permit horizontal displacement of an edge finger of a second board relative thereto, while a second connector defines a second slot configured to receive and permit horizontal displacement of an edge finger of a first board relative thereto, to thereby establish an electrical connection between the first board and the second board.
US09502797B2	Contact A contact that electrically connects a first board and a second board includes a bottom part to be joined to the first board, a first spring that is bent and extends from the bottom part, a second spring configured to be displaced in a first direction toward the bottom part and in a second direction opposite to the first direction by the bending of the first spring, multiple side guides rising from the bottom part, and a stopper provided at an end of each of the side guides in the second direction and configured to come into contact with the second board. The side guides include respective extension parts configured to protect an area in which the second spring is displaced.
US09502794B2	Field-replaceable terminal block divider A terminal block assembly with one or more removable dividers. The dividers include a tenon that can be inserted into a groove in one or more blocks. The dividers can be retained by a fastening member, such as a clip, placed at an open end of the groove.
US09502793B2	Assembly structure of electrical junction box Provided is an assembly structure of an electrical junction box which makes it possible to fit an electrical component attachment block into an insulation case without provision of a lock mechanism. Included are a housing (15) provided in an insulation case (5) and configured to house an electrical component attachment block (7); contact walls (19, 20) provided in an inner wall of the housing (15), and configured to come into contact with the housed electrical component attachment block (7); a terminal receiving portion (23) provided to the insulation case (5), on which to place a connection terminal (8); and a fastening module (9) configure to screw-fix the connection terminal (8) placed on the terminal receiving portion (23) to a conduction bus bar (37) in the electrical component attachment block (7) housed in the housing (15). The electrical component attachment block (7) is fitted into the insulation case (5) by fixing the connection terminal (8) to the conductor bus bar (37) by use of the fastening module (9) with the electrical component attachment block (7) put in contact with the contact walls (19, 20).
US09502790B2	Spring clamp contact and connecting terminal for electrical conductors A resilient clamping contact for contacting electrical conductors, said resilient clamping contact having a current rail and having at least two resilient clamping elements that each have a contacting limb, a resilient bend that adjoins the contacting limb and a clamping limb that adjoins the resilient bend and comprises a clamping section at the free end, and having frame parts that extend away from the current rail and have in each case two lateral connecting pieces that are spaced apart from one another and transverse connecting pieces that connect the lateral connecting pieces one to the other, and a conductor feedthrough opening that is formed by the lateral connecting pieces and the transverse connecting pieces. A resilient clamping element is fastened to the current rail by means of the contact of the contacting limb of the resilient clamping element and/or a retaining element of the current rail to a transverse connecting piece in such a manner that the clamping section acts in the direction of the current rail under the influence of the resilient force of the resilient clamping element. The at least two frame parts for the at least two resilient clamping elements are arranged spaced apart from one another with an intermediate space between two spaced apart lateral connecting pieces of adjacent frame parts.
US09502786B2	Electrical contact element Disclosed is an electrical contact element for contacting an electrical strand conductor, wherein the electrical contact element has a connecting side and a plugging side. A splicing element is provided in a connecting sleeve that forms the connecting side so as to electrically contact an electrical strand conductor in a more effective manner. The splicing element is provided for the purpose of separating out the individual strands of the conductor, contacting as large as possible a surface of the individual strands and penetrating the surface of the strands during a squeezing or crimping action. The arrangement provides a reliable, electrical contact of strand conductors in which a surface of the individual strands that is not suitable for being contacted and is poorly conductive is penetrated.
US09502778B2	Antenna apparatus less susceptible to surrounding conductors and dielectrics An antenna apparatus is provided with: a dielectric substrate, a front array including a feed element and a plurality of parasitic elements, the feed element being formed on the dielectric substrate and having one radiation direction, and the plurality of parasitic elements being formed on the dielectric substrate in an area located in the radiation direction with respect to the feed element; and at least one side array including a plurality of parasitic elements formed on the dielectric a substrate in at least an area located in a direction other than the radiation direction with respect to the feed element. The plurality of parasitic elements of each side array are aligned substantially along the radiation direction.
US09502777B2	Artificial microstructure and artificial electromagnetic material using the same The present invention provides an artificial microstructure. The artificial microstructure includes at least three split rings. The at least three split rings surround and embed in turn. Each split ring is formed by a wire which is made of conductive material, with two terminals of the wire towards each other to form an opening of the corresponding split ring. The present invention also provides an artificial electromagnetic material using the artificial microstructure. The artificial electromagnetic material with the artificial microstructure can achieve the function of broadband wave-absorbing.
US09502776B2	Antenna surrounded by metal housing An antenna system includes a metal housing including a first edge and a second edge that meet at a corner and a slot located proximate the second edge that extends from the first edge parallel to the second edge defining a strip and an antenna located behind and in close proximity to the strip. The antenna is coupled to the strip. A parasitic element is located proximate the antenna and the strip includes a ground coupling that crosses the slot in spaced relation thereto. The parasitic element assists in establishing second and third higher frequency modes of the antenna system.
US09502771B2	Loop antenna for mobile handset and other applications There is disclosed a loop antenna for mobile handsets and other devices. The antenna comprises a dielectric substrate (23) having first and second opposed surfaces and a conductive track (24) formed on the substrate (23). A feed point (26) and a grounding point (25) are provided adjacent to each other on the first surface of the substrate (23), with the conductive track (24) extending in generally opposite directions from the feed point (26) and grounding point (25) respectively and winding around the substrate (23) to the second surface and passing along a path generally opposite to the path taken on the first surface of the dielectric substrate (23). The conductive tracks (24) then connect to respective sides of a conductive arrangement (27) that extends into a central part of a loop formed by the conductive track (24) on the second surface of the dielectric substrate (23). The conductive arrangement (27) comprises both inductive and capacitive elements. The antenna can be multi-moded and operate in several frequency bands. Alternatively, the loop antenna is fed parasitically by a monopole or a feeding loop. The parasitic loop antenna my alternatively comprise a conductive loading plate instead of the conductive arrangement.
US09502770B2	Compact multiple-band antenna for wireless devices A device in a wireless communication system, comprising a transmitter for transmitting information over a plurality of frequency bands, a receiver for receiving information over a plurality of frequency bands and a multiple-band antenna electrically connected to said transmitter and said receiver, wherein said multiple-band antenna is comprised of a first feed point configured to electrically connect said multiple-band antenna to said transmitter and said receiver, wherein said multiple-band antenna forms a first antenna type and a second feed point configured to electrically connect said multiple-band antenna to said transmitter and said receiver, wherein said multiple-band antenna forms a second antenna type.
US09502769B2	Multiband switchable antenna structure A multiband switchable antenna structure includes a feeding element, a first radiation element, a second radiation element, circuit branches, and a switch circuit. A first end of the feeding element is a feeding point. A first end of the first radiation element is coupled to a second end of the feeding element. A second end of the first radiation element is open. A first end of the second radiation element is coupled to the second end of the feeding element. The circuit branches have different impedance values. The switch circuit selects one of the circuit branches as a matching branch according to a control signal. A second end of the second radiation element is coupled through the matching branch to a ground voltage.
US09502766B2	Electronically reconfigurable, piecewise-linear, scalable analog monopulse network A monopulse beam former for an array antenna composed of a plurality of sub-arrays. In one embodiment, a monopulse beam former includes, for each sub-array, a sum feed network and a delta feed network, each feeding an analog processor. The delta beam former includes a plurality of couplers with coupling coefficients increasing linearly across the sub-array. The analog processor includes a first gain-phase module in line with the output of the delta feed network, and a second gain-phase module adjusting the gain and phase of a portion of the output of the sum feed network added to the delta signal. The gain settings and phase settings of the first and second gain-phase modules are adjusted to provide a piecewise-linear approximation to a desired antenna pattern.
US09502765B2	Apparatus and method of a dual polarized broadband agile cylindrical antenna array with reconfigurable radial waveguides Embodiments are provided for an agile antenna that beamsteers radio frequency (RF) signals by selectively activating/de-activating tunable elements on radial-waveguides using direct current (DC) switches. The antenna comprises two parallel radial waveguide structures, each comprising a first radial plate, a second radial plate in parallel with the first radial plate, and conductive elements positioned vertically and distributed radially between the two plates. The radial waveguide structure further includes a plurality of quarter RF chokes which are connected to the conductive elements via respective micro-strips and tunable elements. The two parallel radial plates are separated by a height determined according to a desired transmission frequency range for RF signals, a length of the micro-strips, a diameter of the conductive elements, and a clearance space around each one of the conductive elements.
US09502763B2	Stabilization system for satellite tracking antenna using gyro and kalman filter and stabilization control method for satellite tracking antenna A stabilization control method for a satellite tracking antenna disclosed herein includes outputting a monopulse signal and a gyro signal through a satellite tracking antenna having a gyro mounted thereto, under a situation that disturbance is applied to the satellite tracking antenna, inputting the output monopulse signal and gyro signal into a Kalman filter for stabilization of the satellite tracking antenna, defining a state vector of the Kalman filter based on a pointing-error angle for the satellite tracking, corresponding to the monopulse signal, and a pointing-error angular velocity for the satellite tracking, corresponding to the gyro signal, predicting an original monopulse signal corresponding to a state prior to distortion of the monopulse signal based on the defined state vector, and continuously updating the prediction of the original monopulse signal, and carrying out the stabilization control for the satellite tracking antenna by using the predicted original monopulse signal as a pointing-error-correcting input value.
US09502762B2	Antenna structure An antenna structure includes a base, at least one first extending member and at least one second extending member. The base is detachably and pivotally connected to the first extending member, and includes a first transmitting unit. The first extending member is detachably and pivotally connected to the second extending member, and includes a second transmitting unit. The second extending member includes a third transmitting unit. The first transmitting unit is electrically connected to the second transmitting unit, and the second transmitting unit is electrically connected to the third transmitting unit.
US09502761B2	Electrically small vertical split-ring resonator antennas A vertical split ring resonator antenna is disclosed, comprising a substrate having an upper surface and lower surface, an interdigitated capacitor coupled to the upper surface of the substrate and ground coupled to the lower surface. The interdigitated capacitor includes a first planar segment and a second planar segment, each having interdigitated fingers that are separated by a gap disposed between the first planar segment and second planar segment. The interdigitated capacitor is coupled to the substrate to form a vertical split ring resonator.
US09502756B2	Antenna driving device An antenna driving device includes an antenna driving circuit arranged to generate driving current of a transmission antenna, a power supply circuit arranged to generate an output voltage from an input voltage so as to supply the output voltage to the antenna driving circuit, and a logic circuit arranged to control the antenna driving circuit and the power supply circuit. The power supply circuit has a function of temporarily disabling current feedback control so as to perform voltage feedback control using a reference value just before halting the drive of the transmission antenna when the power supply circuit restarts to drive the transmission antenna, or has a function of performing variable control of a reference value for current feedback control in accordance with a rising edge of the driving current when the power supply circuit restarts to drive the transmission antenna.
US09502755B2	Automotive radio antenna and method for making the same A method and system for increasing the performance of an automotive plate antenna system are provided. A carbon loaded material is used to enhance performance of the plate antenna. The method and resulting systems have a first metallic plate of the antenna arranged and secured on a planar surface of the carbon loaded material. The method realizes an antenna system with reduced size and weight without a reduction in performance.
US09502753B2	Communication terminal device A communication terminal device includes a power feeding coil connected to a power feeding circuit, a planar radiation conductor arranged in the vicinity of the power feeding coil and including a cutout portion overlapping with a coil opening of the power feeding coil when viewed in a plan view, and a rear metal body arranged at a side opposite to the planar radiation conductor with respect to the power feeding coil and in the vicinity of the planar radiation conductor, wherein a punched portion which does not overlap with at least a portion of the power feeding coil when viewed in a plan view and has a shape different from a shape of the cutout portion on the planar radiation conductor is provided on the rear metal body.
US09502752B2	Antenna having flexible feed structure with components Electronic devices may include antenna structures. The antenna structures may form an antenna having first and second feeds at different locations. Transceiver circuitry for transmitting and receiving radio-frequency antenna signals may be mounted on one end of a printed circuit board. Transmission line structures may be used to convey signals between an opposing end of the printed circuit board and the transceiver circuitry. The printed circuit board may be coupled to an antenna feed structure formed from a flexible printed circuit using solder connections. The flexible printed circuit may have a bend and may be screwed to conductive electronic device housing structures using one or more screws at one or more respective antenna feed terminals. Electrical components such as an amplifier circuit and filter circuitry may be mounted on the flexible printed circuit.
US09502750B2	Electronic device with reduced emitted radiation during loaded antenna operating conditions An electronic device may have an antenna for providing coverage in wireless communications bands of interest. The wireless communications bands may include a communications band at a first frequency. The antenna may have a parasitic antenna resonating element that supports a low efficiency resonance. In response to operation of the electronic device in free space, the low efficiency resonance will be located at a second frequency that is greater than the first frequency. In response to operation of the electronic device in proximity to a user's body or other external object, the antenna will be loaded and the low efficiency resonance associated with the parasitic antenna resonating element will shift to the communications band at the first frequency. The antenna may include a resonating element formed on a flexible printed circuit or a dielectric carrier such as a plastic support structure.
US09502749B2	Antenna construction, for example for an RFID transponder system The invention relates to an antenna assembly having a microchip, a first antenna portion of a conducting material supported by a substrate and a second portion of the conducting material wrapped around the substrate, first antenna portion and microchip. Both antenna portions are connected to the microchip and said antenna portions overlap in order to form a capacitance. The antenna assembly may be employed in a construction for an RFID chip for long ranges.
US09502748B2	Holder for antenna testing A holder for antenna testing includes a track base, an antenna carrying device, and at least one displacement-measuring member. The track base has a track platform and a track module disposed on the track platform. A longitudinal direction of the track module defines a displacing direction. The antenna carrying device is movably disposed on the track module along the displacing direction. The displacement-measuring member is movably disposed on the track platform along the displacing direction and is arranged outside the track module. The displacement-measuring member has a zero point and a distance scale counting from the zero point along the displacing direction. The displacement-measuring member is adjustable to align the zero point to the antenna carrying device.
US09502746B2	180 degree hybrid coupler and dual-linearly polarized antenna feed network A 180° hybrid coupler includes three coupled-line couplers connected between two inputs and two outputs. Each of the three coupled-line couplers is defined by at least one ground conductor and only two signal conductors.
US09502745B2	Flexible substrate having a microstrip line connected to a connection portion with a specified conductor pattern A flexible substrate is disclosed. The flexible substrate includes an insulating substrate having a first surface and a second surface opposite to the first surface, a first connection portion having a first conductor, a first ground pattern, and a second ground pattern on the first surface, the first ground pattern and the second ground pattern being spaced apart from the first conductor and respectively located at either side of the first conductor, a conductor pattern formed on the second surface, the conductor pattern being connected to the first conductor, and a third ground pattern formed on the second surface, the third ground pattern being connected to the first ground pattern, wherein a distance between the conductor pattern and the third ground pattern is smaller than a distance between the first conductor and the first ground pattern.
US09502744B2	Microstrip line structures The invention is related to a microstrip line structure, which comprises: a first microstrip line and a second microstrip line, paralleled with the first microstrip line for transferring a transmission signal, and a plurality of grooves periodically arranged on both sides of the second microstrip line by using subwavelength, and each period length in the plurality of grooves is smaller than the wavelength of the transmission signal.
US09502743B2	Systems and methods of waveguide assembly using longitudinal features Various embodiments provide for waveguide assemblies which may be utilized in wireless communication systems. Various embodiments may allow for waveguide assemblies to be assembled using tools and methodologies that are simpler than the conventional alternatives. Some embodiments provide for a waveguide assembly that comprises a straight tubular portion configured to be shortened, using simple techniques and tools, in order to fit into a waveguide assembly. For instance, for some embodiments, the waveguide assembly may be configured such that the straight portion can be shortened, at a cross section of the portion, using a basic cutting tool, such a hacksaw. In some embodiments, the straight portion may be further configured such that regardless of whether the straight tubular portion is shortened, the waveguide assembly remains capable of coupling to flanges, which facilitate coupling the straight tubular portion to connectable assemblies, such as other waveguide assemblies, radio equipment, or antennas.
US09502740B2	Thermal management in electronic apparatus with phase-change material and silicon heat sink Embodiments of an apparatus with a thermal management technique utilizing a silicon heat sink and/or a phase-change material, as well as an assembling method thereof, are described. In one aspect, the apparatus comprises a main unit, a phase-change material and an enclosure enclosing the main unit and the phase-change material. The main unit comprises a substrate and at least one heat-generating device disposed on the substrate. The phase-change material is in direct contact with each heat-generating device of the at least one heat-generating device to absorb and dissipate heat generated by the at least one heat-generating device.
US09502733B2	Electrode assembly and secondary battery having the same A secondary battery includes an electrode assembly designed to prevent an internal short circuit. The electrode assembly includes an electrode group formed by stacking and winding a first electrode plate, a separator and a second electrode plate, and a tape is attached to upper and lower parts of an end of the electrode group. An end of the separator is exposed externally, and the tape is attached to upper and lower parts of the end of the separator. Furthermore, a secondary battery having the electrode assembly is provided.
US09502727B2	Fuel cell system and method of controlling a fuel cell system In a fuel cell system that includes a reformer adapted to reform a feedstock, and a fuel cell that uses fuel gas contained in the reformed gas produced by this reformer to generate electricity, aims to improve generation efficiency in the fuel cell through a relatively simple feature. The fuel cell system includes a feedstock supplying section such as a pressurizing pump for supplying the feedstock to the reformer; a burner adapted to combust the fuel gas that was not consumed by electricity generation in the fuel cell, and heat the reformer; a temperature sensor for sensing the temperature of the burner; and a control unit adapted to control on the basis of the sensed temperature the feed rate of the feedstock supplied from the feedstock supplying section to the reformer, so as to maintain the temperature of the reformer within a prescribed temperature range optimized for reforming the feedstock.
US09502726B2	Cathode humidification unit adapting degradation factor A method and an apparatus to adapt the performance of a cathode humidification unit as a membrane in a fuel cell stack degrades over time. An algorithm compares a sensed humidity profile of the fuel cell stack and model humidity profile of a cathode humidification unit model to calculate a new degradation factor. The cathode humidification unit model uses the degradation factor in the performance of the cathode humidification unit.
US09502718B2	Metal oxygen battery containing oxygen storage materials A method of storing oxygen in a cathode including an oxygen storage metal-organic framework (“MOF”) material comprising a mixture of ionic conductive material, electron conductive material and catalyst material within the MOF.
US09502717B2	Air electrode catalyst This invention proposes metal complexes of polyphenylenediamines as the precursors of carbonized materials used as the air electrode catalysts. Method of production includes mixing phenylenediamine monomer with a catalyst carrier in a solvent, and adding an oxidant with metal salt to produce a metal complex of polyphenylenediamine. After drying the precursor is heat treated in the temperature range 400 C.°-1000 C.° in nitrogen. Then the catalyst is leached and heat treated once again. In a modified procedure the heat treatment is carried out in air while leaching and subsequent thermal treatment are eliminated. The catalyst has demonstrated high performance and stability as the component of the air electrode of a metal-air battery.
US09502716B2	Robust platinum-copper catalysts Highly active and stable platinum-copper (PtCu) electrocatalysts are provided. The PtCu catalysts can be in the form of discrete, spherical PtCu nanoparticles that include a particle interior comprising platinum and copper, and a surface layer comprising platinum surrounding the particle interior. The PtCu nanoparticles can exhibit enhanced oxygen reduction reaction (ORR) activity as compared to other Pt-based catalysts for ORR. The PtCu nanoparticles are also active as electrocatalysts for the oxidation of small molecule organic compounds, including alcohols such as methanol and ethanol.
US09502714B2	Mixed metal oxide, electrode, and sodium secondary battery Disclosed is a mixed metal oxide comprising Na, M1, and M2, where M1 represents at least one element selected from the group consisting of Mg, Ca, Sr, and Ba; and M2 represents at least one element selected from the group consisting of Mn, Fe, Co, and Ni, wherein the molar ratio of Na:M1:M2 is a:b:1, where a is a value within the range of not less than 0.5 and less than 1; b is a value within the range of more than 0 and not more than 0.5; and “a+b” is a value within the range of more than 0.5 and not more than 1. An electrode having an active material containing the mixed metal oxide is also disclosed. Further disclosed is an electrode containing the electrode active material as well as a sodium secondary battery comprising the electrode as a positive electrode.
US09502710B2	Cell terminal seal system and method A battery module includes a hermetically sealed battery cell assembly. The battery cell assembly includes a housing and an electrochemical cell disposed in the housing. The battery cell assembly also includes a first battery terminal coupled to and extending away from the electrochemical cell and extending through a first opening in the housing. The first opening in the housing comprises a flange. The battery cell assembly further includes a sealing ring disposed around the flange to exert a compressive force for hermetically sealing the opening.
US09502709B2	Terminal structure for secondary battery and secondary battery A secondary battery in which the contact resistance is not increased even if the number of housed electrodes is increased is provided. Two screw holes 11d are formed in an opposed surface 11c of a terminal body portion 11b of a positive terminal 11 that faces the stacking direction. A projecting surface 11e is provided between the two screw holes 11d to project toward a positive pressing member 25 with respect to portions provided with the screw holes 11d. The projecting surface 11e projects toward the positive pressing member 25 by 0.2 mm with respect to the portions provided with the two screw holes 11d.
US09502708B2	Ohmically modulated battery A rechargeable battery whose ohmic resistance is modulated according to temperature is disclosed.
US09502706B2	Electric storage device An electric storage device includes a plurality of storage modules and a first storage-module busbar. The plurality of storage modules each include a storage-cell busbar and a plurality of storage cells. The storage-cell busbar includes a first storage-module terminal at a first end of the storage-cell busbar. The plurality of storage cells are electrically connected to each other with the storage-cell busbar. The first storage-module terminal provided in one of the plurality of storage modules is electrically connected to the first storage-module terminal provided in another of the plurality of storage modules with the first storage-module busbar. The first storage-module terminal includes a first stud bolt which extends through a bolt hole provided in the first storage-module busbar and to which a nut is fastened.
US09502701B1	Electronic device An electronic device includes a battery module, a casing and a latching mechanism. The battery module has at least one battery retention tab. A battery compartment is formed on the casing. The battery module is detachably installed in the battery compartment, and the casing has a stopping structure. The latching mechanism is slidably installed on the casing and includes a latching cover, a lock member and a resilient member. The latching cover is installed on the casing in a slidable manner. The lock member is pivoted to the latching cover. The resilient member is installed on the latching cover. When the latching cover slides to the lock position, the resilient member forces the lock member to engage with the stopping structure, so as to fix the latching cover in the lock position.
US09502700B2	Power train battery assembly of an electric, fuel-cell or hybrid vehicle A power train battery assembly of an electric, fuel-cell or hybrid vehicle, said assembly having a plurality of battery cells (16), each encased in an individual and externally-closed cell housing (18), that are combined into a cell stack and moreover having at least one pipe (36) conducting cooling fluid for the removal of heat energy from the battery cells (16). At least one heat-conducting fin (42) that originates from the pipe (36) flatly abuts, at least in sections, at least one cell housing (18).
US09502695B2	Molding packaging material A molding packaging material including a matte coat layer having excellent formability, chemical resistance, solvent resistance, and printability is provided. The molding packaging material 1 includes an outer base material 13 made of a heat-resistant resin, an inner sealant layer 16 made of a thermoplastic resin, a metal foil layer 11 arranged between the outer base material 13 and the inner sealant layer 16, and a matte coat layer 14 formed on one side of the outer base material opposite to the other side thereof to which the metal foil layer 11 is arranged. The matte coat layer 14 is made from a resin composition containing a base compound resin including a phenoxy resin and a urethane resin, a curing agent, and solid fine particles.
US09502693B2	Method of manufacturing organic light-emitting display apparatus Provided is a method of manufacturing an organic light-emitting display apparatus. The method includes: forming a passivation layer on a substrate, on which pixel electrodes are formed, to cover the pixel electrodes; forming a first exposure portion in the passivation layer to expose a first pixel electrode among the pixel electrodes; forming a first intermediate layer on the exposed first pixel electrode; filling the first exposure portion with the same material as the passivation layer; forming a second exposure portion in the passivation layer to expose a second pixel electrode among the pixel electrodes; forming a second intermediate layer on the exposed second pixel electrode; filling the second exposure portion with the same material as the passivation layer; forming a third exposure portion in the passivation layer to expose a third pixel electrode among the pixel electrodes; and forming a third intermediate layer on the exposed third pixel electrode.
US09502691B2	Organic light-emitting diode display panel and manufacturing method thereof An organic light-emitting diode (OLED) display panel and manufacturing method thereof. The method of manufacturing the OLED display panel comprises forming an anode (2), an organic light-emitting layer (3), a cathode (4) and a first optical coupling layer (5) sequentially on a substrate (1), and forming a second optical coupling layer (6) on a side, away from the cathode (4), of the first optical coupling layer (5) by arranging a plurality of protrusion structures with arc-shaped surfaces. Light that would be totally reflected from a surface of the first optical coupling layer are transmitted out through the protrusion structures with the arc-shaped surfaces of the second optical coupling layer, therefore the total reflection of the light is reduced, the light extraction efficiency is increased, and the external quantum efficiency of the device is improved.
US09502688B2	Organic light emitting display apparatus and method of manufacturing the same Provided are an organic light emitting display apparatus and a method of manufacturing the same. The organic light emitting display apparatus includes: a thin film transistor (TFT) substrate including a plurality of thin film transistors, an organic light-emissive device on the TFT substrate, and an encapsulation layer on the TFT substrate and the organic light-emissive device, the encapsulation layer being configured to cover the organic light-emissive device, the encapsulation layer including a hybrid material including: a block copolymer, and functionalized graphene.
US09502684B2	Organic electroluminescence device and method for manufacturing the same A highly reliable organic electroluminescence device and a manufacturing method includes at least one organic electroluminescence element, a structure, a to-be-covered portion and a passivation film. On a substrate, the organic electroluminescence element includes an anode, an organic layer including an organic light emitting layer, and a cathode. The structure is disposed on the substrate, and thickness of the structure is greater than that of the organic electroluminescence element. The to-be-covered portion is disposed at a step bottom portion of the structure and is formed such that the curvature radius of the cross-sectional shape of the to-be-covered portion at the step bottom portion is at least 0.3 micrometers. The passivation film covers the organic electroluminescence element, the structure and the to-be-covered portion.
US09502683B2	Sealing portion structure for display device A display device including a display substrate, the display substrate including an active area including a display unit that displays an image, a circuit area extending from the active area toward an exterior of the display device, and a cell seal area extending from the circuit area toward an exterior of the display device; an encapsulation substrate covering the display substrate; and a sealing portion between the display substrate and the encapsulation substrate, wherein the sealing portion includes a first sealing portion on the cell seal area, and a second sealing portion on the circuit area and extending from the first sealing portion.
US09502679B2	Light emitting device and method of manufacturing the same A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification.
US09502675B2	Methods for passivating a carbonic nanolayer Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer.
US09502671B2	Tridentate cyclometalated metal complexes with six-membered coordination rings Tridentate cyclometalated complexes with rigid six-membered coordination rings of General Formula I having tunable emission wavelengths in the visible range. These emitters are suitable for full color displays and lighting applications.
US09502669B2	Organic light emitting diode The present specification relates to an organic light emitting diode.
US09502666B2	Light-emitting element, light-emitting device, electronic device, and lighting device A light-emitting element emitting phosphorescence and having high emission efficiency, in which a property of injecting holes to a light-emitting layer is increased, is provided. The light-emitting layer of the light-emitting element includes a first organic compound represented by the following general formula (G1) and a second organic compound which is a phosphorescent compound. The difference between the HOMO level of the first organic compound and the HOMO level of the second organic compound is lower than or equal to 0.3 eV.
US09502665B2	Organic semiconductor material Compounds useful as organic semiconductor materials, and semiconductor devices containing such organic semiconductor materials are described.
US09502664B2	4H-imidazo[1,2-a]imidazoles for electronic applications The present invention relates to compounds of formula (I), a process for their production and their use in electronic devices, especially electroluminescent devices. When used as electron transport and/or host material for phosphorescent emitters in electroluminescent devices, the compounds of formula I may provide improved efficiency, stability, manufacturability, or spectral characteristics of electroluminescent devices.
US09502661B2	Amine derivative, organic electroluminescence material having the same and organic electroluminescence device using the material An amine derivative including a fluorine substituted aryl group is represented by compound (1) of the following Formula 1. wherein, each of Ar1 and Ar2 independently represents a substituted or unsubstituted aryl group or a substituted or unsubstituted heteroaryl group, L is a substituted or unsubstituted arylene group or a substituted or unsubstituted heteroarylene group, each of R1 and R2 independently represents a hydrogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkoxy group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted heteroaryl group, a is an integer satisfying 0≦a≦3, and at least one of Ar1 and Ar2 is substituted with at least one fluorine atom.
US09502660B2	Electronic device and compound The present invention relates to an electronic device comprising a compound according to formula 1 A-B (1) and wherein —Ar1 is a C6-C18 arylene, which can be monocyclic or polycyclic and may be optionally substituted by one or more C1-C10-alkyl or C3-C10-cycloalkyl groups, —Ar2 is a C6-C18 arene skeleton, optionally substituted with electron donating groups R4, —B1 and B2 are independently selected from B and Ar2, —B3 is independently selected from the same group as B, —R1, R2, R3 are independently selected from alkyl, arylalkyl, cycloalkyl, aryl, dialkylamino, - x is selected from 0, 1, 2 and 3, wherein for x>1 each Ar1 may be different, - y is a non-zero integer up to the overall count of valence sites on the arene skeleton, - z is a integer from zero up to the overall count of valence sites on the arene skeleton minus y; as well as a respective compound according to formula A-B.
US09502657B2	Organic electroluminescence device and manufacturing method thereof In an organic electroluminescence device (100), a hole transport layer (22) is formed of a cured resin obtained by a ring opening polymerization of a polymerizable compound (a) containing a ring opening polymerizable group in the presence of a polymerization initiator (b). In addition, both of a maximum peak height Rp and a maximum valley depth Rv in an upper surface of the hole transport layer (22) are less than or equal to 14 nm. Accordingly, an organic electroluminescence device having excellent mass productivity and high luminescent efficiency is realized.
US09502654B2	Method of manufacturing a multilayer semiconductor element, and a semiconductor element manufactured as such The present invention is directed to a method of manufacturing a multilayer semiconductor element. According to this method a first device layer is provided on a carrier by solution printing of a first material on the carrier. A second device layer is provided by solution printing of a second material solution on said first device layer; the second material solution comprising second device layer material dissolved in a solvent. Prior to solution printing of the second device layer, a barrier interlayer is added onto the first layer for being arranged in between said first and said second device layer. The barrier interlayer comprises an interlayer material insoluble to said solvent, and arranged for enabling electric interaction between the first and second device layer. The invention further provides a semiconductor element.
US09502652B2	Method of manufacturing EL display device A method of manufacturing an EL display device having a panel part includes a step of forming film of an element constituting the panel part, by using a vapor deposition equipment. The vapor deposition equipment is equipped with crucible configured to accommodate vapor deposition material, metal case configured to dispose the crucible therein, and heater configured to heat vapor deposition material in the crucible. Case includes container and lid. Container is configured to accommodate crucible with a gap between the container and crucible. Lid is configured to be removably attached to an opening of container, and includes a jetting port through which vapors of vapor deposition material jet out.
US09502646B2	Semiconductor integrated circuit device having encapsulation film and method of fabricating the same A semiconductor integrated circuit device and a method of fabricating the same are disclosed. The semiconductor integrated circuit device includes a resistive layer and an encapsulation film formed to surround an outer wall of the resistive layer. The encapsulation film contains an oxygen absorbing ingredient.
US09502645B2	Semiconductor device, related manufacturing method, and related electronic device A method for manufacturing a semiconductor device may include the following steps: preparing a substrate; preparing a first insulating layer on the substrate; preparing an electrode in the first insulating layer; preparing a second insulating layer on the first insulating layer; removing (e.g., using a dry etching process or a wet etching process) a portion of the second insulating layer to form a hole that at least partially exposes the electrode; providing a phase change material layer that may cover the electrode; and removing (e.g., using a sputtering process such as an argon sputtering process), a portion of the phase change material layer positioned inside the hole to form a phase change member that may expose a first portion of (a top side of) the electrode and may directly contact a second portion of (the top side of) the electrode.
US09502643B2	Semiconductor device, magnetic memory device, and method of fabricating the same A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.
US09502641B2	Double synthetic antiferromagnet using rare earth metals and transition metals A mechanism relates to magnetic random access memory (MRAM). A free magnetic layer is provided and first fixed layers are disposed above the free magnetic layer. Second fixed layers are disposed below the free magnetic layer. The first fixed layers and the second fixed layers both comprise a rare earth element.
US09502633B2	Method for current-controlling at least one piezoelectric actuator of a fuel injector of an internal combustion engine Method for controlling a piezoelectric actuator acting on valve elements to open or close a fuel injector respectively allowing or preventing fuel injection into a combustion chamber of an engine, the method includes: applying to the piezoelectric actuator a nominal electrical charge to open the injector, as a function of the torque required and the engine speed, to open the valve elements for fuel injection, thereafter applying to the actuator at least one electrical polarization charge, to polarize the actuator during an opening phase of the injector and fuel injection into the combustion chamber, thereafter commanding the closure of the injector by applying to the actuator at least one electrical discharge to close the valve elements, the step of applying the electrical polarization charge including a prior step of increasing the value of the charge current to a value greater than that of the nominal charge.
US09502630B1	Josephson junction readout for graphene-based single photon detector A detector for detecting single photons of infrared radiation. In one embodiment a waveguide configured to transmit infrared radiation is arranged to be adjacent a graphene sheet and configured so that evanescent waves from the waveguide overlap the graphene sheet. An infrared photon absorbed by the graphene sheet from the evanescent waves heats the graphene sheet. The graphene sheet is coupled to the weak link of a Josephson junction, and a constant bias current is driven through the Josephson junction, so that an increase in the temperature of the graphene sheet results in a decrease in the critical current of the Josephson junction and a voltage pulse in the voltage across the Josephson junction. The voltage pulse is detected by the pulse detector.
US09502623B1	Light emitting device A light emitting device includes a base structure, a wall, a light emitting element, a protection element, and a light reflective portion. The wall includes an inner peripheral surface defining an opening. The opening has a substantially polygonal shape in a planar view of the light emitting device. The light reflective portion has a maximum length which is longest in the light reflective portion. The maximum length is defined at a maximum-length position closest to the first corner among a plurality of positions defined in the light reflective portion. The light reflective portion has a minimum length which is shortest in the light reflective portion. The minimum length is defined at a minimum-length position arranged apart from the maximum-length position. The light reflective portion includes an inclined surface extending from the maximum-length position to the minimum-length position.
US09502621B2	High energy invisible light light emitting diode having safety indication The present invention includes a safety indication structure a high energy invisible light light emitting structure and two potential applying layers. The high energy invisible light light emitting structure includes a high energy invisible light light emitting layer that receives a forward to emit invisible light, and a P-type semiconductor layer and an N-type semiconductor layer respectively disposed at two sides of the high energy invisible light light emitting layer. The two potential applying layers are respectively in contact with the P-type semiconductor layer and the N-type semiconductor layer. The safety indication structure includes a photoluminescent light emitting layer disposed on the high energy invisible light light emitting structure. When the high energy invisible light light emitting structure emits invisible light, the photoluminescent light emitting layer absorbs and converts the invisible light to visible light, which serves as a signal warning for danger to ensure user safety.
US09502615B2	Light-emitting diode device A light-emitting element, includes a substrate; a first light-emitting stack formed on the substrate, including a triangular upper surface parallel to the substrate, and wherein the triangular upper surface has three sides and three vertexes; a first electrode formed on the first light-emitting stack and located near a first side of the three sides of the triangular upper surface; and a second electrode formed on the first light-emitting stack; including a second electrode pad near a first vertex of the three vertexes; and a second electrode extending part extending from the second electrode pad in two directions, disposed along other two sides of the three sides to surround the first electrode and stopping at the first side to form an opening.
US09502608B2	Method of manufacturing a light emitting device in which light emitting element and light transmissive member are directly bonded Provided is a light emitting device capable of reducing light attenuation within the element and having high light extraction efficiency, and a method of manufacturing the light emitting device. The light emitting device has a light emitting element having a light transmissive member and semiconductor stacked layer portion, electrodes disposed on the semiconductor stacked layer portion in this order. The light emitting element has a first region and a second region from the light transmissive member side. The light transmissive member has a third region and a fourth region from the light emitting element side. The first region has an irregular atomic arrangement compared with the second region. The third region has an irregular atomic arrangement compared with the fourth region. The first region and the third region are directly bonded.
US09502606B2	Nitride semiconductor ultraviolet light-emitting element A nitride semiconductor ultraviolet light-emitting element is provided with: an underlying structure portion including a sapphire (0001) substrate and an AlN layer formed on the substrate; and a light-emitting element structure portion including an n-type cladding layer of an n-type AlGaN based semiconductor layer, an active layer having an AlGaN based semiconductor layer, and a p-type cladding layer of a p-type AlGaN based semiconductor layer, formed on the underlying structure portion. The (0001) surface of the substrate is inclined at an off angle which is equal to or greater than 0.6° and is equal to or smaller than 3.0°, and an AlN molar fraction of the n-type cladding layer is equal to or higher than 50%.
US09502605B2	Method of fabricating semiconductor light emitting device A method of fabricating a semiconductor light emitting device includes forming a first conductivity type semiconductor layer, forming an active layer by alternately forming a plurality of quantum well layers and a plurality of quantum barrier layers on the first conductivity type semiconductor layer, and forming a second conductivity type semiconductor layer on the active layer. The plurality of quantum barrier layers include at least one first quantum barrier layer adjacent to the first conductivity type semiconductor layer and at least one second quantum barrier layer adjacent to the second conductivity type semiconductor layer. The forming of the active layer includes allowing the at least one first quantum barrier layer to be grown at a first temperature and allowing the at least one second quantum barrier layer to be grown at a second temperature lower than the first temperature.
US09502601B1	Metallization of solar cells with differentiated P-type and N-type region architectures Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region. Metallization methods, include etching techniques for forming a first and second conductive contact structure are also described.
US09502599B2	Semiconductor device, solid-state imaging device, and electric apparatus There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.
US09502598B2	Monolithic multiple solar cells A monolithic multiple solar cell includes at least three partial cells, with a semiconductor mirror placed between two partial cells. The aim of the invention is to improve the radiation stability of said solar cell. For this purpose, the semiconductor mirror has a high degree of reflection in at least one part of a spectral absorption area of the partial cell which is arranged above the semiconductor mirror and a high degree of transmission within the spectral absorption range of the partial cell arranged below the semiconductor mirror.
US09502597B2	Method for manufacturing a photovoltaic module with two etching steps P2 and P3 and corresponding photovoltaic module The invention relates to a method for manufacturing a photovoltaic module comprising a plurality of solar cells in a thin-layer structure, in which the following are consecutively formed: an electrode on the rear surface (41), a photovoltaic layer (46) obtained by depositing a layer (42) of precursors and by annealing such as to convert the precursors into a semiconductor material, and another semiconductor layer (43) in order to create a pn junction with the photovoltaic layer (46); characterized in that the layer (42) is deposited in a localized manner, such as to leave free at least one area (410) of the electrode on the rear surface (41) placed between two adjacent cells, wherein the annealing step modifies said area (410) which has higher resistivity than the rest of the electrode on the rear surface (41), such as to provide electric insulation between two adjacent cells.
US09502595B2	Methods and apparatus for improving micro-LED devices A μLED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.
US09502590B2	Photovoltaic devices with electroplated metal grids One embodiment of the present invention provides a solar cell. The solar cell includes a photovoltaic structure and a front-side metal grid situated above the photovoltaic structure. The front-side metal grid also includes one or more electroplated metal layers. The front-side metal grid includes one or more finger lines, and each end of a respective finger line is coupled to a corresponding end of an adjacent finger line via an additional metal line, thus ensuring that the respective finger line has no open end.
US09502588B2	Solar cell module A solar cell module comprises a solar cell and sealing material provided on the rear surface side of the solar cell. The sealing material includes a colored layer that reflects light from the light-receiving surface side of the solar cell, and a transparent layer that is provided between the colored layer and the solar cell. The transparent layer has, in a space between adjacent solar cells, a side surface raised along the rear surface-side corner portion of the solar cell.
US09502581B2	Non-volatile floating gate memory cells A storage transistor for non-volatile memory can be fabricated to create controlled sharp polycrystalline silicon (polysilicon) edges. The edges concentrate the electric field in the storage transistor and are used to enhance tunneling between layers of polysilicon for both program and erase operations. The storage transistor includes first and second polysilicon layers and a tunneling dielectric layer between the first and second polysilicon layers, and the second polysilicon layer includes at least a first edge extending towards the first polysilicon layer.
US09502580B2	Semiconductor device and method for manufacturing the same A highly reliable semiconductor device exhibiting stable electrical characteristics is provided. Further, a highly reliable semiconductor device is provided. Oxide semiconductor films are stacked so that the conduction band has a well-shaped structure. A second oxide semiconductor film having a crystalline structure is provided over the first oxide semiconductor film and a third oxide semiconductor film is provided over the second oxide semiconductor film. The bottom of a conduction band in the second oxide semiconductor film is deeper from a vacuum level than the bottom of a conduction band in the first oxide semiconductor film and the bottom of a conduction band in the third oxide semiconductor film.
US09502579B2	Thin film transistor substrate A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.
US09502574B2	Thin film transistor and manufacturing method thereof A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source region and drain region formed by doping both sides of the first semiconductor layer and the second semiconductor layer with impurities, and the source region includes a first source layer on the same plane as the first semiconductor layer and a second source layer on the same plane as the second semiconductor layer, and the drain region includes a first drain layer on the same plane as the first semiconductor layer and a second drain layer on the same plane as the second semiconductor layer, and only one of the first semiconductor layer and the second semiconductor layer is a transistor channel layer.
US09502572B2	Bottom-gate transistor including an oxide semiconductor layer contacting an oxygen-rich insulating layer A highly reliable semiconductor device which includes a transistor including an oxide semiconductor is provided. In a semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a stacked layer of an insulating layer and a metal film is provided in contact with the oxide semiconductor layer. Oxygen doping treatment is performed in a manner such that oxygen is introduced into the insulating layer and the metal film from a position above the metal film. Thus, a region containing oxygen in excess of the stoichiometric composition is formed in the insulating layer, and the metal film is oxidized to form a metal oxide film. Further, resistivity of the metal oxide film is greater than or equal to 1×1010 Ωm and less than or equal to 1×1019 Ωm.
US09502571B2	Thin film layer and manufacturing method thereof, substrate for display and liquid crystal display A thin film layer and manufacturing method thereof, a substrate for display and a liquid crystal display are provided. The embodiments according to the present invention can solve the problem that the gradient at the edge of the thin film layer produced with current methods is too steep or perpendicular, thus the thin film layer deposited in the next step easily has step coverage defect or even breakage. The thin film layer of the embodiments of the present invention comprises a plurality of sub-layers with different densities, wherein, the density of an upper sub-layer is smaller than that of a lower sub-layer. The yield and reliability of the thin film transistor and the thin film transistor liquid crystal display produced with the thin film layer of the embodiments of the present invention are high.
US09502561B1	Semiconductor devices and methods of forming the same An embodiment is a semiconductor device, comprising: a substrate; a plurality of fin structures disposed on the substrate; a plurality of first strained materials disposed on each of the plurality of the fin structures; a plurality of cap layers individually formed on each of the plurality of first strained materials, wherein at least two cap layers are connected to each other; a second strained material disposed on the at least two cap layers which are connected to each other.
US09502560B2	Semiconductor device and method of manufacturing the same Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a substrate having a well formed therein, the well including a first section and a second section, wherein the first section has a lower doping concentration and is closer to a surface of the substrate than the second section; a fin structure formed on the surface of the substrate; an isolation layer formed on the surface of the substrate, wherein the isolation layer exposes a portion of the fin structure, which serves as a fin for the semiconductor device; a gate stack formed on the isolation layer and intersecting the fin, wherein a Punch-Through Stopper (PTS) is formed in only a region directly under a portion of the fin where the fin intersects the gate stack.
US09502556B2	Integrated fabrication of semiconductor devices In a method for manufacturing a semiconductor device, a substrate including a gate structure is provided. A source region and a drain region are formed at opposing sides of the gate structure and an implant region for a resistor device is formed in the substrate. Pocket implant regions are formed in the source region and the drain region. A dielectric layer is formed to cover the gate structure and the substrate. A portion of dopants in the pocket implant regions interact with portions of dopants in the source region and the drain region to form lightly doped drain regions above the pocket implant regions. A resistor region of the resistor device is defined on the implant region. A portion of the dielectric layer is removed to form a spacer on a sidewall of the gate structure and a resistor protection dielectric layer on a portion of the implant region.
US09502555B2	Semiconductor device and fabricating method thereof A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes: a substrate comprising a trench; a first electrode disposed below the trench; a second electrode disposed above the trench, a first insulating layer being disposed between the first electrode and the second electrode; a first contact arranged in a first direction of the substrate and connected to the first electrode; and a second contact arranged in second direction that is different from the first direction, the second contact being connected to the second electrode.
US09502554B2	High frequency switching MOSFETs with low output capacitance using a depletable P-shield Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
US09502553B2	Semiconductor device and method for manufacturing the same In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side of the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first well, the second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.
US09502551B2	Nitride semiconductor transistor device A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alxα1-xN layer (α includes Ga or In, and 0
US09502549B2	Nitride semiconductor device A nitride semiconductor device includes the followings. A semiconductor multilayer structure is above a substrate and includes a first nitride semiconductor layer and a second nitride semiconductor layer. A source electrode, a drain electrode, and a gate electrode are on the semiconductor multilayer structure. A gate wiring line transmits a gate driving signal to gate electrodes. A first shield structure is on the semiconductor multilayer structure between the drain electrode and the gate electrode or between the drain electrode and the gate wiring line in a non-channel region where an actual current path from the drain electrode to the source electrode is not formed in the semiconductor multilayer structure. The first shield structure is a normally-off structure, suppresses a current flowing from the semiconductor multilayer structure, and is set to have a substantially same potential as a potential of the source electrode.
US09502541B2	Forming fins on the sidewalls of a sacrificial fin to form a FinFET A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.
US09502539B2	FINFET device having a channel defined in a diamond-like shape semiconductor structure The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
US09502531B2	Semiconductor device having fin-type field effect transistor and method of manufacturing the same A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate electrode in the first region, the first fin structure having a first buffer pattern, a second buffer pattern, and a first channel pattern which are sequentially stacked on the substrate, and a second MOS transistor including a second fin structure and a second gate electrode in the second region, the second fin structure having a third buffer pattern and a second channel pattern which are sequentially stacked on the substrate. Related fabrication methods are also discussed.
US09502529B2	Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
US09502528B2	Borderless contact formation through metal-recess dual cap integration An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).
US09502521B2	Multi-layer charge trap silicon nitride/oxynitride layer engineering with interface region control A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.
US09502520B2	Method for producing semiconductor device and semiconductor device A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a side wall formed of a fifth insulating film around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a sixth insulating film, forming a third resist for forming a contact hole on the pillar-shaped semiconductor layer, etching the sixth insulating film to form a contact hole on the pillar-shaped semiconductor layer, removing the third resist, depositing a second gate insulating film, depositing a second metal, etching back the second metal, removing the second gate insulating film on the pillar-shaped semiconductor layer so as to form a metal side wall on a side wall of an upper portion of the pillar-shaped semiconductor layer, and depositing a third metal so as to form a contact that connects an upper portion of the metal side wall to an upper portion of the pillar-shaped semiconductor layer.
US09502516B2	Recessed access devices and gate electrodes Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.
US09502512B2	Trench power metal oxide semiconductor field effect transistor and edge terminal structure including an L-shaped electric plate capable of raising a breakdown voltage An edge terminal structure of a trench power semiconductor device includes a first conductive-type substrate, a first conductive-type epitaxial layer thereon, a first electrode on a surface of the first conductive-type epitaxial layer, a second electrode on a back of the first conductive-type substrate, a first and a second field plates. The trench power semiconductor device includes an active area and an edge terminal area. A trench is in the surface of the first conductive-type epitaxial layer. The first field plate includes an L-shaped electric-plate, a gate insulation layer below the L-shaped electric-plate, and the first electrode on the L-shaped electric-plate. The second field plate includes a portion of the first electrode and an insulation layer between the portion of the first electrode and the first conductive-type epitaxial layer. The insulation layer covers the tail of the trench and completely covers the L-shaped electric-plate.
US09502509B2	Stress relieving semiconductor layer A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
US09502507B1	Methods of forming strained channel regions on FinFET devices One illustrative method disclosed herein includes, among other things, removing at least a portion of a vertical height of portions of an overall fin structure that are not covered by a gate structure so as to result in the definition of a fin cavity in a layer of insulating material and the definition of a remaining portion of the overall fin structure that is positioned under the gate structure, wherein the remaining portion comprises a channel portion and a lower portion located under the channel portion. The method continues with the formation of a first semiconductor material within at least the fin cavity and the formation of a second semiconductor material on the first semiconductor material and on exposed edges of the channel portion.
US09502505B2	Method and structure of making enhanced UTBB FDSOI devices An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.
US09502501B2	Lateral field effect transistor device A lateral field effect transistor device has a plurality of source and drain cells. Each source cell has a central semiconductor source region, and each drain cell has a central semiconductor drain region. The device has a first metallic conductive path which extends from a source electrode to join the source regions, thereby connecting the source cells in series to the source electrode. The device has a second metallic conductive path which extends from a drain electrode to join the drain regions, thereby connecting the drain cells in series to the drain electrode. The device has a gate path which extends from a gate electrode around the edges of the cells to form boundaries between neighboring source and drain cells, thereby forming respective field effect transistors between the source and drain regions of neighboring cells. The source cells and drain cells tessellate to cover an area of the device.
US09502499B2	Semiconductor device structure having multi-layered isolation trench structures A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first trench between a first active region and a second active region of the substrate. The semiconductor device structure includes an isolation structure in the first trench. The isolation structure includes a liner layer, an insulating layer, and an isolation layer. The liner layer covers an inner wall and a bottom surface of the first trench. The insulating layer covers the liner layer and has a second trench in the first trench. The isolation layer is over the insulating layer and fills the second trench. A first thickness of the insulating layer is greater than a second thickness of the liner layer.
US09502497B2	Method for preparing power diode A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a terminal protecting ring; forming an oxide layer (30), knot-pushing to the terminal protecting ring; forming a gate oxide layer (60), depositing a poly-silicon layer (70) on the gate oxide layer (60); depositing a SiO2 layer (80) on the surface of the poly-silicon layer (70) and a oxide layer (50); forming a N type heavy doped region (92); forming a P+ region; removing a photoresist, implanting P type ions using the SiO2 layer (80) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (70), the gate oxide layer (60) being etched, and removing the SiO2 layer (80); and processing a front surface metallization and a back surface metallization treatment. According to the method for preparing the power diode, by adjusting the isotropy etching level of the SiO2 layer and the ion implanting dose and energy, the threshold voltage of a DMOS structure can be adjusted, and the adjustment of the forward voltage drop for the device can be achieved.
US09502496B2	Semiconductor device and method of manufacturing the same A semiconductor device includes a vertical trench gate element portion and a lateral n-channel element portion for control which includes a well diffusion region, and a junction edge termination region which surrounds the vertical trench gate element portion and the lateral n-channel element portion for control. The junction edge termination region includes an oxide layer, a sustain region in contact with a trench provided at the end, and a diffusion region in contact with the sustain region. The diffusion region is deeper than the base region and has low concentration. The sustain region is shallower than the diffusion region and has high concentration. The well diffusion region is deeper than the base region and the sustain region and has low concentration. The breakdown voltage of the junction edge termination region and the well diffusion region is higher than that of the vertical trench gate element portion.
US09502491B2	Embedded sheet capacitor A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.
US09502487B2	Organic electroluminescent device and repairing method thereof An organic electroluminescent device includes a substrate including a plurality of pixel regions each having a light emission region and an element region; a plurality of thin film transistors (TFTs) including at least one switching TFT and at least one driving TFT in each element region; a planarization layer on the plurality of TFTs; a first electrode on the planarization layer and including first to third portions connected to one another, wherein the first and second portions are at each pixel region, and the third portion is at a neighboring pixel region; an organic light emitting layer on the first electrode; and a second electrode on the organic light emitting layer, wherein an end of the third portion overlaps the driving TFT of the neighboring pixel region.
US09502485B2	Organic light-emitting diode display having light-blocking portions of black matrix with differing light transmittances Organic light-emitting diode (OLED) displays and methods of manufacturing OLD displays are disclosed. In one aspect, an OLED display includes a substrate having an emission area and a non-emission area, a pixel electrode formed in the emission area, and an intermediate layer formed over the pixel electrode and including an organic emission layer. The display also includes an opposite electrode formed in the emission and non-emission areas and at least partially covering the intermediate layer. The display further includes a black matrix formed over the opposite electrode and including a first light-blocking portion formed in the non-emission area and a second light-blocking portion formed in the emission area and having light transmittance greater than that of the first light-blocking portion.
US09502484B2	Thin-film transistor substrate, related light-emitting apparatus, and related manufacturing method A thin-film transistor substrate may include an electrical wiring structure that includes a first electrode, which may be a source electrode, a drain electrode, or a capacitor electrode. The thin-film transistor substrate may further include a first insulating layer that directly contacts a first side of the first electrode. The thin-film transistor substrate may further include a second insulating layer that directly contacts a second side of the first electrode opposite the first side of the first electrode. The thin-film transistor substrate may further include a first filling layer that is disposed between the first insulating layer and the second insulating layer.
US09502483B2	Light-emitting device There is provided an EL light-emitting device with less uneven brightness. When a drain current of a plurality of current controlling TFTs is Id, a mobility is μ, a gate capacitance per unit area is Co, a maximum gate voltage is Vgs(max), a channel width is W, a channel length is L, an average value of a threshold voltage is Vth, a deviation from the average value of the threshold voltage is ΔVth, and a difference in emission brightness of a plurality of EL elements is within a range of ±n %, a semiconductor display device is characterized in that A = 2 ⁢ ⁢ Id μ * C 0 A ( Vgs ( max ) - Vth ) 2 ≦ W L ≦ ( 1 + n 100 - 1 ) 2 * A Δ ⁢ ⁢ Vth 2  Δ ⁢ ⁢ Vth  ≦ ( 1 + n 100 - 1 ) * A * L / W .
US09502479B2	Transparent display device and manufacturing method thereof Embodiments of the present invention relate to a transparent display device and a manufacturing method thereof. A display region of the transparent display device includes light a transmission area (12) and a light shield area (11). At least one silicon solar cell is disposed in a partial area of the light transmission area (12). The silicon solar cell is configured to absorb optical energy in the direction perpendicular to the light transmission direction of the light transmission area (12) and convert the optical energy into electric energy.
US09502478B2	Organic matter vapor deposition device and organic light emitting display manufactured thereby An organic material deposition device configured to sense a deposition amount of an organic material deposited in a vacuum chamber by detecting a back propagation characteristic variation of a passive radio frequency identification (RFID) sensor. The organic material deposition device includes: a chamber configured to perform an organic material deposition process therein; a deposition source mounted in the chamber to vaporize an organic material; a deposition mask mounted to face the deposition source and configured to bond a substrate at an opposite side to the deposition source; an antenna mounted in the chamber to receive back propagation from a radio frequency identification (RFID) sensor; and a radio frequency (RF) reader connected to the antenna to measure an organic material deposition amount from a variation of the back propagation.
US09502476B2	Structure of pixel A pixel structure in an organic light emitting display panel includes a plurality of pixels. Each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Lengths of the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged along a first direction. Widths of the first sub-pixel, the second sub-pixel, and the third sub-pixel is arranged along a second direction. A length of the first sub-pixel is greater than a length of the second sub-pixel along the first direction and a length of the third sub-pixel along the first direction. The first sub-pixel, the second sub-pixel, and the third sub-pixel are orderly arranged along the second direction.
US09502474B2	Method of fabricating organic electroluminescent device A method of fabricating an organic electroluminescent display includes: forming a plastic layer on a substrate including a first pixel region; patterning the first plastic layer to form a first opening in the first pixel region; forming a first organic light emitting layer on the first plastic layer having the first opening; and removing the first plastic layer from the substrate to form a first organic light emitting pattern in the first opening.
US09502472B2	Image sensor and method of manufacturing the same An image sensor and a method of manufacturing the same. The image sensor includes a plurality of photoelectric conversion units that are horizontally arranged and selectively emit electric signals by absorbing color beams.
US09502471B1	Multi tier three-dimensional memory devices including vertically shared bit lines A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.
US09502470B2	Semiconductor memory device and method for manufacturing same According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films.
US09502468B2	Nonvolatile memory device having a gate coupled to resistors A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.
US09502467B2	Semiconductor device and method of manufacturing the same A semiconductor device includes: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.
US09502466B1	Dummy bottom electrode in interconnect to reduce CMP dishing The present disclosure relates an integrated circuit (IC). The IC comprises a plurality of lower metal lines disposed within a lower inter-layer dielectric (ILD) layer over the substrate. The IC further comprises a plurality of memory cells disposed over the ILD layer and the lower metal lines at a memory region, a memory cell comprising a top electrode and a bottom electrode separated by a resistance switching element. The IC further comprises a dummy structure arranged directly above a first lower metal line at a logic region adjacent to the memory region, comprising a dummy bottom electrode and a dielectric mask on the dummy bottom electrode. The IC further comprises a top etch stop layer disposed on a bottom etch stop layer and extending upwardly along sidewalls of the dummy structure and overlying an upper surface of the dummy structure.
US09502461B2	Methods of fabricating camera module and spacer of a lens structure in the camera module A camera module and a fabrication method thereof are provided. The camera module includes a lens structure and an image sensor device chip disposed under the lens structure. The lens structure includes a transparent substrate and a lens disposed on the transparent substrate. A spacer is disposed on the transparent substrate to surround the lens, wherein the spacer contains a base pattern and a dry film photoresist. The method includes forming a base pattern on a carrier and attaching a dry film photoresist on the carrier. The dry film photoresist is planarized by a lamination process and then patterned to form a spacer. A transparent substrate having a plurality of lenses is provided. The spacer is stripped from the carrier, attaching on the transparent substrate to surround each of the lenses, and then bonded with image sensor device chips.
US09502460B2	Photoelectric conversion element and method of manufacturing the same A method of manufacturing a photoelectric conversion element including a step of forming a layer containing an organic material and particles dispersed in the organic material on a member including a photoelectric conversion portion and a step of roughening a surface of the layer by dry etching.
US09502459B2	Image pickup device, method of manufacturing image pickup device, and electronic apparatus An image pickup device includes: a photodiode provided in a silicon substrate, and configured to generate electric charge corresponding to an amount of received light, by performing photoelectric conversion; and a transfer transistor provided at an epitaxial layer on the silicon substrate, and configured to transfer the electric charge generated in the photodiode, wherein the transfer transistor includes a gate electrode and a channel region, the gate electrode being embedded in the epitaxial layer, and the channel region surrounding the gate electrode, and the channel region has, in a thickness direction, a concentration gradient in which a curvature of a potential gradient is free from a mixture of plus and minus signs.
US09502458B2	Circuit for generating direct timing histogram data in response to photon detection A sensor pixel detects a photon and outputs a first voltage proportional to a time of arrival of the detected photon. This voltage is converted to a multi-bit digital signal in the format of a thermometer code. A number of counter circuits, one counter circuit per bit of the multi-bit digital signal, are provided to accumulate the thermometer coded outputs. Each counter is configured to increment in response to an active logic state of the corresponding bit of the multi-bit digital signal. Accumulated count values in the counter circuits provide a timing histogram with respect to photon detection.
US09502456B2	Electronic component device An electronic component device includes a first electronic component on which a first electrode pad is disposed, a second electronic component on which a second electrode pad having a first pad portion and a second pad portion is disposed, a first bonding wire having one end connected to the first electrode pad and the other end connected to the first pad portion, and a second bonding wire having one end connected to a connection portion between the first pad portion and the first bonding wire and the other end connected to the second pad portion. The second electrode pad is disposed on the second electronic component so that the first pad portion and the second pad portion are laid along a direction intersecting with an extending direction of the first bonding wire. The extending direction of the first bonding wire intersects with an extending direction of the second bonding wire.
US09502451B2	Imaging device having electrode overlying photoelectric conversion layer and having electrical contact to electrode An imaging device includes a plurality of pixels arranged in a pixel region, each of the plurality of pixels including a photoelectric conversion element including a first electrode provided above a substrate, a second electrode provided above the first electrode and a photoelectric conversion layer provided between the first electrode and the second electrode, an interconnection layer provided between the substrate and the first electrode, the interconnection layer including a first conductive member extending in a first direction, and a second conductive member arranged at a level lower than the first conductive member and extending in a second direction intersecting the first direction, a first contact portion provided in the pixel region, the first contact portion electrically connecting the second electrode and the first conductive member, and a second contact portion electrically connecting the first conductive member and the second conductive member.
US09502450B2	Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic device The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate 12 and multiple photoelectric converters 40 that are formed on the substrate 12, an insulating film 21 forms an embedded element separating unit 19. The element separating unit 19 is configured of an insulating film 20 having a fixed charge that is formed so as to coat the inner wall face of a groove portion 30, within the groove portion 30 which is formed in the depth direction from the light input side of the substrate 12.
US09502447B2	Array substrate and manufacturing method thereof, display device An array substrate comprises a base substrate, a gate line, a data line and a thin film transistor arranged in an array on the base substrate, a pixel electrode and a passivation layer, the thin film transistor include a gate electrode, an active layer, a source electrode and a drain electrode, and the pixel electrode and the active layer, the drain are disposed in a same layer and formed integrally. A display device comprising the array substrate and a manufacturing method of the array substrate are further disclosed.
US09502442B2	Thin film transistor array substrate and method of manufacturing the same A thin film transistor array substrate and a method of manufacturing the thin film transistor array substrate are provided. The thin film transistor array substrate may include: a substrate; a thin film transistor (TFT) including an active layer, a gate electrode, a source electrode, and a drain electrode on the substrate. The gate electrode may include a bottom gate electrode and a top gate electrode that covers upper and lateral surfaces of the bottom gate electrode.
US09502439B2	Array substrate and a display device An array substrate comprises a plurality of subpixels, each of the subpixels comprising: at least one thin film transistor, an organic resin layer, and uncontacted first pixel electrode and second pixel electrode arranged along the data line direction; the first pixel electrode extends to the above of a first gate line, the second pixel electrode extends to the above of a second gate line, the first gate line and the second gate line are adjacent to each other; the first pixel electrodes of two adjacent subpixels located at two sides of the first gate line are connected above the first gate line, the second pixel electrodes of two adjacent subpixels located at two sides of the second gate line are connected above the second gate line.
US09502438B2	Array substrate and manufacturing and repairing method thereof, display device An array substrate and manufacturing thereof are provided. The array substrate comprises gate lines, first data lines, second data lines and N×M pixel units defined by the gate lines intersecting with the first data lines and the second data lines. A repairing line for each column of the pixel units is provided for a region at which at least one row of pixel units are located. Projections of two ends of the repairing line on the substrate respectively overlap with regions at which the first data line and the second data line of the same column of pixel units are located, and the repairing line is isolated from the first data line and the second data line.
US09502435B2	Hybrid high electron mobility transistor and active matrix structure Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors.
US09502432B1	Semiconductor device comprising a slit insulating layer configured to pass through a stacked structure The semiconductor device may include a substrate including a trench. The semiconductor device may include an isolation layer formed in the trench and including an etch stop pattern. The semiconductor device may include a stacked structure disposed over the substrate. The semiconductor device may include a slit insulating layer passing through the stacked structure and including a first region extending in a first direction and a second region extending in a second direction intersecting with the first direction. An intersection region between the first region and the second region may pass through a portion of the isolation layer and come into contact with the etch stop pattern.
US09502431B2	Nonvolatile semiconductor memory device and method of manufacturing the same According to one embodiment, a memory device includes a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, . . . an n-th insulating layer, an n-th electrode layer, and an (n+1)-th insulating layer in a first direction perpendicular to a surface of a semiconductor substrate, where n is a natural number, an oxide semiconductor layer extending through the first to n-th electrode layers in the first direction, a second stacked layer structure provided between the first to n-th electrode layers and the oxide semiconductor layer, and including a charge storage layer which storages charges, and a area provided in the oxide semiconductor layer.
US09502425B2	Semiconductor device and method of manufacturing the same The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.
US09502423B2	Semiconductor device layout and method for forming the same A semiconductor includes a gate line having a first portion in a transistor region and a second portion in a decoupling capacitor region.
US09502415B2	Method for providing an NMOS device and a PMOS device on a silicon substrate and silicon substrate comprising an NMOS device and a PMOS device The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the pMOS region. Aspects also include devices formed using the method.
US09502414B2	Adjacent device isolation An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.
US09502409B2	Multi-gate semiconductor devices A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.
US09502406B1	Semiconductor device and method of fabricating the same Provided is a semiconductor device and method of fabricating the same. The device includes a substrate including a first region and a second region, a first gate pattern on the first region, a second gate pattern on the second region, and an interlayer insulating layer enclosing the first and second gate patterns. The first gate pattern including a first gate insulating layer and a first gate electrode, the second gate pattern including a second gate insulating layer and a second gate electrode, the first gate insulating layer is thicker than the second gate insulating layer, and a top width of the second gate pattern is larger than a bottom width thereof.
US09502405B1	Semiconductor device with authentication code A plurality of contact trenches are formed in a semiconductor structure. The plurality of contact trenches are formed with a contact opening width selected to result in improper contact trench formation in a random number of the plurality of contact trenches. Devices are formed from the semiconductor structure using the plurality of contact trenches, wherein devices formed with improperly formed contact trenches are defective and devices formed with properly formed contact trenches are not defective. One or more measurements are performed to determine which devices are defective and which devices are not defective. The results of the measuring step represent a unique authentication code for an integrated circuit in which the devices are formed. Advantageously, the unique authentication code represents a physically unclonable function.
US09502404B2	Epitaxial formation mechanisms of source and drain regions The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.
US09502399B1	Diode string circuit configurations with improved parasitic silicon-controlled rectifier (SCR) conduction during electrostatic discharge (ESD) events Diode string configurations are provided that employ one or more guard bars (GBARS) positioned adjacent an end diode structure of a diode string to create a parasitic silicon-controlled rectifier (SCR) coupling between the end diode structure and the guard bar/s that operates to discharge current of an ESD event through a lateral parasitic bipolar transistor of the SCR and away from the individual diodes of the diode string. One or more of the disclosed guard bars may be positioned adjacent to a diode on a first end of a diode string to create a lateral SCR coupling for ESD discharge away from all of the diodes in the diode string without requiring positioning of a last diode on an opposite end of the same diode string adjacent the first terminal diode.
US09502396B2	Air trench in packages incorporating hybrid bonding A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
US09502392B2	Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.
US09502382B2	Coplaner waveguide transition A coplanar waveguide transition includes a substrate, a first coplanar waveguide on a first side of the substrate, and a second coplanar waveguide on a second side of the substrate. The coplanar waveguide transition includes a first, a second, and a third via through the substrate electrically coupling the first coplanar waveguide to the second coplanar waveguide. The coplanar waveguide transition includes voids through the substrate between the first, second, and third vias and edges of the first coplanar waveguide and edges of the second coplanar waveguide.
US09502379B2	Super CMOS devices on a microelectronics system A low cost IC solution is disclosed in accordance with an embodiment to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.
US09502378B1	Printed circuit boards having blind vias, method of testing electric current flowing through blind via thereof and method of manufacturing semiconductor packages including the same A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. Semiconductor chips are disposed on the plurality of unit substrate regions, respectively. Conductive wires are formed to electrically connect connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips. The connection pads are electrically connected to the blind vias, and forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the unit substrate region.
US09502377B2	Semiconductor package and fabrication method thereof A semiconductor package is disclosed, which includes: a circuit board; a carrier disposed on the circuit board; an RF chip disposed on the carrier; a plurality of high level bonding wires electrically connecting electrode pads of the RF chip and the circuit board; and an encapsulant formed on the circuit board for encapsulating the carrier, the high level bonding wires and the RF chip. The present invention positions the RF chip at a high level so as to facilitate element arrangement and high frequency wiring on the circuit board, thereby achieving a highly integrated wireless SiP (System in Package) module.
US09502374B2	Automatic wire tail adjustment system for wire bonders A capillary is utilized to form the wedge wire bond comprised in a wire interconnection. A wire holding device is located above a wire clamp and the capillary to secure the wire while the wire clamp is open and not clamping onto the wire. The wire clamp and the capillary may be lifted relative to the wire in a direction away from the wedge wire bond and towards the wire holding device so as to pay out a length of wire from the capillary. At a predetermined height of the capillary, the wire clamp is closed to clamp onto the wire, and thereafter, the capillary and wire clamp may be moved further away from the wedge wire bond to cause the wire to break away from the wedge wire bond and to form the wire tail with a desired length extending from the capillary.
US09502372B1	Wafer-level packaging using wire bond wires in place of a redistribution layer An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.
US09502371B2	Methods of forming wire interconnect structures A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.
US09502357B2	Alignment mark formation method and semiconductor device According to one embodiment, at first, a first pattern is formed to an insulating film. Then, a first transparent film is formed on a region of the insulating film, which includes a position where the first pattern is formed. Thereafter, an opaque film which is opaque to light within a visible light region is formed on an entire surface of the insulating film. Then, a second transparent film is generated by selectively oxidizing part of the opaque film in contact with the first transparent film.
US09502356B1	Device and method with physical unclonable function A physical unclonable function device, an encryptable electronic device, and a process for fabricating the physical unclonable function device are described. In an implementation, a physical unclonable function device includes an integrated circuit device including an active layer, the active layer including an electrode array with multiple electrodes; and a physical unclonable function coating disposed on the active layer, wherein the physical unclonable function coating includes a physical unclonable material arranged in a random configuration.
US09502353B2	Semiconductor device having groove-shaped via-hole The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
US09502352B2	Semiconductor wiring patterns A semiconductor device includes a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate includes, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.
US09502350B1	Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.
US09502348B2	Semiconductor device and fabrication method thereof A method for forming a semiconductor device includes, sequentially, providing a substrate having a first region and a second region; forming a first dielectric layer on the substrate; forming a second dielectric layer having a plurality of first openings exposing portions of a top surface of the first dielectric layer; forming a first conductive layer in the first openings; etching the second dielectric layer and the first dielectric layer in the second region until the substrate is exposed to form a plurality of second openings; forming passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; and forming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer.
US09502345B2	Ball-grid-array package, electronic system and method of manufacture A multiple-chip-package (MCP) has multiple chip groups and multiple package terminal groups for electrical connections in the MCP. Semiconductor chips of the same chip group are electrically connected to the package terminals of the same package terminal group, while package terminals of different chip groups are electrically connected to the package terminals of different package terminal groups.
US09502344B2	Wafer level packaging of electronic device Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device.
US09502341B2	Printed circuit board and semiconductor package using the same Embodiments of the inventive aspect include a printed circuit board and a semiconductor package using the same. The semiconductor package includes a substrate having one or more connection pads, semiconductor chips mounted on the substrate, an underfill layer filling a region between the semiconductor chips and the substrate, and solder bumps electrically connecting the connection pads and the semiconductor chips in the underfill layer. The substrate includes void preventing patterns protruding on a top surface of the substrate under the underfill layer.
US09502339B2	Resin-encapsulated semiconductor device and its manufacturing method A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30) encapsulating the semiconductor chip (1), and lead terminals (21) electrically connected to the semiconductor chip (1) and including inner lead portion (21b) covered with the resin-encapsulating layer (30). The lead terminals (21) are made of copper or a copper alloy. The die pad (10) is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals (21).
US09502334B2	Method of making a semiconductor device package with dummy gate A semiconductor device package includes a first substrate, which has a lower substrate surface and an upper substrate surface. A conductive dummy gate structure is disposed over the upper substrate surface. An interconnect structure is disposed over the conductive dummy gate structure. The interconnect structure includes a plurality of metal layers disposed within a dielectric structure and at least one of the metal layers is electrically coupled to the conductive dummy gate structure. A conductive through-substrate via extends from the lower substrate surface to an underside of the conductive dummy gate structure and is electrically coupled to the conductive dummy gate structure.
US09502332B2	Nonvolatile memory device and a method for fabricating the same A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.
US09502331B2	Electric power converter with a spring member An electric power converter includes a semiconductor module, a cooling pipe, a pressing member and a supporting member. A pair of supporting wall portions is disposed so as to sandwich the semiconductor module, the cooling pipe, and the pressing member in an overlapping direction. A semiconductor element includes a small-sized semiconductor element, and a large-sized semiconductor element of which an outer shape is larger than that of the small-sized semiconductor element when projected onto a plane parallel to the overlapping direction. Within the semiconductor module, the large-sized semiconductor element is disposed closer to a connecting end portion side where a connecting portion of the pair of supporting wall portions are disposed than the small-sized semiconductor elements is.
US09502323B2	Method of forming encapsulated semiconductor device package Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.
US09502319B2	Driver integrated circuit chip and display device having the same A driver integrated circuit chip includes a plurality of monitoring bumps, a plurality of output bumps, a plurality of first inner wires electrically connected to the output bumps, a plurality of second inner wires, and a plurality of switching circuits are electrically connected to the second inner wires. Each of the second inner wires is electrically connected between an adjacent pair of monitoring bumps. Each of the switching circuits controls a connection between adjacent monitoring bumps.
US09502313B1	Polysilicon resistor formation in silicon-on-insulator replacement metal gate finFET processes A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over a buried oxide layer of a silicon-on-insulator substrate; forming a trench in the buried oxide layer; forming a polysilicon layer over the semiconductor fins and in the trench, the polysilicon layer having a depression corresponding to a location of the trench; forming an insulating layer over the polysilicon layer, and performing a planarizing operation to remove the insulating layer except for a portion of the insulating layer formed in the depression, thereby defining a protective island; patterning the polysilicon layer to define both a dummy gate structure over the fins and the polysilicon resistor; and etching the polysilicon layer to remove the dummy gate structure, wherein the protective island prevents the polysilicon resistor from being removed.
US09502311B2	Plasma protection diode for a HEMT device A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.
US09502302B2	Process for integrated circuit fabrication including a uniform depth tungsten recess technique Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.
US09502301B2	Fabrication methods for multi-layer semiconductor structures Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.
US09502300B2	MEMS device and fabrication method thereof The present disclosure provides a method for forming micro-electro-mechanical-system (MEMS) devices. The method includes providing a plurality of wafers; bonding a front surface of at least a first wafer onto a front surface of a second wafer; trimming an edge of and thinning the at least first wafer after the at least first wafer is bonded onto the second wafer; and bonding a first supporting plate onto a front surface of a third wafer. The method further includes thinning a back surface of the third wafer and forming alignment marks on a thinned back surface of the third wafer; bonding a second supporting plate onto the thinned back surface of the third wafer according to the alignment marks; and removing the first supporting plate and bonding the at least first wafer onto the third wafer according to the alignment marks to form a stack structure.
US09502299B2	Semiconductor memory A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
US09502298B2	Asymmetric cyclic deposition and etch process for epitaxial formation mechanisms of source and drain regions The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described uses Cl2 as an etchant during the epitaxial formation of the S/D regions. The mechanisms involve using an asymmetric cyclic deposition and etch (ACDE) process that forms a preparation layer enable epitaxial growth of the following epitaxial layer with transistor dopants. The mechanisms also involve soaking the surface of substrate with dopant-containing precursors to enable sufficient incorporation of transistor dopants during the epitaxial growth of the S/D regions. By using Cl2 as etchants, the mechanisms also enables high throughput of the epitaxial growth of the S/D regions.
US09502295B2	Protective film material for laser processing and wafer processing method using the protective film material A protective film material for protecting a surface of a wafer during a laser processing treatment contains a water soluble poly-N-vinyl acetamide. The protective film material is applied to the surface of the wafer which is then irradiated with a laser beam through the protective film material to perform a laser processing treatment. After the laser processing treatment, the protective film material is removed by washing with water.
US09502294B2	Method and system for wafer level singulation A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.
US09502288B2	Method of forming an interconnect structure An interconnect structure is provided that has improved electromigration resistance as well as methods of forming such an interconnect structure. The interconnect structure includes a composite M-MOx cap located at least on the upper surface of the Cu-containing material within the at least one opening. The composite M-MOx cap includes an upper region that is composed of the metal having a higher affinity for oxygen than copper and copper oxide and a lower region that is composed of a non-stoichiometric oxide of said metal.
US09502280B2	Two-step shallow trench isolation (STI) process Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.
US09502279B2	Installation fixture having a micro-grooved non-stick surface An apparatus and method adapted to mount an elastomer band in a mounting groove around a semiconductor substrate support used for supporting a semiconductor substrate in a plasma processing chamber, which includes an installation unit having a top ring, a clamp ring, and a base ring, and upon tightening of the top ring onto the base ring, the elastomer band is clamped between the clamp ring and the base ring, and a clamping surface adapted to release the elastomer band on at least one of a lower surface of the clamp ring and/or an upper surface of the base ring. A latch and release mechanism, which releases the elastomer band into the mounting groove by declamping the elastomer band from between the clamp ring and the base ring.
US09502277B2	Apparatus, in particular end effector An apparatus, in particular end effector, for receiving, transporting and/or positioning a wafer frame which is covered by a carrier film for carrying a wafer, has a holder which has vacuum nozzles for holding the wafer frame on the apparatus, and has a centering device which has at least one stop, which can engage in a cutout in the wafer frame, for centering the wafer frame. In order to precisely position the wafer frame, the holder has Bernoulli nozzles for holding and moving the wafer frame in the direction of the stop without contact, and the stop is mounted such that it can be adjusted against the movement direction generated by the Bernoulli nozzles from an initial position to a centering position, which differs from the initial position, for centering the wafer frame.
US09502276B2	System architecture for vacuum processing A system for processing substrates in plasma chambers, such that all substrates transport and loading/unloading operations are performed in atmospheric environment, but processing is performed in vacuum environment. The substrates are transported throughout the system on carriers. The system's chambers are arranged linearly, such that carriers move from one chamber directly to the next. A conveyor, placed above or below the system's chambers, returns the carriers to the system's entry area after processing is completed. Loading and unloading of substrates may be performed at one side of the system, or loading can be done at the entry side and unloading at the exit side.
US09502275B1	Service tunnel for use on capital equipment in semiconductor manufacturing and research fabs A system for processing substrates is provided, comprising: a wafer transport assembly that is configured to transport wafers to and from one or more process modules, the wafer transport assembly having at least one wafer transport module, wherein lateral sides of the at least one wafer transport module are configured to couple to the one or more process modules; a service floor defined below the wafer transport assembly, the service floor being defined at a height that is less than a height of a fabrication facility floor in which the system is disposed.
US09502269B2	Method and apparatus for cooling electonic components An apparatus for cooling electronic devices to be used in the vacuum of space is described. a window frame is provided as packaging for an electronic device having a substrate and a chip. The window frame includes an opening to allow a heat pipe to be in direct contact with a backside of the chip. The window frame is hermetically sealed to the backside of the chip. The window frame is also welded to a kovar ring located on the backside of the chip to provide a hermetic seal between the window frame and the substrate.
US09502267B1	Integrated circuit packaging system with support structure and method of manufacture thereof An integrated circuit packaging system, and a method of manufacture thereof, includes: a support structure having: an internal insulation layer having a hole, a device connection side, and a removal mark characteristic of a conductive seed layer removed at the device connection side, a first conductive pad in the hole at the device connection side, and an exterior insulation layer over the first conductive pad at the device connection side; an integrated circuit over the exterior insulation layer; and an encapsulation over the integrated circuit.
US09502265B1	Vertical gate all around (VGAA) transistors and methods of forming the same An embodiment method includes forming a nanowire extending upwards from a substrate, wherein the nanowire includes: a bottom semiconductor region; a middle semiconductor region over the bottom semiconductor region; and a top semiconductor region over the middle semiconductor region. The method also includes forming a dielectric layer around and extending over the nanowire and forming a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer using an implantation process. After forming the CMP-stop layer, the dielectric layer is planarized.
US09502263B2	UV assisted CVD AlN film for BEOL etch stop application Implementations described herein generally relate to methods for depositing etch stop layers, such as AlN layers, using UV assisted CVD. Methods disclosed herein generally include positioning a substrate in a process region of a process chamber; delivering an aluminum-containing precursor to the process region, the aluminum-containing precursor depositing an aluminum species onto the substrate; purging the process region of aluminum-containing precursor using an inert gas; delivering a UV responsive nitrogen-containing precursor to the process region, the UV responsive nitrogen-containing gas being activated using UV radiation to create nitrogen radicals, the nitrogen radicals reacting with the aluminum species to form an AlN layer; and purging the process region of UV responsive nitrogen-containing precursor using an inert gas.
US09502257B2	Non-volatile memory device having asymmetrical control gates surrounding a floating gate and manufacturing method thereof A non-volatile memory device and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a floating gate insulating layer and a floating gate disposed on a substrate, a dielectric layer formed perpendicular to the floating gate insulating layer and at two sides of the floating gate, and a first control gate at a first side of the dielectric layer distal from the floating gate and a second control gate at a second side of the dielectric layer distal from the floating gate, wherein the first control gate and the second control gate are connected to each other, and a second width of the second control gate is wider than a first width of the first control gate. A length of a control gate of a non-volatile memory device may be extended to effectively preventing the generation of leakage current when a control gate is off.
US09502255B2	Low-k damage repair and pore sealing agents with photosensitive end groups Methods of repairing damaged low-k dielectric films using UV-activated photosensitive organic compounds are described herein. Methods of sealing pores by exposing porous dielectric films to UV-activated large photosensitive organic compounds are also described. Methods also include mechanically reinforcing dielectric films using photosensitive organic compounds activated by UV radiation. Compounds include at least one photosensitive end group, such as an unsaturated bond or group with high ring strain.
US09502246B2	Methods of forming oxide semiconductor devices and methods of manufacturing display devices having oxide semiconductor devices A method of forming an oxide semiconductor device may be provided. In the method, a substrate comprising a first major surface and a second major surface that faces away from the first major surface may be provided. An oxide semiconductor device may be formed over the first major surface to provide an intermediate device, and the semiconductor device may comprise an oxide active layer. The intermediate device may be subjected to ultraviolet (UV) light (e.g., ultraviolet ray irradiation process) for a first period, and subjected to heat (e.g., thermal treatment process) for a second period. The first and second periods may at least partly overlap.
US09502243B2	Multi-orientation SOI substrates for co-integration of different conductivity type semiconductor devices A method of forming a semiconductor device that includes providing a base semiconductor substrate having a first orientation crystal plane, and forming an epitaxial oxide layer on the base semiconductor substrate. The epitaxial oxide layer has the first orientation crystal plane. A first semiconductor layer having a second orientation crystal plane is then bonded to the epitaxial oxide layer. A portion of the first semiconductor layer is removed to expose a second surface of the epitaxial oxide layer. A remaining portion of the first semiconductor layer is present on the first surface of the epitaxial oxide layer; and epitaxially forming a second semiconductor layer on the second surface of the epitaxial oxide layer, wherein the second semiconductor layer has a first orientation crystal plane.
US09502242B2	Indium gallium zinc oxide layers for thin film transistors Embodiments of the present disclosure generally provide a method and apparatus for forming an IGZO active layer within a thin film transistor (TFT) device. In one embodiment, a method is provided for forming an IGZO active layer on a dielectric surface using a PECVD deposition process. In one embodiment, a method is provided for pretreating and passivating the dielectric surface for receiving the PECVD formed IGZO layer. In another embodiment, a method is provided for treating a PECVD formed IGZO layer after depositing said layer. In another embodiment, a method is provided for forming a multi-layer or complex layering structure of IGZO, within a PECVD processing chamber, for optimizing TFT electrical characteristics such as carrier density, contact resistance, and gate dielectric interfacial properties. In yet another embodiment, a method is provided for forming integrated layers for a TFT including IGZO within an in-situ environment of a cluster tool.
US09502233B2	Method for manufacturing semiconductor device, method for processing substrate, substrate processing device and recording medium In order to extend the cycle of gas cleaning for a film-forming device, a method for manufacturing a semiconductor device includes: a substrate carry-in process for carrying a substrate into a processing chamber; a film forming process for laminating at least two types of films on the substrate in the processing chamber; a substrate carry-out process for carrying the film laminated substrate out from the processing chamber; an etching process for supplying an etching gas into the processing chamber while the substrate is not in the processing chamber after the substrate carry-out process. The etching process includes a first cleaning process for supplying a fluorine-containing gas activated by plasma excitation into the processing chamber as an etching gas; and a second cleaning process for supplying a fluorine-containing gas activated by heat into the processing chamber as an etching gas.
US09502232B2	Inhibiting diffusion of elements between material layers of a layered circuit structure Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.
US09502231B2	Photoresist layer and method A system and method for middle layers is provided. In an embodiment the middle layer comprises a floating component in order to form a floating region along a top surface of the middle layer after the middle layer has dispersed. The floating component may be a polymer with a floating group incorporated into the polymer. The floating group may comprise a fluorine atom.
US09502226B2	Sample collection in compact mass spectrometry systems Mass spectrometry systems include a core featuring an ion source, an ion trap, and an ion detector connected along a gas path, a pressure regulation subsystem connected to the gas path and configured to regulate a gas pressure in the gas path, a sample pre-concentrator connected to the gas path, where the sample pre-concentrator includes an adsorbent material, and a controller connected to the sample pre-concentrator, where during operation of the system, the controller is configured to heat sample particles adsorbed on the adsorbent material to desorb the particles from the adsorbent material and introduce the desorbed particles into the gas path, and a pressure difference between a gas pressure in the sample pre-concentrator and a gas pressure in at least one of the ion source, the ion trap, and the ion detector when the desorbed particles are introduced into the gas path is 50 mTorr or less.
US09502225B2	Integrated sample processing for electrospray ionization devices Methods, systems and devices that generate differential axial transport in a fluidic device having at least one fluidic sample separation flow channel and at least one ESI emitter in communication with the at least one sample separation flow channel. In response to the generated differential axial transport, the at least one target analyte contained in a sample reservoir in communication with the sample separation channel is selectively transported to the at least one ESI emitter while inhibiting transport of contaminant materials contained in the sample reservoir toward the at least one ESI emitter thereby preferentially directing analyte molecules out of the at least one ESI emitter. The methods, systems and devices are particularly suitable for use with a mass spectrometer.
US09502222B2	Integrated anode and activated reactive gas source for use in magnetron sputtering device The invention relates to an integrated anode and activated reactive gas source for use in a magnetron sputtering device and a magnetron sputtering device incorporating the same. The integrated anode and activated reactive gas source comprises a vessel having an interior conductive surface, comprising the anode, and an insulated outer body isolated from the chamber walls of the coating chamber. The vessel has a single opening with a circumference smaller that that of the vessel in communication with the coating chamber. Sputtering gas and reactive gas are coupled through an input into the vessel and through the single opening into the coating chamber. A plasma is ignited by the high density of electrons coming from the cathode and returning to the power supply through the anode. A relatively low anode voltage is sufficient to maintain a plasma of activated reactive gas to form stoichiometric dielectric coatings.
US09502221B2	Etch rate modeling and use thereof with multiple parameters for in-chamber and chamber-to-chamber matching A method includes receiving a voltage and current measured at an output of an RF generator of a first plasma system and calculating a first model etch rate based on the voltage and current, and a power. The method further includes receiving a voltage and current measured at an output of the RF generator of a second plasma system, determining a second model etch rate based on the voltage and current at the output of the RF generator of the second plasma system, and comparing the second model etch rate with the first model etch rate. The method includes adjusting a power at the output of the RF generator of the second plasma system to achieve the first model etch rate associated with the first plasma system upon determining that the second model etch rate does not match the first model etch rate. The method is executed by a processor.
US09502220B2	Plasma processing apparatus and plasma processing method A plasma processing apparatus that performs plasma processing on a substrate held on a transport carrier including an annular frame and a holding sheet. The apparatus includes: a process chamber; a plasma excitation device that generates plasma; a stage in the chamber; a cooling mechanism for cooling the stage; a cover that partly covers the holding sheet and the frame and has a window section through which the substrate is partly exposed to plasma; and a movement device that moves a relative position of the cover to the frame. The cover has a roof section, a cylindrical circumferential side section extending from a circumferential edge of the roof section toward the stage, and a correction member that protrudes from the roof section and/or the circumferential side section toward the frame and presses the frame onto the stage to correct warpage of the frame.
US09502219B2	Plasma processing method The present disclosure provides a method of performing a plasma processing on a substrate by using a plasma processing apparatus including a processing container; an outer upper electrode provided to face a lower electrode; an inner upper electrode disposed inside the outer upper electrode; a first high-frequency power supply; a first power feeding unit; a second power feeding unit; and a variable condenser. The first and second power feeding units, a fixed condenser formed between the outer upper electrode and the inner upper electrode, and a closed circuit including the variable condenser become a resonance state when the variable condenser has a capacitance value in a predetermined resonance region. The method includes selectively using a capacitance value in a first region lower than the resonance region of the variable condenser and a capacitance value in a second region higher than the resonance region to perform the plasma processing.
US09502217B2	Plasma processing apparatus and plasma processing method A plasma processing apparatus includes a processing chamber which plasma-processes a sample, a first high-frequency power supply which supplies first high-frequency power for plasma generation to the processing chamber, a second high-frequency power supply which supplies second high-frequency power to a sample stage on which the sample is placed and a pulse generation device which generate first pulses for time-modulating the first high-frequency power and second pulses for time-modulating the second high-frequency power. The pulse generation device includes a control device which controls the first and second pulses so that frequency of the first pulses is higher than frequency of the second pulses and the on-period of the second pulse is contained in the on-period of the first pulse.
US09502214B2	Method of cleaning the surface of a material coated with an organic substance and generator and device for carrying out said method An apparatus is provided that performs continuous cleaning of a surface of a grounded material which is coated with an organic substance. The apparatus includes a plurality of electrodes covered with a dielectric and disposed along the surface of the material. The electrodes are connected to a high-voltage generator using a MOS power transistor connected to a step up transformer to convert low-voltage pulses generated from a low-voltage power supply into high-voltage pulses. The apparatus is configured to provide a pulsed electric field wherein the maximum voltage of the positive pulses U+ is greater than the arc-striking voltage Ua, and the maximum absolute value of the voltage of the negative pulses U− is less than the striking voltage Ua.
US09502212B2	Charged particle beam apparatus An object of the present invention is to provide a method and an apparatus capable of measuring a potential of a sample surface by using a charged particle beam, or of detecting a compensation value of a variation in an apparatus condition which changes due to sample charging, by measuring a sample potential caused by irradiation with the charged particle beam. In order to achieve the object, a method and an apparatus are provided in which charged particle beams (2(a), 2(b)) emitted from a sample (23) are deflected by a charged particle deflector (33) in a state in which the sample (23) is irradiated with a charged particle beam (1), and information regarding a sample potential is detected by using a signal obtained at that time.
US09502209B2	Multi-step location specific process for substrate edge profile correction for GCIB system Disclosed are an apparatus, system, and method for scanning a substrate or other workpiece through a gas-cluster ion beam (GCIB), or any other type of ion beam. The workpiece scanning apparatus is configured to receive and hold a substrate for irradiation by the GCIB and to scan it through the GCIB in two directions using two movements: a reciprocating fast-scan movement, and a slow-scan movement. The slow-scan movement is actuated using a servo motor and a belt drive system, the belt drive system being configured to reduce the failure rate of the workpiece scanning apparatus.
US09502208B2	Charged particle beam apparatus, stage controlling method, and stage system A stage system includes a stage that holds an object, a linear motor mechanism that moves the stage by a thrust force generated by a current flowing through the coil, and a control section that controls the current flowing through the coil. The current flowing through the coil in a state where the stage is maintained in the static state be greater than a minimum current amount required for generating the thrust force greater than a maximum static friction force of the stage with respect to the guide rails.
US09502207B1	Cam actuated filament clamp An ion source filament clamp has a clamp member having first and second ends. The first end has one of a cam surface and a cam follower, and has first and second portions that are opposed to one another and separated by a slot having a lead opening defined therein to receive a lead of an ion source filament. An actuator pin extends along an actuator pin axis and has first and second sections. The first section is coupled to the first portion of the clamp member. The actuator pin extends through, and is in sliding engagement with, a thru-hole in the second portion of the clamp member. A cam member is operably coupled to the second section of the actuator pin. The cam member has a handle and the other of the cam surface and cam follower and is configured to rotate between a clamped position and an unclamped position. The cam follower slidingly contacts the cam surface. In the clamped position, the cam follower engages the cam surface in a first predetermined manner, thus selectively compressing the first and second portions of the clamp member toward one another and exerting a clamping pressure on the lead within the lead opening while inducing a spring tension between the first and second portions of the clamp member. In the unclamped position, the cam follower engages the cam surface in a second predetermined manner, wherein the spring tension extends the first and second portions of the clamp member apart from one another, therein releasing the clamping pressure on the lead within the lead opening.
US09502200B1	Low tolerance magnetic trip for a miniature circuit A trip assembly for a circuit breaker includes a trip lever and a trip actuator. The trip lever causes electrical contacts, which are in a closed position, to disengage from each other into an open position and interrupt current flow to a circuit, when tripped by the trip actuator due to an overcurrent condition. The trip actuator includes a bimetallic member, a yoke and an armature with an opening in which an end of the trip lever is latched in the closed position. The yoke includes a tab adjacent to the opening. When the trip lever is latched in the opening, the end of the trip lever includes first, second and third surfaces that contact a front surface of the armature, an interior surface of the armature defining the opening, and the tab of the yoke, respectively, to provide a consistent magnetic gap between the back side of the armature and the yoke.
US09502195B2	Switching device A switching device includes a contact system having a movable contact to be moved along a movement direction, a stationary contact and an improved arc quenching device with a configuration for generating a magnetic field formed in a plane perpendicular to the movement direction and an electrode configuration having a first electrode conductively connected to the movable contact and a second electrode conductively connected to the stationary contact. The first electrode and the second electrode are disposed in such a way that an electric field can be generated between the first electrode and the second electrode perpendicularly to the direction of movement and perpendicularly to the magnetic field.
US09502192B2	Surgical instruments with non-contact switch assemblies A non-contact button assembly for a powered surgical instrument includes a light emitter, a rocker switch, and a button shaft. The rocker switch defines a through passage about a longitudinal axis of the button assembly. The button shaft is disposed within the through passage. The button shaft includes a proximal portion, a distal portion, and a flange positioned therebetween. The button shaft has a deactivated position such that the button shaft is configured to prevent light from the light emitter from illuminating a light detector and the button shaft has an activated position such that the button shaft is configured to permit light emitted from the light emitter to illuminate the light detector.
US09502186B2	Electrochemical cell In an electrochemical cell including a cathode 7, an anode 6, electrolyte 10, a hollow container 1 accommodating these members, and terminals extending from the inside to the outside of the hollow container 1, the terminals include a plurality of inner terminals 5a formed on the inner surface of the hollow container 1, a cathode outer terminal 5b 1 formed on the outer surface of the hollow container 1, and an inner layer wire 5c formed on the inner layer of the hollow container 1 for commonly connecting the plurality of inner terminals 5a to the cathode outer terminal 5b1.
US09502182B2	Solar cell and method of manufacturing the same A solar cell is disclosed. The solar cell includes a transparent conductive layer formed on a substrate, microstructures protruding vertically aslant from a surface of the transparent conductive layer, an electron transport layer configured to cover the microstructures and formed of an electron transport metal oxide, a light absorber adhered to inner pores and a surface of the electron transport layer, a hole transport layer configured to cover the surface of the electron transport layer and formed of a hole transport material, and an electrode formed on the hole transport layer. In the solar cell, the thickness of a light absorption layer can be maximized to obtain a high current density and high photoelectric conversion efficiency.
US09502179B2	Metallized film and metallized film capacitor using same A metallized film composed of a dielectric film, a metal thin film layer and a dielectric layer, the metal thin film layer being formed on at least one surface of the dielectric film, the dielectric layer being formed on the metal thin film layer, and the dielectric layer being composed of acrylic acid ester resin as a main component being composed of dimethylol tricyclodecane diacrylate and monoacrylate containing a heterocycle.
US09502178B2	Monolithic capacitor A monolithic capacitor includes a laminated body including stacked dielectric layers and substantially in the shape of a rectangular parallelepiped, and including a first surface being a mounting surface, a second surface opposite to the first surface, opposing third and fourth surfaces orthogonal to the first and second surfaces, and opposing fifth and sixth surfaces orthogonal to the first to fourth surfaces; capacitor electrodes disposed in the laminated body and each including a capacitive portion and a lead portion extending therefrom to at least one surface of the laminated body, the capacitive portions facing each other with dielectric layers interposed therebetween; and first and second outer electrodes disposed on at least one surface of the laminated body and connected to the lead portions. A gap between the first surface and the capacitive portions is greater than a gap between the second surface and the capacitive portions.
US09502177B2	Multilayer ceramic capacitor and board having the same mounted thereon A multilayer ceramic capacitor may include: a ceramic body including dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other; an active layer configured to form capacitance by including first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween and alternately exposed to the first or second side surface; and a first external electrode disposed on the first side surface and electrically connected to the first internal electrodes and a second external electrode disposed on the second side surface and electrically connected to the second internal electrodes. When length of the ceramic body is L and length of the first and second external electrodes in the length direction of the ceramic body is L1, 0.2≦L1/L≦0.96 is satisfied.
US09502176B2	Contactless power supply transfer transformer A contactless power transfer transformer includes main body. The main body includes magnetic pole core members, winding wire core member, and wire. The winding wire core member is orthogonal to the magnetic pole core members and connects one portion of each of the pair of parallel magnetic pole core members with each other. The main body is fixed to fixing plate having a magnetic shield function and heat dissipation function. The connecting position of the winding wire core member with respect to the magnetic pole core members is located toward one side from a center in the longitudinal direction of the magnetic pole core members. At least a space between the pair of the magnetic coil core members each containing an end portion longer in distance to the connecting position is used as an arrangement space of component electrically connected to the electric wire.
US09502175B2	Circuit device A circuit device includes a semiconductor substrate, a first inductor provided over the semiconductor substrate, and a second inductor provided over the semiconductor substrate and coupled to the first inductor. The first inductor and second inductor are wound in a same direction with each other from respective inner end portions to respective outer end portions thereof.
US09502171B2	Inductor with thermally stable resistance An inductor includes an inductor body having a top surface and a first and second opposite end surfaces. There is a void through the inductor body between the first and second opposite end surfaces. A thermally stable resistive element positioned through the void and turned toward the top surface to forms surface mount terminals which can be used for Kelvin type sensing. Where the inductor body is formed of a ferrite, the inductor body includes a slot. The resistive element may be formed of a punched resistive strip and provide for a partial turn or multiple turns. The inductor may be formed of a distributed gap magnetic material formed around the resistive element. A method for manufacturing the inductor includes positioning an inductor body around a thermally stable resistive element such that terminals of the thermally stable resistive element extend from the inductor body.
US09502167B1	High temperature electromagnetic actuator An electromagnetic actuator includes a magnetic circuit that includes a stationary core having a first leg, a second leg and a connecting leg that connects the first and second legs, the stationary core being formed of a high temperature ferromagnetic material, and an armature formed of the high temperature ferromagnetic material. The actuator also includes one or more position returning members disposed between the stationary core and the armature and a first winding surrounding the first leg, the first winding being formed a metal wire with ceramic insulation.
US09502166B2	Variable-cycle permanent-magnet undulator A variable-period permanent-magnet undulator which is applicable not only to a planar undulator but also to a helical undulator, in which permanent-magnets and ferromagnetic substances are alternately arranged, and the ferromagnetic substance interposed between the permanent-magnets is saturated to thus enable the magnets to be effectively spaced apart from each other by the repulsive force between the permanent-magnets, thereby adjusting the period of the magnetic field in an easy and precise manner.
US09502165B2	Permanent magnet, motor, and generator A permanent magnet includes: a composition expressed by a composition formula: RpFeqMrCutCo100-p-q-r-t (R is at least one element selected from rare-earth elements, M is at least one element selected from Zr, Ti, and Hf, 10.5≦p≦12.5 at %, 23≦q≦40 at %, 0.88≦r≦4.5 at %, 4.5≦t≦10.7 at %); and a metal structure containing a Th2Zn17 crystal phase and a Cu-rich phase having a Cu concentration higher than that of the Th2Zn17 crystal phase. In a cross section including a c-axis of the Th2Zn17 crystal phase, a number of intersections of the Cu-rich phases existing in an area of 1 μm square is 10 or more.
US09502164B2	Permanent magnet, motor, and generator A permanent magnet includes: a composition expressed by a composition formula: RpFeqMrCutCo100-p-q-r-t (R is at least one element selected from rare-earth elements, M is at least one element selected from Zr, Ti, and Hf, 10.5≦p≦12.5 at %, 23≦q≦40 at %, 0.88≦r≦4.5 at %, 4.5≦t≦10.7 at %); and a metal structure containing a cell phase having a Th2Zn17 crystal phase, a cell wall phase, an M-rich platelet phase formed vertically to a c-axis of the Th2Zn17 crystal phase, and a Cu-rich platelet phase formed along the M-rich platelet phase.
US09502158B2	Connector Connector 1 comprising: a plurality of twisted-pair cables 6 each comprising two twisted wires 7, 8, each of said wires 7, 8 being connected to a terminal 23, 24; a plurality of cavity blocks 9, each of said cavity blocks 9 has two cavities 17, 18 for accommodating the terminals 23, 24 of one of said twisted-pair cables 6; a housing 3 having an accommodation chamber 10 for accommodating the plurality of said cavity blocks 9.
US09502152B2	Method of selective separation of semiconducting carbon nanotubes, dispersion of semiconducting carbon nanotubes, and electronic device including carbon nanotubes separated by using the method According to example embodiments, a method includes dispersing carbon nanotubes in a mixed solution containing a solvent, the carbon nanotubes, and a dispersant, the carbon nanotubes including semiconducting carbon nanotubes, the dispersant comprising a polythiophene derivative including a thiophene ring and a hydrocarbon sidechain linked to the thiophene ring. The hydrocarbon sidechain includes an alkyl group containing a carbon number of 7 or greater. The hydrocarbon sidechain may be regioregularly arranged, and the semiconducting carbon nanotubes are selectively separated from the mixed solution. An electronic device includes semiconducting carbon nanotubes and the foregoing described polythiophene derivative.
US09502151B2	Ink composition and circuit board and method for producing the same An ink composition and a circuit board and a method for producing the same are provided. The ink composition comprises: an acrylic resin; an epoxy resin; a polyester resin; a curing agent; and an active powder comprising a modified metal compound, in which the metal element of the modified metal compound is at least one selected from the group consisting of Zn, Cr, Co, Cu, Mn, Mo, and Ni.
US09502150B2	Graphene oxide polymer with nonlinear resistivity The invention relates generally to field grading materials and, more particularly, to field grading materials including graphene oxide, reduced graphene oxide, or both, exhibiting non-linear resistivity. In one embodiment, the invention provides a composite material comprising: a polymer material; and reduced graphene oxide distributed within the polymer material.
US09502144B2	Filter for a nuclear reactor containment ventilation system A wet filter for a nuclear reactor primary containment vent that employs an inclined manifold having a plurality of outlets that communicate through a first set of metal fiber filters submerged in a pool of water enclosed within a pressure vessel. A demister suspended above the pool of water to remove any entrained moisture in the filtered effluent before being passed through a second stage of higher density, dry, metal fiber filters connected to a second manifold that communicates with an outlet on the pressure vessel that is connected to an exhaust passage to the atmosphere.
US09502139B1	Fine grained online remapping to handle memory errors An error in a physical memory realization at a physical memory address is detected. A first physical memory line corresponding to the physical memory address is determined. It is ensured that a duplicate of data content associated with the first physical memory line is associated with a second physical memory line. The physical memory address is remapped to use the second physical memory line for data content.
US09502138B2	Data encoding in solid-state storage apparatus A method for encoding an input data block for storage in q-level cells of solid-state memory includes producing a preliminary block from the input data block by modulation encoding at least part of the input block into a first group of qary symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of qary symbols and any remainder of the input block not encoded via the first encoding scheme; generating parity data for the preliminary block via an error-correction encoding scheme; modulation encoding the parity data and any remainder of the input block into a second group of qary symbols via a second drift-tolerant encoding scheme; and supplying the qary symbols of the first and second groups for storage in respective q-level memory cells.
US09502118B2	NAND memory addressing Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).
US09502116B2	Nonvolatile semiconductor memory apparatus According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings. The memory strings include a first select transistor and a second select transistor, and are connected to each of a plurality of bit lines. The row decoder applies a voltage to the first and second select transistors. The controller detects a defect of the bit lines based on data read from the memory cells.
US09502113B2	Configurable non-volatile content addressable memory A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.
US09502108B2	Programming memory cells using a program pulse Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.
US09502105B2	Resistive memory device, operating method thereof, and system having the same A resistive memory device includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal and selecting the resistive memory cells, a read/write control circuit suitable for programming data to the memory cell array or reading data from the memory cell array, a voltage generator suitable for generating operation voltages and providing the operation voltages to the address decoder and a controller suitable for controlling the address decoder, the read/write control circuit, and the voltage generator to perform a write operation in response to a write command and a plurality of write data.
US09502102B1	MLC OTP operation with diode behavior in ZnO RRAM devices for 3D memory Providing for a memory cell capable of forming a one time programmable, multi-level cell two-terminal memory cell or a rewritable, two terminal memory cell is described herein. In some embodiments, one time programmable, multi-level cell two-terminal memory cell can exhibit diode-like characteristics. In other embodiments, the memory cell can comprise a first electrode layer configured to generate ions in response to an electric field applied to the memory cell; a resistive ion migration layer at least in part permeable to migration of the ions within the resistive ion migration layer; a second electrode layer; and a substrate layer comprising a silicon wafer.
US09502101B2	Two-part programming methods A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programming the first memory cell to the first level. After programming the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programming the second memory cell to the second level.
US09502100B2	Methods of operating sense amplifier circuits A method of maintaining a voltage level of a bit line of a sense amplifier circuit includes providing a power supply voltage at a power supply node, receiving the power supply voltage from the power supply node with an NMOS transistor, and maintaining a voltage level of the bit line by supplying sufficient current with the NMOS transistor to compensate a leakage current of the bit line. The method includes receiving the voltage level of the bit line with a noise threshold control circuit, inverting the voltage level with the noise threshold control circuit, and driving a sense amplifier output with the noise threshold control circuit.
US09502095B1	Memory system A memory system is disclosed, which relates to a technology for reducing current consumption needed to perform a refresh operation in a Dual In-line Memory Module. The memory system includes a memory module, which includes a volatile memory and a non-volatile memory, and a host configured to provide a refresh command to the memory module during the refresh operation. The memory module is configured to store cell characteristic information of the volatile memory in the non-volatile memory in an idle state, and control a refresh operation of the volatile memory in response to the cell characteristic information.
US09502094B2	Method for driving memory element To provide a memory element which keeps a stored logic state even without supply of power. To increase an effect of reducing power consumption by facilitating stop of supply of power to the memory element for a short time. Data (potential) held in a node in a logic circuit can be swiftly saved on a node where one of a source and a drain of the transistor and one electrode of the capacitor included in a memory circuit are connected by lowering a potential of the other electrode of a capacitor before a transistor is turned on. By making a potential of the other electrode of the capacitor when the transistor is in an off state higher than a potential of the other electrode of the capacitor when the transistor is in an on state, a potential of the node can be reliably held even without supply of power.
US09502092B2	Unipolar-switching perpendicular MRAM and method for using same MRAM devices that are switched by unipolar electron flow are described. Embodiments use arrays of cells that include a diode or transistor with a pMTJ. The switching between the high and low resistance states of the pMTJ is achieved by electron flow in the same direction, i.e. a unipolar flow. Embodiments of the invention include methods of operating unipolar MRAM devices that include a read step after a write step to verify the operation. Embodiments also include methods of operating unipolar MRAM devices that include an iterative stepped-voltage write process that includes a plurality of write-read steps that begin with a selected voltage for the write pulse for the first iteration and gradually increase the voltage for the write pulse for the next iteration until a successful read operation occurs.
US09502090B2	Memory device including a domain wall and ferromagnetic driver nanowire A memory device comprising a ferromagnetic data nanowire, a ferromagnetic driver nanowire, read element and/or a spaced write element positioned about the data nanowire, wherein driving a domain wall in the driver nanowire remotely drives a domain wall in the data nanowire past the read element and/or the write element.
US09502085B2	Memory buffers and modules supporting dynamic point-to-point connections A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.
US09502084B2	Semiconductor integrated circuit with data latch control A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal.
US09502083B2	Output buffer circuit with low sub-threshold leakage current A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. The cutting circuit is rendered non-conductive when each of the transistors in the first and second output circuits is rendered non-conductive.
US09502081B2	Internal voltage generating circuit for generating internal voltage according to temperature and process variation An internal voltage generation circuit may include a temperature information generation unit configured to generate a temperature code having a code value corresponding to a temperature. The temperature information generation unit may include a process variation information generation unit configured to generate a process code having a code value corresponding to a process variation. The temperature information generation unit may include a code combination unit configured to generate a combination code in response to a ratio control signal, the temperature code, and the process code. The temperature information generation unit may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of the combination code.
US09502080B2	Semiconductor memory device According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells are disposed in a matrix, each memory cell being connectable to any one of a plurality of bit lines, and a capacitance that suppresses coupling noise among the plurality of bit lines, the capacitance being added to at least one of the plurality of bit lines.
US09502077B2	Shingle verify archive appliance An apparatus according to one embodiment includes a controller configured to control a write transducer to perform shingled writing where a currently written track is written over a portions of a previously written track thereby defining a shingled track comprising a remaining portion of the previously written track. The controller is also configured to cause reading of data from at least one shingled track during the shingled writing using a read transducer.
US09502074B2	Media foundation media processor A system and method for a media processor separates the functions of topology creation and maintenance from the functions of processing data through a topology. The system includes a control layer including a topology generating element to generate a topology describing a set of input multimedia streams, one or more sources for the input multimedia streams, a sequence of operations to perform on the multimedia data, and a set of output multimedia streams, and a media processor to govern the passing of the multimedia data as described in the topology and govern the performance of the sequence of multimedia operations on the multimedia data to create the set of output multimedia streams. The core layer includes the input media streams, the sources for the input multimedia streams, one or more transforms to operate on the multimedia data, stream sinks, and media sinks to provide the set of output multimedia streams.
US09502070B2	Materials for near field transducers, near field tranducers containing same, and methods of forming A device including a near field transducer, the near field transducer including gold (Au), silver (Ag), copper (Cu), or aluminum (Al), and at least two other secondary atoms, the at least two other secondary atoms selected from: boron (B), bismuth (Bi), indium (In), sulfur (S), silicon (Si), tin (Sn), manganese (Mn), tellurium (Te), holmium (Ho), lutetium (Lu), praseodymium (Pr), scandium (Sc), uranium (U), barium (Ba), chlorine (Cl), cesium (Cs), dysprosium (Dy), europium (Eu), fluorine (F), germanium (Ge), hydrogen (H), iodine (I), rubidium (Rb), selenium (Se), terbium (Tb), nitrogen (N), oxygen (O), carbon (C), antimony (Sb), gadolinium (Gd), samarium (Sm), thallium (Tl), cadmium (Cd), neodymium (Nd), phosphorus (P), lead (Pb), hafnium (Hf), niobium (Nb), erbium (Er), zinc (Zn), magnesium (Mg), palladium (Pd), vanadium (V), zinc (Zn), chromium (Cr), iron (Fe), lithium (Li), nickel (Ni), platinum (Pt), sodium (Na), strontium (Sr), calcium (Ca), yttrium (Y), thorium (Th), beryllium (Be), thulium (Tm), erbium (Er), ytterbium (Yb), promethium (Pm), neodymium (Nd cobalt (Co), cerium (Ce), lanthanum (La), praseodymium (Pr), or combinations thereof.
US09502069B2	Plasmonic transducer having two metal elements with a gap disposed therebetween A plasmonic transducer includes at least two metal elements with a gap therebetween. The metal elements are elongated along a plasmon-enhanced, near-field radiation delivery axis. Cross sections of the metal elements in a plane normal to the delivery axis vary in shape along the delivery axis. A waveguide is disposed along an elongated side of the plasmonic transducer. The waveguide is optically coupled to the plasmonic transducer along the elongated side.
US09502065B1	Data media with tuned thermal conductivity and magnetic permeability Various magnetic stack embodiments may be constructed with a soft magnetic underlayer (SUL) having a first thickness disposed between a substrate and a magnetic recording layer. A heatsink may have a second thickness and be disposed between the SUL and the magnetic recording layer. The first and second thicknesses may each be tuned to provide predetermined thermal conductivity and magnetic permeability throughout the data media.
US09502064B1	Recording head with surface charge control A data recording head may consist of at least a charge control circuit that has a substrate, ground, surface charge circuitry, and data reader circuitry. The substrate may be electrically isolated from the ground and electrically connected between the surface charge circuitry and a non-zero fixed voltage. The surface charge circuitry can be configured to apply a varying substrate charge to the substrate at a predetermined frequency to alter a head media spacing between the substrate and a data storage medium.
US09502063B1	Apparatus and method for measuring slider fly height relative to bit patterned media A slider having a reader and a writer is moved relative to a magnetic bit pattern medium comprising magnetic dots arranged to include a plurality of pre-written servo sectors, data fields defined between servo sectors to which data can be written and erased, and pre-written timing synchronization fields interspersed within the data fields. In some approaches, two different tone patterns are read from one or more of the timing synchronization fields, and fly height of the slider is determined using the two different tone patterns. In other approaches, two odd harmonics are demodulated from a mixed tone pattern read from one or more of the timing synchronization fields, and fly height of the slider is determined using the two odd harmonics.
US09502062B1	Using two or more offset repeatable runout correction values for a virtual track of a magnetic disk First and second repeatable runout (ZAP) values are both located on a first virtual track of a magnetic disk. The first ZAP value is offset from the first virtual track center in a first direction and the second ZAP value is offset from the first virtual track center in a second direction opposite the first direction. At least one of the first and second ZAP values are accessed when performing repeatable runout correction for a writer of the read/write head that is being positioned over a second virtual track of the magnetic disk.
US09502061B1	Data storage device optimization based on adjacent track interference Systems, devices, processes, and methods of optimizing a data storage device based on adjacent track interference (ATI) are presented. ATI can be detected by writing a specific track of a disc a number of times and measuring a bit error rate (BER) of an adjacent track. In addition, more accurate in-field simulations of ATI can be achieved by seeking to another track, such as an adjacent track, in-between each write to the specific track. Further, in a heat-assisted magnetic recording (HAMR) device, a laser bias control can be implemented during at least one of the seeks to calibrate a laser in-between each write. Even further, the seeks may be anticipatory track seeks (ATS).
US09502057B1	Disk drive suspension having offset swage hub hole A base plate for a suspension has a swage hub whose inner diameter is offset from the outer diameter, and more specifically, the inner diameter of the swage hub is offset so as to be farther away from the head slider than is the outer diameter. The offset reduces variability in post-swaging deflection of the suspension at the distal end of the base plate to which the load beam is mounted.
US09502054B2	Devices including at least one intermixing layer Devices that include a near field transducer (NFT), the NFT including a peg having five surfaces, the peg including a first material, the first material including gold (Au), silver (Ag), aluminum (Al), copper (Cu), ruthenium (Ru), rhodium (Rh), iridium (Ir), or combinations thereof; an overlying structure; and at least one intermixing layer, positioned between the peg and the overlying structure, the at least one intermixing layer positioned on at least one of the five surfaces of the peg, the intermixing layer including at least the first material and a second material.
US09502053B1	Magnetic head for perpendicular magnetic recording with a trailing shield including a plurality of portions different in saturation flux density A magnetic head includes a main pole, a write shield, and a gap section. The write shield includes a trailing shield. The trailing shield includes a first portion, a second portion, a third portion and a fourth portion. The second portion and the third portion are located on opposite sides of the first portion in the track width direction. Top surfaces of the first to third portions are coplanar with each other. The fourth portion lies on the top surfaces of the first to third portions. The first portion is higher in saturation flux density than the second to fourth portions.
US09502052B1	Writing redundant data on tape media A request to write a data set to a magnetic tape medium is received. The data set is written in a first write direction of the magnetic tape medium. The data set is written in an opposite write direction of the magnetic tape medium.
US09502049B2	Time warp activation signal provider, audio signal encoder, method for providing a time warp activation signal, method for encoding an audio signal and computer programs An audio encoder has a window function controller, a windower, a time warper with a final quality check functionality, a time/frequency converter, a TNS stage or a quantizer encoder, the window function controller, the time warper, the TNS stage or an additional noise filling analyzer are controlled by signal analysis results obtained by a time warp analyzer or a signal classifier. Furthermore, a decoder applies a noise filling operation using a manipulated noise filling estimate depending on a harmonic or speech characteristic of the audio signal.
US09502047B2	Talker collisions in an auditory scene From a plurality of received voice signals, a signal interval in which there is a talker collision between at least a first and a second voice signal is detected. A processor receives a positive detection result and processes, in response to this, at least one of the voice signals with the aim of making it perceptually distinguishable. A mixer mixes the voice signals to supply an output signal, wherein the processed signal(s) replaces the corresponding received signals. In example embodiments, signal content is shifted away from the talker collision in frequency or in time. The invention may be useful in a conferencing system.
US09502045B2	Coding independent frames of ambient higher-order ambisonic coefficients In general, techniques are described for coding an ambient higher order ambisonic coefficient. An audio decoding device comprising a memory and a processor may perform the techniques. The memory may store a first frame of a bitstream and a second frame of the bitstream. The processor may obtain, from the first frame, one or more bits indicative of whether the first frame is an independent frame that includes additional reference information to enable the first frame to be decoded without reference to the second frame. The processor may further obtain, in response to the one or more bits indicating that the first frame is not an independent frame, prediction information for first channel side information data of a transport channel. The prediction information may be used to decode the first channel side information data of the transport channel with reference to second channel side information data of the transport channel.
US09502044B2	Compression of decomposed representations of a sound field In general, techniques are described for obtaining decomposed versions of spherical harmonic coefficients. In accordance with these techniques, a device comprising one or more processors may be configured to determine a first non-zero set of coefficients of a vector that represent a distinct component of a sound field, the vector having been decomposed from a plurality of spherical harmonic coefficients that describe the sound field.
US09502043B2	Method and an apparatus for processing an audio signal A method for processing an audio signal at an audio decoder, the method including receiving a downmix signal, a residual signal, and object information; extracting a background-object signal and a foreground-object signal from the downmix signal using the residual signal and object information; receiving mix information including gain information for the background-object signal; generating a downmix processing information based on the object information and the mix information; and generating an output signal including a modified background-object signal and a modified foreground-object signal. The modified background-object signal is obtained by modifying a gain of the background-object signal using the mix information. The modified foreground-object signal is obtained by modifying a gain of the foreground-object signal using the downmix processing information.
US09502042B2	Apparatus for processing an audio signal and method thereof An apparatus for processing an audio signal and method thereof are disclosed. The present invention includes receiving a downmix signal and side information; extracting control restriction information from the side information; receiving control information for controlling gain or panning at least one object signal; generating at least one of first multi-channel information and first downmix processing information based on the control information and object information, without using the control restriction information; and, generating an output signal by applying the at least one of the first multichannel information and the first downmix processing information to the downmix signal, wherein the control restriction information relates to a parameter indicating limiting degree of the control information.
US09502040B2	Encoding and decoding of slot positions of events in an audio signal frame An apparatus for decoding, an apparatus for encoding, a method for decoding and a method for encoding positions of slots having events in an audio signal frame and respective computer programs and encoded signals, wherein the apparatus for decoding has: an analyzing unit for analyzing a frame slots number indicating the total of slots of the audio signal frame, an event slots number indicating the number of slots having the events of the audio signal frame, and an event state number, and a generating unit for generating an indication of a plurality of positions of slots having the events in the audio signal frame using the frame slots number, the event slots number and the event state number.
US09502038B2	Method and device for voiceprint recognition A method and device for voiceprint recognition, include: establishing a first-level Deep Neural Network (DNN) model based on unlabeled speech data, the unlabeled speech data containing no speaker labels and the first-level DNN model specifying a plurality of basic voiceprint features for the unlabeled speech data; obtaining a plurality of high-level voiceprint features by tuning the first-level DNN model based on labeled speech data, the labeled speech data containing speech samples with respective speaker labels, and the tuning producing a second-level DNN model specifying the plurality of high-level voiceprint features; based on the second-level DNN model, registering a respective high-level voiceprint feature sequence for a user based on a registration speech sample received from the user; and performing speaker verification for the user based on the respective high-level voiceprint feature sequence registered for the user.
US09502037B2	Wireless caption communication service system A Wireless Caption Communication Service (“WCCS”) System includes a relay center, a wireless caption communication device, and a wireless captioning service server. The wireless caption communication device has a voice collecting device and a wireless caption communication terminal. Text entered by a first user is transmitted to the wireless captioning service server and converted into a speech. Then, the speech is transmitted to the voice collecting device and the sound of the speech comes out of a speaker of the voice collecting device so that a second user can hear the speech. The voice of the second user is transmitted to the wireless captioning service server and then to the relay center. The voice is converted into a caption data and transmitted to the wireless caption communication device, and the caption data is displayed on the wireless caption communication terminal so that the first user can read the caption data.
US09502031B2	Method for supporting dynamic grammars in WFST-based ASR Systems and processes are disclosed for recognizing speech using a weighted finite state transducer (WFST) approach. Dynamic grammars can be supported by constructing the final recognition cascade during runtime using difference grammars. In a first grammar, non-terminals can be replaced with a, weighted phone loop that produces sequences of mono-phone words. In a second grammar, at runtime, non-terminals can be replaced with sub-grammars derived from user-specific usage data including contact, media, and application lists. Interaction frequencies associated with these entities can be used to weight certain words over others. With all non-terminals replaced, a static recognition cascade with the first grammar can be composed with the personalized second grammar to produce a user-specific WEST. User speech can then be processed to generate candidate words having associated probabilities, and the likeliest result can be output.
US09502028B2	Acoustic activity detection apparatus and method Streaming audio is received. The streaming audio includes a frame having plurality of samples. An energy estimate is obtained for the plurality of samples. The energy estimate is compared to at least one threshold. In addition, a band pass estimate of the signal is determined. An energy estimate is obtained for the band-passed plurality of samples. The two energy estimates are compared to at least one threshold each. Based upon the comparison operation, a determination is made as to whether speech is detected.
US09502025B2	System and method for providing a natural language content dedication service The system and method described herein may provide a natural language content dedication service in a voice services environment. In particular, providing the natural language content dedication service may generally include detecting multi-modal device interactions that include requests to dedicate content, identifying the content requested for dedication from natural language utterances included in the multi-modal device interactions, processing transactions for the content requested for dedication, processing natural language to customize the content for recipients of the dedications, and delivering the customized content to the recipients of the dedications.
US09502022B2	Apparatus and method of generating quiet zone by cancellation-through-injection techniques A quiet zone generation technique is proposed for interference mitigation for a receive antenna by injecting the very interference signals via iterative processing, generating quiet zones dynamically for receive (RCV) antennas. The receive antenna may feature multiple receiving apertures distributed over a finite area. Optimization loops consist of four cascaded functional blocks; (1) a pick-up array to obtain the interference signals, (2) element weighting and/or repositioning processors, (3) an auxiliary transmit (XMIT) array with optimized element positions, (4) a diagnostic network with strategically located probes, and (5) an optimization processor with cost minimization algorithms. To minimize interferences between transmit (Tx) and receiving (Rx) apertures in limited space of an antenna farm for communications and/or radar applications are very tough problems. However, solutions for co-site interference mitigation may not be generic ones but more specific to geometries of antenna farms, Tx apertures and Rx antenna locations, and beam positions of the Tx beams.
US09502020B1	Robust adaptive noise canceling (ANC) in a personal audio device An adaptive noise canceling (ANC) circuit adaptively generates an anti-noise signal that is injected into the speaker or other transducer output to cause cancellation of ambient audio sounds. At least one microphone provides an error signal indicative of the noise cancellation at the transducer, and the adaptive filter is adapted to minimize the error signal. In order to prevent improper adaptation or instabilities in one or both of the adaptive filters, spikes are detected in the error signal by comparing the error signal or its rate of change to a threshold. Therefore, if the magnitude of the coefficient error is greater than a threshold value for an update, the update is skipped. Alternatively the step size of the updates may be reduced. Similar criteria can be applied to a filter modeling the secondary path, based on detection applied to both the source audio and the error signal.
US09502018B2	Whistle play stopper Systems and methods for notifying game-based clocks and players associated with a sporting event using one or more digital whistles are described. More specifically, the one or more digital whistles, for example used by referees, transmit one or more digital signals upon being used. The transmitted digital signals are received by a whistle processor that processes the transmitted digital signals and transmits instructions to the game-based clocks and players in the sporting event for controlling timekeeping and facilitating a flow of the sporting event.
US09502016B2	Adjustable and foldable shoulder rest for violin or viola An adjustable and foldable shoulder rest for a violin or viola includes a shoulder-engaging body having first and second foldable forks at first and second ends of the body for attaching to the violin or viola, first and second slidable end members for supporting the first and second forks, the first and second slidable end members being slidable between retracted and extended position. In the extended position, the end member is cantilevered beyond its respective slot. The shoulder rest may have a foam cushion with openings attached to the shoulder-engaging side of the shoulder rest. The end members may define rotational housings for receiving respective rotatable drums that receive threaded stems of the forks, thereby enabling the height of the forks to be adjusted and further enabling the forks to fold.
US09502015B1	Guitar waist belt Provided is a system for carrying a guitar. The system comprises a belt that wraps around a user's waist, and a cradle or guitar strap button attached to the belt that supports the weight of the guitar. The belt comprises an inner belt and an outer belt that is attached to the inner belt. The belt and cradle may comprise additional straps that extend from the belt to existing attachment points on the guitar. The belt and cradle allow a user to support a guitar without the use of a shoulder strap, to limit the strain on the shoulders of the user.
US09502012B2	Drumstick controller A percussion device includes a drumstick assembly and a sleeve. The drumstick assembly includes a drumstick having a base and a tip end, and a drumstick tip secured to the tip end of the drumstick, the drumstick tip including a sensor. The sleeve is disposed about at least a portion of the drumstick including the base thereof, and includes at least one control button, a communication element, and a processor in communication with the at least one control button, the drumstick tip and the communication element. The processor is configured to receive a signal from the drumstick tip and to generate output to the communication element. The output so generated includes a signal that specifies a sound file selected by operation of the at least one control button.
US09502010B1	Guitar tremolo bridge A tremolo bridge for a guitar comprising a body, a neck attached to said body, a headstock attached to said neck, a plurality of tuners disposed on said headstock and adjacent the neck, at least one post extending from said body, each of said at least one post further comprising a V-shaped notch, and a plurality of strings, whereby each string of said plurality of strings is attached to the tremolo bridge, extends along the neck of the guitar, and is attached to a corresponding one of said plurality of tuners disposed on the headstock, said tremolo bridge comprising: a base plate, a block extending from said base plate, a tremolo arm attached to said base plate, and a locking mechanism for locking the position of the tremolo bridge.
US09502008B2	Methods and apparatus for improving decibel level decay rates of excited strings Methods and apparatus for improving the decibel level decay characteristics of excited strings for stringed musical instruments.
US09502005B2	Guitar neck joint routing system A guitar neck joint routing system. The system includes a probe and router assembly comprising a gantry, a probe, and a plurality of routers, and a guitar neck and body nest comprising clamps and vacuum grips for holding a guitar neck and guitar body in place for taking measurements and routing a dovetail joint.
US09502004B2	Support assembly and keyboard apparatus A support assembly including a support rotatably disposed with respect to a frame, a repetition lever hinge mounted to the support, and a repetition lever supported by the repetition lever hinge and rotatably disposed with respect to the support, wherein the repetition lever has a contact surface and the contact surface contacts a hammer shank roller provided to a hammer shank for rotating a hammer, and the repetition lever hinge is mounted to the support in a mounting direction that crosses with a tangent-line direction of a line tangent to the hammer shank roller at the contact between the hammer shank roller and the contact surface.
US09501997B2	Gate driver and display apparatus A gate driver (103) and a display device, which relate to the technical field of display, and are applicable to the design and manufacture of display devices. The gate driver (103) comprises: a power-off voltage detection circuit (101) and a power-off de-ghosting function circuit (204) connected to the power-off voltage detection circuit (101), wherein the power-off voltage detection circuit (101) is used for detecting a current voltage state, and outputting a control signal to the power-off de-ghosting function circuit (204) according to the voltage state, so that the power-off de-ghosting function circuit (204) outputs a signal to eliminate power-off ghosting according to the control signal. The gate driver (103) integrates the power-off voltage detection circuit (101) and the power-off de-ghosting function circuit (204); the integration level is high, and the display device can eliminate the power-off ghosting without the need to match the selected type of the gate driver (103) and a printed circuit board.
US09501992B2	Alternating current light emitting device An alternating current (AC) light emitting device includes an AC light emitting diode (LED) module and a waveform modulation unit. The AC LED module includes at least two sets of micro-diodes. The waveform modulation unit coupled between the AC LED module and an AC voltage source modulates a waveform of the AC voltage source.
US09501988B2	Display device A display device includes: a plurality of drive electrodes extending in a first direction and arranged side-by-side in a second direction with an inter-electrode slit in between; and a plurality of pixel electrodes arranged in matrix in the first and second directions. Each of the drive electrodes has one or more inner-electrode slits, and a center of the pixel electrode is located in the inter-electrode slit or in the inner-electrode slit.
US09501987B2	Liquid crystal display device and driving method thereof Disclosed is an LCD device. The LCD device includes a panel in which a plurality of gate lines cross a plurality of data lines, a source driving IC configured to alternately output a current data voltage and a current common voltage, a common electrode connected to the source driving IC through at least two or more common voltage lines, and a timing controller configured to generate current image data used to generate the current data voltage and common voltage data used to generate the current common voltage to be outputted to the source driving IC in correspondence with the current data voltage.
US09501984B2	Driving device and driving device control method thereof A driving device includes a driving module, for generating a plurality of driving signals according to a plurality of next channel data and adjusting coupling relationships of the plurality of driving signals according to a charge sharing control signal; and a timing control module, for generating the plurality of next channel data and selecting one of a plurality of charge sharing control commands as the charge sharing control signal.
US09501980B2	Display panel and display panel system A display panel comprises an array of light elements arranged in n rows by m columns. At least one driver is configured to drive one of said columns and rows, wherein the or each driver is configured to drive each of said columns or said rows. A plurality of the display panels may be used together to form a display panel system.
US09501979B2	Image display apparatus and control method thereof The present invention in its first aspect provides an image display apparatus capable of controlling, for each block obtained by dividing a region of a screen, a backlight emission brightness based on image data of an inputted frame. The image display apparatus includes: a detecting unit that detects a block in which a predetermined object is displayed; a determining unit that determines an object block that is a block in which a background and the predetermined object are displayed based on a detection result by the detecting unit; and a control unit that controls a backlight emission brightness for each block. The control unit approximates a backlight emission brightness of the object block to a backlight emission brightness of another block in which the background is displayed.
US09501974B2	Organic light-emitting display apparatus An organic light-emitting display apparatus including a display including pixels arranged in an array, a sensor for detecting respective current characteristics of the pixels, a current sensor for receiving a first current from a first pixel of the pixels, for outputting a first voltage corresponding to the first current, for receiving a second current from a second pixel of the pixels, and for outputting a second voltage corresponding to the second current, a level shifter for receiving the first and second voltages and for generating first and second shift voltages respectively corresponding to the first and second voltages, an intermediate voltage of the first and second voltages being equal to a conversion reference voltage, and an analog-to-digital converter for receiving the first and second shift voltages and for outputting a digital value corresponding to a difference between the first and second shift voltages based on the conversion reference voltage.
US09501973B2	Pixel driving circuit, driving method, array substrate and display apparatus A pixel driving circuit, array substrate and display apparatus, comprise: data line for providing data voltage; gate line for providing scanning voltage; first power supply line for providing first power supply voltage; second power supply line for providing second power supply voltage; light emitting device connected to second power supply line; driving transistor connected to first power supply line; storage capacitor having first terminal connected to gate of driving transistor and configured to transfer information to gate of driving transistor; resetting unit configured to reset voltage across storage capacitor as predetermined signal voltage; data writing unit configured to write information into second terminal of storage capacitor; compensating unit configured to write information into first terminal of storage capacitor; and light emitting control unit configured to write first power supply voltage into second terminal of storage capacitor and control driving transistor to drive light emitting device to emit light.
US09501970B2	Display device and driving method thereof In an organic light emitting diode display, a plurality of sub-pixels sharing a select scan line that extends in a row direction forms a unit pixel, and the plurality of sub-pixels are arranged in a column direction in the unit pixel. A field is divided into a plurality of subfields, and corresponding one of the plurality of sub-pixels emits light in each of the plurality of subfields.
US09501969B2	DC-DC converter and organic light emitting display including the same There are disclosed a DC-DC converter and an organic light emitting display including the same. The DC-DC converter includes a first voltage generator that has an inductor and a plurality of transistors, and converts an input voltage into a first voltage and outputs the first voltage to a first output terminal. The DC-DC converter also includes a controller that controls driving of the first voltage generator by supplying a first driving pulse to each transistor of the first voltage generator. In the DC-DC converter, the amplitude of the first driving pulse is adjustable. Accordingly, it is possible to provide a DC-DC converter and an organic light emitting display including the same, which can achieve high power conversion efficiency by change a driving pulse used in a DC-DC converter.
US09501965B2	Image display apparatus and control method thereof An image display apparatus according to the present invention includes: a light-emitting unit capable of separately controlling the emission brightness in each of a plurality of divided regions in a screen; a determining unit configured to determine a target brightness of a predetermined divided region, based on image data corresponding to the predetermined divided region; an estimating unit configured to estimate the brightness of the predetermined divided region when light is emitted by the light-emitting unit at emission brightness which is based on image data in each of the plurality of divided regions; and a control unit configured to control the emission brightness of two or more divided regions including the predetermined divided region based on the difference between the target brightness determined by the determining unit and the brightness estimated by the estimating unit.
US09501959B2	Mother substrate with switch disconnecting test part, array test method thereof and display substrate A mother substrate includes a display substrate cell defined by a scribe line, the display substrate cell including a plurality of gate lines, a gate circuit part driving the gate lines, and a gate pad part connected to the gate circuit part, a gate test pad part in a peripheral area surrounding the display substrate cell, the gate test pad part being configured to receive a gate test signal, a gate test line part connecting the gate test pad part and the gate pad part, and a switching part connected to the gate test line part and configured to control turning on and turning off of the gate test line part.
US09501953B2	Birthing simulation devices, systems, and methods Devices, systems, and methods appropriate for use in medical training are disclosed. In some instances, a patient simulator system is provided that includes a maternal patient simulator and a fetal patient simulator. The maternal patient simulator includes an internal chamber sized to receive the fetal patient simulator and a birthing mechanism disposed within the internal chamber configured to translate and rotate the fetal patient simulator with respect to the maternal patient simulator to simulate a birth. In some instances, the fetal patient simulator an internal support structure that includes a head, spinal components, left arm components, right arm components, left leg components, and right leg components with a continuous silicon skin layer covering the internal support structure.
US09501948B1	Interactive educational system and method A system for associating an action of a user with a message corresponding to the action, where the message is visually displayed on a series of sequentially disposed discrete mats. The message is uttered by the user and the message is verified using a speech analyzer. The system includes at least two mats, each mat having a display, a transmitter, a receiver, and a presence sensor indicating the presence of the user and configured to indicate the intention of the user to add an answer to a composite answer. The system also includes an audio receiver that receives an audio input from the user and an indicator device that indicates whether the mat is a head mat.
US09501946B1	Systems and methods for stable haptic feedback over packet-switched networks Providing haptic feedback to a user over a packet-switched network includes sensing movement of a haptic device by a user, the haptic device being configured to control a first virtual object within a virtual environment, transmitting data associated with the movement of the haptic device from a client computer to a remote server via the packet-switched network, the server modeling movement of the first virtual object in the virtual environment and estimating an orientation and a position of the first virtual object within the virtual environment, the server determining a type of tactile feedback to be provided to the user, the server transmitting the type of tactile feedback data to the client computer via the packet-switched network, and providing tactile feedback to the user with the haptic device.
US09501943B2	Systems, methods, and computer program products for providing a learning aid using pictorial mnemonics A system, method and computer program product for providing a learning aid using pictorial mnemonics. The method can include receiving a first input including a selection of a content topic. The method further includes displaying a first pictorial mnemonic associated with the selected topic, wherein the first pictorial mnemonic comprises one or more sub-images, and a list of one or more attributes, wherein each attribute is associated with a corresponding sub-image.
US09501942B2	Personalized avatar responsive to user physical state and context Systems and methods are disclosed that facilitate visualizing how a user will appear in response to adhering to a health and fitness program. In an aspect, a system includes a reception component configured to receive information corresponding to a user's physical appearance and physical health, an analysis component configured to determine or infer one or more changes to the user's physical appearance based on predicted performance of a health and fitness program by the user and the user's physical health, and a visualization component is configured to generate a visual representation of the user based on the information and the one or more changes to the user's physical appearance.
US09501933B2	Radio device A first processor derives a first arrival time to be taken for a vehicle and another vehicle travelling straight ahead to intersect at a point. A second processor derives a second arrival time to be taken for the vehicle and the other vehicle running on a straight line linking the vehicle and the other vehicle to encounter at a point. A third processor derives a first range of travelling directions the vehicle can take between the second arrival time and the first arrival time and derives a second range of travelling directions the other vehicle can take between the second arrival time and the first arrival time. A determiner determines relative relation between the vehicle and the other vehicle at a time of intersection between the vehicle and the other vehicle, based on difference between the first range and the second range.
US09501926B1	Two wire sonar telemetry The invention is a two wire telemetry system for an entire towed underwater acoustic sonar array system wherein power and data signals are now shared on a single wire (with a second wire as return) throughout the towed array. Ship electrical power is transmitted from a direct current source onto the tow cable for all of the array nodes to operate on. Downlink commands are also sent to the array nodes via the tow cable. Uplink data is sent up the tow cable to the towing vessel for data storage. A bi-directional time sharing communication protocol allows each node on the array as well as the command and control on the towing vessel a portion of time to transmit signals.
US09501925B2	Modular alert system The present invention provides methods and systems for a modular alert system that includes at least one module having a top portion and a bottom portion. The at least one module provides an alarm for one or more monitored conditions, and the bottom portion and the top portion of the at least one module contains mating features. A mounting plate that has a top portion and a bottom portion contains mounting features, and the mounting features of the bottom portion correspond to the mounting features of the top portion of the module for forming a selectively secured arrangement. The system may also include at least one speaker housed within the module, and a smoke detector.
US09501924B2	Home security system with automatic context-sensitive transition to different modes A home security system may infer a mode of operation based on indications it receives regarding a user's behavior. The disclosed implementations provide for a vacation mode of operation that defines a response for a security event that differs from the response that would be provided by the home security system for the same security event if it operated in another mode such as an away mode.
US09501921B2	Water saving alert system The present invention generally relates to a device that will alert users that they are using (or wasting) more than a certain amount of water. More particularly, the present invention relates to a portable device clip that may be connected to any type of water pipe, will measure and time the flow of water, and will alert users via an audible alarm if and when water flows for more than a user-specified period of time. The invention may be used by both consumers and landlords to educate users in the prevention of undue water consumption, and to save thousands of gallons of water per year.
US09501918B2	Human safety indicator A human safety system includes a circuit including at least one power source; a temperature probe in communication with the circuit; at least one use detector in communication with the circuit; and an alert indicator in communication with the circuit. A method of measuring a temperature of a user includes determining whether at least one use detector is active; determining a user temperature based on sensed temperature; and determining whether the user temperature is within an allowable range.
US09501908B2	System for processing and tracking merchant deposits Embodiments of the invention are directed to systems, methods, and computer program products for processing and tracking merchant deposits. An exemplary apparatus is configured to receive a deposit package that contains one or more deposit items which have been placed in the deposit package by a merchant. The deposit package may also contain and/or be coupled with visual indicia that has been created by the merchant. The visual indicia may specify information about the one or more deposit items placed in the deposit package. The apparatus may be further configured to read the visual indicia upon receiving the deposit package and track the deposit package based at least partially on the visual indicia.
US09501902B2	Gaming system and method for offering simultaneous play of multiple games Gaming apparatus and methods of conducting a wagering game of chance. A gaming machine is disclosed which is configured for mutually concurrent play of a plurality of games of chance on a single display screen. A method of conducting a wagering activity includes providing a player with a plurality of differing games of chance, at least some of which are mutually concurrently playable on a single screen display of a gaming device and enabling mutually concurrent play of the plurality of differing games of chance on the single screen display. Various other gaming machine configurations and methods of play related to multiple differing games of chance on a single display screen are also disclosed herein. Networked gaming machines are also disclosed.
US09501896B2	Security method and system for electronic game virtual refill cartridge A method, system and program product for controlling the operation and configuration of an electronic game terminal for the play of licensed electronic games. A passcode is generated for activating plays on the electronic game terminal. An operator is enabled to enter the passcode into a control component for the electronic game terminal. A maximum number of electronic games that can be played before the electronic game terminal is deactivated is set when the passcode is entered. The number of games remaining following each play of the electronic game is determined dynamically. A request is received from the operator to refill the game plays on the electronic game terminal. A new passcode is then generated wherein the new passcode can enable or disable at least one feature of the electronic game. The new passcode is provided to the operator to enter in order to enable additional plays on the electronic game terminal.
US09501893B2	Contract the game of the century A game assembly for a game associated with instructions and rules for use in playing the game includes a housing having a spinning wheel with slots and numbers used for making wagers, and a wager calculations device. The housing further has a miniature basketball net through which a player participant throws a miniature basketball onto said spinning wheel, and a plurality of miniature basketballs having varying point denominations thereon for wagering. A hand-held remote controller controlling time limits per unit of said game; and the hand-held remote controller controls audio visual displays displayed on the housing, which are related to the game. The wager calculations device maybe the hand held remote controller, or a separate a flat wager board having respective slots and numbers corresponding to those displayed on the spinning wheel.
US09501889B2	Product storage device A product storage device includes: a product rack including a plurality of product storage columns, the product storage column having a product storage path; a main gate member provided the product storage columns to be rotatable in a form of moving into or out of the product storage path; and a restraining unit including a guide member extending along a direction of arranging the product storage columns, and a plurality of piece members slidably housed in a housing region of the guide member. The restraining unit in a normal state restrains all the main gate members from being retreated from the product storage path. The restraining unit allows any one main gate member to be retreated from the product storage path and restrain the other main gate members from being retreated from the product storage path when extraction of a product in the product rack is allowed.
US09501887B2	Object dispenser having a variable orifice and image identification A method and apparatus for dispensing objects from automated storage and retrieval systems such as medications is disclosed which may also include a singulator to assure singulation (retrieval of singular objects). The singulator may be an imaging system to confirm and/or identify the objects being dispensed and/or a variable orifice dynamically adjustable to a specific object or pill size, and through which only a single object or pill is allowed to pass. The system may further include a flexible probe so as to reduce the size of the system where the movement of the probe relative to or while retrieving objects is accomplished by advancing/retracting a flexible tube. The method and apparatus may further include an imaging system.
US09501886B2	Coin feeder The invention provides a coin feeder for feeding coins to a coin sensor. The coin feeder comprises a hopper disc having a first surface and arranged to receive coins on the first surface, and to transport the coins along a first path towards the coin sensor. The coin feeder also comprises one or more coin deflectors to deflect coins received on the first surface from the first path if the coins are above a threshold thickness. At least one of the one or more coin deflectors comprises a rotatable member spaced from the first surface.
US09501884B2	System and method for accessing a structure using directional antennas and a wireless token A wireless device access system that employs directional antennas for short-range wireless communication to detect the proximity and orientation of a user device with respect to a structure is disclosed. The access system receives and authenticates an unlock request and confirms the proximity and orientation of the user device prior to transmitting an unlock command to the structure. This authentication may occur through the use of substantially opposing directional antennas separated by a ground plane. Additionally, the wireless device may require the proximity of a user token prior to operation and/or the access system may include an override within the structure blocking any unlock command.
US09501880B2	Wireless access control system including remote access wireless device generated magnetic field based unlocking and related methods A wireless access control system may include a remote access wireless device that includes a magnetic field generator and a remote controller coupled to remote access wireless device wireless communications circuitry and the magnetic field generator. The system may also include a lock assembly for a door and that includes a magnetic sensor and a lock controller coupled to a lock, lock wireless communications circuitry, and the magnetic sensor. The remote controller may communicate a magnetic field characteristic with the lock wireless communications circuitry, and cooperate with the magnetic field generator to generate a magnetic field based upon the magnetic field characteristic. The lock controller may cooperate with the magnetic sensor to sense the magnetic field, compare the sensed magnetic field to the magnetic field characteristic, and enable lock unlocking when the sensed magnetic field has a sensed magnetic field characteristic that matches the magnetic field characteristic.
US09501879B2	Semiconductor integrated circuit mountable on recording device and method of operating the same A semiconductor integrated circuit has a video encoder including a motion prediction unit, a motion compensation unit, a subtraction unit, a discrete cosine transform unit, a quantization unit, an inverse quantization unit, an inverse discrete cosine transform unit, and an addition unit. The encoder divides the video signal from the camera into a plurality of partial images including the central part of the image and the peripheral part of the image according to the distance from the center of the image, and processes the partial images. A pixel processing unit coordinate-transforms coordinates of a pixel included in the central part of the image into coordinates of the peripheral part of the image, and performs a process of enlarging an object of a subject included in the central part of the image on a pixel-by-pixel basis when performing the coordinate transform.
US09501877B2	Intelligent towing plug An intelligent towing plug apparatus and software system that performs trailer electrical system testing, diagnostic and monitoring routines as well as towing vehicle plug testing utilizing wireless technology housed completely inside a towing adapter plug or attached towing plug compartment housing that interfaces with any smart phone or towing vehicle on-board computer system that has downloaded or preinstalled the intelligent towing plug mobile application or software compatible with the on-board computer's operating system.
US09501875B2	Methods, systems and apparatus for determining whether any vehicle events specified in notification preferences have occurred Computer-implemented methods, systems and apparatus are disclosed for monitoring and reporting notification preferences. A processor of a vehicle determines whether any vehicle events specified in notification preferences have occurred. The notification preferences can be defined by an owner of the vehicle and specify vehicle events that the owner wants to be monitored and reported. When the processor determines that any vehicle event specified in the notification preferences has occurred, the processor can store a record of the vehicle event (and any other vehicle events that occur) in a vehicle event detection log, and then regularly or periodically generate a notification report that includes records for each of the vehicle events that are stored in the vehicle event detection log. The notification report can then be communicated to a remote computer located outside the vehicle. In addition, some vehicle events can trigger generation and communication of an alert message to the remote computer.
US09501872B2	AR image processing apparatus and method technical field A first AR analyzer (3A) analyzes a first captured image including an AR marker image captured by a camera (1), determines the appearance of the AR marker image in the field of view in the first captured image, and virtually places a corresponding CG at an appropriate position in the field of view corresponding to the AR marker image; a second AR analyzer (3B) calculates appearance of the CG object in another field of view of the camera in a second captured image subsequently captured by the camera; a CG rendering unit (5) composites an image of the CG object at an appropriate position in the second captured image corresponding to the appropriate appearance; and a display unit (7) displays the composite image, so that the apparatus can composite and display a CG object in real time on a digital image of a natural landscape captured by a camera.
US09501871B2	Explorable augmented reality displays Concepts and technologies are disclosed herein for explorable augmented reality displays. An augmented reality service can receive a request for augmented reality display data. The request can be associated with a device. The augmented reality service can determine a location associated with the device and identify augmented reality data associated with the location. The augmented reality service can provide augmented reality display data to the device.
US09501869B2	Systems and methods for presenting vehicle component information A system and method for presenting vehicle component information includes storing voxel data in a computerized database. The voxel data represents a plurality of voxels spatially arranged to encompass a shape representing at least part of a vehicle. A plurality of component records is stored in the database, wherein each component record corresponds to a component of the vehicle. Each component record is associated with voxel data representing at least one voxel. A graphical representation of at least one of the components is displayed on a display.
US09501865B2	System, method, and computer program product for determining a quantity of light received by an element of a scene A system, method, and computer program product are provided for determining a quantity of light received by an element of a scene. In use, a quantity of light received by a first element of the scene is determined by averaging a quantity of light received by elements of the scene that are associated with a selected set of light paths.
US09501861B2	System and method for generating product visualizations This disclosure includes a method for electronically generating a single image for product visualization. The method comprises receiving a selection of a first variation of a first consumer product layer with a first depth attribute from a plurality of variations of the first consumer product layer, each variation comprising at least one surface. The method further includes receiving a selection of a second variation of a second consumer product layer with a second depth attribute from a plurality of variations of the second consumer product layer, each variation comprising at least one surface. The method also includes layering the first variation of the first consumer product layer in the single image based at least on the first depth attribute; and layering the second variation of the second consumer product layer in the single image based at least on the second depth attribute. Related systems and apparatuses are also disclosed.
US09501858B2	Display device and computer A display device converts an animation file into first binary data in a data format which can be processed by a first graphics library of a first display, the binary data including a DL, and converts the converted first binary data into second binary data in a data format which can be processed by a second graphics library of a second display.
US09501857B2	Display control method configured to cause an input image to emerge and move on a display region, display control device, and display system configured to perform same A display control method includes: inputting user's image including a drawing portion made by hand drawing and being a display target image; and performing image control including causing the input user's image to emerge from any one of a left end and a right end of a predetermined display region, on which the user's image is to be displayed, and moving the user's image that has emerged.
US09501853B2	Providing in-line previews of a source image for aid in correcting OCR errors The present disclosure is directed toward systems and methods for assisting users in correcting OCR errors. For example, systems and methods described herein involve identifying the position of a cursor within a machine-readable document. Systems and methods described herein also involve identifying corresponding position co-ordinates in a source image, as well as, capturing an image preview from the source image based on the corresponding position co-ordinates. Systems and methods described herein may also involve providing the preview of the source image within the machine-readable document.
US09501851B2	Time-series analysis system Various systems and methods are provided that display various graphs in an interactive user interface in substantially real-time in response to input from a user in order to determine information related to measured data points and provide the determined information to the user in the interactive user interface. For example, a computing device may be configured to retrieve data from one or more databases and generate one or more interactive user interfaces. The one or more interactive user interfaces may display the retrieved data in one or more graphs, such as time-series or scatterplots. The user interface may be interactive in that a user may manipulate one graph, which causes an identical or nearly identical manipulation of another displayed graph in real-time. The manipulations may occur even if the displayed graphs include data across different time ranges.
US09501850B2	Display techniques for graphs A display device for displaying a graph structure in which the graph structure has elements. The display device includes a display screen for displaying at least first and second display regions and a display screen processing section configured to display in the first display region at least a part of the graph structure including a first element. The display also includes a control section configured to cause the display screen to display in the second display region, responsive to selection of the first element displayed in the first display region, at least a part of the graph structure including the first element. Additional embodiments include a display method performed by the display device, and a computer program product used in the display device.
US09501844B2	Virtual cellular staining Systems and methods are used to display cell structures of a biological cell. A plurality of cell structures of a biological cell is stored and for each cell structure of the plurality of cell structures one or more stain colors are stored. A selected cell structure is received from an input device. One or more stain colors of the selected cell structure are retrieved. The one or more stain colors of the selected cell structure are displayed. A selected stain color is received from the input device. The selected cell structure is displayed in the selected stain color in an exemplary cell image. Further, a three-dimensional image of a biological cell is stored. The three-dimensional image is displayed on a display that includes a touch screen. A movement selection is received from the touch screen. The three-dimensional image is displayed on the display according to the movement selection.
US09501841B2	Method for color calibration and user terminal Embodiments of the present invention provide a method for color calibration and a user terminal, which relate to the field of terminal display and are capable of compensating the colors of the displayed content on a screen according to the external light intensity, preventing content color distortion, and improving user experience. The embodiments of the present invention are used by a mobile terminal to calibrate screen colors according to external light.
US09501840B2	Information processing apparatus and clothes proposing method According to one embodiment, an information processing apparatus includes an interface and a control part. The interface receives an image which is transmitted from a first terminal and in which a person and an object as a reference of magnitude of one pixel are photographed. The control part calculates a size of clothes suitable for the person based on the image and a magnitude of the object in the image, and transmits information relating to the clothes with this size to the first terminal through the interface.
US09501833B2	Method and system for providing three-dimensional and range inter-planar estimation A system, apparatus and method of performing 3-D object profile inter-planar estimation and/or range inter-planar estimation of objects within a scene, including: providing a predefined finite set of distinct types of features, resulting in feature types, each feature type being distinguishable according to a unique bi-dimensional formation; providing a coded light pattern having multiple appearances of the feature types; projecting the coded light pattern, having axially varying intensity, on objects within a scene, the scene having at least two planes, resulting in a first plane and a second plane; capturing a 2-D image of the objects having the projected coded light pattern projected thereupon, resulting in a captured 2-D image, the captured 2-D image including reflected feature types; determining intensity values of the 2-D captured image; and performing 3-D object profile inter-planar estimation and/or range inter-planar estimation of objects within the scene based on determined intensity values.
US09501832B1	Using pose data and positioning information to locate online photos of a user The aspects described herein include receiving a request for available images depicting a user. One or more time and location indicators indicating one or more locations visited by the user are determined. Based on at least in part the one or more time and location indicators, a set of candidate images may be identified. The set of candidate images depict one or more locations at a time corresponding to at least one of the time indicators. Pose data related to the user may be obtained based on the location indicators. The pose data indicates a position and orientation of the user during a visit at a given location depicted in the set of candidate images. One or more images from the set of candidate images may be selected based on the pose data and the 3D reconstruction. The selected images include at least a partial view of the user.
US09501831B2	Identification of relative distance of objects in images In one aspect, a hand-held device is provided with a display, camera, motion detector and processor. The processor receives a sequence of images from the camera, the relative distance to the object based on the parallax associated with two or more images of the sequence and the motion of the camera is determined, and the image is augmented and displayed based on the relative distances.
US09501829B2	System and method for atlas registration A system and method for associating anatomically significant regions with regions of one or more images may include automatically modifying images of different modalities according to different correction algorithms, providing a user interface for identifying a plane within three-dimensional data, scaling atlas structures to fit an anatomical image according to identified landmarks, registering an atlas to such an image via a combination of registration algorithms, and/or registering an atlas to such an image using a feature extraction algorithm.
US09501826B2	Rectification techniques for heterogeneous camera arrays Rectification techniques for camera arrays in which the resolutions, fields of view, and/or pixel sizes of various cameras may differ from one another are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to receive a captured image array captured by a heterogeneous camera array, select a rectification process for application to the captured image array, identify a set of rectification maps for the selected rectification process, and apply the identified set of rectification maps to the captured image array to obtain a rectified image array. Other embodiments are described and claimed.
US09501824B2	Non-touch optical detection of vital signs from amplified visual variations of reduced images of skin A microprocessor is operably coupled to a camera from which patient vital signs of reduced images of skin are determined. A temporal variation of reduced images of skin from the camera is generated from multiple filters and then amplified from which the patient vital sign, such as heart rate or respiratory rate, can be determined and then displayed or stored.
US09501823B2	Methods and systems for characterizing angle closure glaucoma for risk assessment or screening A method is proposed for analyzing an optical coherence tomography (OCT) image of the anterior segment (AS) of a subject's eye. A region of interest is defined which is a region of the image containing the junction of the cornea and iris, and an estimated position the junction within the region of interest is derived. Using this a second region of the image is obtained, which is a part of the image containing the estimated position of the junction. Features of the second region are obtained, and those features are input to an adaptive model to generate data characterizing the junction.
US09501822B2	Computer-implemented platform for automated fluorescence imaging and kinetic analysis Automatically selecting time traces from a fluorescence experiment, in one aspect, may include capturing results of the fluorescence experiment in a moving image; localizing sources of fluorescence in the moving image; producing time traces of each fluorescent source by monitoring fluorescence intensity of said localized sources in the moving image over time; removing unuseful time traces from said produced time traces; and selecting useful time traces from said produced time traces based on one or more defined criteria. FRET traces from selected time traces may be further calculated and analyzed. A unified computer-implemented platform in one aspect may include tools to locate single molecules, extract traces, classify smFRET traces according to adjustable parameters, and quantify the kinetic parameters of FRET transitions using analytical procedures such as Hidden Markov Modeling (HMM) procedures.
US09501818B2	Local multiscale tone-mapping operator In a method to generate a tone-mapped image from a high-dynamic range image (HDR), an input HDR image is converted into a logarithmic domain and a global tone-mapping operator generates a high-resolution gray scale ratio image from the input HDR image. Based at least in part on the high-resolution gray scale ratio image, at least two different gray scale ratio images are generated and are merged together to generate a local multiscale gray scale ratio image that represents a weighted combination of the at least two different gray scale ratio images, each being of a different spatial resolution level. An output tone-mapped image is generated based on the high-resolution gray scale image and the local multiscale gray scale ratio image.
US09501815B2	Processing panoramic pictures Various implementations relate to processing pictures. In one particular implementation, a cropped picture is accessed. The cropped picture has been cropped, using a virtual camera window, from a picture in a sequence of pictures. Motion blur is generated for a feature in the cropped picture based on a motion of the virtual camera window and a motion of the feature. The generated motion blur is added to the feature in the cropped picture. In another particular implementation, a signal or signal structure includes a picture section for a cropped picture that has been cropped, using a virtual camera window, from a picture in a sequence of pictures. The signal or signal structure also includes a motion section for an indication of a motion of the virtual camera window.
US09501811B2	Resizing an image The invention notably relates to computer-implemented method for resizing an image I. The method comprises the steps of: providing the image I to resize; and providing an image significance by computing a significance of each pixel in the image to resize. An original spatial domain (Ω) of the significance image is extracted. A transformation Tθ, parameterized as an interpolating spline by a set of control points, is provided from Ω to a resized spatial domain Ω′; subdividing Ω into cells, each cell being defined by a subset of control points of the set. For each cell, a weighted average of the significance of the pixels in the cell is computed, the weighted average being computed using the interpolating spline. The cells of Ω are deformed by displacing one or more control points of the cells having a lesser weighted average. The transformation Tθ over a spatial domain of the image I is computed using the displaced one or more control points. A resized image J is computed by applying the computed transformation Tθ to the spatial domain of the image I to resize.
US09501809B2	System and method for photorealistic imaging workload distribution A graphics client receives a frame, the frame comprising scene model data. A server load balancing factor is set based on the scene model data. A prospective rendering factor is set based on the scene model data. The frame is partitioned into a plurality of server bands based on the server load balancing factor and the prospective rendering factor. The server bands are distributed to a plurality of compute servers. Processed server bands are received from the compute servers. A processed frame is assembled based on the received processed server bands. The processed frame is transmitted for display to a user as an image.
US09501808B2	Division of processing between systems based on business constraints A method includes acts for a method of rendering a result derived from a set of data by performing data processing across first and second data processing systems. The amount of processing performed by the second data processing system can be dynamically adjusted depending on business factors. The first data processing system receives information defining how the result will be rendered. The first data processing system receives information indicating at least one business constraints affecting at least one of the first data processing system or the second data processing system. The first data processing system determines data processing needed for providing the result. The first data processing system dynamically allocates the needed data processing between the first data processing system and the second data processing system, based on the business constraints affecting at least one of the first data processing system or the second data processing system.
US09501806B2	Method of creating or updating a container file for storing image files A method of managing a container file for storing data files includes creating a container file including a container file metadata section by creating one or more empty records in a storage device. Each record of the one or more empty records has a data file section reserved for storing a data file, a file metadata section reserved for storing metadata about the data file, and a record metadata section including information about the record and having at least a record status mark indicating that the record is empty. The method further includes setting a container status mark in the container file metadata section to available, after creating the container file.
US09501805B2	Methods and systems for optimizing a building design Methods and systems for optimizing a building design. A geographic location and a human comfort zone are identified. It is determined whether to adjust the building design based on information comprising building simulated delivered energy data and whether the building design meets pre-determined comfort conditions.
US09501803B2	Devices, systems, and methods for monitoring energy systems Certain exemplary embodiments can provide a system, which can comprise a set of electrical energy monitoring devices. Each of the set of electrical energy monitoring devices can be adapted to be mounted in a circuit breaker panel substantially adjacent to a corresponding circuit breaker. The system can comprise an energy monitoring master controller adapted to be communicatively coupled to each of the set of electrical energy monitoring devices.
US09501800B2	Centralized transaction record storage Methods and systems according to one or more embodiments are provided for storing online transaction records associated with user-merchant transactions. In an embodiment, a system comprises one or more processors. The system also comprises one or more memories adapted to store a plurality of machine-readable instructions which when executed by the one or more processors are adapted to cause the system to: receive transaction information captured and passed from a client device in response to the client device determining that information or content provided by a merchant server comprises transaction information, wherein the transaction information is associated with a user-merchant transaction; and store the received transaction information in a searchable machine-readable transaction record associated with a user account.
US09501799B2	System and method for determination of insurance classification of entities Systems and methods are disclosed herein for determining an insurance evaluation based on an industrial classification. The system may be configured to receive an electronic resource address relating to an entity, access data relating to the entity using the electronic resource address, tokenize the data, generate token counts based on the tokenized data; and apply at least one computerized predictive model to the token counts to determine one or more classifications associated with the entity. The system may further be configured to conduct evaluations of insurability, fraud determinations and other processes using the determined classification(s).
US09501794B2	Prediction market system and methods Systems and methods for operating a prediction market, including methods for finding disagreement with the consensus among participants and methods for managing liquidity. Also, an interactive user interface to facilitate investing, with one user action, in a prediction market.
US09501785B2	Using feedback reports to determine performance of an application in a geographic location Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for ranking applications. In one aspect, a method includes receiving, from a computing device, a feedback report related to an application configured to run on the computing device, the feedback report including information indicative of an error with the application, and a geographic location of the computing device at a time when the application encountered the error; generating, based on the feedback report, one or more metrics indicative of a performance of the application in the geographic location; retrieving information indicative of other applications associated with metrics indicative of a performance of the other applications in the geographic location; and ranking the applications in accordance with the metrics indicative of the performance of the applications in the geographic location.
US09501780B2	Surveying wireless device users by location The present invention is a system and method for conducting survey using wireless devices. The system architecture of the present invention comprises a location server and a location system. The location server can receive a survey request from a subscriber, delineate a survey area for the survey, broadcast a query containing the survey to a plurality of wireless devices, process responses received from the wireless devices, and deliver a result of the survey to the subscriber. The location system can generate location information for each of the wireless devices that received the query. The location system may be a network-based unit or a portable unit provisioned at each of the wireless devices. In one of the embodiments, the location system is a GPS receiver that generates the longitude and the latitude of the wireless devices at which it is provisioned.
US09501778B2	Delivering personalized recommendations that relate to transactions on display Provided are techniques for providing personalized recommendations. One or more transactions are received from one or more customer interaction channels. The received one or more transactions are stored in an incremental data store. One or more predictive rules are generated based on the received one or more transactions and based on one or more transactions previously stored in the incremental data store. In real-time, one or more personalized recommendations specific to a user and to the received one or more transactions are generated using the one or more generated predictive rules.
US09501774B2	Method and apparatus for using at least a portion of a one-time password as a dynamic card verification value Method and apparatus for using at least a portion of a one-time password as a dynamic card verification value (CVV) are disclosed. A credit/debit card is able to generate a dynamic card verification value (CVV). Such a card may also include an indication that the dynamic CVV is to be used as a security code for purchasing or other transactions. A card-based financial transaction can be authorized in accordance with the use of a dynamic CVV by receiving a transaction authorization request for a specific credit/debit card, wherein the transaction authorization request includes a dynamic CVV. The dynamic CVV can be compared to at least a portion of a one-time password generated for the specific credit/debit card, and a transaction authorization can be sent to the merchant or vendor when the dynamic CVV matches all or a portion of the one-time password.
US09501773B2	Secured transaction system The present invention relates to a secured transaction system. In one embodiment, a mobile transaction processing agent system includes a communication module configured to receive a secured transaction description from a mobile client device or an encrypted transaction description from a point-of-sale (POS) device, wherein the secured transaction description is in the form of a bar code generated by the mobile client device, an authentication module configured to decode the secured transaction description and verify the secured transaction description is valid based on the mobile client device or the point-of-sale device, and a transaction processing module configured to process the transaction in accordance with the secured transaction description.
US09501772B2	Systems, methods and apparatuses for secure digital transactions A method for authorizing recurring transaction according to one embodiment includes receiving a defined payment amount associated with a user or entity. Additionally, the method includes receiving a first code associated with a first predetermined currency value, where the first code is also associated with the user or entity. Furthermore, the method includes verifying an availability of funds to pay the defined payment amount and authorizing payment of the defined payment amount if funds are available to pay the defined payment amount. Further still, the method includes generating a new code associated with a new predetermined currency value, and sending the new code to a sender of the defined payment amount.
US09501765B2	Preparing preliminary transaction work for a mobile banking customer Embodiments of the invention are directed to systems, methods and computer program products for transaction queuing. In some embodiments, a system is configured to: receive information associated with an intended transaction, wherein a user will execute the intended transaction at a facility at a user-defined time; determine preliminary work associated with the intended transaction that can be performed prior to the user-defined time; and perform the preliminary work associated with the intended transaction. The preliminary work is placed on a transaction queue until the user arrives at the facility.
US09501749B1	Classification and non-parametric regression framework with reduction of trained models A device receives selection of a classification and regression framework, and receives training data for the classification and regression framework. The device applies the training data to the classification and regression framework to generate a trained model, and monitors performance of the trained model. The device inspects a structure of the trained model, and reduces a size of the trained model. The device generates an object based on the trained model, and provides the object for display.
US09501747B2	Systems and methods that formulate embeddings of problems for solving by a quantum processor Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph. In a second stage, the connected subgraphs are refined such that no vertex represents more than a single decision variable.
US09501745B2	Method, system and device for inferring a mobile user's current context and proactively providing assistance A device, method and system for automatically inferring a mobile user's current context includes applying a user activity knowledge base to real-time inputs and stored user-specific information to determine a current situation. Automated reasoning is used to infer a user-specific context of the current situation. Automated candidate actions may be generated and performed in accordance with the current situation and user-specific context.
US09501742B2	System and method for assessing categorization rule selectivity Assessment of selectivity of categorization rules. One or more categorization rules are applied to a set of un-categorized objects to produce a categorization result set representing assignment of objects the set into at least two categories. A selectivity score for the at least one categorization rule is obtained based on statistical information. The numerical selectivity score represents an estimation of accuracy of the at least one categorization rule, and is produced as a result of application of at least one trained selectivity determination algorithm, which is based on application of a plurality of specially-selected categorization rules to a set of pre-categorized training data, with the application of each one producing a uniform grouping of objects.
US09501741B2	Method and apparatus for building an intelligent automated assistant A method and apparatus are provided for building an intelligent automated assistant. Embodiments of the present invention rely on the concept of “active ontologies” (e.g., execution environments constructed in an ontology-like manner) to build and run applications for use by intelligent automated assistants. In one specific embodiment, a method for building an automated assistant includes interfacing a service-oriented architecture that includes a plurality of remote services to an active ontology, where the active ontology includes at least one active processing element that models a domain. At least one of the remote services is then registered for use in the domain.
US09501738B1	Cellular computational platform and neurally inspired elements thereof A cellular computational platform is disclosed that includes a multiplicity of functionally identical, repeating computational hardware units that are interconnected electrically and optically. Each computational hardware unit includes a reprogrammable local memory and has interconnections to other such units that have reconfigurable weights. Each computational hardware unit is configured to transmit signals into the network for broadcast in a protocol-less manner to other such units in the network, and to respond to protocol-less broadcast messages that it receives from the network. Each computational hardware unit is further configured to reprogram the local memory in response to incoming electrical and/or optical signals.
US09501736B2	Systems and methods for breakaway RFID tags A breakaway RFID tag is configured such that it comprises part of a Printed Circuit Board Assembly (PCB). Thus, the breakaway RFID tag can be used to track the PCB as it migrates through a manufacturing process. In one embodiment, the RFID tag can be assembled first and then used to track the PCB as it is populated with components and installed into larger assemblies and ultimately into the end device. Once the PCB is installed into a larger assembly or the end device, the breakaway RFID tag is configured such that it can be broken off and attached to the outside of the larger assembly or end device.
US09501734B2	RFID tag An RFID tag for location inside a tubular base portion of a freestanding cryogenic vial, the RFID tag comprising: an RFID chip; an antenna connected to the chip; a support medium configured to support the chip and connected antenna; and a plug at least partially surrounding the chip, the antenna and the support medium, the plug being shaped to engage the tubular base portion of the vial. The RFID tag may be used to retrofit vials already stored at cryogenic temperatures.
US09501733B2	Method of manufacturing a functional inlay The method of manufacturing a functional inlay comprises the steps of: —) providing a support layer with at least a first and a second side —) embedding a wire antenna in said support layer —) processing said support layer with said embedded wire antenna to a connection station in which —) said support layer is approached on said first side by a holding device holding a chip with a surface comprising connection pads; —) said support layer is approached on said second side by a connection device; and —) said antenna wire is connected to said connection pads by means of a reciprocal pressure exerted between said holding device and said connection device.
US09501731B2	Multi-frequency transponder The invention concerns a multi-frequency transponder for communicating at a first frequency according to a first communication protocol and at a second different frequency according to a second communication protocol. The transponder comprises a first physical memory for storing a first data of the first communication protocol; a second physical memory for storing a second data, different from the first data, of the second communication protocol; and a logic unit for accessing the first and second physical memories. The logic unit comprises a first control unit for handling communications according to the first protocol, and a second control unit for handling communications according to the second protocol. The transponder comprises a mapping memory to store a logical memory map of the first or second physical memories. The logical memory map comprises mapping information for the first or second control unit to access data items in first and second physical memories.
US09501730B2	Optical barcodes having spatially phase shifted clock and reference tracks Barcodes are provided that are applied to or integrated with a moving carrier, where the barcodes have a plurality of information modules, at least one clock track having a plurality of alternating clock track modules and at least one reference track having a plurality of alternating reference track modules, where the at least one reference track is a second clock track and has a same periodicity as the clock track but a spatial phase shift when compared to the clock track. The barcode is configured to allow at least one barcode reader to determine a direction of movement of the carrier from at least one signal from a clock track detector and at least one signal from a reference detector.
US09501720B2	Object detection apparatus An object detection apparatus for detecting a target object in an input image. The apparatus includes a storage storing, for each of a plurality of part areas forming an area subject to image recognition processing, image recognition dictionaries used to recognize a target object and typed according to variations in appearance of a part of the target object to be detected in the part area. A part score calculator calculates, for each of the part areas, a part score indicative of a degree of similarity between the part area and each of at least some of the image recognition dictionaries. An integrated score calculator calculates an integrated score that is a weighted sum of the part scores for the respective part areas. A determiner determines, on the basis of the integrated score, whether or not the target object is present in the subject area.
US09501717B1	Method and system for coding signals using distributed coding and non-monotonic quantization A method reconstructs and an uncompressed signal by first obtaining an encoded signal corresponding to the uncompressed signal, wherein the encoded signal includes universally quantized dithered linear measurements of the signal, and wherein each universally quantized dithered linear measurement is a quantized dithered linear measurement of the signal missing one or more significant bits. Side information about the signal is obtained, and the side information is used to obtain a prediction of the signal. The missing one or more significant bits are determined from the encoded signal using the prediction of the signal and the missing one or more significant bits are combined with the encoded signal to produce quantized dithered linear measurements of the signal. Then, the signal can be reconstructed as a reconstructed signal using the quantized dithered linear measurements.
US09501716B2	Labeling component parts of objects and detecting component properties in imaging data Techniques related to labeling component parts and detecting component properties in imaging data are discussed. Such techniques may include generating a feature vector including invariant features associated with an area of interest within an image of an object such as an image of a hand and providing a component label such as a hand part label for the area of interest based on an application of a machine learning classifier to the feature vector.
US09501715B2	Method for detecting salient region of stereoscopic image The present invention discloses a method for detecting a salient region of a stereoscopic image, comprising: step 1) calculating flow information of each pixel separately with respect to a left-eye view and a right-eye view of the stereoscopic image; step 2) matching the flow information, to obtain a parallax map; step 3) selecting one of the left-eye view and the right-eye view, dividing it into T non-overlapping square image blocks; step 4) calculating a parallax effect value for each of the image blocks of the parallax map; step 5) for each of the image blocks of the selected one of the left-eye view and the right-eye view, calculating a central bias feature value and a spatial dissimilarity value, and multiplying the three values, to obtain a saliency value of the image block; and step 6) obtaining a saliency gray scale map of the stereoscopic image from saliency values of the image blocks. The present invention provides a method for extracting stereoscopic saliency based on parallax effects and spatial dissimilarity, acquiring depth information by utilizing parallax, and combining visual central bias feature and spatial dissimilarity to realize more accurate detection of a stereoscopic salient region.
US09501713B2	Method of producing compact descriptors from interest points of digital images, corresponding system, apparatus and computer program product Compact descriptors of digital images are produced by detecting interest points representative of the digital images and selecting out of the interest points key points for producing e.g. local and global compact descriptors of the images. The digital images are decomposed into blocks by computing an energy (variance) for each said block and then subjecting the blocks to culling by rejecting those blocks having an energy failing to pass an energy threshold. The interest points are detected only in the blocks resulting from culling, and the key points for producing the compact descriptors are selected out of the interest points thus detected, possibly by using different selection thresholds for local and global compact descriptors, respectively. The number of key points for producing the compact descriptors may be varied e.g. by adaptively varying the number of the interest points detected in the blocks resulting from culling.
US09501712B2	Device for detecting edges and improving the quality of an image Device for edge detection and quality enhancement in an image which comprises a grouping of identical and locally interconnected elementary processing cells. Each processing cell is characterized in turn by a comparator which carries out in parallel the comparison of each pair of neighboring pixels. The threshold voltage which establishes the difference in voltage between pixels considered to be part of an edge is determined by means of a temporary adjustment of a control signal. This adjustment, along with that of the filtering control signal, also temporary in nature, are the only ones necessary for configuring the required processing. No external analog control signals are required making it easier to program the hardware by the device which is used and reducing the number of digital/analog converters of the final system.
US09501711B2	Image processing method and image processing device with correction of pixel statistical values to reduce random noise The present invention is a method including: correcting difference between a pixel statistical value of a specific layer and a pixel statistical value of a layer that is wider than the specific layer using an edge information of a layer that is wider than the specific layer; correcting the pixel statistical value of the specific layer using post-correction difference and the pixel statistical value of layer that is wider than the specific layer; recorrecting the post-correction pixel statistical value of the specific layer using difference between a pre-correction pixel statistical value of the specific layer and the post-correction pixel statistical value of the specific layer and the edge information of a layer that is wider than the specific layer; and correcting the target pixel by repeating correction and recorrection until the layer reduces its range from the maximum range to the minimum range.

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