最新美国发明专利第2016-08-16期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09419318B2	Method of producing photoelectric conversion element, photoelectric conversion element and photoelectrochemical cell A method of producing a photoelectric conversion element, which contains an electrically conductive support, a photosensitive layer having porous semiconductor fine particles that have adsorbed a dye formed on the support, a charge transfer layer; and a counter electrode; containing the steps of: applying a dispersion liquid, in which the content of solids excluding semiconductor fine particles is 1% by mass or less based on the total amount of the dispersion liquid, on the support, to form a coating; heating the coating, to obtain porous semiconductor fine particles; and sensitizing the porous semiconductor fine particles by a dye having a structure represented by Formula (1): M(LL1)m1(LL2)m2(X)m3·CI Formula (1) wherein M represents a metal atom, LL1, LL2, and X each are a ligand, CI represents a counter ion, m1 represents an integer of 1 to 3, m2 and m3 each represent an integer of 0 to 2.
US09419315B2	Polymerized lithium ion battery cells and modules with permeability management features A lithium ion (Li-ion) battery module includes a container with one or more partitions that define compartments within the container. Each of the compartments is configured to receive and hold a prismatic Li-ion electrochemical cell element and electrolyte. The Li-ion battery module also includes a cover configured to be disposed over the container to close the compartments. The container includes an electrically nonconductive polymeric material (e.g., plastic) with a nanomaterial applied to the polymeric material. The nanomaterial enhances the impermeability of the container to reduce ingress of moisture into the compartments and to reduce egress of the electrolyte from the compartments.
US09419314B2	Systems and methods for determining battery system power capability System and methods for determining battery system power capability in a vehicle are presented. Peak power capability estimation systems and methods disclosed herein may compensate regressed parameters in a battery system circuit model for an effect of current magnitude. Utilizing the disclosed methods for accurately estimating peak power capability of a battery system may provide for, among other things, improved battery system performance modeling and/or improved battery system control and management decisions.
US09419312B2	Disablement of connection between connection module and battery Embodiments herein relate to disablement of a connection between a battery and a connection module. In an embodiment, a connection between the battery and a connection module may be disabled if the connection module is drawing current from the battery or if a monitored signal transitions from a high logic level to the low logic level. The connection module is to draw the current or pull the signal down to a low logic level in response to one or more components related to the device becoming exposed or an enclosure related to the device being breached or opened.
US09419310B2	Battery pack A battery pack is disclosed. The battery pack includes a battery cell, a protection circuit module, and a temperature sensor, which are each held by a case. The case includes a dedicated space for the temperature sensor and a fixing element to fix the temperature sensor in the dedicated space.
US09419305B2	Electrolyte for rechargeable lithium battery and rechargeable lithium battery including same An electrolyte for rechargeable lithium battery includes a lithium salt, a non-aqueous organic solvent, a first additive represented by the following Chemical Formula 1, and a second additive represented by the following Chemical Formula 2. A rechargeable lithium battery includes the electrolyte.
US09419296B2	Integrated design of burner, reformer and heat exchangers for the solid oxide fuel cell Thermotechnical units of solid oxide fuel cell (SOFC) are integrated as a whole one. The units may include a burner, a reformer and a heat exchanger. The integrated units can be easily assembled into an SOFC system with cell stacks. Thus, the present invention has a simple structure, operates with ease, saves operational cost, runs with fewer utilities, decreases heat dissipation and enhances system performance.
US09419292B2	Management of operation of PEM-fuel-cell-stack backup electric generator A PEM-fuel-cell-stack backup electric generator comprising: a fuel-cell stack, formed by a plurality of stacked PEM fuel cells electrically connected in series for supplying electrical energy to an electrical load; a cell-voltage monitor for measuring the voltage supplied by each fuel cell; an electrical-energy management and conditioning unit, connected between the fuel-cell stack and the electrical load; a blower for supplying the amount of air necessary for the chemical reactions that occur in the fuel cells; a hydrogen recirculator for recirculating hydrogen between the outlet and the inlet of the fuel-cell stack; a hydrogen-purging device for carrying out a primary purging of hydrogen at a lower flow rate, and a secondary purging of hydrogen at a higher flow rate; and a controller, programmed for managing operation of the electric generator differently at start-up, at shut-down, and during normal operation thereof.
US09419291B2	Moving body A moving body, such as a vehicle, having one or more fuel cells mounted thereon. The fuel cells, which power the moving body, generate electricity and release water as a by-product. Accordingly, the moving body includes a water discharge module that releases water produced by the fuel cells to the atmosphere using a water outlet. The water outlet may be located in a front section of the moving body. The moving body may further include a water tank that temporarily stores water before releasing the water to the atmosphere.
US09419288B2	Thermal battery for power systems An improved emergency power system is disclosed for providing electrical power to a load such as a blowout preventer of a petroleum drilling apparatus. The improved emergency power system comprises a thermal battery having an anode and a cathode with a separator containing an electrolyte disposed therebetween. An internal heat layer is located in proximity to the separator containing the electrolyte. A squib is provided for activating the internal heat layer. The thermal battery remains dormant until the squib is energized to ignite the squib enabling the heat layer to render the electrolyte molten thereby activating battery to provide electrical power to the load. The squib may be energized remotely, mechanically or electrically.
US09419286B2	Wet lamination process for reducing mud cracking in fuel cell components Methods of making a substantially crack-free electrode layer are described. The methods include depositing an electrode ink on a substrate; placing a layer of porous reinforcement layer on a surface of the wet electrode ink; and drying the electrode ink to form the substantially crack-free electrode layer on the substrate. Substantially crack-free electrode layers and fuel cells incorporating substantially crack-free electrode layers are also described.
US09419280B2	Cathode active material, cathode and nonaqueous secondary battery A cathode active material of the present invention is a cathode active material having a composition represented by General Formula (1) below, LiFe1−xMxP1−ySiyO4 (1), where: an average valence of Fe is +2 or more; M is an element having a valence of +2 or more and is at least one type of element selected from the group consisting of Zr, Sn, Y, and Al; the valence of M is different from the average valence of Fe; 0
US09419279B2	Vanadium battery A solid vanadium rechargeable battery, including; a first vanadium compound containing vanadium, whose oxidation number changes between 2 and 3 due to oxidation and reduction reactions, or solid vanadium salt or complex salt including such vanadium, and a surface that becomes a negative electrode; a second vanadium compound containing vanadium, whose oxidation number changes between 5 and 4 due to reduction and oxidation reactions, or solid vanadium salt or complex salt including such vanadium, and a surface that becomes a positive electrode; and a separator sandwiched between the first and the second vanadium compounds for selectively allowing ions to pass through, is provided.
US09419277B2	Composite metal precursor, electrode active material prepared from the same, positive electrode including the same, and lithium secondary battery employing the same A composite metal precursor including a composite metal hydroxide represented by Formula 1 below, wherein an amount of magnesium (Mg) in the composite metal hydroxide is less than or equal to 0.005 wt %, an electrode active material formed from the same, a positive electrode including the same, and a lithium secondary battery employing the same: (A1-x-yBxCy)(OH)2 [Formula 1] wherein in Formula 1, x, y, A, B, and C are as described in the detailed description.
US09419275B2	Electrode material for a lithium-ion battery and a method of manufacturing the same An electrode material for a lithium-ion battery comprises a porous agglomeration of particles, the particles being formed from nanopowder of a transition metal oxide and comprising cores of stoichiometric transition metal oxide surrounded by under stoichiometric oxide of the transition metal. Also described and claimed are the use of a corresponding material in a lithium ion battery and a method of making such an electrode.
US09419272B2	Negative active material for rechargeable lithium battery, method of preparing same, and rechargeable lithium battery including same Disclosed are a negative active material for a rechargeable lithium battery including lithium silicide having a I41-a crystalline phase structure, a method of manufacturing the same, and a rechargeable lithium battery including the same.
US09419271B2	Electrode material and method for forming electrode material An object is to provide an electrode material with high electrical conductivity and a power storage device using the electrode material. An object is to provide an electrode material with high capacity and a power storage device using the electrode material. Provided is a particulate electrode material including a core containing a compound represented by a general formula Li2MSiO4 (in the formula, M represents at least one kind of an element selected from Fe, Co, Mn, and Ni) as a main component, and a covering layer containing a compound represented by a general formula LiMPO4 as a main component and covering the core. Further, a solid solution material is provided between the core and the covering layer. With such a structure, an electrode material with high electrical conductivity can be obtained. Further, with such an electrode material, a power storage device with high discharge capacity can be obtained.
US09419268B2	Secondary battery and circuit board assembly suitable for secondary battery Disclosed are a secondary battery and a circuit board assembly suitable for the secondary battery. The secondary battery includes a bare cell including an electrode terminal, a circuit board electrically connected to the electrode terminal and arranged on a top surface of the bare cell. The circuit board includes an installation part having a smaller thickness than rest of the circuit board. The secondary battery further includes a temperature device installed on the installation part of the circuit board to sense temperature variation of the bare cell.
US09419253B2	Battery pack and its fabricating method, battery, and electronic device The present invention provides a battery pack and its fabricating method, a battery and an electronic device. The battery pack provided by the present invention comprises: an outer package, which is in a laminated form and has a conductive layer therein; and a battery cell, which has a positive electrode terminal and a negative electrode terminal and is housed in the outer package, wherein, the positive electrode terminal or the negative electrode terminal of the battery cell is electrically connected to said conductive layer at the part led out from the outer package. With the battery pack and its fabricating method provided by the present invention, the influence of electrostatic discharge can be eliminated with a more simple structure.
US09419247B2	Organic light emitting diode device and manufacturing method thereof An organic light emitting diode device can have an enhanced thin film encapsulation layer for preventing moisture from permeating from the outside. The thin film encapsulation layer can have a multilayered structure in which one or more inorganic layers and one or more organic layers are alternately laminated. A barrier can be formed outside of a portion of the substrate on which the organic light emitting diode is formed. The organic layers of the thin film encapsulation layer can be formed inside an area defined by the barrier.
US09419245B2	Organic el display device In an organic EL display device configured in which an acrylic resin layer is disposed under a barrier layer that protects an OLED for flattening the barrier layer, floating the barrier layer caused by penetration of moisture into the acrylic resin can be prevented. A side surface of a bank formed in a boundary of pixels is formed into a cliff part having an inclination angle of 90° or larger in most portions of a circumstance of each pixel part, and formed into a gently sloped part having the inclination angle smaller than 90° in a part of the circumference. The electrode parts disposed within the respective pixels are connected to each other through an electrode part disposed on an upper surface of the bank, and electrode parts disposed on the gently sloped parts to form an OLED common electrode.
US09419241B2	Organic electroluminescent element An organic electroluminescent element includes: first and second electrodes; and luminous units between the electrodes on a substrate, adjacent luminous units each being separated by an intermediate electrode layer, wherein at least one of the electrodes is a transparent electrode; the luminous units are each an organic functional layer including an organic luminous layer; the intermediate electrode layer includes an independent connecting terminal for electrical connection; a thin-film layer is disposed on a surface of the transparent electrode being at least one of the electrodes; and the thin-film layer has a variable refractive index across a thickness of the thin-film layer, the variable refractive index having an extreme value at which the refractive index changes from an increase to a decrease or an extreme value at which the refractive index changes from a decrease to an increase.
US09419237B2	Organic compound, light-emitting element, light-emitting device, electronic device, and lighting device A novel organic compound having a high hole-transport property is provided. A long-lifetime light-emitting element is provided. An organic compound represented by General Formula (G0) is provided. In General Formula (G0), Ar1 represents a substituted or unsubstituted naphthyl group, Ar2 represents a substituted or unsubstituted carbazolyl group, Ar3 represents a substituted or unsubstituted fluorenyl group or a substituted or unsubstituted spirofluorenyl group, and α1 and α2 each independently represent a substituted or unsubstituted phenylene group or a substituted or unsubstituted biphenyldiyl group.
US09419232B2	Nanostructured organic materials and a process for the preparation thereof The invention disclosed nanostructured organic materials and a process for the preparation thereof. Further the present invention herein provides nanostructured organic material comprising divalent zinc metal complex of N,N′-Di-(phenyl-3,5 dicarboxylic acid)-perylene-3,4,9,10-tetracarboxylic acid diimide doped with hydrazine hydrate, which exhibits increased charge carrier mobility at low operating voltage at atmospheric condition useful in organic field effect transistors (OFETs).
US09419230B2	Compound for organic optoelectronic device, organic light emitting diode including the same, and display device including the organic light emitting diode A compound for an organic optoelectronic device, an organic light emitting diode including the same, and a display device including the organic light emitting diode are disclosed, and the compound for an organic optoelectronic device represented by Chemical Formula 1 is provided to manufacture an organic optoelectronic device having improved life-span characteristics due to excellent electrochemical and thermal stability, and high luminous efficiency at a low driving voltage.
US09419229B2	Compound, organic optoelectric device including the same and display device including the optoelectric device Disclosed are a compound for an organic optoelectric device, an organic optoelectric device including the same and a display device including the organic optoelectric device, wherein the compound for an organic optoelectric device is represented by the following Chemical Formula 1, In the above Chemical Formula 1, R1 to R7, X, L1 and L2 are the same as described in the detailed description.
US09419227B2	Spirally configured cis-stilbene/fluorene hybrid materials as hole-blocking type electron-transporters for OLED An OLED (organic light emitting diode) comprises a series of spirally configured cis-stilbene/fluorene hybrid materials. The spirally configured cis-stilbene/fluorene hybrid materials are spirally-configured cis-stilbene/fluorene derivatives having the functions to block holes and constructed by at least one cis-Stilbene based component and at least one fluorene based component.
US09419226B2	Condensed fluoranthene compound, material for organic electroluminescent element using this compound, organic electroluminescent element using this material, and electronic device A fused fluoranthene compound which includes an indeno[3,2-b]fluoranthene skeleton having a hetero atom is a novel compound, which is useful as a material for organic electroluminescence devices for use in an organic electroluminescence device and an electronic equipment.
US09419225B2	Organic electroluminescent materials and devices A compound according to a formula I, devices incorporating the same, and formulations including the same are described. The compound according to the formula I can have the structure wherein R1, R2, R3, R4, R5 and R6 each represent mono, di, tri, tetra substitutions, or no substitution, R9 represents mono, di, tri substitutions, or no substitution, R1, R2, R3, R4, R5, R6 and R9 are each independently selected from the group consisting of hydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acid, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof. A1, A2, A3, A4, A5, and A6 are each independently selected from N or C and n is an integer from 1 to 20.
US09419218B2	Resistance variable memory structure and method of forming the same A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.
US09419216B2	Phase change memory cell and phase change memory A phase change memory cell includes a carbon nanotube layer, a phase change layer, a first electrode, a second electrode, and a third electrode. At least part of the phase change layer is overlapped with the carbon nanotube layer. The first electrode and the second electrode are electrically connected with the carbon nanotube layer, wherein the first electrode and the second electrode are configured to apply a first voltage to the carbon nanotube layer. The third electrode is electrically connected with the phase change layer, wherein the third electrode and the first electrode are configured to apply a second voltage to the phase change layer.
US09419215B2	Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.
US09419212B2	Barrier film techniques and configurations for phase-change memory elements Embodiments of the present disclosure describe barrier film techniques and configurations for phase-change memory elements. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a bottom electrode layer, a select device layer disposed on the bottom electrode layer, a middle electrode layer disposed on the select device layer, a phase-change material layer disposed on the middle electrode layer, a top electrode layer disposed on the phase-change material layer, and a barrier film comprising a group IV transition metal, a group VI transition metal, carbon (C) and nitrogen (N), the barrier film being disposed between the bottom electrode layer and the top electrode layer. Other embodiments may be described and/or claimed.
US09419211B2	Etching method and substrate processing apparatus A gas for an etching process and a treatment process of a metal stacked film in which an insulating layer is interposed between two layers of magnetic materials can be optimized. An etching method of etching a multilayered film including a metal stacked film in which an insulating layer is interposed between a first magnetic layer and a second magnetic layer includes etching the metal stacked film with plasma generated by supplying a gas containing at least C, O, and H into a processing chamber; and treating the metal stacked film with plasma generated by supplying a gas containing at least a CF4 gas into the processing chamber.
US09419208B2	Magnetoresistive memory element and method of fabricating same A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
US09419207B2	Magnetic random access memory with multilayered seed structure The present invention is directed to a magnetic random access memory element that includes a multilayered seed structure formed by interleaving a first type sublayer and a second type sublayer to form one or more repeats of a unit bilayer structure and a first magnetic layer formed on top of the multilayered seed structure. The unit bilayer structure is made of the first and second type sublayers with at least one of the first and second type sublayers including therein one or more ferromagnetic elements. The multilayered seed structure may be amorphous or non-magnetic or both. The unit bilayer structure may be made of CoFeB and Ta sublayers.
US09419201B2	Integrating a piezoresistive element in a piezoelectronic transistor A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.
US09419196B2	Oxide nanoparticle-dispersed, chalcogenide-based, and phase-separated composite thermoelectric material Provided is a thermoelectric material containing: a matrix containing a Group 13 element of chalcogenide; and oxide nanoparticles dispersed into the matrix to have excellent thermal stability, wherein the oxide nanoparticle forms a coherent interphase interface with the Group 13 element of the chalcogenide-based matrix and is elongated in a specific direction, such that thermal conductivity may be effectively decreased with a trace amount of the oxide nanoparticle to minimize deterioration of electric conductivity.
US09419194B2	Transparent electron blocking hole transporting layer A light emitting diode includes an active region configured to emit light, a composite electrical contact layer, and a transparent electron blocking hole transport layer (TEBHTL). The composite electrical contact layer includes two materials. At least one of the two materials is a metal configured to reflect a portion of the emitted light. The TEBHTL is arranged between the composite electrical contact layer and the active region. The TEBHTL has a thickness that extends at least a majority of a distance between the active region and the composite electrical contact layer. The TEBHTL has a band-gap greater than a band-gap of light emitting portions of the active region. The band-gap of the TEBHTL decreases as a function of distance from the active region to the composite electrical contact layer over a majority of the thickness of the TEBHTL.
US09419190B2	Potted optoelectronic module having a plurality of semiconductor components and method for producing an optoelectronic module An optoelectronic semiconductor component comprising: a main body (100) having a recess; (102), a first optoelectronic element (104) and a second optoelectronic element; (106) a surface structured element; (110) and a filling compound (112) embedding the first optoelectronic element (104) and the second optoelectronic element (106) in the recess, wherein the surface structured element configures a surface of the filling compound (112) such that at least two domed regions (114, 116, 118) of the surface are formed.
US09419189B1	Small LED source with high brightness and high efficiency Small LED sources with high brightness and high efficiency apparatus including the small LED sources and methods of using the small LED sources are disclosed.
US09419187B2	Light emitting device and method of manufacturing thereof A light emitting device includes a package having side walls which define a recess, a light emitting element arranged in the recess, and a sealing member which seals the light emitting element. The sealing member includes a first portion which contains a fluorescent material and covers the light emitting element, and a second portion which does not contain a fluorescent material and is arranged over the first portion. The fluorescent material is a fluoride fluorescent material activated with tetravalent manganese represented by the following formula (I). The particles of the fluorescent material has a surface region with a tetravalent manganese ion concentration is lower than inner side. A2[M1-bMn4+bF6] (I) In the formula (I), A is a cation which contains K+ and may contain at least one selected from the group consisting of Li+, Na+, Rb+, Cs+, and NH4+, M is at least one of 15 Group 4 and Group 14 elements, and 0
US09419185B2	Method of singulating LED wafer substrates into dice with LED device with Bragg reflector A method of dicing semiconductor devices from a substrate includes forming a Bragg reflector over a bottom side of the substrate, where the bottom side is opposite of a top side, generating a pattern of defects in the substrate with a laser beam from the bottom side of the substrate, and applying pressure to the substrate to dice the substrate along the pattern of defects. The Bragg reflector includes a first layer of dielectric material having a first index of refraction and a second dielectric material having a second index of refraction different from the first index of refraction.
US09419180B2	Light emitting diode having electrode pads A substrate, a first conductive type semiconductor layer arranged on the substrate, a second conductive type semiconductor layer arranged on the first conductive type semiconductor layer, an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, a first electrode pad electrically connected to the first conductive type semiconductor layer, a second electrode pad arranged on the second conductive type semiconductor layer, an insulation layer disposed between the second conductive type semiconductor layer and the second electrode pad, and at least one upper extension electrically connected to the second electrode pad, the at least one upper extension being electrically connected to the second conductive type semiconductor layer.
US09419176B2	Three-dimensional light-emitting device and fabrication method thereof A three-dimensional (3D) light-emitting device may include a plurality of 3D light-emitting structures formed apart from one another, each 3D light-emitting structure including: a semiconductor core vertically grown on one surface and doped in a first conductive type; an active layer formed so as to surround a surface of the semiconductor core; and a first semiconductor layer formed so as to surround a surface of the active layer and doped in a second conductive type. The 3D light-emitting device may include: a first porous insulating layer formed between lower corner portions of the 3D light-emitting structures so as to expose upper end portions of the 3D light-emitting structures; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the semiconductor core.
US09419169B2	Method for producing a semiconductor element of a direct-converting x-ray detector A production method of a semiconductor element of a direct-converting x-ray detector is disclosed, wherein at least one intermediate layer is applied to a semiconductor layer and at least one contact layer is applied to an exposed intermediate layer by chemically currentless deposition of a contact material from a solution in each instance. The materials for the individual layers are selected such that the electrochemical potential of the materials of the at least one intermediate layer is greater than the electrochemical potential of at least one element of the semiconductor layer and the electrochemical potential of the contact material of the contract layer is greater than the electrochemical potential of the materials of the intermediate layers. Semiconductor elements produced in accordance with the method, an x-ray detector with semiconductor elements, an x-ray system with an x-ray detector and also a CT system with an x-ray detector are also disclosed.
US09419168B2	Method of manufacturing a solar cell by texturing a principal surface using an alkaline solution A method of manufacturing a solar cell including a crystalline semiconductor substrate, includes: etching or washing at least part of a first principal surface of the substrate by treatment with an aqueous alkaline solution; and depositing a p-type semiconductor layer containing boron on at least part of a second principal surface of the substrate before the treatment with the aqueous alkaline solution.
US09419166B2	Etching processes for solar cell fabrication A method of fabricating a solar cell can include forming a first dopant region over a silicon substrate and an oxide region over the first dopant region. In an embodiment, the oxide region can protect the first dopant region from a first etching process. In an embodiment, a second dopant region can be formed over the silicon substrate, where a mask can be formed to protect a first portion of the second dopant region from the first etching process. In an embodiment, the first etching process can be performed to expose portions of the silicon substrate and/or a silicon region. A second etching process can be performed to form a trench region to separate a first and second doped region of the solar cell. A third etching process can be performed to remove contaminants from the solar cell and remove any remaining portions of the oxide region.
US09419164B2	Solar cell module having interconnector and method of fabricating the same A solar cell module having an interconnector and a method of fabricating the same are disclosed. The solar cell module includes a plurality of solar cells and an interconnector including a first area electrically connected to one of two adjacent solar cells of the plurality of solar cells, a second area electrically connected to the other of the two adjacent solar cells, and a third area connecting the first area to the second area. At least one of the first area and the second area of the interconnector has at least one uneven surface, and the third area of the interconnector has a substantially planarized surface.
US09419162B2	Array sensor apparatus and forming method thereof An array sensor apparatus and forming method thereof, wherein the array sensor comprises: a driving circuit and a sensor circuit, wherein the driving circuit and the sensor circuit are formed on the same substrate surface, the sensor circuit comprises a pixel cell array including pixel cells and driving lines connected with the pixel cells, output ends of the driving circuit are connected to the driving lines of the sensor circuit, the driving circuit comprises a first transistor, and the pixel cell comprises a second transistor. In the array sensor apparatus of the present disclosure, the driving circuit and the sensor circuit are formed on the same substrate surface, thus occupying less area. Reliability may be improved. Besides, the forming processes can be implemented simultaneously without additional processing steps.
US09419161B2	Hybrid multi-spectrum photosensitive pixel group, photosensitive device, and photosensitive system The present invention relates to a mixed multi-spectrum light-sensing pixel group, a light-sensing device, and a light-sensing system. The mixed multi-spectrum light-sensing pixel group includes at least one chemical coating light-sensing pixel and at least one semiconductor light-sensing pixel. In the present invention, the chemical coating light-sensing pixel and the semiconductor light-sensing pixel are combined to generate a mixed multi-spectrum light-sensing pixel, numerous color signals and other spectral signals may be simultaneously obtained, energy of incident photons can be maximally utilized, and the theoretical upper limit of photoelectric conversion efficiency is achieved or approximately achieved; colors may be completely reconstructed, and meanwhile images of other spectrums including an ultraviolet image, a near-infrared image, and a far-infrared image are obtained.
US09419156B2	Package and method for integration of heterogeneous integrated circuits A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.
US09419153B2	Process for manufacturing a solar cell and solar cell A solar cell segment includes a substrate defining a rear side including a number of base doped regions and emitter doped regions. A dielectric layer and at least one metallizing layer are disposed on the rear side of the substrate. The at least one metallizing layer is structured in an interdigital comb-shaped contact deck arrangement and defines base contact decks for a number of base doped regions and emitter contact decks for a number of base doped regions. The at least one metallization layer is disposed between the rear side of the substrate and the dielectric layer. At least one first row of first contact openings is formed in the dielectric layer lying in a region of the base contact decks and at least one second row of second contact openings is formed in the dielectric layer lying in a region of the emitter contact decks.
US09419141B2	Replacement channel The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure.
US09419140B2	Two-dimensional condensation for uniaxially strained semiconductor fins Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
US09419139B2	Nitride layer protection between PFET source/drain regions and dummy gate during source/drain etch Methods of using a nitride to protect source/drain regions during dummy gate removal and the resulting devices are disclosed. Embodiments include forming an oxide layer on a substrate; forming a nitride protection layer on the oxide layer; forming a dummy gate layer on the nitride protection layer; patterning the oxide, nitride, and dummy gate layers forming first and second dummy gate stacks on first and second portions of the substrate, each dummy gate stack comprising a dummy gate, the nitride protection layer, and the oxide layer, wherein a portion of the oxide layer extends along the substrate beyond side edges of the dummy gate; forming first and second source/drain cavities in the substrate at opposite sides of the first and second dummy gate stacks, respectively; growing first and second eSiGe source/drain regions in the first and second source/drain cavities, respectively; and removing the first dummy gate and the second dummy gate stack.
US09419137B1	Stress memorization film and oxide isolation in fins A method of straining fins of a FinFET device by using a stress memorization film and the resulting device are provided. Embodiments include providing a plurality of bulk Si fins, the plurality of bulk Si fins having a recessed oxide layer therebetween; forming a stress memorization layer over the plurality of bulk Si fins and the recessed oxide layer; annealing the stress memorization layer, the plurality of bulk Si fins, and the recessed oxide layer; and removing the stress memorization layer.
US09419135B2	Three dimensional NAND device having reduced wafer bowing and method of making thereof A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending substantially perpendicular to the major surface of the substrate. The trench is filled with at least a first trench material and a second trench material. The first trench material includes a material under a first magnitude of a first stress type, and the second trench material includes a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate.
US09419134B2	Strain enhancement for FinFETs An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
US09419126B2	Integrated circuits and methods for fabricating integrated circuits with active area protection Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.
US09419118B1	Trench IGBT with tub-shaped floating P-well and hole drains to P-body regions A trench IGBT has a gate electrode disposed in a trench. A tub-shaped floating P-well is disposed on one side of the trench. The tub-shaped floating P-well has a central shallower portion and a peripheral deeper portion. An inner sidewall of the trench is semiconductor material of the peripheral deeper portion of the floating P-well. On the other side of the trench is a P type body region involving a plurality of deeper portions and a plurality of shallower portions. Each deeper portion extends to the trench such that some parts of the outer sidewall of the trench are semiconductor material of these deeper P-body portions. Other parts of the outer sidewall of the trench are semiconductor material of the shallower P-body portions. A shallow N+ emitter region is disposed at the top of the outer sidewall. The IGBT has fast turn off and enhanced on state conductivity modulation.
US09419114B2	Tunnel field-effect transistor A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.
US09419113B2	Semiconductor device and manufacturing method thereof An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. Another object is to provide a method for manufacturing the thin film transistor. A thin film transistor using an oxide semiconductor layer is formed in such a manner that buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, source and drain electrode layers are formed over the buffer layers, and the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween. In addition, the buffer layers are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, whereby the buffer layers having higher conductivity than the oxide semiconductor layer are obtained.
US09419112B2	Method for manufacturing fin structure A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin.
US09419106B2	Non-planar transistors and methods of fabrication thereof The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.
US09419100B2	Method for fabricating a metal gate electrode Exemplary methods for fabricating a metal gate electrode include forming a dielectric layer on a substrate, and forming a first trench having a first width and a second trench having a second width in the dielectric layer where the first width is less than the second width. Also included is depositing a work-function metal layer over the dielectric layer and into the first and second trenches where the deposited work-function layer is in direct contact with the top surface of the dielectric layer. A first signal metal layer is deposited over the work-function metal layer filling the second trench and a second signal metal layer is deposited filling the first trench.
US09419096B2	Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer.
US09419091B1	Trenched gate with sidewall airgap spacer A method for fabricating a semiconductor device may include receiving a device substrate comprising a channel layer and a source or drain layer, forming a gate trench within the source or drain layer of the device substrate, depositing a gate dielectric layer and one or more additional gate layers onto the bottom and sidewalls of the gate trench, and removing a substantial portion of at least the gate dielectric layer from the sidewalls of the gate trench to form a left and a right sidewall airgap adjacent to the sidewalls of the gate trench. A corresponding semiconductor device may include a device substrate comprising a channel layer and a source or drain layer, a gate trench formed within the source or drain layer of the device substrate and a sidewall airgap formed adjacent to the sidewalls of the gate trench.
US09419085B2	Lateral devices containing permanent charge A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.
US09419084B2	Devices, components and methods combining trench field plates with immobile electrostatic charge N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).
US09419083B2	Semiconductor structures having a gate field plate and methods for forming such structure A field effect transistor structure having a semiconductor having a source region, a drain region, and a gate contact region disposed between the source region and the drain region; and a gate electrode having a stem section extending from a top section of the gate electrode to, and in Schottky contact with, the gate contact region. The stem section has an upper portion terminating at the top portion of the gate electrode and a bottom portion narrower than the upper portion, the bottom portion terminating at the gate contact region. The bottom portion of the stem has a step between the upper portion of the stem section and the bottom portion of the stem section in only one side of the stem section. The step of the stem section provides an asymmetric field plate for the field effect transistor.
US09419078B2	Floating body memory with asymmetric channel A semiconductor structure and formation thereof. The semiconductor structure has a fin of a first semiconductor material. The fin has a first side surface opposite a second side surface. The semiconductor structure has a portion of a second semiconductor material that has a third side surface opposite a fourth side surface. The fourth side surface of the second semiconductor material abuts and covers the first side surface of the fin. The semiconductor structure has a portion of a third semiconductor material that abuts and covers the second side surface of the fin. The semiconductor structure has a single gate structure that covers the fin, the portion of the second semiconductor material and the portion of the third semiconductor material. The fin manifests an asymmetry due to the portion of the second semiconductor material and the portion of the third semiconductor material.
US09419076B1	Bipolar junction transistor A bipolar junction transistor (BJT) is formed in a thin (less than about 20 nanometers) segment of a semiconductive material such as silicon where a lower portion of the semiconductive material has doping of a first conductivity type and forms a collector and an upper portion of the semiconductive material has doping of a second conductivity type and forms a base. Either a metal or a polysilicon emitter is formed on the base. An illustrative method for forming the BJT comprises forming first and second layers of a semiconductive material having first and second conductivity types, respectively; forming a hard mask on an upper surface of the second layer; using the hard mask to etch first and second channels in the semiconductive material on first and second opposing sides of the hard mask; removing the hard mask; and forming an emitter on the upper surface of the second layer.
US09419072B2	Semiconductor device and method for fabricating the same A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.
US09419071B2	Integrated circuit comprising at least an integrated antenna An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.
US09419069B2	Method of manufacturing a semiconductor component and structure A semiconductor component and methods for manufacturing the semiconductor component that includes a three dimensional helically shaped common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.
US09419068B2	Organic EL display device and method of manufacturing organic EL display device An organic EL display device includes: a lower electrode disposed in each of pixels; an upper electrode disposed so as to cover the whole of the display area; an organic layer disposed between the lower electrode and the upper electrode and composed of a plurality of layers including a light-emitting layer composed of an organic material; a wire formed outside the display area and composed of conductive material; and a tapered structure layer formed on the wire and including tapered portions at each of which a side surface portion not in contact with the wire extends so as to overhang the wire. At least one layer of the organic layer is formed on the tapered structure layer. The tapered structure layer forms a contact hole surrounded by the side surface portions. The upper electrode is in contact with the wire through the contact hole.
US09419066B2	Light-emitting device and method of manufacturing the same To provide a bright and highly reliable light-emitting device. An anode (102), an EL layer (103), a cathode (104), and an auxiliary electrode (105) are formed sequentially in lamination on a reflecting electrode (101). Further, the anode (102), the cathode (104), and the auxiliary electrode (105) are either transparent or semi-transparent with respect to visible radiation. In such a structure, lights generated in the EL layer (103) are almost all irradiated to the side of the cathode (104), whereby an effect light emitting area of a pixel is drastically enhanced.
US09419064B2	Method for manufacturing display device It is an object of the present invention to provide a technique for manufacturing a highly reliable display device at low cost with high yield. A first electrode layer is formed by a sputtering method using a gas containing hydrogen or H2O, an electroluminescent layer is formed over the first electrode layer, and a second electrode layer is formed over the electroluminescent layer. According to one aspect of the present invention, a display device is manufactured to include a first electrode layer including indium zinc oxide containing silicon oxide and tungsten oxide, an electroluminescent layer over the first electrode layer, and a second electrode layer over the electroluminescent layer, where the electroluminescent layer includes a layer containing an organic compound and an inorganic compound to be in contact with the first electrode layer.
US09419061B2	Organic light-emitting display apparatus and method of manufacturing the same An organic light-emitting display apparatus includes a gate electrode of a thin-film transistor (TFT) and a gate wiring electrically connected to the gate electrode and formed on different layers with an insulating layer disposed between the gate electrode and the gate wiring.
US09419058B1	Memory device with comb-shaped electrode having a plurality of electrode fingers and method of making thereof A memory device, such as a ReRAM device includes plural interdigitated word lines and a single select transistor controlling plural vertical local bit lines. The interdigitated word lines may be word line combs containing word line fingers which are electrically connected using contact pads and a sidewall bridge interconnect. The select transistor may be a vertical TFT or a planar field effect transistor.
US09419055B2	Transistor having a vertical channel A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first work function.
US09419052B2	Solid-state imaging apparatus, method for driving the same, and imaging apparatus A solid-state imaging apparatus includes a plurality of pixel cells arranged in a pixel array unit, a vertical signal line and a pixel power supply line each connected to a source electrode and a drain electrode of an amplifying transistor, a Pch transistor for supplying potential AVDD to the vertical signal line, a Pch transistor for supplying potential PBIAS_H higher than the potential AVDD to the vertical signal line, a Pch transistor for supplying the potential PBIAS_H to the pixel power supply line, wherein while the transfer transistor is turned ON and transfers signal charges photoelectrically converted by a photodiode to the floating diffusion portion, the Pch transistors are turned ON and the potential PBIAS_H is applied to the vertical signal line and the pixel power supply line.
US09419050B2	Manufacturing method of semiconductor structure with protein tape A manufacturing method of a semiconductor structure includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A second surface of the wafer is adhered to an ultraviolet tape on a frame, and the temporary bonding layer and the carrier are removed. A protection tape is adhered to the first surface of the wafer. An ultraviolet light is used to irradiate the ultraviolet tape. A dicing tape is adhered to the protection tape and the frame, and the ultraviolet tape is removed. A first cutter is used to dice the wafer from the second surface of the wafer, such that plural chips and plural gaps between the chips are formed. A second cutter with a width smaller than the width of the first cutter is used to cut the protection tape along the gaps.
US09419048B2	Method of manufracturing structure of dielectric grid for a semiconductor device A method of forming an image sensor device is disclosed. The method includes providing a substrate having sensor elements in a pixel region and having no sensor elements in a non-pixel region. The method further includes forming metal pillars over the pixel region and a metal shield layer over the non-pixel region. The metal pillars are disposed above spaces between adjacent sensor elements. The method further includes depositing a dielectric layer over the metal pillars and the metal shield layer; and etching the dielectric layer to form first and second trenches. The first trenches are formed over the pixel region and the second trenches are formed over the non-pixel region. Each of the first trenches aligns to a respective sensor element and is surrounded by the dielectric layer at its bottom and sidewall surfaces.
US09419047B2	Image sensor device with aligned IR filter and dielectric layer and related methods An image sensor device may include an interconnect layer, an image sensor IC adjacent the interconnect layer and having an image sensing surface, and a dielectric layer adjacent the image sensor IC and having an opening therein aligned with the image sensing surface. The image sensor device may also include an IR filter adjacent and aligned with the image sensing surface, and an encapsulation material adjacent the dielectric layer and laterally surrounding the IR filter.
US09419043B2	Integrated circuit including a directional light sensor An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a directional light sensor. The directional light sensor includes a plurality of photodetectors located on the major surface. The directional light sensor also includes one or more barriers, wherein each barrier is positioned to shade one or more of the photodetectors from light incident upon the integrated circuit from a respective direction. The directional light sensor is operable to determine a direction of light incident upon the integrated circuit by comparing an output signal of at least two of the photodetectors.
US09419041B2	Semiconductor device, manufacturing method thereof, and electronic apparatus A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.
US09419033B2	Chip scale package of image sensor having dam combination Disclosed is a chip scale package of image sensor having a dam combination, comprising an image sensor chip, a dam combination, a transparent lid disposed on the dam combination, and a plurality of external terminals disposed on the backside of the chip. An image sensing area is formed on the active surface of the image sensor chip. A dam combination consists essentially of at least two dam parts and has an image sensing window. The peripheries of the image sensor window are formed by a pre-formed dam part and are adjacent to the image sensing area with horizontal spacing not greater than 200 μm. There is a combination interface between the two dam parts. The combination interface and the post-formed dam part are far away from the image sensing area than the pre-formed dam part to keep residues caused by the disposition of the pre-formed dam part to be away from the 200 μm exclusive region around the image sensing area.
US09419031B1	Semiconductor and optoelectronic devices An integrated device, including: a first mono-crystal layer including a plurality of image sensor pixels and alignment marks; an overlaying oxide on top of the first mono-crystal layer; and a second mono-crystal layer overlaying the oxide, where the second mono-crystal layer includes a plurality of single crystal transistors aligned to the alignment marks.
US09419029B1	Method for manufacturing thin film transistor array substrate and thin film transistor array substrate for the same A method for manufacturing a thin film transistor array substrate includes: forming a polysilicon layer on the substrate; forming a gate insulating layer on the polysilicon layer; forming a metal oxide layer on the gate insulating layer; forming a gate metal layer on the metal oxide layer; etching the metal oxide layer to define a gate; using the gate as a second mask and etching the metal oxide layer excluding a scope of the second mask; performing ion-implantation by using the gate and a remainder of the metal oxide layer as a third mask to form two lightly doped drain regions at opposite sides of the polysilicon layer; forming an insulating layer on the gate and the gate insulating layer respectively; forming a metal layer on the insulating layer and defining a drain and a source which connect to the doped drain region and the doped source region respectively.
US09419021B2	Thin film transistor circuit and display device using it If the threshold of a thin film transistor is depleted, a leak-induced voltage drop takes place and the desired voltage cannot be obtained. Depending on the severity of the phenomenon, the thin film transistor may fail to function. This disclosure offers a thin film transistor circuit having a first transistor connected to a low voltage, and a second transistor connected to the gate of the first transistor. When the gate voltage of the second transistor is changed from the high level to the low level, the gate voltage of the first transistor is brought to a voltage level lower than the low voltage.
US09419018B2	Semiconductor device and method for manufacturing the same A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. A contact plug penetrates the first insulating layer, the conductive layer, and the second insulating layer. In a depth direction from the second insulating layer to the first insulating layer, a diameter of the contact plug changes to a smaller value at an interface between the second insulating layer and the conductive layer.
US09419013B1	Semiconductor device and method of manufacturing the same A semiconductor device, including gate electrodes perpendicularly stacked on a substrate; channel holes extending perpendicularly to the substrate, the channel holes penetrating through the gate electrodes, the channel holes having a channel region; gate pads extended from the gate electrodes by different lengths; and contact plugs connected to the gate pads, at least a portion of the gate pads having a region having a thickness less than a thickness of the gate electrode connected to the at least a portion of the gate pads.
US09419012B1	Three-dimensional memory structure employing air gap isolation Electrically conductive layers for control gate electrodes of a vertical memory device can be vertically spaced by cavities to reduce capacitive coupling between neighboring electrically conductive gate electrodes. An alternating stack of first material layers and second material layers can be provided. After replacing the second material layers with electrically conductive layers, the first material layers can be removed to form cavities between the electrically conductive layers. A dielectric material can be deposited with high anisotropic deposition rate to form an insulating spacer. For example, a plasma assisted atomic layer deposition process can be employed to deposit a dielectric spacer that include laterally protruding portions that encapsulate the cavities at each level between neighboring pairs of electrically conductive layers. A contact via structure can be formed in the insulating spacer to provide electrical contact to a source region.
US09419009B1	3D nonvolatile memory device A 3D nonvolatile memory device is disclosed. The 3D nonvolatile memory device includes a word line stack in which a plurality of word lines are stacked therein and includes a cell region and a slimming region, and pass transistors located below the word line stack, and electrically coupled to the slimming region. A width of the slimming region is larger than that of the cell region.
US09419008B2	Method of fabricating semiconductor devices having vertical cells According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.
US09419006B2	Process for 3D NAND memory with socketed floating gate cells A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.
US09419005B2	Semiconductor device, related manufacturing method, and related electronic device A method for manufacturing a semiconductor device may include the following steps: preparing a stacked structure; processing the stacked structure to form a first gate structure and a preliminary structure; forming a dielectric material layer that covers at least the first gate structure; forming a dielectric layer using the dielectric material layer, such that a portion of the dielectric layer is positioned between the first gate structure and the preliminary structure; performing an annealing process on at least one of the dielectric material layer and the dielectric layer; processing the preliminary structure to form a second gate structure; and after the annealing process has been performed, forming a first metal silicide member on the second gate structure and/or forming a second metal silicide member on an active region associated with the second gate structure.
US09419000B2	Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
US09418999B2	MIM capacitors with improved reliability A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.
US09418995B2	Method and structure for transistors using gate stack dopants with minimal nitrogen penetration Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is maintained on a PFET during a replacement metal gate process that utilizes an NFET-first process flow. Selective nitridation is used to provide nitrogen to the NFET while the PFET is protected from nitrogen by the keep-cap. Additional dopants are provided to the NFET using a gate stack dopant material (GSDM) layer.
US09418992B2	High performance power cell for RF power amplifier A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the Schottky MOSFET. The source node of the enhancement MOSFET and source node of the Schottky MOSFET are connected together to form the power cell.
US09418990B2	Semiconductor device and method of manufacturing the same A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.
US09418985B2	Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.
US09418984B2	Normally off power electronic component An electronic power component including a normally on high-voltage transistor and a normally off low-voltage transistor. The normally on transistor and the normally off transistor are coupled in cascode configuration and are housed in a single package. The normally off transistor is of the bottom-source type.
US09418975B1	Semiconductor module, power conversion device, and method for manufacturing semiconductor module A semiconductor module has a first electrode terminal, a second electrode terminal, a third electrode terminal, a fourth electrode terminal, a fifth electrode terminal, and a sixth electrode terminal. The first electrode terminal and the second electrode terminal are arranged along a first direction. The third electrode terminal, the fourth electrode terminal, the fifth electrode terminal, and the sixth electrode terminal are arranged along a second direction perpendicular to the first direction. The first electrode terminal is arranged at a position where the first direction intersects with the second direction. The fourth electrode terminal, the fifth electrode terminal, and the sixth electrode terminal are AC output terminals or AC input terminals. The first electrode terminal is one of an anode terminal and a cathode terminal. At least one of the second electrode terminal and the third electrode terminal is the other of the anode terminal and the cathode terminal.
US09418972B2	Optoelectronic component with protective circuit An optoelectronic component includes at least one first carrier with at least two light emitting diodes, wherein each diode has two electrical connections, each electrical connection is led to a contact area, the contact areas are arranged on an underside of the first carrier, and a second carrier, wherein at least two zener diodes are arranged in the second carrier, the zener diodes have further electrical connections, each further electrical connection is led to a further contact area, the further contact areas are arranged on a top side of the second carrier, the first carrier bears by the underside on the top side of the second carrier and is fixedly connected to the second carrier, and the zener diodes antiparallelly connect to the diodes.
US09418964B2	Chip package structure A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.
US09418962B2	Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.
US09418961B2	Apparatus and method of substrate to substrate bonding for three dimensional (3D) IC interconnects An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads.
US09418959B1	Systems of bonded substrates A system of bonded substrates may include a first substrate, a second substrate, and a composite bonding layer. The first substrate may include a bonding surface and the second substrate may include a complementary bonding surface. The composite bonding layer may be positioned between the first substrate and the second substrate. The composite boding layer may include a metal matrix and a plurality of stress-reducing additives disposed in the metal matrix. Each stress-reducing additive may include a three-dimensional shape The stress-reducing additives may include a ratio of length:height of at least about 2:1. An elastic modulus of a material of the stress-reducing additive may be less than an elastic modulus of the material of the metal matrix.
US09418957B2	Semiconductor package, printed circuit board substrate and semiconductor device A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.
US09418956B2	Zero stand-off bonding system and method A system and method for a zero stand-off configuration are provided. An embodiment comprises forming a seal layer over a conductive region that is part of a first substrate and breaching the seal with a conductive member of a second substrate in order to bond the first substrate to the second substrate.
US09418955B2	Plasma treatment for semiconductor devices A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.
US09418951B2	Semiconductor structure with composite barrier layer under redistribution layer and manufacturing method thereof A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer.
US09418942B2	Semiconductor device In one embodiment, a semiconductor package includes a first semiconductor die having a first surface facing upwardly to expose a bond pad, a second semiconductor die having a first surface facing downwardly to expose a bond pad and disposed to be offset with the first surface of the first semiconductor die, and an encapsulant encapsulating the first semiconductor die and the second semiconductor die together. Throughholes are disposed in the encapsulant adjacent the bond pad of the first semiconductor die and adjacent the bond pad of the second semiconductor die.
US09418941B2	Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage conductive polymer is deposited over the contact pads on the semiconductor wafer. The semiconductor wafer is singulated to separate the die. An insulating layer is formed over a carrier with openings formed in the insulating layer. The die is mounted to the carrier with the conductive polymer disposed in the openings of the insulating layer. The conductive polymer is heated to a glass transition temperature to liquefy the conductive polymer to an electrically conductive state. An encapsulant is deposited over the die and insulating layer. The carrier is removed to expose the conductive polymer. An interconnect structure is formed over the die, encapsulant, and conductive polymer. The interconnect structure is electrically connected through the conductive polymer to the contact pads on the die.
US09418938B2	Semiconductor device having a graphene interconnect A semiconductor device includes a graphene interconnect, an insulation film formed on the graphene interconnect, and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film. The graphene interconnect has a region containing an impurity at least around the via hole.
US09418937B2	Integrated circuit and method of forming an integrated circuit An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.
US09418935B1	Integrated circuit line ends formed using additive processing Integrated circuit structures formed using methods herein include a layer, and a material-filled line in the layer. The material-filled line includes a first linear item and a second linear item separated by a separation area of the layer. The first linear item has a first line end where the first linear item contacts the separation area. The second linear item has a second line end where the second linear item contacts the separation area. The first line end and the second line end include line end openings (filled with a material) that increase critical dimension uniformity of the first line end and the second line end.
US09418933B2	Through-substrate via formation with improved topography control A device include a substrate and an interconnect structure over the substrate. The interconnect structure comprising an inter-layer dielectric (ILD) and a first inter-metal dielectric (IMD) formed over the ILD. A through-substrate via (TSV) is formed at the IMD extending a first depth through the interconnect structure into the substrate. A metallic pad is formed at the IMD adjoining the TSV and extending a second depth into the interconnect structure, wherein the second depth is less than the first depth. Connections to the TSV are made through the metallic pad.
US09418930B2	Power module A power module, having a printed circuit board core, which contains at least one electronic power component embedded in an insulating layer, the core being arranged between two heat dissipation plates, wherein each heat dissipation plate has a metal outer layer and a metal inner layer electrically separated from said metal outer layer by a thermally conductive, electrically insulating intermediate layer, and electrode terminals of the at least one power component are guided out from the core via terminal lines, wherein the printed circuit board core on both sides of the insulating layer has a conductor layer, at least one conductor layer is structured at least in portions, and each conductor layer is connected at least in portions via a conductive, metal intermediate layer to a metal inner layer of the heat dissipation plate, contacts run from the structured conductor layer to the electrode terminals of the at least one power component, and at least one power terminal of the at least one power component is connected via a contact, a portion of a structured conductor layer, and the conductive, metal intermediate layer to at least one portion of the metal inner layer of the heat dissipation plate, which forms part of the terminal line to the electrode terminal.
US09418928B2	Protrusion bump pads for bond-on-trace processing An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace.
US09418927B2	Stretchable electronic device A stretchable electronic device is disclosed. In one aspect, the device includes at least one combination of a stretchable electronic structure having a first Young's modulus and a rigid or flexible electronic structure having a second Young's modulus higher than the first Young's modulus. The stretchable electronic structure and the rigid or flexible electronic structure may be electrically connected to each other by a semi-transition structure having a third Young's modulus with a value in a range between the first and the second Young's modulus.
US09418922B2	Semiconductor device with reduced thickness A semiconductor device with reduced thickness is disclosed and may include forming a back end of line (BEOL) comprising a redistribution layer on a dummy substrate. A first semiconductor die may be bonded to a first surface of the BEOL and a second semiconductor die may be bonded to the first semiconductor die. The first and second semiconductor dies may be electrically coupled to the BEOL. The first and second semiconductor dies and the BEOL may be encapsulated utilizing a first encapsulant. The dummy substrate may be removed thereby exposing a second surface of the BEOL opposite to the first surface. A solder ball may be placed on the exposed second surface of the BEOL. The second semiconductor may be stacked stepwise on the first semiconductor and may be flip-chip bonded. The semiconductor dies may be electrically coupled to the BEOL utilizing a lateral plating layer or conductive wires.
US09418920B2	Integrated circuit (IC) package with thick die pad functioning as a heat sink An integrated circuit (IC) package includes a die pad and an IC die secured on the die pad. The IC die had outer edges aligned with outer edges of the die pad. An encapsulating material body surrounds the die pad and IC die. Leads extend outwardly from the encapsulating material body and are coupled to the IC die. Each lead has an upper surface coplanar with an upper surface of the IC die. The die pad has a lower surface exposed through the encapsulating material body, and has a thickness greater than a thickness of each of the plurality of leads.
US09418916B2	Semiconductor device A semiconductor device including a semiconductor chip, a first electrode pad and second electrode pad included on one surface of the semiconductor chip, a first conductive post joined by a joining material to the first electrode pad, a plurality of second conductive posts joined by a joining material to the second electrode pad, and a printed substrate, disposed opposing the one surface of the semiconductor chip, on which is formed an electrical circuit to which the first conductive post and second conductive posts are connected. The second conductive posts on the side near the first conductive post are arrayed avoiding a short-circuit prevention region at a distance such that the joining material of the first conductive post and the joining material of the second conductive posts do not link.
US09418915B2	Semiconductor device and method for fabricating the same Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a gate structure formed in the interlayer insulating layer, an isolation layer formed in the semiconductor substrate, a through-silicon via formed to penetrate the semiconductor substrate, the interlayer insulating layer, and the isolation layer, and a first conduction type first impurity region coming in contact with the isolation layer and formed to surround only a portion of a sidewall of the through-silicon via in the semiconductor substrate.
US09418913B2	Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around bumps between the semiconductor die and substrate.
US09418907B2	Method for manufacturing semiconductor device A sample semiconductor device is manufactured and the curvature of the sample is measured. An area is set to be removed from an encapsulation resin layer on the basis of the measurement value. After forming the encapsulation resin layer during the process of manufacturing the semiconductor device, the removal area is removed.
US09418906B2	Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
US09418902B2	Forming isolated fins from a substrate A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a top portion of the fin above the masking layer, removing the masking layer to expose the base portion of the fin, and converting the base portion of the fin to an isolation region that electrically isolates the fin from the substrate. The base portion of the fin may be converted to an isolation region by oxidizing the base portion of the fin, using for example a thermal oxidation process. While converting the base portion of the fin to an isolation region, the spacers prevent the top portion of the fin from also being converted.
US09418900B1	Silicon germanium and silicon fins on oxide from bulk wafer A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.
US09418897B1	Wrap around silicide for FinFETs A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
US09418896B2	Semiconductor device and fabricating method thereof Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first direction, to be spaced apart in a second direction intersecting the first direction, forming first and second gate lines, each extending in the second direction, on the first to fourth fins to be spaced apart in the first direction, forming a first contact on the first gate line between the first and second fins, forming a second contact on the first gate line between the third and fourth fins, forming a third contact on the second gate line between the first and second fins, forming a fourth contact on the second gate line between the third and fourth fins and forming a fifth contact on the first to fourth contacts so as to overlap with the second contact and the third contact and so as not to overlap with the first contact and the fourth contact, wherein the fifth contact is arranged to diagonally traverse a quadrangle defined by the first to fourth contacts.
US09418885B2	Semiconductor manufacturing apparatus Disclosed is a semiconductor manufacturing apparatus including at least one pocket on which a passive subject on which deposition will be executed is mounted, and a carrier body having an insertion space to which the at least one pocket is detachably attached. Therefore, the semiconductor manufacturing apparatus shortens process time and reduces process expenses. The semiconductor manufacturing apparatus allows respective pockets to have different structures according to the positions of the pockets on the wafer carrier, and thus achieves uniform growth of a material on the surfaces of wafers regardless of the positions of the pockets.
US09418884B2	Electrostatic chuck and semiconductor manufacturing device An electrostatic chuck includes a placing stage formed from a ceramic including aluminum oxide and yttrium oxide, and an electrostatic electrode arranged in the placing stage, wherein a content rate of the yttrium oxide is 0.5 wt % to 2.0 wt %. Preferably, the electrostatic chuck is used while being heated at a temperature of 100° C. to 200° C.
US09418883B2	Device for holding wafer shaped articles A device for holding a wafer-shaped article comprises an annular chuck base body having a plurality of movable contact elements for securing a wafer-shaped article to the annular chuck base body, and a gear mechanism driving the contact elements in unison between a first position and a second position. The annular chuck base body comprises a housing formed from a material that is resistant to attack by strong inorganic acids. The annular chuck base body also comprises a reinforcing ring fitted within the housing and formed from a material whose coefficient of linear thermal expansion is substantially less than that of the housing material.
US09418881B2	Substrate processing apparatus capable of switching control mode of heater Provided is a substrate processing apparatus capable of suppressing inferiority when heat treatment is controlled using a temperature sensor. The substrate processing apparatus includes a heating means configured to heat a process chamber wherein a substrate is accommodated; a first temperature detection means configured to detect a temperature about the substrate using a first thermocouple; a second temperature detection means configured to detect a temperature about the heating means using a second thermocouple; a control unit configured to control the heating means based on the temperature detected by the first temperature detection means and the temperature detected by the second temperature detection means; and a control switching means configured to control the control unit based on the temperatures detected by the first temperature detection means and the second temperature detection means such that the control unit is switched between a first control mode and a second control mode, wherein a heat resistance of the first thermocouple is greater than that of the second thermocouple, and a temperature detection performance of the second thermocouple is higher than that of the first thermocouple.
US09418879B2	Low cost interposer and method of fabrication A method for making an interposer is provided. A conductive layer is formed by contacting a replicate such that a shape of a surface of the conductive layer conforms to a shape of the contacted portion of the replicate. The conductive layer is formed to have a base and a plurality of conductive posts projecting away from the base. Each conductive post is formed to have a post end opposite the base. A dielectric layer is formed to cover the base and to separate adjacent ones of the posts from each other. The posts are for forming vias. Conductive material is removed from the conductive layer to insulate at least one post from at least one other post.
US09418871B2	Systems and methods for annealing semiconductor structures Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure. The semiconductor structure may include at least one material selected from the group consisting of boron-doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, n-type doped silicon, and aluminum capped silicon carbide. The heat reflecting structure may include a material substantially transparent to microwave radiation and having substantial reflectivity with respect to infrared radiation.
US09418869B2	Method to etch a tungsten containing layer A method for etching a tungsten containing layer is provided. An etch gas is provided comprising O2 and a fluorine containing component, wherein the etch gas has at least as many oxygen atoms as fluorine atoms. A plasma is formed from the etch gas. The tungsten containing layer is etched with the plasma formed from the etch gas.
US09418867B2	Mask passivation using plasma A gas comprising hydrogen is supplied to a plasma source. Plasma comprising hydrogen plasma particles is generated from the gas. A passivation layer is deposited on a first mask layer on a second mask layer over a substrate using the hydrogen plasma particles.
US09418862B2	Method for integrated circuit patterning A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.
US09418861B2	Method of manufacturing a display substrate using two etch masks Provided are a display substrate, a display device, and a method of manufacturing the display substrate. The display substrate includes: a substrate in which a pixel region is defined; a gate electrode and a gate pad are formed on the substrate; a gate insulating layer formed on the gate electrode and the gate pad; a buffer layer pattern overlaps the gate electrode and is formed on the gate insulating layer; an insulating film pattern formed on the buffer layer pattern; an oxide semiconductor pattern formed on the insulating film pattern; a source electrode formed on the oxide semiconductor pattern; and a drain electrode formed on the oxide semiconductor pattern and is separated from the source electrode.
US09418860B2	Use of topography to direct assembly of block copolymers in grapho-epitaxial applications A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed self-assembly (DSA) is formed surrounding the exposed topography. Further to the method, the exposed template surfaces are chemically treated. In one embodiment, the surfaces are treated with a hydrogen-containing reducing chemistry to alter the surfaces to a less oxidized state. In another embodiment, the surfaces are coated with a first phase of a block copolymer (BCP) to render the surfaces more attractive to the first phase than prior to the coating. The template is then filled with the BCP to cover the exposed topography, and then the BCP is annealed within the template to drive self-assembly in alignment with the topography. Developing the annealed BCP exposes a DSA pattern immediately overlying the topography.
US09418858B2	Selective etch of silicon by way of metastable hydrogen termination Methods of etching exposed silicon on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon while very slowly removing other exposed materials. The silicon selectivity results, in part, from a preponderance of hydrogen-containing precursor in the remote plasma which hydrogen terminates surfaces on the patterned heterogeneous structures. A much lower flow of the fluorine-containing precursor progressively substitutes fluorine for hydrogen on the hydrogen-terminated silicon thereby selectively removing silicon from exposed regions of silicon. The silicon selectivity also results from the presence of an ion suppressor positioned between the remote plasma and the substrate processing region. The ion suppressor reduces or substantially eliminates the number of ionically-charged species that reach the substrate. The methods may be used to selectively remove silicon far faster than silicon oxide, silicon nitride and a variety of metal-containing materials.
US09418854B2	Semiconductor device including buried gate, module and system, and method for manufacturing An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device.
US09418851B2	Method for manufacturing a semiconductor device A wafer includes a semiconductor layer having a concentration of n-dopants. A first mask is formed on the wafer and has first openings in an active area of a semiconductor device and at least one second opening in a peripheral area of the device. The first openings define first zones in the semiconductor layer and each second opening defines a second zone in the layer. Donor ions are implanted through the first mask into the first and second zones. The first mask is replaced by a second mask which has third openings in the active area and at least one fourth opening in the peripheral area. Each fourth opening defines a fourth zone in the semiconductor layer which at least partially overlaps with the second zone. The third openings define third zones in the semiconductor layer. Acceptor ions are implanted through the second mask into the third and fourth zones.
US09418846B1	Selective dopant junction for a group III-V semiconductor device An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.
US09418841B2	Type III-V and type IV semiconductor device formation Forming a semiconductor device is disclosed, according to embodiments of the present disclosure. Forming the semiconductor device can include forming a first semiconductor layer directly on a silicon substrate. Forming the semiconductor device can include forming a second semiconductor layer directly on the first semiconductor layer and forming an insulating trench in the second semiconductor layer. Forming the semiconductor device can include removing the second portion of the second semiconductor layer, and forming a third semiconductor layer directly on the first semiconductor layer and adjacent to the insulating trench such that the first portion of second semiconductor layer is electrically insulated from the third semiconductor layer. The first semiconductor layer and the third semiconductor layer can each be a type III-V semiconductor and the second semiconductor layer can be a type IV semiconductor.
US09418840B2	Silicon carbide semiconductor device manufacturing method and silicon carbide semiconductor device Silicon-containing gas, carbon-containing gas, and chlorine-containing gas are introduced into a reacting furnace. Next, a SiC epitaxial film is grown on the front surface of a 4H-SiC substrate by a halide CVD method in a mixed gas atmosphere made of the plurality of gasses introduced. In the SiC epitaxial film growing, a SiC epitaxial film of a first predetermined thickness is grown at a first growth rate. The first growth rate is increased from an initial growth rate to a higher growth rate. Furthermore, the SiC epitaxial film is grown, at a second growth rate, until the thickness of the SiC epitaxial film reaches a second predetermined thickness. By so doing, it is possible to improve the crystallinity of a silicon carbide semiconductor film grown in a gas atmosphere containing halide.
US09418836B2	Polyoxometalate and heteropolyoxometalate compositions and methods for their use The present invention relates to novel compositions comprising a metal component selected from a group chosen from at least one polyoxometalate, at least one heteropolyoxometalate and a mixture thereof; and, at least one organic component. The present invention also relates to methods of preparing the nanorod arrays and the nanorod materials and films. The present invention also relates to novel compositions to generate metal-oxide rich films, and also relates to processes for via or trench filling, reverse via or trench filling and imaging with underlayers. The materials are useful in wide range of manufacturing applications in many industries, including the semiconductor devices, electro-optical devices and energy storage industry.
US09418831B2	Method for precision cleaning and drying flat objects Cleaning and drying of semiconductor wafers is carried out in a single-chamber type cleaning/drying apparatus for flat objects such as semiconductor wafer, where cleaning is carried out by impinging both sides of the wafer which rotates at a relatively low speed with jets of a washing liquid and where subsequent drying is carried out in the same chamber by increasing the rotation speed of the wafer and supplying an isopropyl-alcohol (IPA) mist onto the wafer from the top of the chamber. After the IPA forms a solution with the residue of water on the wafer, the drying process is accelerated by supplying gaseous nitrogen through nozzles arranged on both side of the coaxial with the wafer center. As a result, the IPA-water solution quickly evaporates without leaving traces of water drops on the dried surface.
US09418829B2	Low pressure lamp using non-mercury materials A mercury-free low-pressure lamp having a bulb is provided. The bulb includes a non-mercury emissive material. When the bulb is in a non-operational state, the emissive material condenses into a liquid or solid, and when the bulb is in an operational state the emissive material forms an emitter, the emitter in combination with one or more gases generate photons when excited by an electrical discharge.
US09418827B2	Methods of ion source fabrication A method of ion source fabrication for a mass spectrometer includes simultaneously forming aligned component portions of an ion source using direct metal laser fusing of sequential layers. The method can further include forming the component portions on a base plate made from a ceramic material by applying fused powder to the base plate to build the component portions thereon.
US09418824B2	Lock component corrections A method of mass spectrometry is disclosed comprising initially calibrating or recalibrating a mass spectrometer at a time T0 and at the same time measuring a time of flight or mass to charge ratio M0 of one or more lockmass ions. The mass spectrometer is then operated at a subsequent time T1 and the time of flight or mass to charge ratio M1 of the one or more lockmass ions is measured at subsequent time T1. The time of flight or mass to charge ratio of ions is then adjusted by or based upon the difference between the time of flight or mass to charge ratio M1 of the one or more lockmass ions as measured at time T1 and the time of flight or mass to charge ratio M0 of the one or more lockmass ions as measured at time T0.
US09418819B2	Asymmetrical detector design and methodology A charged particle detection device has an active portion for configured to produce a signal in response secondary charged particles emitted from a sample landing on the active portion. The active portion is shaped to accommodate an expected asymmetric pattern of the secondary charged particles at a detector. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
US09418818B2	Charged particle beam device and sample observation method A sample observation method includes irradiating a sample with a primary charged particle beam, detecting a secondary charged particle signal obtained by the irradiating, and observing the sample. The method is characterized by causing the primary charged particle beam generated in a charged particle optical lens barrel, which is maintained in a vacuum state, to be transmitted or passed through a separating film disposed to isolate a space in which the sample is placed from the charged particle optical lens barrel; and detecting a transmitted charged particle beam obtained by irradiating the sample, placed in an atmospheric pressure or a predetermined gas atmosphere of a slightly negative pressure state compared with the atmospheric pressure, with the primary charged particle beam.
US09418814B2	Planar field emitters and high efficiency photocathodes based on ultrananocrystalline diamond A method of forming a field emitter comprises disposing a first layer on a substrate. The first layer is seeded with nanodiamond particles. The substrate with the first layer disposed thereon is maintained at a first temperature and a first pressure in a mixture of gases which includes nitrogen. The first layer is exposed to a microwave plasma to form a nitrogen doped ultrananocrystalline diamond film on the first layer, which has a percentage of nitrogen in the range of about 0.05 atom % to about 0.5 atom %. The field emitter has about 1012 to about 1014 emitting sites per cm2. A photocathode can also be formed similarly by forming a nitrogen doped ultrananocrystalline diamond film on a substrate similar to the field emitter, and then hydrogen terminating the film. The photocathode is responsive to near ultraviolet light as well as to visible light.
US09418813B2	Fuse assembly A first and a second pair of projecting portions are provided in a cavity portion of a fuse mounting portion made of resin. An upper end surface of each projecting portion is tapered, so as to guide a pair of male terminals of a fuse sub-assembly toward a corresponding female terminals attached to the cavity portion, when the fuse sub-assembly is inserted into the cavity portion. A gap is formed between the fuse sub-assembly and the tapered upper end surfaces in a fuse-mounted condition, in which the fuse sub-assembly is in contact with a stopper portion of the cavity portion, in order to prevent contact failure caused by thermal shock.
US09418807B2	Electrical switch forming a fast-acting circuit breaker A normally closed electric switch having a sliding assembly that is actuated to open the switch, e.g. by a pyrotechnic gas generator. Prior to actuation, a conductive portion of the sliding assembly (21) is in tight contact with two rings (13a, 14a) that are axially offset on the same axis, belonging respectively to two electrically conductive tabs (13, 14), and after the actuator has been triggered, the upstream tab (13) is separated from the conductive portion of the sliding assembly. According to the invention, sliding assembly comprises a tube split by a slot extending along its entire length, and the conductive portion of the sliding assembly is constituted by all or part of said split tube, the clamping force between the conductive portion and the primary electrically conductive tabs being provided by the resilience of the split tube.
US09418804B2	Switching device A switching device having at least one contact pair includes a first contact and a second contact, where at least the second contact is movable relative to the first contact. There is an extinguishing device with at least one extinguishing chamber for extinguishing an arc produced between the contacts, a first guide rail arrangement for guiding the arc with one direction of current and a second guide rail arrangement for guiding the arc with the second direction of current in said extinguishing chamber. Both guide rail arrangements have a first guide rail and a second guide rail, where both first guide rails starting from the first contact run in the opposite direction, and both second guide rails starting from the second contact run in the opposite direction. The first guide rails are connected with each other in an electrically conductive arrangement in the form of a closed loop.
US09418803B2	Inertia switch An inertia switch includes a stack of a base plate and a base cover. The base plate provided inside a liquid storage chamber and a sensing chamber communicating with a liquid storage chamber. The liquid storage chamber contains working fluid, and the sensing chamber equipped with a sensing electrode extending to and connected to an external equipment that tend to interact with the inertia switch. The electricity-conductive liquid is utilized as a medium for inertia detection. Furthermore, by the width, depth and angle of the flow channel design, when the liquid material flows into the sensing chamber through the channel after a time delay, a sensing signal is obtained by the sensing electrodes through a change of a resistance value or a capacitance value to actuate the switch. The inertia switch has a simple structure and is low cost.
US09418802B2	Switch automation device An automation device to control a pre-existing light switch is described which attaches to the light switch by internal magnets at locations corresponding to the magnetic screw heads of the light switch. This makes installation a simple process requiring no hand tools or electrical connections be made with the light switch. The automation device can be wired or wirelessly controlled and works with both toggle light switches and rocker light switches. Additional functionalities include various timed and automated operations as well as device and user location determinations.
US09418799B2	Key button assembly for electronic device and operating method thereof An electronic device includes a substrate having a key sensor region and a touch sensor regions, a dome key unit, a key button, and a touch sensor. The dome key unit is arranged on the key sensor region of the substrate. The key button is arranged above the dome key unit in alignment with the dome key unit. The touch sensor is arranged on the touch sensor region of the substrate. The touch sensor is arranged such that it includes a region overlapping with a part of the key button. The key button can perform at least two functions associated with different input schemes at the same input point of the key button by means of the dome key unit and the touch sensor.
US09418798B2	Keyboard A keyboard including a plurality of keys, a baseplate which supports each of the keys, and a frame which is arranged to stand substantially perpendicularly to the baseplate and to surround the each of the keys, in which the each of the keys includes an keycap configured to be depressed, the keycap including a keycap top end which constitutes a top end of the keycap and a keycap sidewall which hangs down from an edge of the keycap top end to the baseplate, and in which the baseplate has a hole arranged at a site that corresponds to a bottom end of the keycap sidewall, the hole configured to insert the bottom end of the keycap sidewall therein from above, and in which, when the keycap is in a depressed state, the bottom end of the keycap sidewall is inserted into the hole.
US09418788B2	Precision half cell for sub-FEMTO unit cap and capacitive DAC architecture in SAR ADC A capacitive device is disclosed, including a first conductor formed on a lower metal layer and coupled to a first terminal. A second conductor is formed on an upper metal layer and a plurality of wires is partitioned into groups, each group including one wire from a respective metal layer. First and second wires of each group are coupled to a second terminal. A third wire of each group, adjacent to the first wire, is coupled to the first conductor. A fourth wire of each group, adjacent to the second wire, is coupled to the second conductor. Fifth wires of a first subset of the groups are coupled to the second conductor and fifth wires of a second subset of the groups are coupled to the first conductor. The fifth wire of each group is adjacent to the first wire and the second wire.
US09418786B2	R—Fe—B porous magnet and method for producing the same An R—Fe—B based porous magnet according to the present invention has an aggregate structure of Nd2Fe14B type crystalline phases with an average grain size of 0.1 μm to 1 μm. At least a portion of the magnet is porous and has micropores with a major axis of 1 μm to 20 μm.
US09418784B2	Electrical connection configuration for an ignition coil An electrical connection configuration, e.g., for an ignition coil, includes: an enameled wire sheathed in insulating enamel, and a contact element for the electrical contacting of the enameled wire, the contact element having a contact region for the electrical contacting of the enameled wire. The contact region has at least one sharp edge, and the enameled wire is routed along the sharp edge, such that a region of the enameled wire stripped of the enamel is provided, which rests against the contact region of the contact element for the electrical contacting.
US09418781B2	Magnetic system of three interactions Magnetic system possessing and producing polar and field properties comprising an application of organized ensemble of constituted constructions of magnetic apparatus as means of construction. The magnetic system as an application produces magnetic phenomena and interactions, such as the production of three different interactions and also their related respective three opposites, depending on the distance existing between the magnetic constructions. It is a fully systemized product that can be used as an experimental instrument for exploitation of new designing possibilities in magnetic constructions, containing also a process of operation.
US09418775B2	Separator tape for twisted pair in LAN cable A cable includes a jacket surrounding first and second insulated conductors and a first dielectric tape, wherein the first insulated conductor is twisted with the second insulated conductor with the first dielectric tape residing therebetween to form a first twisted pair. The cable's jacket may also surround additional twisted pairs, which are similarly formed. In alternative or supplemental embodiments of the invention, the first dielectric tape has a hollow core possessing a gas or material with a lower dielectric constant and/or at least a first side of said first dielectric tape facing to said first insulated conductor includes a plurality of ridges and valleys.
US09418774B2	Curable epoxy resin composition A curable epoxy resin composition including a defined aromatic epoxy resin component and a defined latent catalyst system, and optionally further additives, the curable composition being a single epoxy resin composition having a prolonged pot life at a processing temperature within the range of 40° C. to 70° C., wherein: (a) the epoxy resin component is a compound of formula (I) in monomeric form or in a low polymeric form thereof, or is a mixture of such compounds: the epoxy resin component having an inherent viscosity within the range of 80 mPas to 300 mPas, measured at a temperature of 50° C.; (b) the latent catalyst system includes at least one metal acetylacetonate and at least one phenolic compound.
US09418773B2	Composition of polyamides with low concentration of carboxamide groups and electrically conductive carbon A polyamide composition comprising the following components: a) at least 40 parts by weight of a polyamide whose monomer units contain an arithmetic average of at least 7.5 carbon atoms, b) 0.1 to 15 parts by weight of at least one salt with a non-metallic cation, c) 0.1 to 25 parts by weight of at least one dispersant based on esters or amides and d) an electrically conductive carbon selected from the group of carbon black, graphite powder, carbon fibers, carbon nanotubes and/or graphene, in an amount which results in a specific surface resistance of the polymer composition to IEC 60167 of 10−1 to 1010Ω, e) 0 to 5 parts by weight of at least one metal salt, and optionally f) customary assistants and additives, where the polyamide of component a) is not a PA12 if carbon nanotubes are present as component d), and where the sum of the parts by weight of components a) to f) is 100, can be used for production of mouldings with improved electrical conductivity and improved surface quality.
US09418766B2	Fuel assembly for a boiling water reactor A fuel assembly of a boiling water reactor contains a fuel assembly base closed at the top by a filter plate, a fuel assembly head, and, disposed between them, a bundle of long and medium-length fuel rods extending away from the fuel assembly base. A water channel is disposed inside the fuel rod bundle. A plurality of the medium-length fuel rods are fixed axially on a separate holding part which is connected to the upper side of the fuel assembly base.
US09418765B2	Nuclear reactor cores comprising a plurality of fuel elements, and fuel elements for use therein In a nuclear reactor core, each of a plurality of pressure tubes contains fuel elements spaced apart to permit coolant to flow through spaces between adjacent fuel elements. Each fuel element comprises fuel pellets in cladding, e.g., sapphire, having a melting temperature of at least 1900° C. and does not form significant hydrogen if exposed to high temperature steam. Each pressure tube has an internal insulator sleeve, e.g., fused silica, that has relatively low thermal conductivity over a range of normal operating temperatures and relatively high thermal radiation transmission at temperatures higher than said normal operating temperature range. When coolant is absent from said spaces, the insulator sleeve transmits to the pressure tube at least about 10%, but preferably more than about 40% of thermal radiation from the fuel for conduction through the pressure tube to the moderator and fuel temperature remains within safe limits after the reactor is shut down.
US09418763B2	Memory array, memory device, and methods for reading and operating the same The present invention provides a memory. The memory includes a plurality of memory cells arranged as an array with a plurality of rows and a plurality of column. A memory cell is connected to at least one redundant memory cell in a same row for storing same data as the memory cell; and a column of memory cells correspond to one redundant column of redundant memory cells wherein each redundant memory cell in the redundant column stores same data as the memory cell in a same row.
US09418762B1	Semiconductor memory device A semiconductor memory device may include: a first fuse set unit suitable for storing a first repair address during a first mode; a second fuse set unit suitable for storing an input address during a second mode; and a comparison unit suitable for comparing the input address with the first repair address, wherein the first fuse set unit is reset when the first repair address is the same as the input address.
US09418761B2	Apparatus for boosting source-line voltage to reduce leakage in resistive memories Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.
US09418758B2	Test circuit of semiconductor apparatus A test circuit of a semiconductor apparatus includes a plurality of memory blocks, and a comparison block configured to compare data of two memory blocks, wherein the two of the plurality of memory blocks do not share word lines.
US09418757B2	Method for testing semiconductor apparatus and test system using the same This technique may include a semiconductor apparatus configured to perform data read/write operations in a test mode or a normal mode and a tester configured to simultaneously perform a data test and a leakage current test through a write operation using data read by a read operation in the normal mode after writing data into the semiconductor apparatus in the test mode.
US09418756B2	Threshold voltage compensation circuit of thin film transistor and method for the same, shift register, and display device Provided are a threshold voltage compensation circuit of TFT and a method for the same, a shift register and a display device. The threshold voltage compensation circuit includes an input terminal, an output terminal connected to the source of the thin film transistor, a first resistor to a Kth resistor connected in series, and Kth connectable link and at least one first connectable link. Since a voltage dividing circuit having connectable links divides the voltage input to the source of the thin film transistor, such that the gate-source voltage of the thin film transistor can be changed by changing the voltage of the source of the thin film transistor when the voltage of the gate of the thin film transistor is maintained unchanged, so as to control a leakage current of the thin film transistor under a turn-off state, such that the thin film transistor can be turned off normally.
US09418755B2	Shift register and flat panel display device including the same Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a plurality of gate lines formed in a display panel. Each of the stages includes a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node, a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node, a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal, and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines using the clock signal.
US09418752B2	Ramping inhibit voltage during memory programming The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.
US09418749B2	Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.
US09418748B2	Semiconductor memory device and method of operating the same A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.
US09418747B2	Nonvolatile memory device maintaining a bitline precharge during program verification periods for multi-level memory cells and related programming method A nonvolatile memory device comprises a memory cell array comprising multiple memory cells disposed at intersections of corresponding word lines and bitlines, and multiple page buffers connected to the bitlines, respectively, and performing consecutive verify read operations on selected memory cells programmed in first to N-th logic states (N>2), wherein, in the consecutive verify read operations, the bitlines are placed in a precharged state by precharging them to a first level during a verification period of memory cells programmed in the first logic state, are maintained in the precharged state during verification periods of memory cells programmed in the second to (N−1)-th logic states, and are discharged after a verification period of memory cells programmed in the N-th logic state.
US09418745B1	Rebalancing in twin cell memory schemes to enable multiple writes A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.
US09418742B2	Nonvolatile semiconductor memory device and memory system having the same A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.
US09418725B2	Semiconductor device and method of driving the same A semiconductor device may include a common coupling block suitable for coupling a plurality of first data lines to a plurality of second data lines in response to a common control signal, which is activated regardless of a data bandwidth option mode, a first coupling block suitable for coupling a part of the plurality of second data lines to a part of a plurality of third data lines in response to a first operation control signal, a second coupling block suitable for coupling the other part of the plurality of second data lines to the other part of the plurality of third data lines in response to a second operation control signal, and a control block suitable for activating one or more of the first and second operation control signals based on the data bandwidth option mode, during a data input/output operation.
US09418721B2	Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM) Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter, a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.
US09418717B2	Tracking mechanism for writing to a memory cell A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.
US09418714B2	Sense amplifier with transistor threshold compensation One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors. The method also includes applying the voltage differential between a gate of the first transistor and a gate of the second transistor, the first and second transistors configured to oppose each other in a cross-coupled inverter stage of the sense amplifier.
US09418711B2	Semiconductor memory device having main word lines and sub-word lines A plurality of memory mats classified into groups selected by bits of a row address, a main word driver for selecting a main word line based on bits of the row address, an FX driver for selecting a word driver selecting line based on bits regardless of the bits of the row address, and a plurality of sub-word drivers selected by the main word line and the word driver selecting line to drive the corresponding sub-word line are arranged.
US09418710B1	Nanoparticulate-trapping filter for hard disk drive A hard disk drive (HDD) filter assembly may include an inlet for receiving an input gas, a cyclonic particle separator configured for separating certain sized particulates from the gas, and a trap chamber for securing the particulates separated from the gas. Such a filter assembly may be designed and configured to separate and secure nanoparticulates from the input gas, such as nanoparticulates with diameters less than around 100 nm. A filter assembly may further include a desiccant chamber for controlling the humidity of the cleaned gas and a membrane for absorbing and/or adsorbing some remaining particulates from the gas before the gas enters the main chamber of the HDD.
US09418709B1	Method for minimizing contamination in hard disk drive assembly A removable tool for reducing contamination in a cleanroom assembly environment during assembly of a hard disk drive may include a handle assembly and a positive locking assembly. The handle assembly may define a proximal and distal end such that, in use, the proximal end is further away from the hard disk drive being assembled than is the distal end. The positive locking assembly may be configured to lock onto a portion of an upper perimeter of a Motor Base Assembly (MBA) of a hard disk drive and onto a corresponding portion of a lower perimeter of the MBA. The handle assembly and the positive locking assembly may be further configured to enable free access to an interior of the MBA during subsequent assembly steps. The positive locking assembly may be further configured to be selectively releasable without touching the MBA, to thereby enable the removal of the tool.
US09418708B2	Data-storage device mounting apparatus A data-storage device mounting apparatus includes an enclosure and one or more elastic members. The enclosure includes a shell and a cover. The elastic member includes a mounting portion mounted on the cover, a deformable portion, and an engaging portion. The mounting portion is attached to a first end of the deformable portion and the engaging portion attached to a second end of the deformable portion. The first deformable portion end is opposite the second deformable portion. The shell defines an opening, a cavity, and an engaging hole. The engaging portion engages with the engaging hole when the cover is engaged with the shell to substantially cover the shell opening. The engaging portion may be disengaged from the engaging hole allowing the cover to be disengaged from the shell. The data-storage device is positioned within the cavity when the cover is engaged with the shell.
US09418707B2	Accommodating case for portable recording medium An accommodating case from which a user can easily detach a recording medium is provided. An accommodating case includes an inner surface thereof with a medium disposition area that is an area to dispose the recording medium. In addition, the accommodating case includes an engagement plate portion for engaging with edges of the recording medium so that the recording medium disposed in the medium disposition area is prevented from separating from the inner surface thereof. Furthermore, the accommodating case includes a movable plate portion defining a part of the inner surface thereof. The movable plate portion is movable relative the other portion of the inner surface of the accommodating case to be recessed toward the outside of the accommodating case. The movable plate portion is located over the medium disposition area and an outside area of the medium disposition area.
US09418706B2	Method and apparatus for displaying a plurality of items A method of displaying a plurality of items is described. The items are arranged in a plurality of hierarchical levels, each of the hierarchical levels comprises a plurality of sets of items, each set comprising at least one of the plurality of items and each item has associated therewith at least one other item in another hierarchical level. An item within a first hierarchical level is selected (step 206), at least two sets of items of at least one second hierarchical level (the second hierarchical level being a level lower than the first hierarchical level) are arranged in an order determined by the selected one of the items (step 208) and the ordered sets of items are displayed (step 210).
US09418704B2	Program, recording medium, and reproducing apparatus The problem to be solved is to make it possible to download via a network, efficiently manage, retrieve, and reproduce an external content associated with a content recorded on a recording medium. To solve the problem, a program is used which controls reproduction of information located on a recording medium and related information. The program includes the steps of: obtaining from the outside specific information associated with predetermined information recorded on a recording medium; and obtaining medium identification information located on a recording medium; wherein if the specific information has been obtained, a storage unit in a reproducing apparatus is controlled to associate the specific information with the medium identification information for storage.
US09418702B1	Interactive movie timeline and method for interacting with a movie timeline An interactive movie timeline and method for interacting with a movie timeline that includes play of a video mainstream along a movie timeline, said video mainstream including at least one meta-video prompt tag encoded into the movie timeline wherein read of the meta-video prompt tag effects display of an electable option to a viewer enabling selection between alternate content playable as video streams insertable into the movie timeline between each of a meta-video insert tag and a meta-video end tag encoded into the timeline, whereby alternate content is playable in lieu of the video mainstream in sequence with the movie timeline and a viewer is enabled a customizable viewing experience thereby.
US09418701B2	Method for determining identifiers of segments forming an audiovisual document and receiver implementing the method The invention relates to a method for determining identifiers associated with segments of a document. Each segment consists of a series of individual elements such as images or sound sequences. Each segment of the document is subdivided into a determined number of portions comprising the same number of individual elements. An individual element is extracted from the most central portion of each segment and associated with the segment as identifier.The invention also relates to the receiver capable of implementing the method.
US09418698B2	Dynamic gain control for use with adaptive equalizers According to one embodiment, a magnetic tape drive includes a controller configured to direct first data through a first finite impulse response (FIR) gain module in response to a determination that the first data is being read from a magnetic tape medium in an asynchronous mode to control FIR gain of the first data. The controller is also configured to direct second data through a second FIR gain module in response to a determination that the second data is being read from the magnetic tape medium in a synchronous mode to control FIR gain of the second data. A FIR gain value of the second FIR gain module is automatically controlled. Other systems for dynamic gain control with adaptive equalizers are described according to more embodiments.
US09418695B2	Optical information apparatus and information processing apparatus An RF hologram is divided in a direction perpendicular to a tangent line of an information track of an information recording surface of an optical disc, and includes a central region including an optical axis of laser light as well as a first end portion region and a second end portion region which sandwich the central region, the central region is formed by a binary diffraction grating and generates ±1 order diffracted light, the first end portion region is formed by a blazed diffraction grating and generates first +1 order diffracted light, the second end portion region is formed by a blazed diffraction grating and generates second +1 order diffracted light, and an RF light receiving element receives both the ±1 order diffracted light, the first +1 order diffracted light, and the second +1 order diffracted light.
US09418688B1	System and method for detecting shifting of reader-writer offset in a heat-assisted magnetic recording head A heat-assisted magnetic recording head is configured to write data to and read data from a magnetic recording medium. The head comprises a reader and a writer including a near-field transducer (NFT). The reader comprises a center which is laterally offset relative to a center of the writer to define a reader-writer offset (RWO) therebetween. A controller is configured to control the writer to write data to data tracks of the medium, detect a shift in the RWO, and in response to the detected shift in the RWO, control the writer to write data to a plurality of tracks defining a reserved band during an open period of the reserved band.
US09418686B1	Monitoring head wear A method, executed by a computer, for monitoring head wear includes reading from a cartridge a high frequency pattern and a low frequency pattern, determining a first read amplitude corresponding to the high frequency pattern and a second read amplitude corresponding to the low frequency pattern, and determining a head wear metric according to the first read amplitude and the second read amplitude.
US09418685B1	Compensating for loss of current through shorted tunneling magnetoresistance sensors Embodiments of the present invention provide methods, systems, and computer program products for compensating for loss of current through shorted tunneling magnetoresistance (TMR) sensors. In one embodiment, for a magnetic head having multiple TMR read sensors, a first voltage limit is set for most parts and a second voltage limit is set for all of the parts. A number of TMR read sensors which are allowed to function between the first and the second voltage limits is determined using a probability algorithm, which determines the probability that the application of the second voltage limit will result in a dielectric breakdown within an expected lifetime of a drive is below a threshold value. For the number of TMR read sensors which are allowed to function at voltages between the first and second voltage limits, a determined subset of those sensors are then allowed to function at the second voltage limit.
US09418683B2	Mass production of multichannel current perpendicular to plane head modules via preferred milling A process according to one embodiment includes milling a media facing surface of a module having an array of sensors at a first angle, and milling the media facing surface of the magnetic head module at a second angle, not necessarily in that order. After the milling at the first and second angles, the media facing surface of the module is milled at a third angle between 55 degrees and 65 degrees from normal. An apparatus according to one embodiment includes a tape head module having an array of at least eight current perpendicular to plane sensors, wherein none of the sensors has a resistance more than about 10% away from the resistances of its nearest neighbors.
US09418672B2	Navigation application with adaptive instruction text Some embodiments provide a navigation application. The navigation application includes an interface for receiving data describing junctures along a route from a first location on a map to a second location on the map. The data for each juncture includes a set of angles at which roads leave the juncture. The navigation application includes a juncture decoder for synthesizing, from the juncture data, instruction elements for each juncture that describe different aspects of a maneuver to be performed at the juncture. The navigation application includes an instruction generator for generating at least two different instruction sets for a maneuver by combining one or more of the instruction elements for the juncture at which the maneuver is to be performed. The navigation application includes an instruction retriever for selecting one of the different instruction sets for the maneuver according to a context in which the instruction set will be displayed.
US09418670B2	Encoding apparatus, encoding method, and program An encoding apparatus includes a noise detector configured to detect noise included in a certain band in accordance with an audio signal, a gain controller configured to perform gain control on the audio signal so that components in the certain band of the audio signal are attenuated when the noise is detected by the noise detector, a bit allocation calculation unit configured to calculate the numbers of bits to be allocated to frequency spectra of the audio signal which have been subjected to the gain control performed by the gain controller in accordance with the frequency spectra, and a quantization unit configured to quantize the frequency spectra of the audio signal which have been subjected to the gain control in accordance with the numbers of the bits.
US09418669B2	Discovery of music artist and title for syndicated content played by radio stations Radio stations broadcasting syndicated content for which the broadcast automation system is not provided with the artist and title of songs has a software application in an associated computer that receives and analyzes the audio stream to detect songs, and creates a digital fingerprint of the songs. Fingerprints are compared against an acoustic fingerprinting song database to obtain the artist and title of the song. When a match is discovered, the song artist and title are provided to encoding software that inserts the artist and title into the radio station's digital broadcast for receipt and display by compatible radio receivers, and are transmitted on the Internet to simulcast media players of listeners for presentation of the artist and title of songs as they are playing.
US09418668B2	Matrix encoder with improved channel separation An encoder is disclosed for use in a surround sound system wherein at least four audio input signals (FL, FR, RL, RR) representing an original sound field are encoded into two channel signals (L, R) and the encoded two channel signals are decoded into at least four audio output signals (FL′, FR′, RL′, RR′) corresponding to the four audio input signals. The encoder includes matrix means connected to receive the four audio input signals for encoding the four input signals into two channel (L and R) output signals. The matrix means includes means responsive to the four input signals for producing Lenc and Renc output signals as follows: Lenc=FL+kFR+jRL+jkRR Renc=FR+kFL−jRR−jkRL wherein k denotes a transformation or matrix coefficient having a value that is steered dynamically based on level of rear signal (RL+RR) content relative to front signal (FL+FR) content. An encoding method for use in a surround sound system is also disclosed.
US09418664B2	System and method of speaker recognition An authentication and authorization apparatus combines a unique identifier for a communications device with pre-stored voice recognition information. Incoming audio, associated with the unique identifier, is processed to authenticate the speaker. In response to successful authentication, a requested function or action embedded in the audio can be recognized and, if authorized, implemented by a displaced system.
US09418662B2	Method, apparatus and computer program product for providing compound models for speech recognition adaptation An apparatus for providing compound models for speech recognition adaptation. The apparatus may include processor and memory including computer program code with the memory, the computer program code being configured, with the processor, to cause the apparatus to at least receive a speech signal corresponding to a particular speaker. The apparatus may further be configured to select a cluster model including both a speaker independent portion and a speaker dependent portion based at least in part on a characteristic of speech of the particular speaker. The apparatus may be further configured to process the speech using the selected cluster model. The apparatus may be further configured to cause at least a speaker dependent portion of one or more non-selected cluster models to be stored remotely. A corresponding method and computer program product are also provided.
US09418661B2	Vehicle voice recognition systems and methods A voice recognition system includes a microphone for receiving speech from a user and processing electronics. The processing electronics are in communication with the microphone and are configured to use a plurality of rules to evaluate user interactions with the voice recognition system. The processing electronics automatically determine and set an expertise level in response to and based on the evaluation. The processing electronics are configured to automatically adjust at least one setting of the voice recognition system in response to the set expertise level.
US09418654B1	Presentation of written works based on character identities and attributes A method is provided for presenting a written work. A character identity is recognized within a written work. Presentation information for the written work, such as a graphical scheme or an electronic voice, is determined based on the character identity. The presentation information is provided to a user computing device. The user computing device renders the written work or a portion thereof using the presentation information.
US09418651B2	Method and apparatus for mitigating false accepts of trigger phrases An electronic device includes a microphone that receives an audio signal, and a processor that is electrically coupled to the microphone. The processor detects a trigger phrase in the received audio signal and measure characteristics of the detected trigger phrase. Based on the measured characteristics of the detected trigger phrase, the processor determines whether the detected trigger phrase is valid.
US09418650B2	Training speech recognition using captions In embodiments, apparatuses, methods and storage media are described that are associated with training adaptive speech recognition systems (“ASR”) using audio and text obtained from captioned video. In various embodiments, the audio and caption may be aligned for identification, such as according to a start and end time associated with a caption, and the alignment may be adjusted to better fit audio to a given caption. In various embodiments, the aligned audio and caption may then be used for training if an error value associated with the audio and caption demonstrates that the audio and caption will aid in training the ASR. In various embodiments, filters may be used on audio and text prior to training. Such filters may be used to exclude potential training audio and text based on filter criteria. Other embodiments may be described and claimed.
US09418648B1	Effective generation of ultra-high frequency sound in conductive ferromagnetic material An apparatus for generation of an ultra-high frequency sound waves with frequencies between (1 GHz-10 GHz) is proposed. The apparatus comprises a spin injector, a tunnel junction, a conductive ferromagnetic material including magnon gain medium, a ferromagnetic dielectric material including magnetic phonon-gain medium, and an ultra-high frequency sound waveguide coupled to the ferromagnetic dielectric material. The spin injector is configured to inject minority non-equilibrium elections into the conductive ferromagnetic material via the tunnel junction. The non-equilibrium magnons generated in the magnon gain medium of the conductive ferromagnetic material propagate into the ferromagnetic dielectric material and having the magnon velocity exceeding the sound velocity in the phonon-gain medium of the ferromagnetic dielectric material cause generation of ultra-high frequency non-equilibrium phonons in the ferromagnetic dielectric material. The ultra-high frequency sound waveguide is configured to output the ultra-high frequency sound generated in the ferromagnetic dielectric material.
US09418645B2	Method of playing chord inversions on a virtual instrument A user interface implemented on a touch-sensitive display for a virtual musical instrument comprising a plurality of chord touch regions configured in a predetermined sequence, each chord touch region corresponding to a chord in a musical key and being divided into a plurality of separate touch zones, the plurality of chord touch regions defining a predetermined set of chords, where each of the plurality of separate touch zones in each region is associated with one or more preselected MIDI files stored in a computer-readable medium. In some embodiments, the touch zones are configured to provide different harmonic configurations of a base chord associated with the chord touch region. Some harmonic configurations provide progressively wider harmonic ranges across each adjacent touch zone. Other harmonic configurations can provide chords with a progressively higher relative pitch across each adjacent touch zone.
US09418643B2	Audio signal analysis A server system 500 is provided for receiving video clips having an associated audio/musical track for processing at the server system. The system comprises a first beat tracking module for generating a first beat time sequence from the audio signal using an estimation of the signal's tempo and chroma accent information. A ceiling and floor function is applied to the tempo estimation to provide integer versions which are subsequently applied separately to a further accent signal derived from a lower-frequency sub-band of the audio signal to generate second and third beat time sequences. A selection module then compares each of the beat time sequences with the further accent signal to identify a best match.
US09418642B2	Vocal processing with accompaniment music input Systems, including methods and apparatus, for generating audio effects based on accompaniment audio produced by live or pre-recorded accompaniment instruments, in combination with melody audio produced by a singer. Audible broadcast of the accompaniment audio may be delayed by a predetermined time, such as the time required to determine chord information contained in the accompaniment signal. As a result, audio effects that require the chord information may be substantially synchronized with the audible broadcast of the accompaniment audio. The present teachings may be especially suitable for use in karaoke systems, to correct and add sound effects to a singer's voice that sings along with a pre-recorded accompaniment track.
US09418641B2	Swap Divisi process A divisi process in which different samplings are provided of full section, half a section, quarter section, etc. When a first note on input is received, the note is assigned to the full section. When a subsequent note on input is received, it is assigned to a half section. At that time, the volume of the full section may be reduced. Upon receiving further note on inputs, the notes may be assigned to another half section or to a quarter section depending on the number of notes being played simultaneously. The volume of notes being played is adjusted when a new note is added.
US09418640B2	Recording apparatus A recording apparatus capable of readily setting a desired recording condition at the time of recording a music signal to music data and maintaining the recording conditions even when transmitting the recorded music file data to another equipment. A system controller acquires recording condition parameters employed in recording a voice signal, appends the parameters to music data to generate music file data, and stores the data into SD memory, or the like. Music file data are selected at the time of new recording operation, and recording condition parameters appended to the selected music file data are read, whereby recording conditions are automatically set.
US09418639B2	Smart drumsticks Embodiments of a smart drumstick, a device interacting with the drumstick, and related methods are disclosed. Some embodiments include a computer-readable storage medium whose contents are capable of causing a computing system to perform a method of managing data related to lighting and motion for a device having a drumstick shape, the method comprising: identifying a light signal corresponding to a given type of motion; sending a definition of the determined light signal to the device; receiving a description of a type of motion of the device; determining whether the given type of motion matches the type of motion of the device; and transmitting the determination result to the device.
US09418634B1	O-ring tuning system for wind instruments A method and apparatus of tuning a wind instrument which stabilizes the mating sections of a jointed instrument when the mating sections are pulled out or pushed in during tuning. At least one O-ring is inserted between the mating sections which seals the interface between the sections to create an air tight seal and firm support between sections. The O-rings may have differing thickness, and any number of O-rings may be used. During tuning, the O-rings may be compressed in order to seal the interface between segments when the segments are pulled out or pushed in with respect to each other.
US09418633B1	Pick holder for stringed musical instrument picks The present invention is a pick holder for a musical instrument. The pick holder has a plurality of retention clips on its face, in which can be placed musical instrument picks. The material of the face of the flexible container and pick holder is such that the musician's thumb can easily swipe or move a guitar pick across it. The present invention can be positioned so that the musician can easily reach the face containing the picks using the thumb of the strumming hand.
US09418632B2	Speed pick, associated systems and methods The disclosure is a plectrum used for playing a stringed instrument comprising a generally acute isosceles triangle body and further comprising at least one pad, groove, inlet or opening. These picks are designed to provide the user with improved control, dexterity and further provide certain acoustic advantages.
US09418631B2	Display control apparatus and method and image processing method A display control apparatus is capable of reducing image scaling times, maintaining image quality, and extending a turn-on time of a pair of 3D glasses. The display control apparatus includes a data processing unit and a timing generating unit. The data processing unit provides an image frame comprising a valid data region, which is larger than a visual region of a display panel. The timing generating unit generates an output timing signal according to a relative position of the visual region corresponding to the valid data region, so that a partial region of the valid data region corresponds to the visual region of the display panel. The partial region of the valid data region is displayed in the visual region of the display panel according to the output timing signal.
US09418625B2	Resolution loss mitigation for 3D displays Systems, devices and methods are described including determining a display type and a display mode, preparing stereoscopic image content in response to the display mode, where preparing the stereoscopic image content includes storing a full resolution left image and a full resolution right image in memory, and determining a display refresh rate in response to at least a content frame rate of the stereoscopic image content. The stereoscopic image content may then be processed for display according to the display type, the display refresh rate, and a power policy.
US09418622B2	Method for producing a color image and imaging device employing same A method of producing a color image comprising providing input image data from an image source such as a camera; generating an at least three-dimensional look-up table of values of input colors and output colors, wherein the values in the lookup table convert the input image color data to output image color data in an image rendering unit; loading the at least three-dimensional look-up table into an image color rendering controller; loading the input image data into the imaging color rendering controller; processing the input image data through the at least three-dimensional look-up table to produce output color values stored at the addresses in the at least three-dimensional look-up table; and outputting the output color values to the image rendering unit to produce an output image that is perceived to have at least one of enhanced brightness, enhanced contrast, or enhanced colorfulness compared to the input image.
US09418620B2	Methods and systems for controlling interferometric modulators of reflective display devices Systems and methods process standard video signal data and control a reflective display panel to brightly display videos and images in colors selected from a broad range of colors. In certain implementations, an input video/image signal is first transformed from a RGB encoding to an encoding based on a new color system that encodes colors using spectral, black, and white components. The reflective display panel includes an array of pixels, with each pixel comprising one or more self-parallelizing interferometric modulators (“SPIMs”). Each SPIM contains a plurality of electrodes disposed on a bottom plate, a fixed top plate, and a movable plate separated by a cavity. Appropriate voltages are applied to the electrodes to vary the cavity depth of the SPIM in order for the SPIM to reflect a color of a particular wavelength or to appear black or white.
US09418618B2	Video signal transmission apparatus, play system and video signal transmission method There is provided a video signal transmission apparatus, a play system and a transmission method. The video signal transmission apparatus comprises: a first interface configured to be connected with a video signal source; a second interface configured to be connected with a display device; a signal receiving unit and a control unit arranged between the first interface and the second interface, the control unit being connected with the display device through the second interface and the signal receiving unit being connected with the video signal source through the first interface. The control unit comprises an acquiring module configured to acquire parameter information of the display device and feed acquired parameter information back to the signal receiving unit., the parameter information comprising a video format supported by the display device; the signal receiving unit comprises a converting module configured to convert a received video signal into the video format supported by the display device according to the parameter information. The present disclosure can realize plugging and playing and avoid such problem that the system has a failure of output or disorder of display configuration caused by the hot swap or disconnection with the display device and thus needs to be restarted, and so on.
US09418617B1	Methods and systems for receiving input controls Examples methods and systems for distinguishing winks from other eye motions are described. In some examples, a method for distinguishing winks from other eye motions may account for changes in orientation of a computing device relative to a user, calibrate eye gesture recognition, or increase efficiency of the computing device. A computing device may be configured to receive sensor data corresponding to an eye and determine a distribution of magnitude changes in the sensor data over an interval of time. The computing device may identify clusters that correspond to ranges of magnitude changes within the distribution and use the clusters as reference data to identify ranges of sensor data for different types of eye motions, including differentiating winks from clusters indicative of ranges of normal eye activity and blinks.
US09418615B2	Voltage generator A voltage generator for providing a plurality of output voltages having different levels includes: a reference block and a plurality of digital-to-analog conversion blocks. The reference block is employed for providing a plurality of reference voltages according to a supply voltage. The plurality of digital-to-analog conversion blocks is coupled to the reference block, and each of the digital-to-analog conversion blocks receives the reference voltages and generates a digital-to-analog output voltage according to a digital code, wherein digital-to-analog output voltages generated by the digital-to-analog conversion blocks have different levels, respectively. In addition, a range of the digital-to-analog output voltage generated by a first digital-to-analog conversion block of the digital-to-analog conversion blocks is different from that of the digital-to-analog output voltage generated by a second digital-to-analog conversion block.
US09418612B2	Liquid crystal display and method for driving the same A liquid crystal display is disclosed. The liquid crystal display includes a power module, which senses an input voltage and outputs a mode conversion signal when the input voltage is equal to or less than a reference voltage, and a timing controller which changes a driving mode of a source driver integrated circuit (IC) in response to receiving the mode conversion signal from the power module.
US09418611B2	LED backlight controller The line banding image artifact that results from the interaction of LCD ripple and LED flicker in an LCD device that utilizes LED backlighting strings is substantially reduced by selecting a number of LED strings, individually driving the number of LED strings with a corresponding number of identical clock signals that are equally phase delayed, and selecting the frequency of the clock signals so that the product of the frequency of the clock signal multiplied by the number of LED strings is equal to the line clock frequency.
US09418607B2	Utilizing gray code to reduce power consumption in display system A system and method are disclosed to utilize Gray code in order to reduce the power consumption of column drivers in a display system. Binary source data is received from a timing controller. A Gray code digitizer converts and encodes the binary source data into a binary portion of data and a Gray code data. The binary portion data and the Gray code data are transmitted through a shift register to a digital-to-analog converter. The shift register consumes less power processing the converted binary portion of data and Gray code data than the corresponding binary source data. The digital-to-analog converter decodes the Gray code and generates corresponding gamma voltage levels for display use.
US09418604B2	Method of compensatiing a left-right gamma difference, vision inspection apparatus performing the method and display apparatus utilizing the method A method of compensating a left-right gamma difference in a display apparatus using a vision inspection apparatus, which includes sensing sample grayscales displayed on areas defined on a display area of the display apparatus using image sensors of the vision inspection apparatus, estimating intensity values of a left reference boundary at a central area, a left boundary area, a right reference boundary area at the central area and a right boundary area, calculating a first grayscale correction value of the left boundary area such that an intensity estimation value of the left boundary area is substantially equal to an intensity estimation value of the left reference boundary area, and calculating a second grayscale correction value of the right boundary area such that an intensity estimation value of the right boundary area is substantially equal to an intensity estimation value of the right reference boundary area.
US09418601B2	Display device with luminance boosting unit A display device includes a display panel configured to display an image corresponding to image data input thereto and be divided into a plurality of display blocks, a backlight unit configured to supply light to the display panel and including a light guide panel and a main light source module which supplies light to the light guide panel, and a luminance boosting unit configured to supply boosted light to the plurality of display blocks based on the image data and including a plurality of light source modules arranged to correspond to the plurality of display blocks, respectively.
US09418595B2	Display device, OLED pixel driving circuit and driving method therefor The present disclosure provides a display device, an OLED pixel driving circuit and a driving method therefor. The OLED pixel driving circuit includes: an electroluminescent element, a switching unit, a storage unit, a compensation unit, a driving transistor, a reset unit and a partition unit; wherein, the switching unit is connected with a data signal and is connected with the storage unit; the compensation unit is connected with the storage unit; the storage unit is connected with a gate electrode of the driving transistor; a source electrode of the driving transistor is connected with a driving voltage, a drain electrode thereof is connected with the compensation unit; the partition unit is connected with the drain electrode and is connected with the electroluminescent element; the reset unit is connected with a reset signal and is connected with the gate electrode.
US09418594B2	Display device A display device has a plurality of arrayed display pixels. A drive transistor includes a first gate electrode and supplies the current corresponding to a level of a luminance signal to the luminescence element. A switching transistor includes a source electrode, a drain electrode, a second gate electrode and a semiconductor layer. The semiconductor layer is faced with the second gate electrode and has, in a channel width direction perpendicular to a channel length direction of the switching transistor, a channel region with a first width and a remainder region with a second width larger than the first width. The source electrode or the drain electrode is connected to the first gate electrode. The source electrode and the drain electrode are provided on the semiconductor layer at an interval. The second gate electrode overlaps, in a plan view, the channel region entirely and the remainder region at least partially.
US09418586B2	Subpixel arrangements of displays and method for rendering the same An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a plurality of zigzag subpixel groups. Each zigzag subpixel group includes at least three zigzag subpixel units arranged adjacently along a horizontal or vertical direction. Each zigzag subpixel unit includes a plurality of subpixels of the same color arranged in a zigzag pattern. In each zigzag subpixel unit, a first plurality of subpixels are arranged along one diagonal direction from a turning subpixel disposed at a turning corner of the zigzag pattern, and a second plurality of subpixels are arranged along another diagonal direction from the turning subpixel. In another example, the display includes an array of subpixels having a novel subpixel repeating group. The control logic is operatively coupled to the display and configured to receive display data and render the display data into control signals for driving the display.
US09418585B2	Dynamic image modification for a color deficient user A system and method for detecting spectrum of colors that is indistinguishable to a color blind individual and modifying the colors to fade in or out to the shade of same color, is provided. While the partial color blind user is enabled to view and better distinguish colors that were problematic earlier, the present invention achieves a significant reduction in power consumption of the display device with this modified color set.
US09418584B2	Display device A display device includes a display panel including a plurality of scan lines, a plurality of data lines which crosses the plurality of scan lines, and a plurality of pixels that is connected to the plurality of scan lines and the plurality of data lines, a scan driving unit which provides a plurality of scan signals, each of which includes a scan-on signal and a scan-off signal, to the plurality of scan lines, a data driving unit that provides data voltages to the plurality of data lines, and a timing control unit that determines an order in which the scan signals are provided to the plurality of scan lines, where the scan-on signal is provided to each of the plurality of scan lines based on an order of averages of the data voltages transferred to the pixels connected thereto.
US09418582B2	Test cell structure of display panel and related display panel A test cell structure of a display panel is disposed in the peripheral region of the display panel. First conductive lines and second conductive lines extend from the display region to the peripheral region, and the amounts of the first and second conductive lines are the same. The test cell structure includes a plurality of first test transistors, a plurality of second test transistors, and a plurality of first shorting bars. The drains of the first test transistors are electrically connected to the first conductive lines respectively, and their sources are electrically connected to the first shorting bars. The sources of the second test transistors are electrically connected to the drains of the first test transistors respectively, and their drains are electrically connected to the second conductive lines. The first test transistors are disposed between the second test transistors and the display region.
US09418577B2	Polyester-based metalizing film The present invention relates to a metalizing film including a polyester-based film layer having a heat-shrinking property, and a use of the metalizing film used as a film label capable of replacing a paper label attached to a glass bottle.
US09418574B2	Surgical operation training device A surgical operation training device 13 comprises a simulation body 83 subjected to a predetermined treatment during surgical operation training, a holder 84 for holding the simulation body 83 from below, a support 85 for supporting the holder 84 workably, a wire 86 for coupling the holder 84 with the support 85, and a control unit 71 for controlling operation of the holder 84. The wire 86 is formed of a shape memory material which can contract from an original shape when a current flows through the wire. The control unit 71 comprises a drive signal generating means 114 for supplying a current to the wire 86 at a predetermined timing and for performing operation control on the holder 84 with a change in the shape of the wire 86 by varying the supply state of current to the wire 86.
US09418572B2	System for enabling a visually impaired or blind person to use an input device having at least one key System for enabling a visually impaired or blind person to use an input device having at least one key, comprising: at least one tactile sensor array, in particular a pressure sensor array, attachable to a fingertip of a visually impaired or blind person for acquiring a pressure distribution image of a key slightly touched by a finger of said person when attached to said finger, a pressure distribution image processing and character recognition unit that is connected to said tactile sensor array for processing said pressure distribution image and for recognizing the key label of the touched key and an audio output device that is connected to said unit for outputting and acoustic reproduction of said key label.
US09418569B2	Methods and system for visually representing a rate of writing a plurality of identical chinese characters for at least one user on a display There are provided methods and a system for visually representing a rate of writing a plurality of identical Chinese characters for at least one user on a first portion of a display, with the visual representation having both a discrete movement component and a rate of activity component.
US09418567B1	Selecting questions for a challenge-response test Methods, systems, and apparatus, including compute program products, for selecting a question for a challenge-response test. One of the methods includes obtaining question response pairs, wherein each question response pair includes a question about a first entity and a response to the question. Respective difficulty values for each question response pair are determined from a count of a number of times the question in the question response pair has been submitted as a search query to a search engine by users of the search engine. A request for a challenge-response test is received, wherein the request includes a context for the challenge-response test. Difficulty criteria for the challenge-response test are determined from the context. A first question response pair is selected that has a difficulty value that satisfies the difficulty criteria for the challenge-response test, the question from the first question response pair is provided in response to the request.
US09418566B2	Determining comprehensiveness of question paper given syllabus A mechanism is provided in a data processing system for determining comprehensiveness of a question paper given a syllabus of topics. An answer and evidence generator of a question answering system executing on the data processing system finds one or more answers based on the syllabus of topics for each question in the question paper. The answer and evidence generator identifies evidence for the one or more answers in the syllabus for each question in the question paper. A concept identifier of the question answering system identifies a set of concepts in the syllabus corresponding to the evidence for each question in the question paper to form a plurality of sets of concepts. The mechanism determines a value for a comprehensiveness metric for the question paper with respect to the syllabus of topics based on the plurality of sets of concepts.
US09418561B2	System and method for displaying predictive conformal configuration cues for executing a landing A system and method for displaying predictive cues on an aircraft display system for executing a landing after an engine failure is provided. The system and method displays the cues for various aircraft configurations, and each cue is displayed in perspective (conformally) on a three dimensional graphical display of the surrounding terrain.
US09418560B1	Automated sensor platform routing and tracking for observing a region of interest while avoiding obstacles A path is automatically routed for a sensor platform that projects a constant sensor footprint to the surface to observe a region of interest without crossing into an excluded area and to tracking that path. The path is routed by defining a bounding region around the region of interest and defining a convex hull around an obstacle within the region of interest. A parallel arrangement of rectangular planks is generated from each edge of the convex hull out to the bounding region. The extent of each rectangular plank is bounded at one end by the intersection of the plank with the bounding region and at the other end by the intersection of the plank with an extension of a next edge of the convex hull. The path is routed to traverse the parallel arrangement of rectangular planks for each edge of the convex hull in a raster scan pattern and to circle the convex hull in a clockwise or counter-clockwise direction. The path is tracked and the surface below sensed to capture a sequence of sensor outputs that together cover the entire region of interest except the region excluded by the convex hull.
US09418559B2	Method and system for determining height above ground using indirect information Techniques and systems are described that allow an air traffic display and/or avionics system of an aircraft to display and/or warn a pilot of aircraft targets for air traffic proximate to the aircraft or to suppress the display of on-ground air traffic targets. In some implementations, an integrated avionics system can use indirect information to determine whether an individual aircraft traffic target is to be presented to a pilot. For example, the integrated avionics system can determine whether an aircraft target is in proximity to the ground based on traffic tracking data corresponding to other aircraft.
US09418558B1	Autonomous collision avoidance navigation system and method An Autonomous Collision Avoidance Navigation System comprising navigating a route between a first location and a second location using a route tracking algorithm, detecting an obstacle and the obstacle's bearing, speed, distance, and direction of travel with respect to ownship, determining whether a collision between the ownship and the obstacle is probable, reducing ownship speed when a collision distance is less than a predetermined distance, determining a new heading using fuzzy logic and MCAD, and changing ownship course to the new heading, and to resume the route tracking algorithm when the obstacle is cleared from probably collision.
US09418556B2	Apparatus and method for displaying a blind spot An apparatus and method for displaying a blind spot, which involve displaying at least one image of the surroundings of a vehicle, in which the image is provided by an imaging unit including a camera, a GPS navigation system, and/or a street-view receiver, so as to provide a driver with information on the blind spots of a front portion, a rear portion, and a side portion of a vehicle that are hidden by the vehicle and thus not easily seen within the field of view of the driver during travel of the vehicle.
US09418554B2	Method and system for determining road conditions based on driver data A system and method for determining adverse/dangerous road conditions based on sensor data received from a vehicle and generating alerts for other vehicles which may encounter the same condition. The system receives sensor data from a vehicle and evaluates the data to determine if the vehicle encountered a potentially dangerous road condition. The system may apply one or more thresholds to the data, where the thresholds are designed to detect various sudden movements of the vehicle. The system may monitor the location associated with the potentially dangerous road condition and evaluate sensor data from one or more other vehicles that drive near the same location to determine whether they encounter a similar condition. The system may generate one or more alerts and transmit those alerts to vehicles that are approaching the location of the dangerous condition using location data provided by the approaching vehicles.
US09418552B2	Method and system for automatically locating vacant parking places An Automatic-vacant-parking-place locator (AVPPL) system and method in which a community member may get (manually or automatically) information on a vacant parking place in an area he/she is searching for a parking place. Further an AVPPL community member may provide information on vacant parking place in different areas, he/she is driving through, to other AVPPL community members and/or to an AVPPL mutual database.
US09418551B2	Position and/or distance measurement, parking and/or vehicle detection, apparatus, networks, operations and/or systems The following are disclosed: Vehicle parking detection, sensors and an On-Board Device (OBD) to create a parking session. Radars, microwave antennas, rechargeable power supplies and their power management circuits. A localized communications protocol between the wireless nodes and repeaters within a wireless network is disclosed. Wireless sensors and wireline sensors. The networks and/or systems may support parking spot management/monitoring, vehicle traffic analysis and/or management of stationary and/or moving vehicles, monitor storage areas and/or manage production facilities. These networks and/or systems may be operated to generate reports of incorrectly parked vehicles, such as reserved parking spots for other vehicles, vehicles parked in multiple parking spots and/or overstaying the time they are permitted to park.
US09418550B2	Navigation apparatus, server apparatus and method of collecting parking location information A navigation apparatus comprises a processing resource operably coupled to a receiver for location-related data and arranged to perform, when in use, location determination. The processing resource supports a parking location determination module the parking location determination module is arranged to determine when the location determined is substantially unchanged and to determine that the location determined constitutes a candidate parking location in response to the location determined remaining substantially unchanged relative to a predetermined period of time.
US09418544B2	Traffic monitoring systems and methods In an exemplary method, a mobile device provides mobile device attribute data to a traffic monitoring subsystem, receives traffic condition data generated by the traffic monitoring subsystem based at least in part on the mobile device attribute data, presents, by way of a user interface, the traffic condition data for consideration by a user of the mobile device, and provides an interface tool configured to be used by the user to report a traffic condition to the traffic monitoring subsystem. In certain embodiments, the mobile device receives, by way of the interface tool, user input indicating a user observance of the traffic condition and provides, in response to the receiving of the user input, a notification of the user observance of the traffic condition to the traffic monitoring subsystem.
US09418541B2	Method of remotely controlling electrical appliances A method of remotely controlling electrical appliances includes the steps of: inputting ID codes of a plurality of electrical appliances into a remote control device; selecting one of the electrical appliances and a corresponding operating command on the remote control device; generating a Wi-Fi signal to carry the first packet; transmitting the Wi-Fi signal to a repeater; converting the first packet carried thereby into a second packet; generating a RF signal to carry the second packet; transmitting the RF signal to the electrical appliances; comparing a ID code kept in a second ID code field of the second packet to the ID codes of the electrical appliances. Finally, the electrical appliance which has the matched ID code performs an operation according to an operating command in a second data field of the second packet.
US09418540B2	Electrical control system An electrical control system includes a power supply circuit comprising a load. Further, the electrical control system includes a master node that is electrically coupled to the load via the power supply circuit. The master node includes a first power line communication interface and a first wireless communication interface. Furthermore, the electrical control system includes at least one slave node that is electrically coupled to the master node via the power supply circuit. The at least one slave node includes a second power line communication interface that is communicable with the first power line communication interface to send a first control signal to the master node through power line communication for controlling the load. The electrical control system further includes a controller that is wirelessly coupled to the master node to send a second control signal wirelessly to the master node for controlling the load.
US09418537B2	Mobile computing device including personal security system A mobile communication device includes at least one processor to display a user interface on a touch screen, the user interface comprising a button to receive a touch event, determine that the touch event is currently being received by the button and enter an alarm armed state, determine that the touch event ends and enter an alarm active state, and after a particular period of time in the alarm active state, trigger a communication to an emergency responder.
US09418534B2	Water heater pressure relief valve alarm A water heater pressure relief valve alarm monitors the state of a discharge pipe of a water heater and produces an audible alarm upon detection of water being discharged through the pipe. A clamp with a pipe receiving aperture is removably attached to the pipe. A sensor is positioned adjacent to the pipe receiving aperture. A housing connected to the clamp contains a signal processing circuit, a sound producing device and a battery. The signal processing circuit receives a signal from the sensor and activates the sound producing device upon detection of discharge from the pipe.
US09418532B2	Infrared detector Methods, systems, and apparatus, for an infrared detector are provided. In one aspect, an infrared detector is provided that includes a pyroelectric sensor; a controller for receiving a trigger signal outputted by the pyroelectric sensor; a thermopile sensor, wherein the controller starts the thermopile sensor after receiving the trigger signal output by the pyroelectric sensor; and an alarm, wherein when the thermopile sensor determines that a difference between a current temperature and a background temperature is larger than a threshold value, the controller controls the alarm to generate an alarm signal.
US09418531B2	System and method for tracking people The present invention relates to receiving information of detected wireless electronic tags, comparing the received information to information stored in the server, and updating the information stored in the server based on the received information. Further, the invention relates to receiving a request regarding location information of an electronic wireless tag, determining whether identification information regarding the electronic wireless tag is available, and transmitting the identification information regarding the electronic wireless tag in response to the request regarding location information after determining that the identification information is available.
US09418530B2	Wireless safety alert signaling system An emergency alert system comprising one or more access-controlled wireless transmitters and a plurality of wireless wearable receivers that can be deployed locally to privately warn users of potential danger, by allowing authorized users to use the transmitters to send alert signals to the receivers.
US09418528B2	Oven appliance with cavity fire detection An oven appliance with features for detecting and containing a fire and/or smoke within the cooking chamber of the oven appliance is provided. A method for operating an oven appliance to detect and contain a fire and/or smoke within the cooking chamber of the oven appliance is also provided.
US09418527B2	Pneumatic detector switch having a single diaphragm for alarm and fault conditions A pneumatic pressure detector switch is disclosed that includes a retainer assembly adapted to communicate with a source of pressure, a deformable diaphragm supported within the retainer assembly and movable in response to changes in pressure communicated to the retainer assembly, a fault contact element supported by the retainer assembly adjacent a first side surface of the diaphragm, and an alarm contact element supported by the retainer assembly adjacent a second side surface of the diaphragm.
US09418526B1	Pedestrian security dye pack system The pedestrian security dye pack system serves as a key component of law enforcement efforts across countries and communities as an investigative tool in emergency response situations, as an eyewitness in investigations and prosecutions, and as a citizen-driven virtual guard and security system. Via included multiple airwave communications, identification and notification capabilities such as WiFi, Bluetooth®, GPS, RFID, and dye projector, the pedestrian security dye pack system isolates, reports and aids authorities in offender detection and apprehension by offering the advantages of a wearable parental unit and a plurality of accompanying dye packs with a radio-controlled incendiary propelled dye projector in each.
US09418525B2	Monitoring system A master device sends image data transmitted from a monitoring camera to a mobile phone terminal, the mobile phone terminal sends a request signal for starting a call to the monitoring camera when receiving an operation on a predetermined icon displayed on a display/input unit in a state in which the image data is displayed on the display/input unit, and the master device transmits the request signal for starting the call to the monitoring camera from the mobile phone terminal.
US09418523B1	Intelligent wireless doorbell alarm system An intelligent wireless doorbell alarm system driven and set by a wireless communication protocol includes at least one doorbell switch, plural lamps and an electronic device. The doorbell switch has a wireless signal module for generating a startup signal after the being triggered. The lamps are electrically coupled to one another. Each lamp has a wireless transmission module and a driving module and is electrically coupled to the doorbell switch for receiving the startup signal. The electronic device is electrically coupled to the lamps and has a setup module for setting the lamps.
US09418522B2	Electronic hinged safety switch An electronic hinged safety switch adapted for installation on protection barriers (B) of machines and/or automatic plants having one or more electric safety circuits (S). The switch comprises a substantially box-like fixed member (2) designed to be secured to a stationary part (M) of a protection barrier (B) and a movable member (3) designed to be secured to a pivotal part (P) of the protection barrier (B) and coupled to the fixed member (2) through hinge means (4). Sensing means (5) are housed in said box-like fixed member (2) for interacting with the hinge means (4) to send an electric control signal (SC) to one or more electric safety circuits (S) at a predetermined switching angle (α). The sensing means (5) comprise at least one sensor for generating a corresponding actuation signal (SA) at the switching angle (α), and an electronic control unit (8) operatively connected to at least one sensor (6). The electronic control unit (8) has at least one input (9) electrically connected to said sensor (6) for receiving the actuation signal (SA) and at least one output (10) connected to the electronic safety circuits (S) for generating the electric control signal (SC) in response to the actuation signal (SA).
US09418521B1	Aggregating results in a slot game A system and method for aggregating results in a slot game are disclosed. In a given pull outcome of the slot game, multiple results may be determined. An order or orders for aggregating the results in the given pull outcome may be obtained. In some examples, the obtained order(s) may specify temporal sequence for applying different types of results in the given pull outcome. In some examples, the order(s) may be based on the player character(s). In some examples, the order(s) may be based on a difficulty level selected by the player. In some examples, such orders may be for purchase for selection by the players. In some implementations, the results in the pull outcome may include gameplays for implementation in a game space associated with the slot game. In those implementations, the implementation of those gameplays may be in accordance with the obtained order(s).
US09418519B2	Determining and selling outcomes for table games to be viewed remotely In accordance with some embodiments, a plurality of outcomes are generated and used to create a video presentation of representative outcomes (e.g., for a roulette game) for one or more players. The video presentation is recorded onto a tangible medium (e.g., DVD or CD-ROM) or otherwise provided to one or more players (e.g., a player may access the video presentation online). This allows one or more players to purchase a video presentation of (e.g., predetermined) outcomes in a jurisdiction in which gambling is legal yet view the presentation at the player's convenience (e.g., from any jurisdiction and at any time). At least one player who is associated with such a video presentation may subsequently redeem it for a redemption value associated therewith.
US09418518B2	Gaming system and method for providing a cascading symbol game with interacting symbols A gaming system including a cascading symbol game which utilizes a plurality of interacting symbols. In certain embodiments, the cascading symbol game utilizes a plurality of symbol display position matrices or grids. Each symbol display position matrix includes a plurality of symbol display positions. In operation, the gaming system generates and displays a symbol at each symbol display position of each employed symbol display position matrix, wherein the gaming system utilizes a separate set or pool of available symbols for each employed symbol display position matrix. Upon an occurrence of an interacting symbol triggering event, such as the shifting of one or more symbols between symbol display position matrices, the gaming system causes one or more symbols to interact to provide one or more benefits to a player.
US09418517B1	Ball race wagering game apparatus and methods of use A rolling ball-race betting apparatus has at least two decline planes with deflectors to allow balls to race down along the decline planes into a collector. A person may place any number of different types of wagers on a race result, such as selecting one ball to win. Each ball in the ball-race apparatus has a designation such as a number, symbol, color or other marking. A ball-race apparatus may have stops, wherein one or more of the balls may be trapped in the stop and will not finish the race. A person may place a wager on one or more balls to not finish the race. A ball-race apparatus may have a shortcut conduit that transfers balls from the first decline plane to the second decline plane. A ball race game apparatus may include a spinning deflector that is configured to hit and propel the balls in any number of directions.
US09418516B2	Loss-reduction insurance in electronic gaming An apparatus enables play of a wagering game in which winning outcomes are determined by random appearance of specific predetermined symbols in which: a player places a wager worth monetary value on a single gaming event in the wagering game; the player purchases with monetary value a safeguard action useful only in the single gaming event; the player receives a first complete set of symbols; if one symbol in the first complete set of symbols prevents or limits an amount of award in the single gaming event, the player exercises the safeguard action to discard the one symbol and have that one symbol replaced with one randomly provided symbol to form a second complete set of symbols; and the wager is resolved against a paytable using the second set of complete symbols.
US09418514B2	Method, apparatus, and program product for controlling contributions to progressive prize pools A method for controlling contributions to a progressive prize pool includes randomly determining whether a progressive pool growth event is triggered for the given play input in a wagering game. Where it is determined that a progressive pool growth event is triggered, the contribution amount is determined and the progressive pool is increased by this contribution amount. Where multiple progressive pools are maintained in a system, additional steps are taken to identify which pool or pools are to be increased when a progressive pool growth event is triggered.
US09418512B2	Perceived skill game and method Disclosed are a game device and method for providing a predetermined prize to a player of an apparent skill game. The player perception is that his skill in playing the device affects the outcome even though the win amount is predetermined. Even if the player does not play with optimum skill, the player will still win the predetermined amount. The perceived skill game may be played as part of a game including wagering or as part of an amusement-only game.
US09418504B2	3-D reels and 3-D wheels in a gaming machine A gaming machine is configured to receive a request for a location of at least one player of at least one gaming device, determine the location of the at least one player; and present on a display of the gaming machine, location information including the determined location of the at least one player. Where the gaming machine is located within a casino, the gaming machine may further be configured to present, on the display, a 3D virtual gaming environment which is a model of the casino.
US09418501B2	Method for digital signature authentication of pin-less debit card account transactions A systems and methods for authenticating a consumer with a transaction card using digital signatures according to one embodiment of the invention is disclosed. These systems and methods allow consumers to digitally sign transaction information with a private key. The private key may be used to digitally sign the transaction, for example, through a hosted or local system that protects the integrity of the private key. A financial institution may authenticate the consumer by decrypting the digital signature with a public key.
US09418498B2	Electronic voter card and method for electronic voting A method for electronic selection includes providing an electronic database, providing an identification card, wherein the card has electronic information storage capacity, providing an electronic selection system, registering and activating the identification card, electronically verifying a unique identifier with the identification card, providing an associated user with options from the electronic selection system, wherein the options are tied to the identification card, electronically confirming selections made by the associated user, electronically downloading the selections from the electronic database to a second electronic database, electronically scanning the identification card, and electronically extracting the selections after scanning the identification card.
US09418495B2	Electronic lock apparatus, method and system A locking device comprising: a code generation means for generating a plurality of access codes in a first series and a second series, each access code being valid for a predetermined period of time, a code input means for receiving an input code, and a code comparison means, wherein the code comparison means is configured to unlock the lock in response to input of a code that corresponds to a currently valid access code, wherein the period of validity of each access code in first series partially overlaps the period of validity two adjacent access codes in the second series.
US09418492B2	Mobile phone enabled data processing system A system monitors and controls pressure of vehicle parts. The system consists of: a fleet of vehicles, each vehicle of the fleet having a cab and a trailer; a controller maintaining a wireless server and database for the fleet of vehicles; a first cellular device transmitting data to and from an electronic control unit of the cab of each vehicle and the controller; and a second cellular device transmitting data to and from an electronic control unit of the trailer of each vehicle and the controller. The first cellular device and the second cellular device each utilize a publicly accessible cellular network for communication with the controller.
US09418488B1	Driver productivity snapshots and dynamic capture of driver status A system for determining productivity coaching information comprises an input interface and a processor. The input interface is configured to receive vehicle event recorder data. The processor is configured to determine a first state based at least in part on a first set of vehicle event recorder data, and determine a second state based at least in part on a second set of vehicle event recorder data. The second set of vehicle event recorder data is different from the first set of vehicle event recorder data. The processor is configured to determine whether the second state following the first state indicates a productivity characterization mode, and indicate to acquire a third set of vehicle event recorder data for a productivity coaching determination.
US09418485B2	Adjusting heights for road path indicators Some embodiments provide a mapping application that receives input to adjust an amount of tilt from which to view a 3D map for a viewing mode in which the 3D map is specified to be textured with camera captured images (CCIs) of the real world. The mapping application also adjusts a set of heights for a set of road path indicators in the 3D map based on the adjusted amount of tilt. Each road path indicator indicates a path of a road in the 3D map. The mapping application further displays the 3D map with the adjusted amount of tilt and the set of road path indicators at the adjusted set of heights in the 3D map.
US09418484B2	Learning system with augmented reality and related learning method using mobile device to conduct simulations and operational training A learning system with augmented reality is provided. The learning system includes a cloud server recording an operation history of a learner and providing feedback messages, and a mobile device having an image-capturing module capturing an image of a substantial object. Also, the learning system comprises an object database storing a simulated object corresponding to the substantial object, an identification module identifying the image and generating image information, and a processing module which receives and analyzes the image information, obtains the simulated object from the object database according to analyzing results, and displays the simulated object on a display interface of the mobile device. The learning system allows learner to operate simulated object operation instructions on the display interface or directly operate the substantial object to control a display status of the simulated object, and the operation history of learner is transmitted to the cloud server. Learner conducts simulation scientific experiments and substantial operational trainings by operating the simulated object or the substantial object, thereby facilitating learning abstract concepts without being limited by the time and space constraints in a conventional learning system.
US09418482B1	Discovering visited travel destinations from a set of digital images Aspects of the disclosure relate to identifying visited travel destinations from a set of digital images associated with users of a social networking system. For example, one or more computing devices provide access to an individual user's account, including the individual user and other users affiliated with the individual user via the social networking system. One or more digital images are received from a computing device associated with the individual user and from one or more second computing devices associated with the other users of the social networking system. From each digital image, a geo-location is determined for each digital image. The one or more computing devices display each geo-located image on a map at a position corresponding to the determined geo-location for the geo-located image.
US09418481B2	Visual overlay for augmenting reality Augmented reality may be provided to one or more users in a real-world environment. For instance, information related to a recognized object may be displayed as a visual overlay appearing to be in the vicinity of the object in the real-world environment that the user is currently viewing. The information displayed may be determined based on at least one of captured images and transmissions from other devices. In one example, a portable apparatus receives a transmitted user identifier (ID) and may submit the user ID to a remote computing device that compares a profile of a user corresponding to the user ID with a profile associated with the portable apparatus for determining, at least in part, information to be displayed as the visual overlay. As another example, the portable apparatus may include a camera to capture images that are analyzed for recognizing objects and identifying other users.
US09418479B1	Quasi-virtual objects in an augmented reality environment A virtual overlay alters the appearance of a quasi-virtual object within an augmented reality environment. This quasi-virtual object may display information to the user, accept input from the user via motions or physical interactions between the user and the object, or both. Quasi-virtual objects allow a virtual object to have a physical manifestation within the augmented reality environment.
US09418478B2	Methods and apparatus for building a three-dimensional model from multiple data sets Methods and apparatus for a map tool displaying a three-dimensional view of a map based on a three-dimensional model of the surrounding environment. The three-dimensional map view of a map may be based on a model constructed from multiple data sets, where the multiple data sets include mapping information for an overlapping area of the map displayed in the map view. For example, one data set may include two-dimensional data including object footprints, where the object footprints may be extruded into a three-dimensional object based on data from a data set composed of three-dimensional data. In this example, the three-dimensional data may include height information that corresponds to the two-dimensional object, where the height may be obtained by correlating the location of the two-dimensional object within the three-dimensional data.
US09418475B2	3D body modeling from one or more depth cameras in the presence of articulated motion The present disclosure describes systems and techniques relating to generating three dimensional (3D) models from range sensor data. According to an aspect, multiple 3D point clouds, which are captured using one or more 3D cameras, are obtained. At least two of the 3D point clouds correspond to different positions of a body relative to at least a single one of the one or more 3D cameras. Two or more of the 3D point clouds are identified as corresponding to two or more predefined poses, and a segmented representation of the body is generated, in accordance with a 3D part-based volumetric model including cylindrical representations, based on the two 3D point clouds identified as corresponding to the two predefined pose.
US09418473B2	Relightable texture for use in rendering an image A model of a scene of an image (e.g. a frame of a video sequence) is generated from one or more views of the scene captured from one or more different camera viewpoints. An initial texture for applying to the model is derived from the one or more views of the scene. The initial texture is separated into a lighting estimate and a color estimate, which may be orthogonal and which may be processed independently. The lighting estimate is filtered with a high-pass filter to thereby determine shadow regions of the scene which are regions of detailed shadow which are likely to be caused by ambient occlusion in the scene and which are therefore retained when the texture is relit for rendering the image. A shadow-detail estimate (or “dark map”) is provided which indicates one or more shadow regions of the texture which are to remain in shadow when the image is rendered.
US09418467B2	3D human models applied to pedestrian pose classification A pedestrian pose classification model is trained. A three-dimensional (3D) model of a pedestrian is received. A set of image parameters indicating how to generate an image of a pedestrian is received. A two-dimensional (2D) synthetic image is generated based on the received 3D model and the received set of image parameters. The generated synthetic image is annotated with the set of image parameters. A plurality of pedestrian pose classifiers is trained through the annotated synthetic image.
US09418464B2	Control of timing for animations in dynamic icons Dynamic icons are described that can employ animations, such as visual effects, audio, and other content that change with time. If multiple animations are scheduled to occur simultaneously, the timing of the animations can be controlled so that timing overlap of the animations is reduced. For example, the starting times of the animations can be staggered so that multiple animations are not initiated too close in time. It has been found that too much motion in the user interface can be distracting and cause confusion amongst users.
US09418457B1	Force-directed graphs Embodiments of the present invention provide systems and methods for graphing networks. In one embodiment, a dampening heuristic is utilized to graph networks to increase their stability. Nodes are visualized by finding local and global minima and equilibrium positions. Factors such as the influence of neighboring nodes; attraction and repulsion phases; and dynamism of complex networks are addressed by embodiments of the present invention. The stability of nodes are measured quantitatively using vectors, degree of influence of neighboring nodes on other nodes, and updating dampening heuristics.
US09418455B1	Graphing parameters of a virtualized computing environment A computer-implemented method for generating a graph of parameters of a virtualized computing environment. The method includes accessing parameters from virtual machine groupings, generating a first graph depicting overall allocation of resources and overall current usage of resources for the virtual data centers, generating a second graph depicting aggregate health of the virtual machine groupings, and generating a third graph depicting allocation of resources of the virtual data centers overlaid with the current usage of resources of the virtual data centers, wherein the first graph, the second graph and the third graph are for display in a single view.
US09418454B1	Generating markup encodings for the compact rendering of curves in interactive graphical designs Various methods and systems that involve systems generating encodings for the compact rendering of curves in interactive graphical designs are disclosed. One method is conducted by a processor and comprises providing an interactive graphical design to a memory. The method also comprises parsing the interactive graphical design to identify a curve having graphical information. The method also comprises decomposing the curve into a set of at least two curve components. The method also comprises generating a markup-coded representation of the interactive graphical design that includes a set of independent elements for rendering the curve, wherein each of the independent elements in the set of independent elements uniquely corresponds to a curve component in the set of at least two curve components.
US09418453B2	Transmission image reconstruction and imaging using poissonian detector data An image reconstruction method for reconstructing an image fmin representing a region of investigation within an object includes providing detector data (yi) having Poisson random values from an X-ray transmission measurement using an X-ray source and a detector device, the detector data (yi) being measured at an i-th of a plurality of different pixel positions of the detector device relative to the object, and reconstructing the image fmin based on the detector data (yi), the reconstructing step including a procedure of minimizing a functional F ⁡ ( f _ ) = 1 k ⁢ ∑ i = 1 k ⁢ ⁢ ( μ i - y i ⁢ log ⁢ ⁢ μ i ) + a ⁢  T - 1 ⁢ f _  p where f is a current test image used for minimizing the functional F(f). The image fmin represents the global minimum of F(f).
US09418450B2	Texture compression techniques A texture compression method is described. The method comprises splitting an original texture having a plurality of pixels into original blocks of pixels. Then, for each of the original blocks of pixels, a partition is identified that has one or more disjoint subsets of pixels whose union is the original block of pixels. The original block of pixels is further subdivided into one or more subsets according to the identified partition. Finally, each subset is independently compressed to form a compressed texture block.
US09418446B2	Method and apparatus for determining a building location based on a building image A method, apparatus and computer program product are provided for determining a building location based on a building image. In the context of a method, the method includes receiving an image including at least one building, extracting building texture features from the image, and receiving reference building texture features. The method also includes determining, using a processor, building texture features comparisons between building texture features and reference building texture features which satisfy a predetermined match threshold and determining a matching building location based upon the building texture features comparison.
US09418441B1	Using depth maps of a scene to identify movement of a video camera A process recomputes zones for a scene. The process is performed at a computing device having one or more processors and memory. The memory stores one or more programs configured for execution by the one or more processors. The process receives a first image of a scene taken by an array of image sensors of a camera system at a first time and receives designation from a user of a zone within the first image. The process also receives a second image of the scene taken by the array of image sensors at a second time that is after the first time. The process compares the first and second images to identify movement of the camera and notifies the user about a change to the zone when the camera has moved.
US09418437B2	Stencil then cover path rendering with shared edges One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.
US09418433B2	Computing a depth map A system for computing a depth map comprising depth values representing distances to a viewer for respective pixels of an image. The system comprises an optimization unit (902) for determining a minimal depth related cost value of a current pixel, among a plurality of candidate cost values, wherein at least one of the candidate cost values is based on a depth related cost value of at least one pixel in a local neighborhood of the current pixel and on a difference between a color attribute of the at least one pixel in the local neighborhood and a corresponding color attribute of the current pixel, and at least one of the candidate cost values is based on a depth related cost value relating to at least one pixel outside the local neighborhood and on a difference between a color attribute of the at least one pixel outside the local neighborhood and a corresponding color attribute of the current pixel.
US09418427B2	Population-guided deformable registration A registration technique is provided that can combine one or more related registrations to enhance accuracy of a registration of image volumes. A registration relationship between a first source volume and a target volume and a registration relationship between the first source volume and a second source volume are concatenated to provide an estimate of a registration relationship between the second source volume and the target volume. The estimate is utilized to inform the direct registration of the second source volume to the target volume or utilized in place of the direct registration.
US09418417B2	Image processing apparatus, tomography apparatus, image processing method, and storage medium An image processing apparatus of the present invention performs reconstruction processing on a projected image of an object obtained by using a radiation source and a detector in order to obtain a tomographic image in which noise has been reduced regardless of the type of reconstruction filter that is used. The image processing apparatus includes a selection unit that selects a reconstruction filter in accordance with an imaging technique; a setting unit that sets an image processing parameter for noise reduction according to the type of the selected reconstruction filter; an image processing unit that performs image processing on the projected image using the image processing parameter; and a reconstruction unit that uses the selected reconstruction filter to perform reconstruction processing on the projected image resulting from the image processing and obtain a tomographic image of the object.
US09418416B2	Methods and apparati for nondestructive detection of undissolved particles in a fluid The apparati, methods, and computer program products disclosed herein can be used to nondestructively detect undissolved particles, such as glass flakes and/or protein aggregates, in a fluid in a vessel, such as, but not limited to, a fluid that contains a drug.
US09418414B2	Image measurement apparatus, image measurement method and image measurement system An image measurement apparatus includes: an image acquiring unit that acquires a sample image that is an image obtained by capturing an image of a sample; a standard color space converting unit that converts the sample image into a standard sample image that is an image in a standard color space; a color distribution normalizing unit that converts the standard sample image into a normalized sample image by converting pixel values of pixels in the standard sample image to cause a color distribution vector indicating a color distribution of the standard sample image to match a predetermined standard color distribution vector indicating a standard color distribution; and a positive rate acquiring unit that detects positive pixels by performing threshold processing on pixel values of pixels in the normalized sample image, and acquires a positive rate indicating a proportion of the detected positive pixels.
US09418413B1	System and a method for automatic recipe validation and selection A system, a non-transitory computer program product and a method for selecting an inspection recipe, the method includes: (i) obtaining an image of a structural element of the semiconductor device; (ii) calculating multiple types of distances between the image of the structural element and each of a plurality of reference images obtained by applying a plurality of inspection recipes; and (iii) automatically selecting at least one selected inspection recipe out of the plurality of inspection recipes based on values of the multiple types of distances.
US09418404B2	Infrared detector system and method An infrared detector system is described in which a despeckle filter is applied to image data generated by a High Operating Temperature (HOT) detector array. The filter reads the data associated with each pixel of the image generated and compares it with selected neighboring pixels. The comparison yields a series of values that are compared to predetermined thresholds and the pixel is scored according to the number of values that exceed the threshold set. The score assigned to the pixel then determines the treatment of the pixel in the image to be generated. The data value of the pixel may be ignored, included or substituted with an alternative calculated value.
US09418403B2	Image processor and non-transitory computer readable medium for generating a reproduction image which is reproduced so that visibility of an original image is enhanced An image processor includes: an image group generating unit that generates, from an original image, a group of images including at least one smoothed image; an illumination image generating unit that generates an illumination image by use of at least one of the images included in the group of images; a smoothed image acquiring unit that acquires a particular smoothed image based on the at least one smoothed image; a reflection rate image generating unit that generates a reflection rate image based on the original image, the particular smoothed image, a synthesizing degree information which represents a synthesizing degree of the original image and the particular smoothed image, and the illumination image, and a reproduction image generating unit that generates a reproduction image which is reproduced so that visibility of the original image is enhanced, based on at least the reflection rate image and an enhancing degree information.
US09418400B2	Method and system for rendering simulated depth-of-field visual effect Systems and methods for rendering depth-of-field visual effect on images with high computing efficiency and performance. A diffusion blurring process and a Fast Fourier Transform (FFT)-based convolution are combined to achieve high-fidelity depth-of-field visual effect with Bokeh spots in real-time applications. The brightest regions in the background of an original image are enhanced with Bokeh effect by virtue of FFT convolution with a convolution kernel. A diffusion solver can be used to blur the background of the original image. By blending the Bokeh spots with the image with gradually blurred background, a resultant image can present an enhanced depth-of-field visual effect. The FFT-based convolution can be computed with multi-threaded parallelism.
US09418390B2	Determining and communicating user's emotional state related to user's physiological and non-physiological data According to various aspects of the present disclosure, a system and associated method and functions to determine an emotional state of a user are disclosed. In some embodiments, the disclosed system includes a data acquisition unit, an emotion determination unit, and an emotion reporting unit. The data acquisition unit is configured to detect user information including physiological and non-physiological data associated with the user. The emotion determination unit is operatively connected to the data acquisition unit, and is configured to process the user information to determine an emotional state of the user. The emotion reporting unit is configured to communicate the emotional state based on a predetermined reporting preference to an application of a communication device, e.g., a social-networking application to share the emotional state of the user such that other members of the social network associated with the user are notified of the user's emotional state.
US09418389B2	Social intelligence architecture using social media message queues A social intelligence system is presented that streams information from a source, queues the streamed information, analyzes/scores the queued data, and stores the analyzed/scored data in an analysis database. The analyzed/scored data can then be retrieved from the database for post-processing and stored in a client specific database for further reporting. By streaming the data into various message queues and scoring the data before storing in the analysis database, large volumes of data can be efficiently processed and analyzed for a particular person and/or entity.
US09418385B1	Assembling a tax-information data structure The disclosed embodiments relate to a tax-information assembly technique, which extracts tax information and associated context information from income-tax documents, where these income-tax documents are associated with an income-tax agency, and some of the income-tax documents include the same tax information in different document formats. During this technique, semantic and structural heuristics are used to identify tax phrases in the extracted tax information. Moreover, additional tax phrases in the extracted tax information are identified using a statistical identification technique. Next, relationships between the tax phrases and the additional tax phrases are determined, and the context information is used to consolidate the tax phrases and the additional tax phrases into a tax-information data structure.
US09418380B2	Information providing device, information providing method, program, information storage medium, and information providing system A plurality of items of data, each having a plurality of items of attribute information, are sorted in order of most comprehensively satisfying conditions relating to the plurality of items of attribute information. An information providing server includes a single sorting unit that calculates, for each of the plurality of items of data having the plurality of items of attribute information and included in a data group, an evaluation value for sorting the data group based on a sort key designated for one of the plurality of items of attribute information. The information providing server includes a multiple sorting unit that sorts the data group based on a plurality of multiple evaluation values that are calculated, for respective items of data included in the data group, based on the evaluation values and the respective weights of the plurality of sort keys, each of the evaluation values being calculated.
US09418379B2	System and method for providing access to product information and related functionalities A system and method for allowing a consumer to quickly access product information and/or commerce functionalities as related to one or more products that are associated with an electronic document, such as a web page, that is currently being viewed by the consumer in an electronic document viewing program, such as an Internet browser.
US09418378B2	Method and system for trying out a product in relation to a real world environment A method, system and computer program are provided to allow one or more users to try out one or more products. The method, system and computer program involve providing information on one or more products offered for sale under restricted conditions of time or quantity, obtaining a real image of an object, determining one or more features from the object image, determining a position to overlay a first product image on the object image based on the determined one or more features, overlaying the first product image on the object image based on the determined position to provide an overlaid image, and displaying the overlaid image. The first product image is an image of a product from the one or more products.
US09418366B1	Ad payment for physical presence A computer-implemented method of determining reaction to promotional items includes providing to a mobile device a promotional item associated with a geographic location, determining whether the mobile device is proximate to the geographic location, and charging an advertising account if the mobile device is proximate to the geographic location.
US09418361B2	Managing recurring payments from mobile terminals Equipments and methods are disclosed for facilitating service provisioning in a system that comprises a payment processor, a number of service providers and a mediator that mediates information exchange between the payment processor and service providers, and a mobile terminal operated by payment card holder. In some implementations, service provisioning can be facilitated in cases wherein the payment processor must reside in a strictly regulated Payment Card Industry (PCI) compliant environment and the service providers operate servers that are not PCI-compliant.
US09418358B2	Pre-configure and customize ATM interaction using mobile device Embodiments of the invention are directed to a system, method, or computer program product for communicating customer preferences to an automated teller machine (ATM). In this way, the system receives at least one customer preference for conducting transactions at an ATM and input from the customer indicating the customer's desire to conduct an ATM transaction. In response to receiving the customer input, the system may generate a customer preference communication for receipt by the ATM, wherein the customer preference communication comprises at least of the at least one customer preferences for conducting transactions at an ATM.
US09418355B2	Crowdsourced responses management to cases A response management system and method configured to allow management of responses to a case submitted by an entity in a crowdsourced network. The system includes a processing circuit that receives, from the entity over the crowdsourced network, the case. The processing circuit federates the case, into a plurality of federated cases, based on one or more parameters. The processing circuit routes the federated cases to the crowd of respondents in the network. The processing circuit receives responses from the crowd for each of the federated cases. The processing circuit integrates responses for each of the federated cases to yield a single integrated response for the case. The processing circuit publishes the integrated response anonymously that is viewable publicly.
US09418353B2	Methods and systems for delivering content to differentiated client devices Methods and systems are disclosed for delivery of tailored content to differentiated devices, such as desktop, mobile, and tablet devices, over a computer network. In one embodiment, a proxy cache server has a content cache for storing previously retrieved objects like web pages or multimedia files. For at least some objects, several versions are stored, each version representing an object suited for a given set of client device characteristics. A device-equivalency data structure maintained at the proxy facilitates a determination of whether such cached versions can be used to service a current request. The versions might represent, for example, modified versions created using, e.g., mobile device transcoding techniques, in response to prior requests. They may also represent a set of alternate content created by a content provider and available from an origin server. Such methods and systems may be implemented in a distributed computing networks, e.g., a content delivery network.
US09418349B2	Fitness facility equipment usage control system A system and method manage distribution of fitness equipment units based upon automatically collected usage information for the fitness equipment units.
US09418348B2	Automatic task assignment system A system is provided that automatically assigns tasks to resources. The system receives a notification that a resource is about to enter an idle period or has entered the idle period. The system further automatically assigns a filler task or a portion of the filler task to the resource, where the filler task is a task that can be split into multiple portions. The system further receives a notification that the resource is about to exit the idle period or has exited the idle period. The system further automatically un-assigns the filler task or the portion of the filler task from the resource.
US09418346B2	Method and apparatus for providing a drawer-based user interface for content access or recommendation An approach is provided for causing, at least in part, a generation of at least one representation of at least one building, wherein one or more floors of the at least one building are represented as one or more drawer user interface elements in the at least one representation. The approach also involves causing, at least in part, an association of one or more content items with the one or more drawer user interface elements, wherein one or more user interactions with the one or more drawer user interface elements causes, at least in part, an initiation of one or more operations on the one or more content items.
US09418334B2	Hybrid pre-training of deep belief networks Pretraining for a DBN initializes weights of the DBN (Deep Belief Network) using a hybrid pre-training methodology. Hybrid pre-training employs generative component that allows the hybrid PT method to have better performance in WER (Word Error Rate) compared to the discriminative PT method. Hybrid pre-training learns weights which are more closely linked to the final objective function, allowing for a much larger batch size compared to generative PT, which allows for improvements in speed; and a larger batch size allows for parallelization of the gradient computation, speeding up training further.
US09418333B2	Synapse array, pulse shaper circuit and neuromorphic system A synapse array based on a static random access memory (SRAM), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits. At least one synapse circuit among the plurality of synapse circuits includes at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor.
US09418331B2	Methods and apparatus for tagging classes using supervised learning Certain aspects of the present disclosure provide methods and apparatus for creating tags (static or dynamic) for input/output classes of a neural network model using supervised learning. The method includes augmenting a neural network model with a plurality of neurons and training the augmented network using spike timing dependent plasticity (STDP) to determine one or more tags.
US09418327B1	Security key system An aspect of the disclosure includes a security system and method having a key with nanoscale features. The key includes a body. At least one pattern member disposed on the body, the pattern member formed using a directed self-assembly polymer to define a pattern of random feature structures thereon, the feature structures having a width of less than 100 nanometers.
US09418321B1	Tagging of tissue carriers with light-activated microtransponders Provided herein, among other things, is an assembly consisting of a tissue cassette or slide and an affixed transponder.
US09418319B2	Object detection using cascaded convolutional neural networks Different candidate windows in an image are identified, such as by sliding a rectangular or other geometric shape of different sizes over an image to identify portions of the image (groups of pixels in the image). The candidate windows are analyzed by a set of convolutional neural networks, which are cascaded so that the input of one convolutional neural network layer is based on the input of another convolutional neural network layer. Each convolutional neural network layer drops or rejects one or more candidate windows that the convolutional neural network layer determines does not include an object (e.g., a face). The candidate windows that are identified as including an object (e.g., a face) are analyzed by another one of the convolutional neural network layers. The candidate windows identified by the last of the convolutional neural network layers are the indications of the objects (e.g., faces) in the image.
US09418317B2	End-to end visual recognition system and methods We describe an end-to-end visual recognition system, where “end-to-end” refers to the ability of the system of performing all aspects of the system, from the construction of “maps” of scenes, or “models” of objects from training data, to the determination of the class, identity, location and other inferred parameters from test data. Our visual recognition system is capable of operating on a mobile hand-held device, such as a mobile phone, tablet or other portable device equipped with sensing and computing power. Our system employs a video based feature descriptor, and we characterize its invariance and discriminative properties. Feature selection and tracking are performed in real-time, and used to train a template-based classifier during a capture phase prompted by the user. During normal operation, the system scores objects in the field of view based on their ranking.
US09418315B1	Systems, methods, and computer readable media for extracting data from portable document format (PDF) files According to one method, the method occurs at a data file analyzer. The method includes identifying at least one document identifier associated with a first document in a portable document format (PDF) file. The method further includes determining, using the at least one document identifier, a reference point identifier for identifying a reference point in the first document, an offset value for indicating a location of a first detection area in the first document, and size information for indicating a size of the first detection area in the first document. The method also includes identifying, using a reference point identifier, the reference point in the first document. The method further includes identifying, using the offset value and the size information, the first detection area in the first document and extracting, by processing binary data of the PDF file, data within the first detection area of the first document.
US09418312B2	Coarse document classification Systems and methods coarsely classify unknown documents in a group or not with reference document(s). Documents get scanned into digital images. Counts of contours are taken. The closer the counts of the contours of the unknown document reside to the reference document(s), the more likely the documents are all of a same type. Embodiments typify contour analysis, classification acceptance or not, application of algorithms, and imaging devices with scanners, to name a few.
US09418311B2	Multi-scale tone mapping Methods, devices and computer readable instructions to generate multi-scale tone curves are disclosed. One method includes finding, for a given input image, a global tone curve that exhibits monotonic behavior. The input image may then be partitioned into a first number of sub-regions. For each sub-region, a local tone curve may be determined that has an output level that is constrained to the global tone curve at one or more first luminance levels so that each sub-region's local tone curve's output follows the global tone curve's monotonic behavior. If the resulting local tone curves provide sufficient control of shadow-boost, highlight-suppression, and contrast optimization the first number of local tone curves may be applied directly to the input image. If additional control is needed, each sub-region may again be partitioned and local tone curves determined for each of the new sub-regions.
US09418308B2	Automatic evaluation of line weights Systems and methods may automatically evaluate printed line weights in an image composition. An image composition may be received and the number of horizontal and vertical rows of pixels may be determined. The number of positive pixels in each of the horizontal and vertical rows may then be determined. An actual size of a pixel may be calculated. The actual size of a pixel may be multiplied by the number of positive pixels in each of the horizontal rows and each of the vertical rows to determine a positive line weight of each of the horizontal rows and each of the vertical rows. A predetermined minimum permissible positive line weight for the image composition may be identified and compared to the positive line weight of each of the horizontal rows and each of the vertical rows.
US09418306B2	Iris recognition device and mobile device having the same An iris recognition device, a mobile device having the same, and a method of biometric authentication using the same are provided. The iris recognition device includes: a light source unit configured to transmit a light signal to an iris; and a light source receiver configured to receive a reflected light signal of an image of the iris from the iris, and remove an offset of the reflected light signal, corresponding to noise in the iris image, using a plurality of reference signals having different phases.
US09418302B2	Method and apparatus for recognizing road shape A method and an apparatus are provided to recognize a shape of a road on which a vehicle is traveling. Road edge shapes on a left side and a right side of the vehicle are recognized, from positions of roadside objects detected based on detection information from an on-board radar. Lane shapes that are shapes of lane boundary lines on the left side and the right side of the vehicle are recognized, from positions of lane boundary lines detected based on an image captured by an on-board camera. For each of the left side and the right side, such that the recognized road edge shape and the recognized lane shape are compared with each other, and the road shape is identified based on the comparison results.
US09418301B2	Low-speed impact detection sensor array A vehicle system has a sensor array and a processing device. The sensor array includes a first group of sensors and a second group of sensors. The sensors of the first group are offset relative to the sensors in the second group. The processing device is configured to determine a general shape of an impact object based at least in part on signals received from the sensor array.
US09418300B2	Device, method, and computer for image-based counting of objects passing through a counting section in a specified direction For operators of public or commercial buildings, such as supermarkets, it is interesting to determine how many persons, in particular potential buyers, enter the building each day. In other areas, as well, entering and exiting moving objects are counted: it is typical, for example, that cars driving into and out of a parking garage are counted. The invention relates to a device 1 for counting objects in a monitoring area, having a counting module 9, wherein the counting module comprises an object counter increasing by one counting value when one of the objects completely passes through a counting section 6 in a counting direction 4 as a counting object, having at least one monitoring camera 2 for capturing the monitoring area, wherein the monitoring camera 2 is designed for outputting an image data stream of the monitoring area, and having an extraction module 10 designed for extracting moving image areas in a current image of the image data flow, wherein the moving image areas can represent the objects or partial segments thereof, wherein the counting module 9 is designed for increasing the object counter 9 by a partial value for each current image for one of the moving image areas 3, the direction of motion thereof corresponding to the counting direction 4 and thus representing a potential counting object or a partial segment thereof, said partial value being less than the counting value.
US09418294B2	Storing information for access using a captured image An electronic device associates first information and at least a first portion of a first image, and uses a second image that includes a portion corresponding to at least the first portion of the first image to access the associated first information.
US09418293B2	Information processing apparatus, content providing method, and computer program There is provided an information processing apparatus including a trigger recognition unit configured to acquire a captured image of a trigger and recognize predetermined trigger information included in the captured image, and a content acquisition unit configured to acquire a content including augmented reality information which is based on a state at a time of capturing the captured image or a state of content acquisition in a past and which corresponds to the predetermined trigger information recognized by the trigger recognition unit.
US09418290B2	System and method for managing water A device includes an image data receiving component, a vegetation index generation component, a GLC matrix component, a plurality of classifying components and a voting component. The image data receiving component receives multiband image data of a geographic region. The vegetation index generation component generates a normalized difference vegetation index based on the received multiband image data. The GLC matrix component generates a grey level co-occurrence matrix image band based on the received multiband image data. The classifying components generate land cover classifications based on the received multiband image data, the normalized difference vegetation index and the grey level co-occurrence matrix image band. The voting component generates a final land cover classification based a majority vote of the land cover classifications.
US09418286B2	Information processing device, information processing method, and program An information processing device includes a feature amount extraction unit configured to extract each feature amount from a connected image generated by connecting images photographed from different viewpoints; and a specific object recognition unit configured to perform a process of determining a position of a specific object based on the feature amount extracted by the feature amount extraction unit. The feature amount extraction unit performs a feature amount extraction process to which a separated filter in which filter-formed regions are set to be separated is applied.
US09418282B2	Method and device for authenticating documents marked with photochromic systems A method for checking the genuineness of a security feature on a security document. The security feature exhibits an alteration in the visible range when excited by a flash of light. The method comprises taking at least one first image of the unexcited security feature using a mobile telephone camera with an integrated flash function. Then, exciting at least one second image of the security feature using the flash function of the same mobile telephone. Optionally, setting up a wireless link using the telephone function or an Internet function on the mobile telephone, and at least one or both of the images or an authentication function derived from the difference between the two images is/are transmitted to a receiver having a database, the authentication is evaluated and/or the authentication is logged with the receiver.
US09418280B2	Image segmentation method and image segmentation device An image segmentation method and an image segmentation device are provided. The method comprises receiving a video image of a dynamic movement of a target object, acquiring a full-image optical flow of the video image to estimate a first displacement of each pixel therein, acquiring a background optical flow of the video image to estimate a second displacement of a background pixel therein; comparing the first displacement with the second displacement to obtain a foreground region of the target object; extracting feature points in the video image in the foreground region, calculating a probability density of the feature points to determine a number of the target objects; performing visual tracking and movement trajectory analysis on the target object to track the same; performing stationary judgment and image segmentation on the target object according to an interframe displacement of the feature points, an interframe cutting window similarity and tracking box scaling.
US09418273B2	Structure for multicolor biometric scanning user interface A mobile computing device including a biometric scanning interface that changes color in response to a predetermined condition. The biometric scanning interface comprises a layer of heat-sensing elements and a multi-element layer comprising heating elements and thermochromic polymer elements. When the predetermined condition is detected, a driver is adapted to control the thermochromic layer to change color.
US09418272B2	Configurable barcode processing system A barcode processing system receives barcode data obtained by scanning a barcode. The system then determines a path of a software object, processes the barcode data with the software object, and determines whether the barcode is of a barcode type that is implemented by the software object. When the barcode is not of the barcode type that is implemented by the software object, the system repeats the determining of the path, the processing of the barcode data, and the determining of whether the barcode is of the barcode type implemented by the software object.
US09418271B2	Embedding information in an image for fast retrieval A binary bit-string is encoded in a circular image. The circular image encodes substrings of the bit-string in sectors of the circular image and includes redundant bits, error correcting codes, and metadata pertaining to the encoding scheme. To encode the bit-strings, a circular image is generated that includes a center ring and a first ring. Outward from the first ring, additional rings represent bits in the bit-string according to the width of each ring. The exterior of the image includes an outer boundary ring. The width of the boundary rings is used to define the widths representing the value of each ring. To extract a bit-string from an image, the center of the circular image is identified and a direction is selected to evaluate the image outward, determining the boundaries of each ring. The boundaries are analyzed to determine the width of each ring and the encoded bit values.
US09418268B2	System and method for setting a real-time clock of a barcode reading device The present disclosure provides a system and method for setting the time for an internal clock function of a barcode reader and enabling the barcode reader to associate time, as determined by the internal clock function, with production barcodes read during operator use of the barcode reader and delivery of the combination of production barcodes and the associated time to a host system.
US09418266B1	Tracking oilfield assets with a universal identification protocol Systems and methods for tracking assets are provided. In some aspects, a method includes generating a tracking identifier for an asset and storing the tracking identifier in a wireless tag associated with the asset. The tracking identifier includes a protocol identifier that identifies a protocol used for generating the tracking identifier. The tracking identifier also includes an asset identifier that identifies a class to which the asset belongs. The tracking identifier also includes at least one data load that identifies an element specific to the asset. The tracking identifier also includes at least one data load type identifier that identifies a type of a corresponding element specific to the asset or provides an end-of-data indication. The tracking identifier also includes at least one data load size identifier that identifies a size of a corresponding data load.
US09418265B2	RFID reader having an array of antennas An RFID reader for tracking a plurality of RFID tags, the RFID reader comprising an array of multilayer antennas each multilayer antenna comprising a first coil and a second coil, the first coil being superimposed above the second coil; and an electronics unit configured to transmit a signal to and receive and process information from each multilayer antenna.
US09418260B2	Methods and apparatus for ceiling-mounted RFID-enabled tracking Systems and methods for tracking a subject using radio-frequency identification (RFID). In an embodiment, an antenna array comprising a plurality of articulating brackets and a plurality of antennas is provided. Each of the articulating brackets is configured to move one of the plurality of antennas into a plurality of positions, and each of the antennas is configured to receive a RFID signal. In addition, a processor receives RFID data based on RFID signals received by the antennas of the antenna array, and determines a trajectory of a subject based on the RFID data. Based on the determined trajectory of the subject, the processor controls one or more of the articulating brackets to move one or more of the antennas into a position to track the subject.
US09418256B2	RFID system The present invention provides an automated system for asset tracking and management and utilizes near field Radio Frequency IDentification (RFID) technology. RFID tags are attached to the assets via a flexible mounting system, and RFID antennas (and corresponding readers) are strategically located in close proximity to read the tags. As applied to a rack or cabinet, near-field antennas are mounted along one of the mounting posts at each rack unit location such that when a piece of equipment (rack mounted or rail mounted) is installed at a particular rack unit space, the tag will be read and registered in an RFID management system. A magnetic field shaping arrangement ensures that crosstalk between adjacent rack positions is prevented. Ferrite elements are used to control the magnetic field.
US09418252B2	Symbol reading system having predictive diagnostics A retail information network includes one or more POS scanning and checkout systems, each including (i) a bar code symbol reading subsystem, and (ii) a cash register computer subsystem interfaced with the bar code symbol reading subsystem and a network infrastructure, and each having access to product and price data maintained in a product/price database. The bar code symbol reading subsystem includes a local predictive error event (PEE) data store for logging and storing predictive error events (PEEs) detected within the bar code symbol reading system, wherein said PEEs are subsequently sent to POS information servers used to create predictive error alerts (PEAs) and corresponding instructions to maintain and/or repair certain aspects of the bar code symbol reading system.
US09418251B2	Mesh grid protection system A mesh grid protection system is provided. The system includes assertion logic configured to transmit a first set of signals on a first set of grid lines and a second set of grid lines. The system also includes transformation logic to transform the first set of signals to generate a second set of signals, to transmit the second set of signals on a third set of grid lines that are coupled to the first set of grid lines, and to transmit the second set of signals on a fourth set of grid lines that are coupled to the second set of grid lines. In addition, the system includes verification logic to compare the second set of signals on the third and fourth set of grid lines to an expected set of signals.
US09418247B2	Security system and methods for integrated devices Systems and methods for implementing security mechanisms in integrated devices and related structures. This method can include validating a device ID, generating a random value based on selected seed parameters, performing logic operations from hardware using the random value, and validating the integrated device based on logic operations from software using the random value. The system can include executable instructions for performing the method in a computing system. Various embodiments of the present invention represent several implementations of a security mechanism for integrated devices. These implementations provide several levels of encryption or protection of integrated devices, which can be tailored depending on the hardware and/or software requirements of specific applications.
US09418246B2	Decryption systems and related methods for on-the-fly decryption within integrated circuits Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.
US09418240B2	Database hierarchical inheritance A database system comprising a plurality of access keys stored in a first data memory device sector, each access key associated with a node value stored in a second data memory device sector. An access key processor configured to receive an input value and return the associated node value for the input value if the input value matches an access key stored in the first data memory device sector. The access key processor is configured to generate a revised input value if the input value does not match an access key stored in the first data memory device; a default node value stored in the second data memory device sector and associated with a portion of the input value, wherein the access key processor is configured to return the default node value as part of the revised input value.
US09418237B2	System and method for data masking A system, computer-readable medium, and method for masking data including receiving a request directed to a network service, applying a rule set to the request to identify sensitive data which is responsive to the request, rewriting the request, based on the rule set, such that the rewritten request will result in the sensitive data being retrieved and converted into a masked format according to one or more instructions in the rewritten request, and transmitting the rewritten request to the network service.
US09418236B2	Method and system for dynamically and automatically managing resource access permissions Employment role data, trust data, and special permissions data, associated with a party is automatically obtained and/or monitored. The employment role data associated with the party, the trust data associated with the party, and the special permissions data associated with the party, is then analyzed to determine a set of allowed access permissions data to be associated with the party, the set of allowed access permissions data providing the party access to one or more resources. It is then either recommended that the set of allowed access permissions data be provided to the party, or the set of allowed access permissions data is automatically provided to the party.
US09418232B1	Providing data loss prevention for copying data to unauthorized media A processing device detects a file system call that is associated with copying data to a destination file. The processing device identifies an application initiating the copying of the data to the destination file and determines one or more files that are opened by the application. The processing device identifies a source file from the one or more files opened by the application. The source file corresponds to the destination file. The processing device determines whether the source file includes data to be protected and allows or denies the copying of the data to the destination file based on whether the source file includes data to be protected.
US09418231B2	Perturbation of field programmable gate array code to prevent side channel attack Technologies are provided to automatically vary a structure of a netlist computation arranged to configure a field programmable gate array (FPGA). In an example scenario, an FPGA netlist may be received from a client to configure the FPGA. A perturbation generator may be activated in response to a detection of one or more security risk factors associated with the netlist. The netlist may be altered through schemes designed to repair one or more FPGAs. The repair schemes may be used to repair the FPGAs to work around failed cells and failed sub-cells. The perturbation generator may produce a false map of failed cells. The false map may be used to generate different timings and different intermediate values associated with the netlist to generate an alternate netlist. The alternate netlist may be used to configure the FPGA to prevent side channel attacks.
US09418229B2	Firmware security One embodiment provides an apparatus adapted to perform a secure firmware upgrade. The apparatus includes a first memory and a second memory. The first memory stores a private key for use in decrypting content and a unique identifier corresponding to the apparatus. The second memory includes a first version of firmware for the apparatus. The apparatus further includes a controller configured to perform an operation that includes receiving a first request to perform a firmware update operation for the apparatus. The operation also includes transmitting a second request for a second version of firmware to a remote server, the second request specifying the unique identifier corresponding to the apparatus. Additionally, in response to transmitting the second request, an encrypted firmware package is received from the remote server. The operation further includes decrypting the encrypted firmware package using the private key and installing the decrypted firmware package on the apparatus.
US09418228B2	Information technology enterprise intrusion prevention implementation tool The software application for implementing intrusion prevention devices of the present invention has an information flow schema, mathematical calculation algorithm and a Web portal. The devices have built-in intelligence, which is used to match user's implementation requirements.
US09418227B2	Detecting malicious software A computer implemented method, apparatus, and program code for detecting malicious software components. A series of calls made by a software component is monitored to identify an identified respective series of call types to components named in said calls. A determination is made as to whether the identified respective series of call types to components named in said calls is indicative of malicious behavior.
US09418223B2	System and method for securing embedded controller communications by verifying host system management mode execution An information handling system includes a processor operable to provide a branch trace message, and an embedded controller coupled to the processor via a primary interface and via a management interface. The embedded controller receives a management transaction from the processor via the primary interface. In response to receiving the management transaction, the embedded controller requests the branch trace message via the management interface and determines if the processor is operating in a system management mode based upon the branch trace message.
US09418222B1	Techniques for detecting advanced security threats Techniques for detecting advanced security threats are disclosed. In one particular embodiment, the techniques may be realized as a method for detecting a security threat including generating a resource at a client, implementing the resource on the client, monitoring system behavior of the client having the resource implemented thereon, determining whether a security event involving the implemented resource has occurred based on the monitored system behavior, and generating a report when it has been determined that the security event has occurred.
US09418218B2	Dynamic rendering of a document object model The present application relates to a computer having a processor configured to execute a set of instructions to render a customized version of a restricted document object model. A restricted element in a document object model is identified and at least one rule associated with the restricted element is accessed. The at least one rule is applied to the restricted element to generate a modified document object model which is then rendered. A related computer-implemented method is also covered by the present application. The present application relates to server-side authentication techniques; content filtering based on user-specific and context-based requirements; and audit trail techniques.
US09418213B1	Delegated permissions in a distributed electronic environment Permissions can be delegated to enable access to resources associated with one or more different accounts, which might be associated with one or more different entities. Delegation profiles are established that are associated with at least one secured account of at least one customer. Each delegation profile includes information such as a name, a validation policy that specifies principals which may be external to the account and which are permitted to assume the delegation profile, and an authorization policy that indicates the permitted actions within the account for those principals which are acting within the delegation profile. Once a delegation profile is created, the profile can be available for external principals or services that provide a user credential delegated access under the account, where that credential is provided by a trusted identity service. Access can be provided across accounts using the user credential.
US09418212B2	Memory access control An apparatus comprising: a memory having at least two sections; a security element associated with at least one of said at least two sections; and a processor for controlling access to at least one of the at least two sections of the memory in dependence on a value of the security element. The apparatus may be an integrated circuit and the memory may be a read-only-memory storing generic code in one of the sections and code specific to a mobile communication device provider in the second section. The security element may be a permanently programmed memory element programmed by the IC manufacturer.
US09418208B2	Distribution of digital content protected by watermark-generating password A receiver receives digital content scrambled using a control word and a user code for the scrambled content. A user inputs the user code that is forwarded to a code extractor that generates the control word and a user identifier from it. The control word is sent to a descrambler, a watermark information generator and a visible watermark insertion unit. The descrambler descrambles the scrambled content using the control word, an invisible watermark insertion unit inserts invisible watermark information obtained from the watermark information generator into the descrambled content and the visible watermark insertion unit inserts the user identifier as a visible watermark. Also provided are a corresponding method for processing digital content and a method and a device for generating the user code.
US09418205B2	Proximity-based system for automatic application or data access and item tracking A system and method provide automatic access to applications or data. A portable physical device, referred to herein as a Personal Digital Key or “PDK”, stores one or more profiles in memory, including a biometric profile acquired in a secure trusted process and uniquely associated with a user that is authorized to use and associated with the PDK. The PDK wirelessly transmits identification information including a unique PDK identification number, the biometric profile and a profile over a secure wireless channel to a reader. A computing device is coupled to the reader. An auto login server is coupled to the reader and the computing device and launches one or more applications associated with a user name identified by the received profile.
US09418202B2	Predicting transition from laminar to turbulent flow over a surface A prediction of whether a point on a computer-generated surface is adjacent to laminar or turbulent flow is made using a transition prediction technique. A plurality of instability modes are obtained, each defined by one or more mode parameters. A vector of regressor weights is obtained for the known instability growth rates in a training dataset. For an instability mode in the plurality of instability modes, a covariance vector is determined. A predicted local instability growth rate at the point is determined using the covariance vector and the vector of regressor weights. Based on the predicted local instability growth rate, an n-factor envelope at the point is determined.
US09418200B2	Integrated circuit design system and method of generating proposed device array layout A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints.
US09418195B2	Layout content analysis for source mask optimization acceleration The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign. In further implementations, the difficult-to-print sections may be subjected to a source mask optimization process. Subsequently, the entire layout design may receive a conventional resolution enhancement treatment using the optimized source.
US09418192B1	Pass eco flow based on reduced timing scope timer Modifying a circuit includes: obtaining timing information of the circuit, wherein the timing information includes timing information pertaining to a critical path of the circuit; determining a scope associated with the critical path, the scope including a subset of the circuit; and performing a fix based at least in part on physical information associated with the circuit to improve timing of the scope.
US09418189B2	SRAM layouts Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.
US09418184B2	Determining flow through a fracture junction in a complex fracture network Determining flow through a fracture junction in a complex fracture network. A flow of a fracturing fluid through a fracture junction of a complex fracture network is modeled using a fluid flow model that models flow based, in part, on mass balance and momentum balance. The fracture junction includes a first outlet to flow a first portion of the fracturing fluid and a second outlet to flow a second portion of the fracturing fluid. A ratio of a first volumetric flow rate of the first portion and a second volumetric flow rate of the second portion, and the pressure drop across the junction are determined in response to modeling the flow of the fracturing fluid through the fracture junction according to the fluid flow model. The determined ratio of flow rates and/or the determined pressure drop is provided.
US09418183B2	Model development environment for assisting user in developing model describing condition of industrial asset Among other things, one or more techniques and/or systems are provided for facilitating development, by a user, of a model describing a condition of an industrial asset. An output parameter of the model can be defined within a model development environment. The output parameter describes a condition of the industrial asset and can be defined using one or more variables. During deployment of the model within a deployment environment, respective variables of the model can be mapped to a data store where data associated with the variable is located. In this way, during development, a user can specify variables to be used within the model without specifying where to fetch and/or push data associated with the variable, for example. Further, the model can be executed within the deployment environment to assess the condition for a plurality of industrial assets.
US09418174B1	Relationship identification system According to one embodiment, a computer-executed system includes a relationship identification tool coupled to one or more data storage systems and a user interface. Each data storage system has multiple data entities that are organized in at least one folder according to a particular taxonomy scheme. The relationship identification tool is operable to receive data entities from the data storage systems, and determine relationship intimacy values for each data entity relative to the other plurality of data entities according to its taxonomy scheme. These relationship intimacy values are then displayed on the user interface.
US09418167B2	System and method for invoking web services from command-line program A method for invoking web services includes invoking a command-line program. The program receives a plurality of parameters. The method further includes generating a web service request based on the plurality of parameters. The web service request comprises an extensible markup language (XML) document, and the XML document comprises information indicating an application command. The method also includes transmitting the web service request to a server using a network communication protocol.
US09418165B2	Context recognition through screensharing A method and a system for contextual recognition through screen-sharing are provided. Example embodiments may include receiving a data stream related to a presenter screen in a network-based collaboration session from a first user; extracting characteristic data from the data stream; associating added data with the data stream, based on the data; and presenting, in real time, to a second user, a viewer screen including the data stream and the added data. The method may also include recognizing the characteristic data before the extracting of the data.
US09418160B2	Hash tag management in a microblogging infrastructure Architecture that provides enhanced tag telemetry in a microblogging communications infrastructure. The architecture provides efficient discovery and tracking of topics that are of interest to a specific user by enabling users to follow (track) hash tags (#tag) and to receive and view all messages tagged with the hash tag appear in the user's personal feed. Each hash tag has a persisted tag page that aggregates all the associated activity, and includes a list that includes, but is not limited to, the tag followers, the most frequent user (uses the tag the most often in a specific time frame), a description, related tags, for example. The user can receive all the updates in the user's personal feed, and see an aggregation of all the messages and conversations associated with the tag in single place. The user can also mute the tag to prevent the receiving of tag information.
US09418158B2	Providing multi-lingual searching of mono-lingual content Approaches for translating a transliterated search query are provided. An approach includes receiving a search query containing a transliterated word. The approach also includes determining a source language corresponding to the transliterated word. The approach further includes converting the transliterated word to a word in the source language. The approach additionally includes translating the word in the source language to a word in a target language. The approach also includes performing a search using the word in the target language.
US09418155B2	Disambiguation of entities Methods, systems, algorithms, and media are provided for disambiguating entities present in a received search query. Lists of categories from semi-structured data from external sites as well as internal sources are used to detect if ambiguity exists in an entity within the search query. Multiple senses or categories of the ambiguous entity are determined by ascertaining the primary intent of an entity extracted from a main term of a document. The probability of each sense is calculated by computing a total amount of traffic received for each of the senses of the ambiguous entity. The sense with the highest amount of computed traffic is the most probable determined sense.
US09418154B2	Push-model based index updating A method and apparatus for push-model based index updating. In one embodiment of the method, a first transaction generated for modifying or inserting a first data object into a memory. A first message is generated in response to generating the first transaction, wherein the first message comprises information related to an identifier of the first data object, wherein the first message comprises information that indicates that the first data object was or will be modified or inserted into the memory, and wherein the first message comprises a copy of some or all of the data contents of the first data object; transmitting the first message to a computer system that implements a search engine.
US09418151B2	Lexical enrichment of structured and semi-structured data Generally discussed herein are systems and methods for lexically enriching structured and semi-structured data. In one or more embodiments, a method can include receiving a code, lexicalizing the code, lexically combining the lexicalized code with a lexical descriptor, and sending the lexical combination to a keyword database.
US09418147B2	Method and apparatus of determining product category information A user may submit product title information to a server. The server may generate a phrase based on the product title information. The server may then search a database to find relevancies between the phrase and product categories corresponding to multiple nodes in a product category tree. Based on the relevancies, the server may select a node from the multiple nodes. The server may associate the product title information with the node corresponding to a product category when the node is a leaf node of the product category tree.
US09418145B2	Method and system for visualizing documents Method and system for visualizing documents. N-dimensional compact representations are obtained for a set of documents. A plurality of documents is retrieved with corresponding N-dimensional compact representations and each of the retrieved documents is associated with one or more concepts. Each retrieved document is projected to a point on a K-dimensional map based on its N-dimensional compact representation so that projected document points in the K-dimensional map maintain the relative distances among the retrieved documents in the N-dimensional space. Regions in the K-dimensional map associated with concepts are identified. A label is generated for each concept in each identified region. Then generated labels are then rendered on the K-dimensional map in a corresponding region identified.
US09418142B2	Overlapping community detection in weighted graphs The disclosure includes a system and method for detecting communities in a weighted graph. The community detection module includes a tagset data aggregator, a counts statistics engine, a weighted graph generator, a coherence engine, a community detector and a tag recommendation engine. The tagset data aggregator receives tagset data. The counts statistics engine determines counts statistics for the tagset data. The weighted graph generator generates and denoises weighted tag occurrence graph based on the counts statistics. The coherence engine determines importance score for all tags and coherence score for all tagsets in the tagset data. The community detector determines maximally coherent communities in the weighted tag co-occurrence graph. The tag recommendation engine recommends tags in real time using the maximally coherent communities.
US09418141B2	Systems and methods for providing a multi-function search box for creating word pages A multi-function search box on a word page is provided to enable a user to enter a word. The multi-function search box includes a text input control to provide text input functionality. The text input control is capable of suggesting a complete word based on a partially entered word. A dropdown display area is provided in the multi-function search box to display a list of words, every word therein contextually related to the fully entered or partially entered word. Another dropdown display area is provided to display contextually related options for a selected word in the list of contextually related words.
US09418140B2	Method of updating an inverted index, and a server implementing the method A method of updating an inverted index from at least one electronic document in which each electronic document is constituted by at least one ordered set of objects comprises is described. The method includes, for each object, identifying a descriptor of the object where the descriptor is represented in the form of a tree and then determining a terminal leaf of the tree. Subsequently, a packet of information pointed to by the leaf is updated where the packet of information includes at least a list of documents that include the object.
US09418139B2	Systems, methods, software, and interfaces for multilingual information retrieval The present inventors have a devised one or more novel methods, systems, and interfaces for facilitating multi-lingual searches. One exemplary method entails creating multiple language-specific indices for a collection of documents, with each index including stemmed and non-stemmed versions of terms from the documents. Users submit queries that are associated with a set of one or more target languages. Query processing entails translating original and stemmed versions of each term in a query into each of the target languages, using one or more techniques that each yield a set of potentially equivalent query terms. Each set of potentially equivalent query terms is then processed against the corresponding language-specific index, using a conventional monolingual search technique, such as a Boolean or natural language query, to identify documents from the collection. The resultant documents are presented to the user in language groupings or by computed relevance.
US09418135B2	Primary database system, replication database system and method for replicating data of a primary database system Embodiments of the present disclosure are directed to a database system and methods for storing and replicating data of a primary database. A method for replicating data item may include receiving replication data from a primary database system and replicating the one or more data items of the primary database system in accordance with the replication data. The replication data may include a transaction log including information on transactions processed by the primary database system and database lock data relating to at least one lock on the one or more data items of the primary database system in order to support simultaneous queries to the primary and replication database systems. The method may also include rolling-back the replication data in the at least one replication database system based on the information on transactions processed by the primary database system and the database lock data.
US09418134B2	Managing replication configuration availability A computer-implemented method, carried out by one or more processors, for managing replication configurations. In an embodiment, the method comprises receiving, by one or more processors, a replication configuration for replicating data, wherein the replication configuration defines at least a target table in a target database based on a source table in a source database; initializing, by one or more processors, a federated view, wherein the federated view is based on at least the source table in the source database as defined in the replication configuration; utilizing, by one or more processors, the federated view to satisfy requesting applications, where requesting applications obtain data from the federated view; responsive to determining the replication of data is in spec, utilizing, by one or more processors, the target table in the target database to satisfy requesting applications.
US09418133B2	Data replication with delta compression Data replication with delta compression is disclosed. A primary system and a replica system are determined to both have an identical first data segment that is similar to a second data segment. The second data segment is encoded, wherein the encoding refers to the first data segment.
US09418130B2	Data replication protocol with efficient update of replica machines Steady state data distribution is provided between a client application, a leader machine, and a plurality of replica machines. The distribution comprises the leader machine receiving an operation request from the client application, the leader machine sending the prepare message to each of the plurality of replica machines, the replica machines recording in their logs information on the operation, the replica machines sending acknowledgement messages to the leader machine, and the leader machine sending commit command messages to the replica machines. A new quorum of the replica machines is created by using log information. Replica machines that become part of the new quorum are updated in an efficient manner.
US09418129B2	Adaptive high-performance database redo log synchronization A method, system, and computer program product for adaptive high-performance database redo log synchronization. The method commences upon performing a write operation of a redo log entry, the write operation concluding with an indication of completion of the write operation of the redo log entry. Any number of committing processes may be waiting for the indication of completion, and upon indication of completion, then (using a first synchronization mode) the processes or proxy measures the waiting time as experienced by the committing processes (e.g., while waiting for the indication of completion of the write operation of the redo log entry). In some cases a second synchronization mode would introduce less latency than the first synchronization mode, so the system changes to a second synchronization mode. The system can also change mode when a predicted second mode waiting time is smaller than the measured waiting time.
US09418128B2	Linking documents with entities, actions and applications Individuals often perform search queries with the intent of performing a particular action based on the search results. In an embodiment, mentions are identified in a document and candidate entities for the mention are identified. Confidence scores for mention-entity pairs are determined based on relationships between candidate entities, and entities are selected based on the scores. Selected entities are ranked indicating their relevance to a topic of the document. Actions associated with the selected entities are identified. Based on an intent of a search query that returned the document in search results, relevant actions are selected and links are presented within the search results to applications that perform the actions.
US09418127B2	Method and system for designing business domain model, data warehouse model and mapping therebetween synchronously Method and system for designing a business domain model, a Data Warehouse (DW) model and a mapping therebetween synchronously are provided. The method includes: designing a business domain model based on business logic; designing a DW model based on a structure of a data cube in a DW and designing a mapping between the business domain model and the DW model synchronously; analyzing the business domain model, the DW model and the mapping therebetween based on a predetermined syntax rule; and generating a transactional database corresponding to the business domain model, a DW database corresponding to the DW model, and a mapping between data in the transactional database and in the DW database automatically and synchronously. The system includes a business domain model design unit, a DW model design unit, a mapping design unit, an analysis unit and an automatic generation unit. Mappings are designed more easily, efficiently and accurately.
US09418125B2	Method and apparatus for employing a searchable abstraction layer over enterprise-wide searchable objects A mechanism for dynamically configuring searchable fields of interest within an enterprise-wide search center is provided. Such functionality is provided through the creation and maintaining of an abstraction layer that represents the searchable fields of interest, which are gathered from the total available fields from enterprise-wide searchable objects. The abstraction layer is defined through the use of a field mappings file that relates searchable fields of interest in searchable objects with fields within a search index accessible to the search center. The field mappings file can provide the defined relationships between searchable object fields and search index fields at runtime of a user session, thus avoiding a rigid configuration at the time of search center initialization. Through such runtime modification of the abstraction layer, costly downtime due to revision of a configuration of the search center can be avoided and a dynamic flexibility in the presentation of the fields in the searchable objects can be provided without a need for modification of the searchable objects themselves.
US09418122B2	Adaptive user interface for real-time search relevance feedback A method and apparatus for dynamically adjusting the user interface of a search engine in order to effectively communicate the improved relevancy achieved through real-time implicit re-ranking of search results is described. Real-time implicit re-ranking occurs without delay after every user action as the search is being conducted, so finding methods of immediately altering the search page without disrupting the user experience is important. Graphical icons next to search results are employed to enable generating and removing re-ranked results, referred to as “recommended” search results. Clusters based on the real-time user model are also displayed to facilitate query reformulations. Sponsored links are selected using the real-time user model along with a combination of RPC and CTR information and are displayed in a manner similar to the organic results, or used to replace the initial sponsored links altogether.
US09418119B2	Method and system to determine a category score of a social network member A method and system to determine a category score of a social network member is described. An example system comprises a sample selector, a weight value module, a storing module, an access module, and a category score module. The sample selector selects a sample of member profiles from the profiles maintained by an on-line social network system. The weight value module obtains respective weight values associated with various phrases present in the sample of member profiles. The access module accesses a member profile and the weighted phrases associated with a certain category. The category score module determines a category score for the member profile based on a presence of one or more phrases from the plurality of weighted phrases in the member profile.
US09418118B2	System and method for personalized snippet generation A method of producing search results is disclosed. The method comprises, at a computerized search engine system distinct from a client system: receiving a search request associated with a user from the client system, the search request having one or more search terms; obtaining a user profile corresponding to the user, where the user profile is generated based in part on the user's prior computing activities, comprising one or more of browsing, searching, and messaging; obtaining search results for the search request; generating a personalized snippet for at least one of the search results in accordance with the obtained user profile, the snippet comprising a text portion of the search result chosen based on at least one or more search terms and one or more terms of the obtained user profile; and transmitting the search results and personalized snippet to the client system for display.
US09418117B1	Displaying relevant messages of a conversation graph A method, system, and non-transitory computer readable medium for displaying relevant messages of a conversation graph. A reverse chronological stream of messages broadcasted to a recipient account of a messaging platform is received. The set of authoring accounts having a predefined graph relationship with the recipient account. Among the stream of messages, a message determined to be a part of a relevant conversation is identified. Additional content associated with the conversation is then inserted into the stream. A client displaying the stream displays the conversation related content with one or more display elements depicting relationships among messages of the conversation.
US09418111B1	Recursive aggregates Methods, systems, and apparatus, including computer programs encoded on computer storage media, for expressing and evaluating aggregation functions, including aggregation functions in the context of recursive aggregates, in data languages that implement fixed point semantics. One of the methods includes receiving input specifying, explicitly or implicitly, an aggregation function agg having an input type and an output type, a relation s that has a domain and a range and that represents one or more entities to be aggregated over, and a relation t that is a relation from the range of s to the input type of the aggregation function agg; and evaluating an aggregation construct agg* to calculate a relation between the domain of s and the output type of the aggregation function agg according to agg*(s,t)={(m,agg(n))\|∃d:(m,d)εs,nεΠ{\|t(y)\|yεs(m)\|}}.
US09418107B2	Method and apparatus for performing query aware partitioning A method and system for providing query aware partitioning are disclosed. For example, the method receives a query plan comprising a plurality of queries, and classifies each one of the plurality of queries. The method computes an optimal partition set for each one of the plurality of queries, and reconciles the optimal partition set of each one of the plurality of queries with at least one subset of queries of the plurality of queries. The method selects at least one reconciled optimal partition set to be used by each query of the plurality of queries, and stores the selected at least one reconciled optimal partition set in a computer readable medium.
US09418105B2	Email conversation management system Methods and systems for searching conversations are provided. At a computer system having one or more processors and memory storing programs executed by the one or more processors a search query is receive from a client. A conversation relevant to the search query is identified. The conversation has two or more messages. There is returned to the client for display a portion of a body of a message in the two or more messages responsive to the search query.
US09418103B2	Techniques for reformulating search queries A method includes receiving a search query and identifying an entity record in an entity data store using the search query. The entity data store includes a plurality of entity records. Each of the entity records includes an entity name, an entity type, and entity information. The entity type indicates a category in which the entity name and the entity information belongs. The method further includes generating a reformulated query by inserting one or more terms from the identified entity record into the search query. Additionally, the method includes performing a search for software applications using the reformulated query and generating a list of software applications identified during the search.
US09418101B2	Query optimization Provided are techniques for generating a relational query. Information is collected from a query specification and a model for an On-Line Analytical Processing (OLAP) query having at least a first expression and a second expression. The collected information is used to generate a relational query to retrieve report data to be used to satisfy the first expression and the second expression.
US09418100B1	System and method for storage management A method, computer program product, and computing system for defining a transactional log file for a data storage system including a data array. A first plurality of IO requests for the data storage system is processed. The transactional log file is updated to include information concerning the first plurality of IO requests. An IO pointer is defined to locate a specific IO request of the first plurality of IO requests within the transactional log file. File system metadata is defined on the data array for the data storage system.
US09418095B2	Managing changes to collections of data Managing changes to a collection of records includes storing a first set of records in a data storage system, the first set of records representing a first version of the collection of records, and validating a proposed change to the collection of records specified by an input received over a user interface. The data storage system is queried based on validation criteria associated with the proposed change, and a first result is received in response to the querying. A second set of records is processed representing changes not yet applied to the collection of records to generate a second result. The first result is updated based on the second result to generate a third result. The third result is processed to determine whether the proposed change is valid according to the validation criteria.
US09418091B2	Database operations on a columnar table database A computer system includes at least one processor and at least one memory operably coupled to the at least one processor. The memory includes a memory pool and a database partitioned into multiple fragments. Each of the fragments is allocated a block of memory from the memory pool and the fragments store compressed data in a columnar table format. A database operation is applied in a compressed format to the compressed data in at least one of the fragments.
US09418088B1	Identification of storage system elements causing performance degradation The invention relates to a digital storage system, wherein the digital storage system includes one or more digital storage system elements. The digital storage system elements comprise a plurality of digital storage devices, and one or more network components to connect the digital storage elements. Execution of the machine executable instructions causes a processor to repeatedly record performance metric data descriptive of the performance of the storage system elements in the database, locate outliers in the performance metric data using a statistical algorithm, and to calculate a problem contribution probability value for at least a portion of the outliers. The problem contribution probability value is weighted using an instantiated configuration dependency tree and an instantiated performance metric dependency tree. The processor uses the problem contribution probability value to determine a sequential list of outliers. The order in the sequential list is determined using the problem contribution probability value.
US09418086B2	Database access Database access is described, for example, where data in a database is accessed by an inference engine. In various examples, the inference engine executes inference algorithms to access data from the database and carry out inference using the data. In examples the inference algorithms are compiled from a schema of the database which is annotated with expressions of probability distributions over data in the database. In various examples the schema of the database is modified by adding one or more latent columns or latent tables to the schema for storing data to be inferred by the inference engine. In examples the expressions are compositional so, for example, an expression annotating a column of a database table may be used as part of an expression annotating another column of the database.
US09418082B2	Overloading R language constructs with database engine constructs A method, system, and computer program product for interfacing an R language client with a separate database engine environment. The method commences by interpreting an R language code fragment to identify and select R language constructs and transforming the R language constructs into queries or other database language constructs to execute within the database engine environment. The method further implements techniques for transmitting marshalled results (resulting from the execution of the database language constructs) back to the R client environment. In some situations, the marshalled results include an XML schema or DTD or another metadata description of the structure of the results. User conveniences in the form of transparent database query construction, and transparent exploitation of parallelism is achieved by determining the computation resource requirements of executable language constructs, and mapping the execution to one (or more) of, a local R client, a database engine, or a remote execution engine.
US09418079B2	Image comparison process A computer-implemented method and computing system for comparing, on a computing device, data concerning a first image within a social network to data concerning a plurality of images within the social network. A subset of similar images is identified, chosen from the plurality of images, based, at least in part, upon the comparison. At least a portion of the subset is presented to a computing device associated with a user.
US09418077B2	System and method for geo-location data type searching in an on demand environment Methods and systems are provided for retrieving, from a database containing a list of records, a subset of the list of records located within a user defined distance from a target point, each record in the list of records having a compound geo-location data type including a first data field and a second data field. The method involves generating a circle around the target point; identifying records having a geo-location within the circle; including the identified records in a result set; and presenting the result set to a user on a display screen. The method further includes treating the first data field and the second data field as a single data element.
US09418076B2	System and method for determining interests from location data A system and method are provided, for example, for determining interests from location data, by receiving location data from a mobile device, using the location data to determine a uniform resource locator associated with a point of interest, determining classification data associated with the uniform resource locator, and updating an interest graph associated with the mobile device using the classification data. The updated interest graph may also be subsequently used and the classification data may be used to provide information to the mobile device in real-time, such as recommendations or suggestions.
US09418074B2	System and method for updating a search results page in response to a user map interaction The present invention is directed towards systems and methods for updating a search results page in response to user interaction with a map resource. The method of the present invention comprises receiving a first search results page in response to a search query comprising at least a first map resource. The method monitors a change in position of a map resource in response to a user interaction and calculates a location corresponding to a map position. The method then re-executes at least one search query based upon said calculated location and displays a second search results page comprising a plurality of updated search results.
US09418073B2	System and method for converting format of jobs associated with a job stream System(s) and method(s) converting format of jobs associated with a software job stream are disclosed. A file containing syntax in an original format is received. The syntax defines the jobs and schedules in the original format. At least one keyword associated with the jobs and schedules and definition format of the jobs is identified. At least one mandatory parameter or optional parameter is checked while applying logic rules. The logic rules define mapping conditions with respect to each attribute associated with the mandatory and optional parameters. The keywords and the definition format associated with the job and schedule are mapped to a set of pre-defined keywords and definition format to obtain a set of mapped keywords and mapped definition format. The mapped keywords and mapped definition format are used to convert original syntax into a desired syntax thereby converting original format of the jobs and schedules into the desired format.
US09418072B2	Cross-file differential content synchronization Methods, systems and techniques for synchronizing content, such as a file, between one or more clients and one or more servers are provided. Example embodiments provide a Cross-File Differential Content Synchronization System (CDCSS) to synchronize files between remote systems in a nearly instantaneous manner without necessitating the transfer of the entire contents of a file. These components cooperate to transfer only the differences in data content wherever possible to a recipient system by providing a patch mechanism that instructs the recipient to build the modified or new data content based upon content it already has access to. In addition, in one embodiment the CDCSS synchronization solution provides a client-based index, rather than a server-based index, for tracking patches and files, which reduces the amount of computational and I/O overhead on the server and which does not require a negotiation between a client and a server to provide an update.
US09418068B2	Dimensional conversion in presentations Technologies are described herein for converting presentations between differing slide dimensions and aspect ratios. A scaling factor is calculated from the difference between the original dimensions of the slide and the new dimensions of the converted slide. Next, the content objects on the slide are scaled based on the scaling factor such that the aspect ratio of the content object is maintained. Finally, the content objects are repositioned on the slide in order to maintain a relative distance between the position of the content object and the center of the slide.
US09418064B1	Resource queues A method, article of manufacture, and apparatus for processing queries, comprising receiving a query, determining a query classification for the query, assigning the query to a resource queue based on the determined query classification, and placing the query in the assigned resource queue. In some embodiments, the resource queue is divided into a plurality of slots, and the query is placed in a slot. The resource queue may be associated with a resource queue memory allocation, and each of the plurality of slots is associated with a slot memory allocation.
US09418063B2	Determining delay for language translation in video communication Disclosed are various embodiments for translation of speech in a video messaging application. A segment of streaming video is decoded to separate the visual component from the audio component. The audio component is then converted to text, which may then be translated and converted to a translation output comprising a new language. In response, the translation output may be encoded with the previously separated visual component. A delay is imposed on the visual component to account for any delays that may arise in translation. The translated video may then be streamed to participants giving the appearance of real-time video conferencing.
US09418057B2	Fraud detection using text analysis In one embodiment, a method executed by at least one processor includes receiving text from submitted by a user. The method also includes determining a text score for the received text by comparing a first set of phrases included in the received text to a second set of phrases. The second set of phrases includes phrases from stored text. The stored text includes stored text known to be genuine and stored text known to be fraudulent. The method also includes determining that the received text is fraudulent based on the text score.
US09418054B2	Document comment management Apparatus, systems, and methods may operate to detect a position of an insertion point in an electronic document being presented in a graphical user interface and dynamically positioning a graphical user interface control to correspond to the position of the insertion point. Additional apparatus, systems, and methods are disclosed.
US09418049B2	Method and system for establishing parametric model A method for establishing a parametric model of a semiconductor process is provided. A first intermediate result is generated according to layout data and a non-parametric model of the semiconductor process. A first response is obtained according to the first intermediate result. A specific mathematical function is selected from a plurality of mathematical functions, and the parametric model is obtained according to the specific mathematical function. A second intermediate result is generated according to the layout data and the parametric model. A second response is obtained according to the second intermediate result. It is determined whether the parametric model is an optimal model according to the first and second responses.
US09418042B2	Memory interface and method of interfacing between functional entities A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.
US09418040B2	Dynamically deployable self configuring distributed network management system Systems, software, and methods for managing networks of connected electronic devices are described. In one example, network management policy and network management applications are transferred automatically upon detection and identification of a new device, protocol or application on the network. In another example, information related to at least one aspect of the network is obtained by an NMAS, and at least one applicable management policy is identified by the NMAS; and the identified policy is used to manage at least one aspect of the network's operation.
US09418038B2	Method and system for accessing data A method and a system for accessing data are provided. A management module is used for receiving multiple transmission data and multiple identification codes from application programs respectively and storing the transmission data to a queue according to a receiving order. One of the transmission data from the queue is obtained by the management module according to a delivering order, and the obtained transmission data is transferred to a corresponding device through an inter-integrated circuit (I2C) driving module. The management module is used for receiving response data from the device through the I2C driving module and then transferring the received response data to the corresponding application program.
US09418037B2	SPI interface and method for serial communication via an SPI interface having an SPI protocol handler for evaluating signal transitions of SPI signals In accordance with an aspect of the invention, there is provided an SPI interface including a plurality of synchronizers configured to receive a plurality of SPI signals and an internal clock signal and synchronize the received SPI signals using the internal clock signal. The SPI interface also includes an SPI protocol handler configured to receive the synchronized SPI signals and the internal clock signal, and detect and evaluate signal transitions of at least one of the synchronized SPI signals according to an SPI protocol.
US09418034B2	Ascertaining configuration of a virtual adapter in a computing environment A control component of a computing environment activates a virtual adapter hosted on a physical adapter of a host system of the computing environment. The virtual adapter is for use by a guest of the host system in performing data input and output. The activating activates the virtual adapter absent involvement of the guest. Based on activating the virtual adapter, the control component obtains configuration information of the activated virtual adapter from the physical adapter, the configuration information generated based on the activating. The control component ascertains a configuration of the activated virtual adapter based on the obtained configuration information.
US09418032B2	Adaptive accessory detection and mode negotiation Methods and apparatus for providing device detection and operational mode negotiation entirely over extant high-speed data bus pins or terminals. In one exemplary embodiment, methods and apparatus are disclosed enabling detection, negotiation and serial/video data transfer over USB 2.0 data interface pins in order to consolidate pin count on the interface and associated connector. Existing USB detection mechanisms are also leveraged to the maximum extent so as to eliminate the need for additional detection protocols. This approach allows for smaller connector and parent device form factor, while still maintaining all of the functional capabilities required for that interface. The breadth of USB-capable devices supported by such an interface is also markedly improved over prior art techniques.
US09418031B2	Media content asset recovery methods and systems An exemplary method includes a media content asset recovery system 1) detecting a migration of a user account from being associated with a first DVR system to being associated with a second DVR system, 2) identifying, in response to the detecting, a media content asset included within a library of one or more media content assets stored by the first DVR system at a time associated with the migration, 3) selecting, in accordance with a source selection heuristic, a media content source other than the first DVR system and that is configured to distribute the media content asset, and 4) directing the second DVR system to acquire the media content asset from the selected media content source for storage by the second DVR system.
US09418025B2	Information processing device, information processing method, and control system An information processing device includes a storage device that stores information, and a controller that adjusts a consumption of read time of reading information to be read per unit data amount according to the priority of the information to be read from the storage device and a permitted read time during which read of information from the storage device is permitted. The permitted read time varies according to the processing time of another control different from the control of the read.
US09418024B2	Apparatus and method for efficient handling of critical chunks An apparatus and method for efficient handling of critical chunks. For example, one embodiment of an apparatus comprises a plurality of agents to perform a respective plurality of data processing functions, at least one of the data processing functions comprising transmitting and receiving chunks of data to and from a memory controller, respectively; a system agent to coordinate requests for transmitting and receiving the chunks of data to and from the memory controller, the system agent comprising: a memory for temporarily storing the chunks of data during transmission between the agents and the memory controller; and scheduling logic to prioritize critical chunks over non-critical chunks across multiple outstanding requests while ensuring that the non-critical chunks do not result in starvation.
US09418023B2	Method for delivering user input, and device using same Provided is a method of delivering a user input received from a Human Interface Device (HID) to a source device by a sink device. The method includes: receiving the user input from the HID; generating HID user input information including a first field that represents a type of the HID, a second field that represents an interface type of the HID, and a third field that includes the user input received from the HID; and transmitting the configured HID user input information to the source device.
US09418019B2	Cache replacement policy methods and systems An embodiment includes a system, comprising: a cache configured to store a plurality of cache lines, each cache line associated with a priority state from among N priority states; and a controller coupled to the cache and configured to: search the cache lines for a cache line with a lowest priority state of the priority states to use as a victim cache line; if the cache line with the lowest priority state is not found, reduce the priority state of at least one of the cache lines; and select a random cache line of the cache lines as the victim cache line if, after performing each of the searching of the cache lines and the reducing of the priority state of at least one cache line K times, the cache line with the lowest priority state is not found. N is an integer greater than or equal to 3; and K is an integer greater than or equal to 1 and less than or equal to N−2.
US09418018B2	Efficient fill-buffer data forwarding supporting high frequencies A Fill Buffer (FB) based data forwarding scheme that stores a combination of Virtual Address (VA), TLB (Translation Look-aside Buffer) entry# or an indication of a location of a Page Table Entry (PTE) in the TLB, and a TLB page size information in the FB and uses these values to expedite FB forwarding. Load (Ld) operations send their non-translated VA for an early comparison against the VA entries in the FB, and are then further qualified with the TLB entry# to determine a “hit.” This hit determination is fast and enables FB forwarding at higher frequencies without waiting for a comparison of Physical Addresses (PA) to conclude in the FB. A safety mechanism may detect a false hit in the FB and generate a late load cancel indication to cancel the earlier-started FB forwarding by ignoring the data obtained as a result of the Ld execution. The Ld is then re-executed later and tries to complete successfully with the correct data.
US09418016B2	Method and apparatus for optimizing the usage of cache memories A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.
US09418008B2	Electronic device with variable resistive patterns An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. Each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns is disposed outside a region in which a corresponding first line and a corresponding second line overlap with each other.
US09418003B2	System, method and computer program product for conditionally performing garbage collection In accordance with embodiments, there are provided mechanisms and methods for conditionally performing garbage collection. These mechanisms and methods for conditionally performing garbage collection include identifying a predetermined portion of memory within a system, comparing one or more aspects of the predetermined portion of memory to a threshold, and conditionally performing garbage collection on the predetermined portion of memory, based on the comparison.
US09417998B2	Apparatus and method to provide cache move with non-volatile mass memory system A method includes, in one non-limiting embodiment, receiving a command originating from an initiator at a controller associated with a non-volatile mass memory coupled with a host device, the command being a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory; moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory; and acknowledging to the initiator that the command to write the data to the non-volatile mass memory has been executed. An apparatus configured to perform the method is also described.
US09417997B1	Automated policy based scheduling and placement of storage resources A computer-executable method, system, and computer program product comprising providing a policy based scheduling model comprising modeled instances of objects representing resources, wherein the resources are provisioned within a heterogeneous storage environment, wherein the modeled instances of objects includes a transport zone for mapping a data storage resource within the heterogeneous storage environment to a data storage host, wherein each of the modeled instances of objects includes one or more ports to create I/O paths between the data storage resource and the data storage host, and using the policy based scheduling model to manage the provisioning of the data storage resource in the heterogeneous storage environment.
US09417996B2	Shared physical memory protocol A computer implemented method for receiving data to a targeted logical partition. A computer locates buffer element in reliance on a connection status bit array. The computer copies control information to the targeted logical partition's local storage. The computer updates a targeted logical partition's local producer cursor based on the control information. The computer copies data to an application receive buffer. The computer determines that an application completes a receive operation. Responsive to a determination that the application completed the receive operation, the computer a targeted logical partition's local consumer cursor to match the targeted logical partition's producer cursor.
US09417994B2	Software test automation system and method The present disclosure provides methods, systems, and apparatuses for testing software. The method may comprise associating a plurality of controls on a software application screen with testing actions to be performed on the controls, thereby creating a plurality of test steps, and then generating a test component comprised of the plurality of test steps. The method may then comprise comparing the generated test component to a second test component that is associated with a previous version of the software application screen, and displaying, on a user interface, a graphical representation of one or more differences between the generated test component and the second test component.
US09417993B2	Real time analysis of tracer summaries to change tracer behavior Real time analysis of tracing data may identify functions for which tracing may be enhanced or reduced. A tracer that generates function-level data may have an aggregator that summarizes the data. Potential changes to tracing configuration may be identified by analyzing the summarized data to determine whether or not each function is being traced at a level commensurate with that function's impact to the summarized data. Those functions with little significant contribution may have their tracing reduced, while those functions with more significant contribution may have their tracing enhanced. The analysis of the summarized data may be performed in real time in some instances, causing a tracer to change the data collected while an application executes.
US09417992B2	Web portal API test report generation A system for generating application programming interface (“API”) test reports for a software application derives one or more Java APIs to be tested from the software application and derives Java Unit (“JUnit”) test methods used to test the Java APIs. The system then maps each Java API with a corresponding JUnit test method and generates one or more test reports.
US09417990B2	Graphical model for test case viewing, editing, and reporting Various techniques for interacting with a test case via a graphical model are disclosed. For example, one method involves displaying a first icon, which represents a first testing activity within a test case; displaying a second icon, which represents a second testing activity within the test case; and displaying a connector, which couples the first icon and the second icon. An assertion (e.g., against test results obtained by performing the first testing activity) is associated with the connector.
US09417985B2	Distributed analysis and attribution of source code Methods, systems, and apparatus, including computer programs encoded on computer storage media, for distributing analysis tasks and attribution tasks. One of the methods includes receiving data representing a plurality of snapshots of a code base, wherein each snapshot comprises source code files, wherein one or more snapshots have a parent snapshot in the code base according to a revision graph of snapshots in the code base. An attribution set is generated from the plurality of snapshots, the attribution set having a target set of attributable snapshots to be attributed and a support set of all parent snapshots of all snapshots in the target set. An attribution task is distributed for the attribution set to a particular worker node of a plurality of worker nodes.
US09417984B1	Preemptively generating statistical feedback on a design file and presenting the feedback in an input context Techniques are provided for assisting programmers of electronics components and systems, as well as software components and systems, assess the effectiveness of their designs. Various embodiments provide improved processes for providing statistical feedback to programmers concerning performance features of a system or component they are designing. The techniques provide for faster generation and more effective communication of feedback to the programmer. Such techniques include automatically launching a process for generating such feedback either at periodic intervals or in response to a predefined event. Additionally, techniques are provided for providing the feedback to the programmer in a same working environment in which the programmer is editing the program file, and for displaying the feedback in a format that is more useful to the programmer.
US09417981B2	Data processing system, data processing method, and program A data processing system for storing observation data including an observation value corresponding to a point in a storage area and calculating a comparison value to be compared with a future observation value, the data processing system comprising: an observation data collection unit for specifying first observation data and second observation data which are observation data before the first point; a past similar data selection unit for selecting parts for the same duration as the first predetermined time, the observation values of which are identical to the observation values of the first observation data, from the second observation data as past similar data; a parameter data selection unit for selecting the observation values for a predetermined time from the latest time of the parts selected as the past similar data as parameter data; and a comparison value calculation unit for calculating the comparison value based on the parameter data.
US09417976B2	Preventing migration of a virtual machine from affecting disaster recovery of replica A storage migration engine and a recovery manager are provided that enable failover operations to be performed in situations where storage migration and array-based replication are involved. The storage migration engine stores information related to storage migrations directly into a source datastore and a destination datastore, which are then replicated over to a recovery site. The recovery manager uses the information stored in the recovered datastores to select which instance of virtual machine data is to be used to fail over to a virtual machine at the recovery site.
US09417973B2	Apparatus and method for fault recovery An apparatus and a method for fault recovery are provided. The fault recovery apparatus includes a log manager configured to record system resource allocation information about a thread. The fault recovery apparatus further includes a recovery manager configured to create a recovery thread that substitutes for a target thread where a fault has occurred. The fault recovery apparatus further includes a resource manager configured to map a system resource that the target thread has used to the recovery thread based on referencing to the system resource allocation information.
US09417971B2	Cascade ordering A method comprises creating a cascade of target storage volumes from a plurality of target storage volumes by inserting each most recent target storage volumes between a last added target storage volume and a source storage volume, the most recent target storage volumes each having a copy rate faster than the last added target storage volume, such that each added target storage volume has a faster copy rate than an immediately prior added target storage volume, and a most recent target storage volume added to the cascade of target storage volumes has a fastest copy rate; and receiving one or more instructions initiating a plurality of backup processes from the source storage volume to a plurality of target storage volumes.
US09417968B2	Efficiently restoring execution of a backed up virtual machine based on coordination with virtual-machine-file-relocation operations Systems and methods enable a virtual machine, including applications executing thereon, to quickly start executing and servicing users based on pre-staged data blocks supplied from a backup copy in secondary storage. Substantially concurrently with the ongoing execution of the virtual machine, a virtual-machine-file-relocation operation moves data blocks from backup to a primary storage destination that becomes the virtual machine's primary data store after relocation completes. An enhanced data agent, operating in conjunction with an enhanced media agent in a storage management system, coordinates restoring the virtual machine and launching the relocation operation. The enhanced media agent pre-stages certain backed up data blocks based on predictive analysis pertaining to the virtual machine's operational profile. The enhanced media agent also pre-stages backed up data blocks for the relocation operation, based on the operation's relocation scheme. The media agent tracks read requests and maintains the contents of an associated read cache.
US09417966B2	Post backup catalogs A method, article of manufacture, and apparatus for processing data. In some embodiments, this includes analyzing a first container at a block level, determining a first level of granularity based on the analysis of the first container, based on the first level of granularity, identifying a first set of data objects, storing metadata of the first set of data objects in a recovery catalog, based on the first set of data objects, identifying a second container, analyzing the second container at a block level, determining a second level of granularity based on the analysis of the second container, based on the second level of granularity, identifying a second set of data objects, storing metadata of the second set of data objects in the recovery catalog, wherein the recovery catalog is stored in a storage device.
US09417965B2	Low overhead fault tolerance through hybrid checkpointing and replay A virtualized computer system provides fault tolerant operation of a primary virtual machine. In one embodiment, this system includes a backup computer system that stores a snapshot of the primary virtual machine and a log file containing non-deterministic events occurring in the instruction stream of the primary virtual machine. The primary virtual machine periodically updates the snapshot and the log file. Upon a failure of the primary virtual machine, the backup computer can instantiate a failover backup virtual machine by consuming the stored snapshot and log file.
US09417964B2	Destaging cache data using a distributed freezer Methods, apparatus and computer program products implement embodiments of the present invention that enable digital information devices having respective storage devices and memories to distributedly store, for a logical volume, data and first and second parity values across corresponding regions of the storage devices. Freezers having a one-to-one correspondence with the storage devices are distributedly stored in the memories. Upon detecting, in a cache, updated data for one or more first regions on the storage devices, existing data from the one or more first regions, and additional data for parity calculations are retrieved from one or more corresponding second regions on the storage devices, and first and the second parity values are calculated using the updated data, the existing data and the additional data, and the updated data and the calculated first and second parity values are stored to the freezers.
US09417961B2	Resource allocation and deallocation for power management in devices In general, techniques are described for resource allocation and deallocation that facilitates power management. A device comprising one or more processors and a memory may be configured to perform the techniques. The processor may be configured to determine usage of a first non-zero subset of a plurality of resources, the plurality of resources allocated and released in accordance with a thermometer data structure. The processors may further be configured to compare the usage of the first non-zero subset of the plurality of resources to a threshold separating the first non-zero subset of the plurality of resources from a second non-zero subset of the plurality of resources, and power on the second non-zero subset of the plurality of resources based at least on the comparison. The memory may be configured to store the threshold.
US09417959B2	Flash device and operating method thereof A flash device is provided. A flash memory includes a plurality of pages. A controller coupled to the flash memory includes an operating unit, an error correction code (ECC) decoder and a processing unit. The operating unit receives a plurality of bytes of the page which are from the flash memory and corresponding to a read command, and obtains an operating result according to a logic level of each bit of each of the bytes. The ECC decoder decodes the bytes of the page according to an ECC code. The processing unit determines whether the page is valid data according to the decoded bytes, and determines whether the page is an empty page according to the operating result when the page is not the valid data.
US09417955B2	Data reconstruction in distributed data storage system with key-based addressing In a Distributed Virtual Array data storage system, data chunks making up data containers are stored in a key order in storage devices according to layouts specified in a layout data structure. When any of the storage devices becomes inaccessible, the storage devices iteratively return, in storage order, their stored chunks. Chunks belonging to the same container are identified and, if that container had a chunk in the inaccessible storage device, are used to reconstruct the inaccessible chunk. The chunks of the container are then stored according to an updated layout. The keys are independent of physical storage locations.
US09417951B2	Method and apparatus for cipher fault detection What is disclosed is an embodiment of a method for ciphering data. Data is provided for ciphering thereof. The data is ciphered in a plurality of steps. For each step, an encoding for error detection of the data for being processed within the step is determined. An output error detection encoding for the step is determined. The data for being processed within the round is processed to provide output error detection encoding which is then verified against the determined output error detection encoding. When the output error detection encoding is other than same as the determined error detection encoding, providing a signal indicative of an error within the cipher process.
US09417947B1	System and method for robust storage of error event information A system and method for robust storage of error event information is provided. Binary image information is stored in a compressed data structure in a read only portion of memory. In the event of an error condition, state information is written to a file in a series of carriage return delineated lines.
US09417942B1	Event-based in-band host registration A method of registering a host bus port (HBP) of a host computer (host) at a storage bus port (SBP) of a data storage array over a storage network includes (a) acquiring a configuration instruction directing the host to process registration messages from an event processing engine, (b) receiving a registration message from the event processing engine indicating that the HBP needs to be registered with the SBP, the registration message having been generated by the event processing engine in response to receiving an event notification message indicating that a data path across the storage network between the HBP and the SBP is available, and (c) in response to receiving the registration message, processing the registration message by registering the HBP with the SBP by sending a registration command from the HBP to the SBP across the storage network, the registration command including registration information associated with the HBP.
US09417941B2	Processing device and method of executing an instruction sequence A processing device and a method of executing an instruction sequence are described. The processing device comprises a status register for providing a status word, wherein execution of an instruction by the processing device comprises updating the status word, wherein the instruction sequence comprises a subsequence of one or more selected instructions, and wherein execution of a selected instruction by the processing device further comprises a status check which comprises: providing a set of valid status words; verifying whether the updated status word is in the set of valid status words; and initiating an alert action if the updated status word is not in the set of valid status words.
US09417939B2	Dynamic escalation of service conditions Systems, methods, and software are provided for dynamically escalating service conditions associated with data center failures. In one implementation, a monitoring system detects a service condition. The service condition may be indicative of a failure of at least one service element within a data center monitored by the monitoring system. The monitoring system determines whether or not the service condition qualifies for escalation based at least in part on an access condition associated with the data center. The access condition may be identified by at least another monitoring system that is located in a geographic region distinct from that of the first monitoring system. Upon determining that the service condition qualifies for escalation, the monitoring system escalates the service condition to an escalated condition and initiates an escalated response.
US09417938B2	Remote procedure call chains A remote procedure call chain is provided that replaces multiple consecutive remote procedure calls to multiple servers from a client by allowing a client to specify multiple functions to be performed consecutively at multiple servers in a single remote procedure call chain. The remote procedure call chain is executed by a sequence of multiple servers. Each server executes a service function and a chaining function of the remote procedure call chain. The chaining function uses the state of the remote procedure call chain in the sequence of servers to determine the next server to receive the remote procedure call chain, and the service function to be executed by that server. After the last service function is performed, the last server in the sequence of servers sends the results of the executed service functions to the client that originated the remote procedure call chain.
US09417929B2	Runtime profile determinations of virtual machines for graphics processing unit (GPU) allocation Methods, techniques, and systems for dynamically allocating graphics processing units among virtual machines are provided. Example embodiments provide a dynamic GPU allocation system (“DGAS”), which enables the efficient allocation of physical GPU resources to one or more virtual machines. In one embodiment, the DGAS determines runtime profiles of a plurality of virtual machines. The runtime profiles are determined by determining a runtime assessment of workload indicative of a potential benefit that the virtual machine can receive from using a GPU resource. The DGAS then causes the processing bandwidth of the physical GPU resources to be allocated to some of the plurality of virtual machines based upon the dynamically determined runtime assessments of workload.
US09417925B2	Dynamic functionality partitioning A sensor and processing system dynamically partitions functionality between various remote sensor nodes and a processing subsystem based on available communication capabilities. Redundant functionality is located at the processing subsystem and each of the various remote sensor nodes, and each sensor node coordinates with the processing subsystem to determine the location (e.g., at the processing subsystem or at the sensor node) at which a particular functionality is executed.
US09417921B2	Method and system for a graph based video streaming platform A method implemented in an electronic device serving as an orchestrator managing video and audio stream processing of a streaming platform system is disclosed. The method includes the electronic device receiving a request to process a video source and creating a task graph based on the request, where the task graph is a directed acyclic graph of tasks for processing the video source, where each node of the task graph represents a processing task, and where each edge of the task graph represents a data flow across two processing tasks and corresponding input and output of each processing task. The method also includes the electronic device estimating resource requirements of each processing tasks, and splitting the task graph into a plurality of subsets, wherein each subset corresponds to a task group to be executed by one or more workers of a plurality of processing units of the streaming platform system.
US09417919B2	Computer cluster with objective-based resource sharing A computer cluster with objectives-based resource sharing. The cluster includes cloud nodes each with one or more resources, a terminal, data storage, and an allocation node to monitor cloud node resources, provide information descriptive of the cloud node resources to a customer through the terminal, receive a reservation for cloud node resources from the customer, store the reservation in the data storage, determine assignments of the cloud node resources for the reservation and any other pending reservations according to one or more objectives, and allocate the cloud node resources to customers according to the resource assignments.
US09417915B2	Methods for rule-based dynamic resource adjustment for upstream and downstream processing units in response to an intermediate processing unit event A method dynamically adjusts the resources available to a processing unit of a distributed computer process executing on a multi-node computer system. The resources for the processing unit are adjusted based on the data other processing units handle or the execution path of code in an upstream or downstream processing unit in the distributed process or application.
US09417910B2	System and method for implementing shared probabilistic counters storing update probability values The systems and methods described herein may implement probabilistic counters and/or update mechanisms for those counters such that they are dependent on the value of a configurable accuracy parameter. The accuracy parameter value may be adjusted to provide fine-grained control over the tradeoff between the accuracy of the counters and the performance of applications that access them. The counters may be implemented as data structures that include a mantissa portion and an exponent portion that collectively represent an update probability value. When updating the counters, the value of the configurable accuracy parameter may affect whether, when, how often, or by what amount the mantissa portion and/or the exponent portion are updated. Updating a probabilistic counter may include multiplying its value by a constant that is dependent on the value of a configurable accuracy parameter. The counters may be accessible within transactions. The counters may have deterministic update policies.
US09417906B2	Transaction participant registration with caveats In a distributed computing system, a processing device executing a caveat enabled transaction manager registers one or more transaction participants with the transaction manager. To register a transaction participant, the caveat enabled transaction manager records an address of the transaction participant. The caveat enabled transaction manager additionally determines whether the transaction participant is associated with any transaction caveats. If the transaction participant is associated with a transaction caveat, the caveat enabled transaction manager records the transaction caveat.
US09417905B2	Terminating an accelerator application program in a hybrid computing environment Terminating an accelerator application program in a hybrid computing environment that includes a host computer having a host computer architecture and an accelerator having an accelerator architecture, where the host computer and the accelerator are adapted to one another for data communications by a system level message passing module (‘SLMPM’), and terminating an accelerator application program in a hybrid computing environment includes receiving, by the SLMPM from a host application executing on the host computer, a request to terminate an accelerator application program executing on the accelerator; terminating, by the SLMPM, execution of the accelerator application program; returning, by the SLMPM to the host application, a signal indicating that execution of the accelerator application program was terminated; and performing, by the SLMPM, a cleanup of the execution environment associated with the terminated accelerator application program.
US09417904B2	Cyber-physical system and method of monitoring virtual machine thereof A cyber-physical system and a method of monitoring a virtual machine thereof are provided. The cyber-physical system includes a plurality of target controllers that includes middleware operating based on different operating systems and that control different targets, and a system monitor that includes integrated middleware of analyzing and synthesizing information collected from the middleware. First virtual machines corresponding to virtualization of the target controllers and a second virtual machine corresponding to virtualization of the system monitor are independently formed through a virtual machine monitor.
US09417899B2	Memory page de-duplication in a computer system that includes a plurality of virtual machines Memory page de-duplication in a computer system that includes a plurality of virtual machine partitions managed by a hypervisor, where each virtual machine is assigned a different dedicated memory partition, may include: identifying, by the hypervisor, a plurality of identical memory pages in memory of one or more dedicated memory partitions; assigning, by the hypervisor, one of the identical memory pages as a master page; mapping, for each virtual machine having an identical memory page, each of the identical memory pages to the master page; and directing, by the hypervisor, reads of the memory page to the master page.
US09417889B2	Fast provisioning of a centralized virtual desktop using linked clones with overlaid centralized virtual desktop layers Methods and systems for n-way cloning and synchronization of a user desktop image are provided. Example embodiments provide a Cloning and Synchronization System (“CSS”) which binds a server stored CVD object representing the user's desktop image to one or more endpoint devices. Each endpoint device receives a clone of the CVD object that comprises one or more layers of the server CVD depending upon the suitability of the endpoint device hardware and operating system to the server stored desktop. The cloned CVDs in the endpoint devices are then kept synchronized by synchronization operations. In one embodiment, the CSS allows only one endpoint device to act as a master device and push up changes to the server CVD. These changes are then pushed down to the other devices using different synchronization methods dependent upon the layer.
US09417883B2	Video decoding system supporting multiple standards System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
US09417882B2	Load synchronization with streaming thread cohorts There is provided a processor implemented method for controlling a lock-stepped cohort. The method includes receiving instructions for each of a first lane and a second lane. The first lane is for the lock-stepped cohort and the second lane is for another cohort. The method further includes detecting a condition in which a first instruction at the first lane will have a higher latency than a second instruction at the second lane. The method also includes setting an indicator indicating where the first lane encountered the first instruction. The method additionally includes setting the first lane to inactive, while keeping the second lane active. The method further includes setting the first lane to active on a subsequent opportunity to execute said first instruction.
US09417876B2	Thread context restoration in a multithreading computer system Embodiments relate to thread context restoration. One aspect is a multithreading computer system including a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.
US09417873B2	Apparatus and method for a hybrid latency-throughput processor An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.
US09417871B2	Automatic generation of certificate of origin (COO) for software systems A system includes at least one computing device. The computing device has one or more processors, a memory, and a storage storing computer executable code. The computer executable code, when executed at the processors, is configured to process a plurality of source modules to generate a plurality of binary modules corresponding to the source modules. Each source module has at least one source file and a control file including a certificate of origin (COO) of the source module, and each binary module generated from each source module has at least one corresponding binary file and a copy of the control file. Once the binary modules are generated, the computer executable code combines the binary files of each of the binary modules to generate an executable file, and generates a COO file for the executable file based on the control files from the source modules or the binary modules.
US09417868B2	Entity wide software tracking and maintenance reporting tool Embodiments of the invention are directed to a system, method, or computer program product for providing an entity wide software tracking and maintenance tool for monitoring maintenance and software updates across an entity. As such, the invention provides a uniform and stable method of monitoring software updates and software instillation across an entity's information technology infrastructure. The invention receives software updates or new programs for installation across the entity. The invention then creates a tracking module to link to the maintenance update. The tracking module is a self-contained, self-describing module that contains static information related to the maintenance. Subsequently, the tracking module allows users to monitor the progress of maintenance levels. In some embodiments, the user may query the system to determine the progress of a specific maintenance. In some embodiments, the system may automatically notify a user of the success or failure of maintenance at one or more stages.
US09417867B2	Smart source code evaluation and suggestion system A method for s identifying program files within one or more programs that will likely require update to implement a proposed programming task is disclosed. A processor identifies a previous programming task that matches the proposed programming task. The processor also identifies a set of program files that were updated to implement the previous programming task. The processor then displays the set of program files or existing versions of the set of program files as program files that will likely require update for the proposed programming task.
US09417863B2	System and method for expedited loading of an image onto a storage device Embodiments of an image loading system are disclosed for installing testing software on a storage device. In one embodiment, the system includes a network storage that stores testing software for storage devices, a software loader operating on a storage device, and a testing manager. In an embodiment, the testing manager is configured to broadcast at least one packet containing a specific code on a network, wherein receipt of the specific code causes the software loader to request a location of the testing software and transmit a location of the network storage to the software loader, thereby causing the software loader to obtain the testing software from the network storage and load the testing software on the storage device.
US09417862B2	Information processing apparatus, function extension method for information processing apparatus, and non-transitory computer-readable storage medium An information processing apparatus provided with an extension unit for performing control to download and install an extension program for extending functionality, the extension unit comprises: a first control unit that performs control to download from an external server an introduction program that provides information about the extension program which can be downloaded, and installs the introduction program; an obtaining unit that obtains, from the installed introduction program, information about the extension program; a provision unit that provides a screen for displaying the obtained information about the extension program and for receiving an instruction to install the extension program; and a second control unit that, in response to the instruction by a user via the screen, performs control to use key information included in the obtained information to download and install the extension program.
US09417856B2	Efficient interpreter profiling to obtain accurate call-path information A method for obtaining accurate call path information in a mixed-mode environment where interpreted methods and non-interpreted methods can call one another is disclosed. In one embodiment, such a method includes generating an event and recording it in a buffer when an interpreted method calls an interpreted method. The method also generates an event and records it in the buffer when an interpreted method calls a non-interpreted method. The method further generates an event and records it in the buffer when a non-interpreted method calls an interpreted method. The method refrains from generating an event when a non-interpreted method calls a non-interpreted method. A corresponding apparatus and computer program product are also disclosed.
US09417855B2	Instruction and logic to perform dynamic binary translation A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.
US09417854B1	Functional use-case generation Functional use-case generation may include determining whether a requirements context is available. In response to a determination that the requirements context is available, the requirements context may be determined as a task context and as a rule context for a requirements sentence of a requirements document. The task context and the rule context may be used to select a functional model from a plurality of functional models. A functional use-case that includes an entity that is to perform a task based on a rule may be generated. Further, in response to a determination that the requirements context is not available, a functional model may be selected from the plurality of functional models based on process context, where the functional model includes a process related to the process context, and the functional model that includes the process related to the process context may be used to generate the functional use-case.
US09417849B2	Communications network, computer architecture, computer-implemented method and computer program product for development and management of femtocell-based applications In one aspect, the present application is directed to a communications network, a computer architecture, a computer-implemented method, and a computer program product for development and management of femtocell-based applications. In one aspect, the communications network may comprise at least one femtocell; a mobile operator network; and a computer architecture integrated in the mobile operator network, wherein the computer architecture is operable to support development and lifecycle management of at least one femtocell-based application for the at least one femtocell.
US09417846B1	Techniques for improving random number generation security A technique for improving random number generation (RNG) security for a data processing system includes a storage subsystem of a processing unit receiving a first deliver a random number (DARN) operation. The storage subsystem issues the first DARN operation with a first value, retrieved from a first base address register (BAR), on a first bus. The processing unit receives (from a first RNG unit) at least one of a first data and a first indication (that indicate whether the first RNG unit is functional) when a second value stored in a second BAR of the first RNG unit is the same as the first value. In response to the first and second values not being the same or the first RNG unit not being functional, the storage subsystem issues the first DARN operation with the first value on a second bus that is coupled to a second RNG unit.

1 2 3 4 5 6 7 8 9 10