最新美国发明专利第2016-08-09期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

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US09412983B2	Battery pack A battery pack includes a battery module including a plurality of battery cells that are electrically connected, a first case accommodating the battery module, and a second case opposite to the first case so as to be coupled to the first case. The first or second case includes an extending portion, the extending portion being provided to extend in a first direction, the first direction being a direction in which the first and second cases are coupled to each other, so as to shield a portion at which the first and second cases are coupled to each other.
US09412980B2	Battery cell assembly A battery cell assembly having first and second rectangular-shaped end plates, a battery cell, and a metal spring clip are provided. The first rectangular-shaped end plate includes first and second grooves, and the second rectangular-shaped end plate includes first and second grooves. The battery cell is disposed between the first and second rectangular-shaped end plates. The metal spring clip has first and second end portions. The first end portion is disposed in the first groove of the first rectangular-shaped end plate, and the second end portion is disposed in the first groove of the second substantially rectangular-shaped end plate to bias the first rectangular-shaped end plate toward the second rectangular-shaped end plate.
US09412976B2	Organic light emitting diode device and method for manufacturing the same, display device and electronic product The OLED device according to this disclosure at least includes a first electrode, a second electrode and an organic functional layer disposed between the first electrode and the second electrode. The organic functional layer at least includes a first part functional layer formed through a first process, a second part functional layer formed through a second process, and a hybrid connecting layer disposed between the first part functional layer and the second part functional layer. The hybrid connecting layer is formed by using at least a first host material and a second host material. The first host material has a hole mobility greater than its electron mobility, and the second host material has an electron mobility greater than its hole mobility.
US09412974B2	Display device using photonic crystal A display device including a light emitting transistor, and a photonic crystal on the light emitting transistor.
US09412964B2	Organic electroluminescent element [It is an object] to provide an organic electroluminescent element with which the initial durability of the element can be greatly improved while maintaining the efficiency of the element at a high level. This is an organic electroluminescent element having an anode, a hole injection layer, a first hole transport layer, a second hole transport layer, a light-emitting layer, and a cathode, in this order, with this organic electroluminescent element being such that the aforementioned hole injection layer includes a material for which the energy of the lowest unoccupied molecular orbital (LUMO) is less than −4.0 eV and also such that the energy E1(LUMO) of the LUMO of the material included in the aforementioned first hole transport layer and the energy E2(LUMO) of the LUMO of the material included in the aforementioned second hole transport layer satisfy [the inequality] E1(LUMO)>E2(LUMO).
US09412961B2	Method of manufacturing organic light-emitting display apparatus A vapor deposition apparatus for depositing a thin film on a substrate, by which a deposition process is efficiently performed and deposition film characteristics are easily improved, and a vapor deposition apparatus including: a stage onto which a substrate is disposed; and a supply unit disposed to face the substrate and having a main body member and a nozzle member disposed on one surface of the main body member facing the substrate, to sequentially supply a plurality of gases towards the substrate, and a method of manufacturing an organic light-emitting display apparatus using the same.
US09412960B2	Light trapping architecture for photovoltaic and photodector applications There is disclosed photovoltaic device structures which trap admitted light and recycle it through the contained photosensitive materials to maximize photoabsorption. For example, there is disclosed a photosensitive optoelectronic device comprising: a first reflective layer comprising a thermoplastic resin; a second reflective layer substantially parallel to the first reflective layer; a first transparent electrode layer on at least one of the first and second reflective layer; and a photosensitive region adjacent to the first electrode, wherein the first transparent electrode layer is substantially parallel to the first reflective layer and adjacent to the photosensitive region, and wherein the device has an exterior face transverse to the planes of the reflective layers where the exterior face has an aperture for admission of incident radiation to the interior of the device.
US09412954B2	Heterocyclic compound and organic electronic element containing same The present disclosure provides a novel compound capable of greatly improving the lifetime, efficiency, electrochemical stability and thermal stability of an organic electronic device, and an organic electronic device including an organic compound layer containing the compound.
US09412950B2	Polymer compound and organic photoelectric conversion device A polymer compound comprising a repeating unit represented by the formula (A) and a repeating unit represented by the formula (B) manifests large absorbance of light having long wavelength, and can be used in an organic photoelectric conversion device and an organic thin film transistor. [in the formula (A) and the formula (B), R represents a hydrogen atom, a fluorine atom, an optionally substituted alkyl group, an alkoxy group optionally substituted by a fluorine atom, an aryl group, a heteroaryl group, a group represented by the formula (2a) or a group represented by the formula (2b). A plurality of R may be the same or mutually different. Ar1 and Ar2 represent an optionally substituted tri-valent aromatic hydrocarbon group having 6 to 60 carbon atoms or a trivalent heterocyclic group having 4 to 60 carbon atoms.].
US09412946B2	Method for manufacturing an organic light emitting display panel and related organic light emitting display panel A method for manufacturing an organic light emitting display panel is disclosed. The organic light emitting display panel includes a substrate. The method includes forming a plurality of bank arrays, each of which has a plurality of banks, utilizing a plurality of ink-jet heads, each of which has a plurality of nozzles arranged alternately, to move relative to the substrate along a moving direction perpendicular to a border of the substrate, and utilizing at least one of the plurality of nozzles to drop organic light emitting ink for forming at least one organic light emitting pixel in at least one bank. An oblique angle is formed between an arrangement direction of the plurality of banks and the border of the substrate. Each ink-jet head forms the oblique angle cooperatively with the border of the substrate.
US09412945B1	Storage elements, structures and methods having edgeless features for programmable layer(s) A storage element can include a bottom structure having at least one edge formed by a top surface and a side surface; a programmable layer, programmable between at least two different impedance states, and formed over the at least one edge and in contact with a portion of the bottom structure; an insulating layer that extends above the top surface of the bottom structure having an opening to the bottom structure formed therein, the opening having sloped sides; and at least one top layer formed within the opening and in contact with the programmable layer. Methods of making such a storage element are also disclosed.
US09412944B2	Organic molecular memory An organic molecular memory in an embodiment includes a first electrode having a first work function; a second electrode having a second work function; and an organic molecular layer provided between the first electrode and the second electrode, the organic molecular layer containing a first organic molecule chemically bonded to the first electrode, the first organic molecule having a resistance-change type molecular chain, and the first organic molecule having a first energy level higher than the first work function, and a second organic molecule chemically bonded to the second electrode and the second organic molecule having a second energy level higher than the second work function and lower than the first energy level.
US09412942B2	Resistive memory cell with bottom electrode having a sloped side wall A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface, forming an oxidation layer on each sloped surface of the remaining bottom electrode layer, performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.
US09412940B2	Resistive switching element and use thereof A bipolar resistive switching device (RSM device, FIG. 35) comprises an electrically conductive bottom electrode (BE, FIG. 35); a stack of transition metal oxides layers (RSM, FIG. 35), a number of transition metal oxide layers (RSO, FIG. 35) being equal or greater than 2, the stack comprising: at least one MOx layer (RSOA, FIG. 35), at least one oxygen gettering layer NOy (RSOB, FIG. 35). The resistive switching device further comprises an electrically conductive top electrode (TE, FIG. 35).
US09412934B2	Microelectromechanical resonator A method for manufacturing microelectromechanical flexural resonators with a deforming element that has an elongate body extending along a spring axis. A deforming element is positioned on the semiconductor wafer with a defined nominal n-type doping concentration such that a crystal orientation angle is formed between the spring axis of the deforming element and a crystal axis of the silicon semiconductor wafer. The combination of the crystal orientation angle and the nominal n-type doping concentration is adjusted to a specific range, based on total frequency error of the deforming element in a broad temperature range. The combination is optimized to a range where also sensitivity to variations in the material properties is minimized.
US09412923B2	Lead frame for mounting LED elements, lead frame with resin, method for manufacturing semiconductor devices, and lead frame for mounting semiconductor elements A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.
US09412922B2	Wafer level light-emitting diode array A wafer level light-emitting diode (LED) array includes: a growth substrate; a plurality of LEDs arranged over the substrate, each including a first semiconductor layer, an activation layer, and a second semiconductor layer; a plurality of upper electrodes formed from a common material and electrically connected to the first semiconductor layers of the corresponding LEDs; and first and second pads arranged over the upper electrodes. The LEDs are connected in series by the upper electrodes, the first pad is electrically connected to an input LED from among the LEDs connected in series, and the second pad is electrically connected to an output LED from among the LEDs connected in series. Accordingly, a flip chip-type LED array can be provided which can be driven with a high voltage.
US09412921B2	Module structure Disclosed is a module structure including a front sheet, a back sheet, and an optoelectronic device disposed between the front sheet and the back sheet. A first packaging layer is disposed between the optoelectronic device and the front sheet. The back sheet is a layered structure of a hydrogenated styrene elastomer resin layer and a polyolefin layer, wherein the hydrogenated styrene elastomer resin layer is disposed between the optoelectronic device and the polyolefin layer.
US09412920B2	Phosphor reflecting sheet, light emitting diode device, and producing method thereof A phosphor reflecting sheet provides a phosphor layer on one side in a thickness direction of a light emitting diode element and provides a reflecting resin layer at the side of the light emitting diode element. The phosphor reflecting sheet includes the phosphor layer and the reflecting resin layer provided on one surface in the thickness direction of the phosphor layer. The reflecting resin layer is formed corresponding to the light emitting diode element so as to be disposed in opposed relation to the side surface of the light emitting diode element.
US09412908B2	Semiconductor light emitting device Disclosed are a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a pad on the plurality of compound semiconductor layers; an electrode layer under the plurality of compound semiconductor layers; and a supporting member disposed under the plurality of compound semiconductor layers and corresponding to the pad.
US09412906B2	Light-emitting device A light-emitting device comprises: a light-emitting stack comprising a first side, a second side opposite to the first side, and an upper surface between the first side and the second side; a first electrode pad formed on the upper surface; a second electrode pad formed on the upper surface, and the first electrode pad is closer to the first side than the second electrode pad; and a first extension electrode comprising a first section extended from the first electrode pad toward the second electrode pad, and a second section extended from the first electrode pad toward the first side.
US09412901B2	Superlattice structure A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.
US09412898B2	Apparatus and method of testing a substrate using a supporting nest and testing probes Embodiments of the invention may provide a testing apparatus that is used to test solar cells or other electronic devices. The testing apparatus may comprise a substantially flat support that is configured to support a substrate or other device that is to be electrically tested and a plurality of testing probes. The support comprises a plurality of through holes, each suitable for the insertion of a corresponding testing probe, to allow each probe to make contact with a testing area formed on the substrate. The testing apparatus may comprise a suction device that is associated or associable with the support, and is able to exert a holding force on the substrate that counteracts the thrusting force exerted by the testing probes.
US09412896B2	Method for manufacturing solar cells, attenuating lid phenomena To reduce degradation, by the LID effect, of the conversion efficiency of photovoltaic cells made of crystalline silicon, one or more steps of controlled introduction of voids into the silicon are carried out by one or more steps chosen from among: siliciding, nitriding, ion implantation, laser irradiation, mechanical bending stress applied on one face of the silicon substrate, in combination with a temperature promoting the formation of voids in the substrate. These voids make it possible to reduce the level of interstitial oxygen by an effect of diffusion of VO complexes and precipitation of oxygen. The introduction of voids has the other effect of reducing the level of autointerstitials, and therefore of limiting the formation of interstitial boron. The phenomena of LID by activation of BiOi2 complexes are thus limited. This applies notably to photovoltaic cells based on monocrystalline or polycrystalline silicon having a high concentration of boron and oxygen.
US09412894B2	Photovoltaic device including gap passivation layer and method of manufacturing the same A photovoltaic device includes a semiconductor substrate; an amorphous first conductive semiconductor layer on a first region of a first surface of the semiconductor substrate and containing a first impurity; an amorphous second conductive semiconductor layer on a second region of the first surface of the semiconductor substrate and containing a second impurity; and a gap passivation layer located between the first region and the second region on the semiconductor substrate, wherein the first conductive semiconductor layer is also on the gap passivation layer.
US09412893B2	Solar module and process for production thereof The present invention relates to a solar module comprising a first layer, a solar cell arranged above the first layer and a second layer arranged above the solar cell. The first and/or the second layer comprise a fiber composite material which comprises a preferably aliphatic polyurethane polymer “dual cure” system) crosslinked thermally and by means of electromagnetic radiation. The material of the fibers of the fiber composite material is transparent at least in the region of visible light. The invention further relates to the use of this type of solar module and to a process for production thereof.
US09412892B2	Vapor deposition apparatus and process for continuous indirect deposition of a thin film layer on a substrate An apparatus and related process are provided for vapor deposition of a sublimated source material as a thin film on a photovoltaic (PV) module substrate. A deposition head is configured for sublimating a source material supplied thereto. The sublimated source material condenses onto a transport conveyor disposed below the deposition head. A substrate conveyor is disposed below the transport conveyor and conveys substrates in a conveyance path through the apparatus such that an upper surface of the substrates is opposite from and spaced below a lower leg of the transport conveyor. A heat source is configured adjacent the lower leg of the transport conveyor. The source material plated onto the transport conveyor is sublimated along the lower leg and condenses onto to the upper surface of substrates conveyed by the substrate conveyor.
US09412881B2	Power device integration on a common substrate A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
US09412879B2	Integration of the silicon IMPATT diode in an analog technology A method to integrate a vertical IMPATT diode in a planar process.
US09412878B2	Semiconductor device and manufacturing method thereof A semiconductor device having improved reliability is disclosed. In a semiconductor device according to one embodiment, an element isolation region extending in an X direction has a crossing region that crosses, in plan view, a memory gate electrode extending in a Y direction that intersects with the X direction at right angles. In this case, in the crossing region, a width in the Y direction of one edge side, the one edge side being near to a source region, is larger than a width in the Y direction of the other edge side, the other edge side being near to a control gate electrode.
US09412876B2	Semiconductor device The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. Furthermore, the first transistor provided in the driver circuit portion may include the oxide semiconductor film in which a first film and a second film are stacked, and the second transistor provided in the pixel portion may include the oxide semiconductor film which differs from the first film in the atomic ratio of metal elements.
US09412874B2	Semiconductor device A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a first gate insulating layer over the gate electrode layer, a second gate insulating layer being over the first gate insulating layer and having a smaller thickness than the first gate insulating layer, an oxide semiconductor layer over the second gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The first gate insulating layer contains nitrogen and has a spin density of 1×1017 spins/cm3 or less corresponding to a signal that appears at a g-factor of 2.003 in electron spin resonance spectroscopy. The second gate insulating layer contains nitrogen and has a lower hydrogen concentration than the first gate insulating layer.
US09412872B2	N-type and P-type tunneling field effect transistors (TFETs) Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
US09412870B2	Device with engineered epitaxial region and methods of making same A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.
US09412867B2	Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
US09412866B2	BEOL selectivity stress film The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.
US09412863B2	Enhanced breakdown voltages for high voltage MOSFETS An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.
US09412862B2	Electronic device including a conductive electrode and a process of forming the same An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.
US09412859B2	Contact geometry having a gate silicon length decoupled from a transistor length Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.
US09412853B2	Protective device for a voltage-controlled semiconductor switch A protective device for a voltage-controlled semiconductor switch has a gate connection, a power emitter connection, an auxiliary emitter connection and a collector connection. The semiconductor switch can switch a current between the collector connection and the power emitter connection. A voltage-limiting device limits the voltage between the gate connection and the power emitter connection. A deactivation device is connected to the voltage-limiting device and deactivates the voltage-limiting device during a switch-on of the semiconductor switch.
US09412851B2	Method for fabricating semiconductor device including a patterned multi-layered dielectric film with an exposed edge A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.
US09412847B2	Self-aligned passivation of active regions A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).
US09412844B2	Trench power MOSFET A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
US09412840B1	Sacrificial layer for replacement metal semiconductor alloy contact formation A sacrificial layer is formed on exposed surfaces of source/drain structures that are located at the footprint of a gate stack. A stack of, from bottom to top, a middle-of-the-line (MOL) liner, a MOL dielectric material, and an optional dielectric cap material layer is then formed surrounding the gate stack. A contact opening is then formed that exposes a portion of the sacrificial layer. The entirety of the sacrificial layer is then removed and replaced with a metal semiconductor alloy. A conductive metal structure is then provided in the remaining volume of the contact opening.
US09412839B2	Methods of forming replacement gate structures on FinFET devices and the resulting devices One illustrative method disclosed herein includes, among other things, forming at least one layer of insulating material with a substantially planar upper surface that is positioned above the upper surface of the fin, forming a layer of sacrificial gate material on the layer of insulating material, the layer of sacrificial gate material having an as-deposited upper surface and a substantially uniform thickness, forming a layer of gate cap material on the as-deposited upper surface of the layer of sacrificial gate material, forming a patterned sacrificial gate structure comprised of at least the gate cap material and the sacrificial gate material, forming a sidewall spacer adjacent the patterned sacrificial gate structure, removing the patterned sacrificial gate structure and replacing it with a replacement gate structure.
US09412838B2	Ion implantation methods and structures thereof A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins. In some examples, a mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure. By way of example, a first ion implantation may be performed, at a first temperature, through the group of fins and the test structure. Additionally, a second ion implantation may be performed, at a second temperature greater than the first temperature, through the group of fins and the test structure. In various examples, an interstitial cluster is formed within the group of fins and within the test structure. In some embodiments, an anneal process is performed, where the anneal process serves to remove the interstitial cluster from the group of fins and form at least one dislocation loop within the test structure.
US09412836B2	Contacts for transistors The present disclosure relates to a semiconductor device having a delta doped sheet layer within a transistor's source/drain region to reduce contact resistance, and an associated method. In some embodiments, a dielectric layer is disposed over the transistor. A trench is disposed through the dielectric layer to the source/drain region and a conductive contact is disposed in the trench. The source/drain region comprises a delta doped sheet layer with a doping concentration that is higher than rest of the source/drain region.
US09412834B2	Method of manufacturing HEMTs with an integrated Schottky diode A method of manufacturing a transistor device includes forming a compound semiconductor material on a semiconductor carrier, forming a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions, forming a Schottky diode integrated with the semiconductor carrier, and forming contacts extending from the source and drain regions through the compound semiconductor material and in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions.
US09412833B2	Narrow semiconductor trench structure Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.
US09412831B2	Manufacturing method for silicon carbide semiconductor device In a method of manufacturing a silicon carbide semiconductor device having a JFET, after forming a second concave portion configuring a second mesa portion, a thickness of a source region is detected by observing a pn junction between the source region and a first gate region exposed by the second concave portion. Selective etching is conducted on the basis of the detection result to form a first concave portion deeper than the thickness of the source region and configuring a first mesa portion inside of an outer peripheral region in an outer periphery of a cell region, and to make the second concave portion deeper than the second gate region.
US09412829B2	Method for fabricating semiconductor device and semiconductor device A method for fabricating a semiconductor device includes: forming a metal pattern including nickel on a semiconductor layer, the metal pattern having upper and side surfaces; forming a mask pattern having an opening in which upper and side surfaces of the metal pattern therein being exposed; forming a barrier layer on the metal pattern exposed in the opening by a plating method; and forming a conducting layer on the barrier layer exposed in the opening.
US09412828B2	Aligned gate-all-around structure A semiconductor device includes a gate disposed over a substrate. The gate has a first gate portion of the gate including a gate dielectric and a gate electrode disposed above a first channel region and a second gate portion including a gate dielectric and a gate electrode disposed between the substrate and the first channel region and aligned with the first gate portion. A source and a drain region are disposed adjacent the gate. A dielectric layer is disposed on the substrate and has a first portion underlying at least some of the source, a second portion underlying at least some of the drain; and a third portion underlying at least some of the first channel, the first gate portion and the second gate portion.
US09412822B2	Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material.
US09412821B2	Stacked thin channels for boost and leakage improvement A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.
US09412819B2	Semiconductor device and manufacturing method thereof In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p-type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n−-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p−-type body layer, and the n−-type drift layer between the p−-type body layer and the n−-type drift layer. By those measures, it is possible to inhibit the operating characteristic from varying.
US09412818B2	System and method of manufacturing a fin field-effect transistor having multiple fin heights An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a second FinFET device extending from a surface of a second etch stop layer. A first compound layer is interposed between the first etch stop layer and the second etch stop layer.
US09412817B2	Silicide regions in vertical gate all around (VGAA) devices and methods of forming same An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.
US09412811B2	Semiconductor device having localized charge balance structure and method In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region.
US09412809B2	Semiconductor device and manufacturing method thereof Provided is a semiconductor device in which movable ions in an insulation layer on a main surface are reduced and dielectric strength is enhanced. A semiconductor device has a plurality of FLRs, an insulation layer, and a semiconductor layer. The plurality of FLRs surrounds, in a plan view of a substrate, an active region in which an element is formed. The insulation layer is provided on the main surface of the semiconductor device and covers the plurality of FLRs. The semiconductor layer is provided in the insulation layer and surrounds the active region in parallel to the FLRs. The semiconductor layer contains impurities at a surface density lower than a surface density that satisfies a RESURF condition. In the plan view, the semiconductor layer overlaps with a part of the region (an inter-ring region) between adjacent FLRs and does not overlap with rest of the inter-ring region.
US09412808B2	Silicon carbide device and a method for manufacturing a silicon carbide device A silicon carbide device includes an epitaxial silicon carbide layer including a first conductivity type and a buried lateral silicon carbide edge termination region located within the epitaxial silicon carbide layer including a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including the first conductivity type.
US09412806B2	Making multilayer 3D capacitors using arrays of upstanding rods or ridges In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.
US09412800B2	Thin film transistor array substrate and organic light-emitting display apparatus including the same A substrate includes a driving transistor, a capacitor, a driving voltage line, and a connection line. The driving transistor has a gate electrode overlapping a channel region of a curved active layer. The capacitor has a first electrode is formed of the gate electrode of the driving transistor and a second electrode overlapping the first electrode. The driving voltage line includes driving voltage line portions on the capacitor and connected to edges of the second electrode of the capacitor. The first connection line is located at a portion of a region on the capacitor separated from the driving voltage line. A via hole is on the first connection line.
US09412799B2	Display driver circuitry for liquid crystal displays with semiconducting-oxide thin-film transistors An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.
US09412797B2	Array substrate with color film An embodiment of the present invention relates to a technical field of display and provides an array substrate and a method for producing the same and a display apparatus that may simplify the layer arrangements and producing process of the array substrate, reduce the difficulty for producing the array substrate and improve the product yield of the array substrate. The array substrate comprises: a substrate base; and a thin film transistor unit and a color film on the substrate base, wherein the color film is conductive and electrically connected with a drain electrode of the thin film transistor unit.
US09412793B2	Light-emitting element, light-emitting device, electronic device, and lighting device Provided is a light-emitting device which can emit monochromatic light with high purity due to a microcavity effect and which can emit white light in the case of a combination of monochromatic light. Provided is a high-definition light-emitting device. Provided is a light-emitting device with low power consumption. In a light-emitting device with a white-color filter top emission structure, one pixel is formed of four sub-pixels of RBGY, an EL layer includes a first light-emitting substance which emits blue light and a second light-emitting substance which emits light corresponding to a complementary color of blue, and a semi-transmissive and semi-reflective electrode (an upper electrode) is formed so as to cover an edge portion of the EL layer.
US09412790B1	Scalable RRAM device architecture for a non-volatile memory device and method A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring structure is formed overlying the first dielectric material. The method forms one or more first structure comprising a junction material overlying the first wiring structure. A second structure comprising a stack of material is formed overlying the first structure. The second structure includes a resistive switching material, an active conductive material overlying the resistive switching material, and a second wiring material overlying the active conductive material. The second structure is configured such that the resistive switching material is free from a coincident vertical sidewall region with the junction material.
US09412789B1	Stackable non-volatile resistive switching memory device and method of fabricating the same A memory device includes a first plurality of memory cells arranged in a first crossbar array, a first thickness of dielectric material overlying the first plurality of memory cells, and a second plurality of memory cells arranged in a second crossbar array overlying the first thickness of dielectric material. The memory device further includes a second thickness of dielectric material overlying the second plurality of memory cells. In a specific embodiment, the memory device further includes a Nth thickness of dielectric material overlying an Nth plurality of memory cells, where N is an integer ranging from 3 to 8.
US09412780B2	Image sensor An image sensor has photodiodes formed in a Si substrate and configured to prevent carriers generated at a deep position of the Si substrate from affecting adjacent photodiodes due to lateral diffusion (crosstalk between pixels). A modified layer is formed between adjacent photodiodes and at a depth below that of the photodiodes by a laser to generate a recombination level to thereby suppress crosstalk between pixels.
US09412770B2	Pixel structure of display panel The present invention provides a pixel structure of a display panel and a method for manufacturing the same. The pixel structure comprises a first pixel area and a second pixel area that are adjacent to each other. The first pixel area has a first transparent conductive layer disposed therein and the second pixel area has a second transparent conductive layer disposed therein. The first transparent conductive layer in the first pixel area and the second transparent conductive layer in the second pixel area are located at different heights. The pixel structure of the present invention can efficiently increase an aperture ratio for the pixels on the display panel.
US09412765B2	Thin film transistor, manufacturing method of same, and display device According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer.
US09412759B2	CMOS gate contact resistance reduction A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact.
US09412747B2	Semiconductor device and a method of manufacturing the same A method of manufacturing a semiconductor device having a non-volatile memory cell includes forming first insulating films with first conductive films arranged therebetween, recessing the first insulating films using the first conductive films as a mask, so that heights of top surfaces of the first insulating films are lower than heights of top surfaces of the first conductive films, forming a second insulating film over the first conductive and insulating films, forming a second conductive film over the second insulating film, and patterning the first and second conductive films, and the second insulating film. A length of the floating gate in a second direction is larger than a maximum length of the floating gate in a first direction, and a length from a top surface of the second insulating film to a top surface of the floating gate is larger than a length of a space between a plurality the floating gates.
US09412742B2	Layout design for manufacturing a memory cell A layout design usable for manufacturing a memory cell includes a first and second active area layout pattern associated with forming a first and second active area, an isolation region outside the first and second active area, a first polysilicon layout pattern associated with forming a first polysilicon structure, a second polysilicon layout pattern associated with forming a second polysilicon structure, a first interconnection layout pattern associated with forming a first interconnection structure, and a second interconnection layout pattern associated with forming a second interconnection structure. The first active area does not overlap the second active area. The first polysilicon layout pattern overlaps the first active area layout pattern. The second polysilicon layout pattern overlaps the first active area layout pattern and the second active area layout pattern. The first interconnection layout pattern overlaps the second active area layout pattern. The second interconnection layout pattern overlaps the isolation region.
US09412740B2	Integrated circuit product with a gate height registration structure One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.
US09412739B2	Semiconductor device A semiconductor with reduced area is provided. A first transistor includes a first conductor, a first insulator over the first conductor, an oxide semiconductor provided over the first insulator so as to overlap with the first conductor, a second insulator over the oxide semiconductor, a second conductor over the second insulator, and a third conductor and a fourth conductor in contact with the oxide semiconductor. The oxide semiconductor includes a region overlapping with the first region and not overlapping with the second region, and a region not overlapping with the first conductor and overlapping with the second conductor in a region positioned between the third conductor and the fourth conductor when viewed from above. The second transistor is a p-channel transistor. A layer in which the first transistor is provided and a layer in which the second transistor is provided are stacked together.
US09412736B2	Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.
US09412734B2	Structure with inductor and MIM capacitor A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core.
US09412733B2	MOSFET with integrated schottky diode Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each other by a mesa. Each trench may have first and second conductive portions lining the first and second sidewalls. The first and second portions of conductive material are electrically isolated from each other in each trench. The Schottky contact may be formed at any location between the outermost conductive portions. The Schottky structure may be formed in the active area or the termination area of a device die. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
US09412732B2	Semiconductor device In a high-side region, a first n-diffusion region, in which a PMOS constituting a gate drive circuit is formed, and a second n-diffusion region, in which a p-diffusion region is formed, are provided on a surface layer of a p−− substrate. An NMOS constituting a gate drive circuit is formed in the p-diffusion region. A p-type isolation diffusion region at ground potential is provided between the first n-diffusion region and the second n-diffusion region, and the first re-diffusion region and the second n-diffusion region are electrically isolated. The first n-diffusion region is connected to a VB terminal at a power source potential. The second n-diffusion region is connected to a terminal at a reference or floating potential. The p-diffusion region is connected to a VS terminal at a reference potential. Accordingly, it is possible to suppress parasitic operation due to a surge, without using external components, and without element breakdown.
US09412731B2	Semiconductor device Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.
US09412730B2	Integrated circuits, standard cells, and methods for generating a layout of an integrated circuit An integrated circuit according to an embodiment of the invention includes a substrate having a first cell and a second cell, the first and the second cells being adapted to perform a substantially same functionality. Corresponding functional structures of the first and the second cell are electrically connected, at different locations inside the standard cells, to information carrying signal interconnection lines, wherein the functional structures are adapted to serve as an information carrying signal input or as an information carrying signal output.
US09412729B2	Semiconductor package and fabricating method thereof A semiconductor package includes a first package comprising a circuit board and a first semiconductor die mounded on the circuit board, and a second package comprising a mounting board. At least one second semiconductor die may be mounted on the mounting board, and one or more leads may be electrically connected to the mounting board and/or the second semiconductor die. An adhesion member may bond the first package to the second package, and an encapsulant may encapsulate the first package and the second package. the circuit board, the mounting board, and the one or more leads may be arranged to surround the first semiconductor die and the second semiconductor die, and the plurality of leads may be electrically connected to the circuit board and to a constant potential or ground, to reduce the effects of external electromagnetic interference upon the semiconductor package.
US09412727B2	Printing transferable components using microstructured elastomeric surfaces with pressure modulated reversible adhesion In a method of printing a transferable component, a stamp including an elastomeric post having three-dimensional relief features protruding from a surface thereof is pressed against a component on a donor substrate with a first pressure that is sufficient to mechanically deform the relief features and a region of the post between the relief features to contact the component over a first contact area. The stamp is retracted from the donor substrate such that the component is adhered to the stamp. The stamp including the component adhered thereto is pressed against a receiving substrate with a second pressure that is less than the first pressure to contact the component over a second contact area that is smaller than the first contact area. The stamp is then retracted from the receiving substrate to delaminate the component from the stamp and print the component onto the receiving substrate. Related apparatus and stamps are also discussed.
US09412726B2	Display device A display device includes a substrate on which a plurality of pixels are arranged and a circuit for displaying images with respect to each pixel is formed, a substrate terminal as a terminal formed on the substrate, and an electronic component terminal as a terminal of an electronic component electrically connected to the terminal via an anisotropic conductive film. A conductive region that conducts to the anisotropic conductive film in the substrate terminal has a light transmissive part in which a material having light transmissivity penetrates the substrate surface in a perpendicular direction.
US09412725B2	Method and apparatus for image sensor packaging Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond bad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding between the sensor and the ASIC.
US09412720B2	Semiconductor package having supporting plate and method of forming the same A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate.
US09412713B2	Treatment method of electrodeposited copper for wafer-level-packaging process flow A method of treating a copper containing structure on a substrate is disclosed. The method includes electrodepositing the copper containing structure on a substrate, annealing the copper containing structure, and forming an interface between a pad of the copper containing structure and a solder structure after anneal. The interface can have improved resistance to interfacial voiding. The copper containing structure is configured to deliver current between one or more ports and one or more solder structures in the integrated circuit package. Annealing the copper containing structure can move impurities and vacancies to the surface of the copper containing structure for subsequent removal.
US09412710B2	Semiconductor device In order to prevent a crack from developing in an interlayer insulating film formed under a bonding pad due to impact forces, the bonding pad is formed so that small diameter metal plugs and large diameter metal plugs are arranged between a first metal film and a second metal film as an uppermost layer. Holes are formed in the centers of the larger diameter metal plugs and recessed portions are formed in surface areas of the second metal film above the large diameter metal plugs.
US09412703B1	Chip package structure having a shielded molding compound A chip package structure including a main substrate, a carrier substrate, at least a chip, a molding compound, a shielding layer and a plurality of connection structures between the main substrate and the carrier substrate. The shielding layer covers the top surface and the sidewalls of the molding compound and a portion of the carrier substrate. The shielding layer is electrically grounded through the connection structures.
US09412701B2	Semiconductor device including a DC-DC converter The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
US09412700B2	Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
US09412698B2	Semiconductor device having groove-shaped via-hole The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.
US09412690B2	Package substrates, packages including the same, methods of fabricating the packages with the package substrates, electronic systems including the packages, and memory cards including the packages A package substrate includes a substrate body and a plurality of patterns disposed on the substrate body. The substrate body has a first region including a chip attachment region and a second region adjacent to the first region. The plurality of patterns are disposed on the substrate body in the second region. Each of the plurality of patterns extends in a first direction to have a stripe shape, and the plurality of patterns are spaced apart from each other in a second direction which is substantially perpendicular to the first direction. Related fabrication methods, electronic systems and memory cards are also provided.
US09412688B2	Wiring board The wiring board of the present invention includes at least one insulating layer and at least one conductor layer being alternately laminated, a semiconductor element connection pad formed on an upper surface of the insulating layer at an uppermost layer of the insulating layers, a cap connection pattern arranged so as to surround a region where the semiconductor element connection pad is formed, and at least one strip-shaped pattern extending from the semiconductor element connection pad to a region outside an end portion on the region side of the cap connection pattern. The cap connection pattern is formed by a plurality of island-shaped patterns spaced apart from one another, and the strip-shaped pattern is formed between the adjacent island-shaped patterns on the upper surface of the insulating layer at the uppermost layer.
US09412687B2	Wiring substrate and method of manufacturing the same A wiring substrate includes a first wiring layer including a first wiring part having a first wiring interval and a second wiring part having a second wiring interval wider than the first wiring interval, a metal plane layer formed on a portion of a first insulation layer formed on the first wiring layer, the first wiring part being located below the portion, a second insulation layer formed on the first insulation layer and the metal plane layer and having a first via hole and a second via hole, a second wiring layer formed on the second insulation layer and connected to the first wiring layer via a first via conductor formed in the first via hole, and a third wiring layer formed on the second insulation layer and connected to the metal plane layer via a second via conductor formed in the second via hole.
US09412682B2	Through-silicon via access device for integrated circuits A through-silicon via access device (TSVAD) for establishing an electrical connection to a through-silicon via (TSV) located in a planar stack of semiconductor chips is disclosed. The TSVAD may include a switching circuit, having a conductive pad terminal, a TSV terminal, an input terminal coupled to a sending logic circuit, an output terminal coupled to a receiving logic circuit, and logic devices to, in response to control signals, couple the TSV terminal to the conductive pad terminal, in one configuration, and couple the TSV terminal to another terminal in another configuration. The TSVAD may also include a control circuit to generate control signals to cause an input selection circuit to drive a signal from the sending logic circuit onto the input terminal, and to cause an output selection circuit to drive a logic signal from the output terminal to the receiving logic circuit.
US09412677B2	Computer systems having an interposer including a flexible material Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer may absorb thermally induced stresses and conform to warped or uneven surfaces. Embodiments of electronic device packages including a semiconductor die mounted to and electrically connected to the interposer, as well as methods for forming the electronic device packages, are also disclosed. In one electronic device package, the semiconductor die is electrically connected to the interposer with wire bonds attached to a routing layer of the interposer. In another electronic device package, the semiconductor die is electrically connected to the interposer by bonding the semiconductor die to the flexible solder pad elements of the interposer in a flip-chip configuration. A computer system incorporating an electronic device package with an interposer according to the present invention is also disclosed.
US09412673B2	Multi-model metrology Disclosed are apparatus and methods for characterizing a plurality of structures of interest on a semiconductor wafer. A plurality of models having varying combinations of floating and fixed critical parameters and corresponding simulated spectra is generated. Each model is generated to determine one or more critical parameters for unknown structures based on spectra collected from such unknown structures. It is determined which one of the models best correlates with each critical parameter based on reference data that includes a plurality of known values for each of a plurality of critical parameters and corresponding known spectra. For spectra obtained from an unknown structure using a metrology tool, different ones of the models are selected and used to determine different ones of the critical parameters of the unknown structure based on determining which one of the models best correlates with each critical parameter based on the reference data.
US09412668B2	Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
US09412666B2	Equal gate height control method for semiconductor device with different pattern densites A method of forming a semiconductor integrated circuit (IC) includes forming a first semiconductor layer over a substrate, the first semiconductor layer having an uneven upper surface, forming a stop layer over the first semiconductor layer, the first semiconductor layer disposed between the substrate and the stop layer, and treating the stop layer to change its etch selectivity relative to the first semiconductor layer.
US09412665B2	Semiconductor device and method of fabricating the same A semiconductor device and a method for manufacturing the same are capable of improving GIDL in a buried gate, and preventing degradation of device characteristics and reliability due to reduction in gate resistance. The semiconductor device may include: junction regions formed at both sidewalls of a trench formed in a semiconductor substrate; a first gate electrode formed in a lower portion of the trench; a second gate electrode formed on at least one inner sidewall of the trench which overlaps one of the junction regions on the first gate electrode; and a third gate electrode formed on one side of the second gate electrode on the first gate electrode.
US09412664B2	Dual material finFET on single substrate A semiconductor device and a method for fabricating the device are provided. The semiconductor device has a substrate having a first device region and a second device region. A p-type fin field effect transistor is formed in the first device region. The p-type fin field effect transistor has a first fin structure including a first semiconductor material. An n-type fin field effect transistor is formed in the second device region. The n-type fin field effect transistor has a second fin structure including a second semiconductor material that is different than the first semiconductor material. To fabricate the semiconductor device, a substrate having an active layer present on a dielectric layer is provided. The active layer is etched to provide a first region having the first fin structure and a second region having a mandrel structure. The second fin structure is formed on a sidewall of the mandrel structure.
US09412660B1	Methods of forming V0 structures for semiconductor devices that includes recessing a contact structure One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate structures, recessing the source/drain contact structure to define a source/drain contact etch cavity and depositing a conformal second layer of insulating material above a first layer of insulating material and in the source/drain contact etch cavity. The method also includes forming a third layer of insulating material above the conformal second layer of insulating material, forming an opening in the conformal second layer of insulating material and forming a V0 via that is conductively coupled to the exposed portion of the recessed source/drain contact structure.
US09412653B2	Through silicon via (TSV) process A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
US09412651B2	Air-gap formation in interconnect structures A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space, wherein an edge of the first metal line is exposed to the first air gap. A second air gap is on a sidewall of the second metal line and in the space, wherein an edge of the second metal line is exposed to the second air gap. A dielectric material is disposed in the space and between the first and the second air gaps.
US09412647B2	Via definition scheme A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.
US09412646B2	Via in substrate with deposited layer An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties.
US09412645B1	Semiconductor devices and structures A method for fabricating semiconductor devices, including: providing a CMOS fabric and metal layers, the metal layers including a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer, the metal layers providing interconnection for the CMOS fabric, and constructing mask defined connections between the third metal layer and the fourth metal layer, the mask defined connections are substantially similar to antifuse programmed connections of a programmed antifuse programmable device, where the antifuse programmable device is a 3D antifuse programmable device including antifuses and antifuse programming transistors, where the antifuse programming transistors overlay the antifuses, and where the antifuse programming transistors include a monocrystalline channel.
US09412641B1	FinFET having controlled dielectric region height Embodiments are directed to a method of forming a dielectric region of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric region adjacent a lower portion of the at least one fin, wherein the dielectric region includes a top surface. The method further includes forming a blocking layer on the top surface of the dielectric region, wherein the blocking layer is configured to prevent at least one subsequent FinFET fabrication operation from impacting the top surface of the dielectric region.
US09412638B2	End effector pads An end effector pad including a fence member, a first recessed support member extending from a first side of the fence member, a second recessed support member extending from a second side of the fence member opposite the first side, a first glass plate having a relatively low coefficient of friction disposed on top of the first recessed support member for supporting a substrate thereon, and a second glass plate having a relatively low coefficient of friction disposed on top of the second recessed support member for supporting a substrate thereon.
US09412635B2	Electrostatic chuck device An electrostatic chuck device includes an electrostatic chuck part that has an upper surface as a placement surface for placing a plate-shaped sample and has an internal electrode for electrostatic attraction built therein; and a cooling base part that cools the electrostatic chuck part. The electrostatic chuck part and the cooling base part are integrally adhered to each other via an adhesive layer. An insulator having a double pipe structure including an insulator and an insulator provided coaxially with an outer peripheral portion of the insulator is provided in a cooling gas hole, formed in the electrostatic chuck part and the cooling base part, so as to cover an exposed surface of the adhesive layer on the cooling gas hole side.
US09412632B2	Reticle pod A reticle pod includes an outer pod shell and an outer pod door disposed under the outer pod shell. The outer pod door has at least one gas control hole. A seal ring is disposed between the outer pod shell and the outer pod door. A valve is disposed in each gas control hole. The outer pod shell and the outer pod door are configured to form an enclosure space in order to store a reticle. The seal ring seals the gap between the outer pod shell and the outer pod door. The at least one valve is configured to control gas flow in and out of the enclosure space.
US09412628B2	Acid treatment strategies useful to fabricate microelectronic devices and precursors thereof A method of treating one or more wafers is provided. The method comprises the steps of: a) providing at least one wafer, that has first and second opposed major faces and at least one feature, such as a metal silicide, that is sensitive to a neutralizing chemistry on the first major face; b) causing an acidic chemistry, such as a sulfuric acid and/or phosphoric acid, to contact the first major face of the wafer and causing the wafer to spin; c) after causing the acidic chemistry to contact the wafer, causing a non-etching rinsing fluid to contact the first major face while the wafer is spinning; and d) during at least a portion of the time that the non-etching rinsing fluid is caused to contact the first major face of the spinning wafer, causing a neutralizing liquid to contact the second major face of the spinning wafer.
US09412627B2	Liquid processing method and liquid processing apparatus A surface of a substrate can be dried cleanly after liquid-processed by a liquid processing method and a liquid processing apparatus. The liquid processing method includes forming a liquid film of a rinse solution on an entire surface of a substrate having thereon a hydrophobic region by supplying, onto a central portion of the surface of the substrate, the rinse solution for rinsing a chemical liquid supplied on the substrate at a first flow rate while rotating the substrate at a first rotation speed; forming a stripe-shaped flow of the rinse solution on the surface of the substrate by breaking the liquid film formed on the entire surface of the substrate; and moving a discharge unit configured to supply the rinse solution toward a periphery of the substrate until the stripe-shaped flow of the rinse solution is moved outside the surface of the substrate.
US09412621B2	Semiconductor device and method for forming the same A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.
US09412618B2	Pattern forming method A pattern forming method of forming a pattern on an underlying layer of a target object includes forming a block copolymer layer, which includes a first polymer and a second polymer and is configured to be self-assembled, on the underlying layer; processing the target object to form a first region containing the first polymer and a second region containing the second polymer in the block copolymer layer; etching the second region partway in a thickness direction thereof in a capacitively coupled plasma processing apparatus after the processing of the target object; generating secondary electrons from an upper electrode of the plasma processing apparatus by applying a negative DC voltage to the upper electrode and irradiating the secondary electrons onto the target object, after the etching of the second region; and additionally etching the second region in the plasma processing apparatus after the irradiating of the secondary electrons.
US09412617B2	Plasma processing method and plasma processing apparatus Plasma etching is performed while suppressing bowing during etching of a multi-layer film. The plasma etching is performed multiple times using a processing gas containing HBr gas and C4F8 gas, and the etching gradually forms recesses from a SiN layer through a laminated film. By adding a gas containing boron to the processing gas during the etching at a predetermined timing and at a predetermined flow ratio while etching the laminated film, a protective film is formed on side walls of the SiN layer that are exposed to the recess.
US09412616B1	Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of material and first and second openings that extend through both of the first and second layers of material, wherein the first opening is positioned above a first area of the substrate where the DDB isolation structure will be formed and the second opening is positioned above a second area of the substrate where the SDB isolation structure will be formed. The method also includes performing a first process operation through the first opening to form the DDB isolation structure, performing a second process operation to remove the second layer of material and to expose the first opening in the first layer of material, and performing a third process operation through the second opening to form the SDB isolation structure.
US09412613B2	Development of high etch selective hardmask material by ion implantation into amorphous carbon films Embodiments described herein provide for a method of forming an etch selective hardmask. An amorphous carbon hardmask is implanted with various dopants to increase the hardness and density of the hardmask. The ion implantation of the amorphous carbon hardmask also maintains or reduces the internal stress of the hardmask. The etch selective hardmask generally provides for improved patterning in advanced NAND and DRAM devices.
US09412611B2	Use of grapho-epitaxial directed self-assembly to precisely cut lines A method for forming a patterned topography on a substrate is provided. The substrate is initially provided with an exposed plurality of lines formed atop. An embodiment of the method includes aligning and preparing a first directed self-assembly pattern (DSA) pattern immediately overlying the plurality of lines, and transferring the first DSA pattern to form a first set of cuts in the plurality of lines. The embodiment further includes aligning and preparing a second DSA pattern immediately overlying the plurality of lines having the first set of cuts formed therein, and transferring the second DSA pattern to form a second set of cuts in the plurality of lines. The first and second DSA patterns each comprise a block copolymer having a hexagonal close-packed (HCP) morphology and a characteristic dimension Lo that is between 0.9 and 1.1 times the spacing between individual lines of the plurality of lines.
US09412610B2	Semiconductor devices and methods of manufacturing the same A method of manufacturing a semiconductor device is disclosed. In the method, a substrate having a first surface and a second surface is provided. The second surface is opposed to the first surface. A via hole is formed to penetrate the substrate from the first surface toward the second surface. The via hole includes a first portion and a second portion. The first portion has a first sidewall which is substantially perpendicular to the first surface. The second portion has a second sidewall which gradually decreases from the first surface toward the second surface, and has a bottom surface that substantially flat. A seed pattern is formed on the first sidewall of the first portion, the second sidewall of the second portion and the bottom surface of the second portion of the via hole. A first thickness (Vt) of the seed pattern on the first sidewall of the first portion is less than a second thickness (VIt) of the seed pattern on the second sidewall of the second portion. A through via is formed to fill the via hole.
US09412608B2	Dry-etch for selective tungsten removal Methods of selectively etching tungsten relative to silicon-containing films (e.g. silicon oxide, silicon carbon nitride and (poly)silicon) as well as tungsten oxide are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten. The plasma effluents react with exposed surfaces and selectively remove tungsten while very slowly removing other exposed materials. Sequential and simultaneous methods are included to remove thin tungsten oxide which may, for example, result from exposure to the atmosphere.
US09412607B2	Plasma etching method An isotropic etching process can be performed with high uniformity. A plasma etching method of etching an etching target layer containing silicon includes preparing a processing target object having the etching target layer in a processing chamber; removing an oxide film on a surface of the etching target layer by generating plasma of a first processing gas that contains a fluorocarbon gas or a fluorohydrocarbon gas but does not contain oxygen; removing a carbon-based reaction product generated when the removing of the oxide film by generating plasma of a second processing gas that does not contain oxygen; and etching the etching target layer without applying a high frequency bias power to a lower electrode serving as a mounting table configured to mount the processing target object thereon by generating plasma of a third processing gas containing a fluorocarbon gas or a fluorohydrocarbon gas with a microwave.
US09412604B2	Methods of manufacturing semiconductor device The present inventive concept provides methods of manufacturing a semiconductor device including forming an inner mask layer on an etching target film, the inner mask layer including a polymer; forming a porous film on the etching target film, the porous film covering the inner mask layer; supplying an acid source to an outer surface area of the inner mask layer through the porous film; inducing a chemical reaction of the polymer included in the inner mask layer in the outer surface area by using the acid source; forming inner mask patterns by removing a chemically reacted portion of the inner mask layer; and etching the etching target film by using at least a portion of the porous film and the inner mask patterns as an etching mask.
US09412603B2	Trimming silicon fin width through oxidation and etch Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a trench defining a mandrel structure. Sidewalls of the mandrel structure and a bottom surface of the trench are oxidized and subsequently etched to reduce a width of the mandrel structure. The oxidation and etching of the mandrel structure may be repeated until a desired width of the mandrel structure is achieved. A semiconducting material is subsequently deposited on a regrowth region of the mandrel structure to form a fin structure. The oxidizing and etching the mandrel structure provides a method for forming the fin structure which can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.
US09412601B2	Method for processing a carrier A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed.
US09412598B2	Edge rounded field effect transistors and methods of manufacturing Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.
US09412597B2	Flash memory semiconductor device and method thereof The present disclosure provides a method of fabricating a flash memory semiconductor device. In one embodiment, a method of fabricating a resistive memory array includes providing a semiconductor substrate having at least one memory cell array region and at least one shunt region, forming a control gate electrode on the memory cell array region and the shunt region, depositing a dielectric film lamination and a conductive film to cover the control gate electrode and the semiconductor substrate, forming two recesses respectively corresponding to two sides of the control gate electrode on the shunt region, patterning the conductive film to form two sidewall memory gate electrodes and one top memory gate electrode, removing one of the sidewall memory gate electrodes on the memory cell array region, and removing the dielectric film lamination which is exposed from the memory gate electrodes.
US09412594B2	Integrated circuit fabrication A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
US09412593B2	Composition for film formation, resist underlayer film, and forming method of resist underlayer film, and pattern-forming method A composition for film formation includes a compound represented by formula (1), and a solvent. R1 represents a monovalent group including an aromatic ring. n is an integer of 3 to 6. At least one monovalent group represented by R1 further includes a group including an ethylenic double bond. a plurality of R1s are identical or different. A part or all of hydrogen atoms on the benzene ring in the formula (1) and on the aromatic ring are unsubstituted or substituted with a halogen atom or an alkyl group having 1 to 10 carbon atoms.
US09412591B2	Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The deposited negative photoresist layer is patterned, thereby removing photoresist from between the spacers in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers is facilitated. The pattern defined by the spacers and the patterned negative photoresist is transferred to one or more underlying masking layers before being transferred to a substrate.
US09412590B1	Manufacturing method of oxide semiconductor device A manufacturing method of an oxide semiconductor device includes the following steps. A barrier layer is formed on a substrate. An annealing process is performed after the step of forming the barrier layer. A first oxygen treatment is performed on the barrier layer after the annealing process for forming a first oxygen provider layer on the barrier layer. An oxide semiconductor layer is then formed on the first oxygen provider layer.
US09412588B2	Method of growing nitride semiconductor layer and nitride semiconductor formed by the same A method of growing a nitride semiconductor layer includes forming a plurality of nano-structures on a substrate, forming a first buffer layer on the substrate such that upper portions of each of the nano-structures are exposed, removing the nano-structures to form voids in the first buffer layer, and growing a nitride semiconductor layer on the first buffer layer including the voids.
US09412586B2	Method for producing a template for epitaxial growth having a sapphire (0001) substrate, an initial-stage A1N layer and laterally overgrown A1XGAYN (0001) layer A surface of a sapphire (0001) substrate is processed to form recesses and protrusions so that protrusion tops are flat and a given plane-view pattern is provided. An initial-stage AlN layer is grown on the surface of the sapphire (0001) substrate having recesses and protrusions by performing a C+ orientation control so that a C+ oriented AlN layer is grown on flat surfaces of the protrusion tops, excluding edges, in such a thickness that the recesses are not completely filled and the openings of the recesses are not closed. An AlxGayN(0001) layer (1≧x>0, x+y=1) is epitaxially grown on the initial-stage AlN layer by a lateral overgrowth method. The recesses are covered with the AlxGayN(0001) layer laterally overgrown from above the protrusion tops. Thus, an template for epitaxial growth having a fine and flat surface and a reduced threading dislocation density is produced.
US09412585B2	Method of manufacturing a SiOCN film, substrate processing apparatus, and recording medium A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times after supplying a nitriding gas to the substrate. The cycle includes performing the following steps in the following order: supplying a carbon-containing gas to the substrate; supplying a predetermined element-containing gas to the substrate; supplying the carbon-containing gas to the substrate; supplying an oxidizing gas to the substrate; and supplying the nitriding gas to the substrate.
US09412584B2	Method of manufacturing a thin film having a high tolerance to etching and non-transitory computer-readable recording medium A thin film containing boron and a borazine ring structure is formed on a substrate by performing a cycle a predetermined number of times under a condition where the borazine ring structure is preserved in a borazine compound. The cycle includes: supplying a source gas containing boron and a halogen element to the substrate; and supplying a reactive gas including a borazine compound to the substrate.
US09412583B2	Methods of forming dielectric layers and methods of manufacturing semiconductor devices using the same To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
US09412581B2	Low-K dielectric gapfill by flowable deposition Methods are described for forming a flowable low-k dielectric layer on a patterned substrate. The film may be a silicon-carbon-oxygen (Si—C—O) layer in which the silicon and carbon constituents come from a silicon and carbon containing precursor while the oxygen may come from an oxygen-containing precursor activated in a remote plasma region. A similarly deposited silicon oxide layer may be deposited first to improve the gapfill capabilities. Alternatively, or in combination, the flow of a silicon-and-carbon-containing precursor may be reduced during deposition to change the properties from low-k to high strength roughly following the filling of features of the patterned substrate.
US09412578B2	Charged particle analysers and methods of separating charged particles A method of separating charged particles using an analyzer is provided, the method comprising: causing a beam of charged particles to fly through the analyzer and undergo within the analyzer at least one full oscillation in the direction of an analyzer axis (z) of the analyzer whilst orbiting about the axis (z) along a main flight path; constraining the arcuate divergence of the beam as it flies through the analyzer; and separating the charged particles according to their flight time. An analyzer for performing the method is also provided. At least one arcuate focusing lens is preferably used to constrain the divergence, which may comprise a pair of opposed electrodes located either side of the beam. An array of arcuate focusing lenses may be used which are located at substantially the same z coordinate, the arcuate focusing lenses in the array being spaced apart in the arcuate direction and the array extending at least partially around the z axis, thereby constraining the arcuate divergence of the beam a plurality of times as it flies through the analyzer.
US09412575B2	Ion guide with orthogonal sampling A mass spectrometer is disclosed comprising a RF ion guide wherein in a mode of operation a continuous, quasi-continuous or pulsed beam of ions is orthogonally sampled from the ion guide and wherein the continuous, quasi-continuous or pulsed beam of ions is not axially trapped or otherwise axially confined within the RF ion guide. The ion guide is maintained, in use, at a pressure selected from the group consisting of: (i) 0.0001-0.001 mbar; (ii) 0.001-0.01 mbar; (iii) 0.01-0.1 mbar; (iv) 0.1-1 mbar; (v) 1-10 mbar; (vi) 10-100 mbar; and (vii) >100 mbar.
US09412572B2	Sample holders and methods of using them Certain embodiments described herein are directed to sample holders that can be used to retain a sample support effective for use in direct sample analysis. In some embodiments, the sample support can include a first and a second plate with apertures to permit a sample to be analyzed using direct sample analysis.
US09412571B2	Imaging mass spectrometric data processing method and imaging mass spectrometer Compressed data of mass spectra obtained at respective measurement points and normalization coefficients for XIC normalization or the like are stored in a memory (21). When a normalized imaging graphic at a specific m/z value is to be displayed, a data decompression processor (23) reads the minimally required set of compressed data from the memory (21) and restores the intensity value corresponding to the m/z value at each measurement point. A normalizing calculation processor (29) reads an XIC normalization coefficient corresponding to the m/z value from the memory (21) and corrects the intensity values at each measurement point by multiplying those values by the coefficient. An imaging graphic creation processor (27) assigns a display color to each of the corrected intensity values to create an imaging graphic, and displays the imaging graphic on the screen of a display unit (6). According to this method, even in the case of sequentially displaying imaging graphics while changing the normalization condition, those graphics can be displayed at high speeds if the normalization coefficients are previously calculated and stored.
US09412569B2	Remote arc discharge plasma assisted processes A coating system includes a vacuum chamber and a coating assembly positioned within the vacuum chamber. The coating assembly includes a vapor source that provides material to be coated onto a substrate, a substrate holder to hold substrates to be coated such that the substrates are positioned in front of the vapor source, a cathode chamber assembly, and a remote anode. The cathode chamber assembly includes a cathode, an optional primary anode and a shield which isolates the cathode from the vacuum chamber. The shield defines openings for transmitting an electron emission current from the cathode into the vacuum chamber. The vapor source is positioned between the cathode and the remote anode while the remote anode is coupled to the cathode.
US09412563B2	Spatially discrete multi-loop RF-driven plasma source having plural independent zones An RF plasma source has a resonator with its shorted end joined to the processing chamber ceiling and inductively coupled to two arrays of radial toroidal channels in the ceiling, the resonator having two radial zones and the two arrays of toroidal channels lying in respective ones of the radial zones.
US09412562B2	Capacitive coupling plasma processing apparatus A capacitive coupling plasma processing apparatus includes a process chamber configured to have a vacuum atmosphere, and a process gas supply section configured to supply a process gas into the chamber. In the chamber, a first electrode and a second electrode are disposed opposite each other. The second electrode includes a plurality of conductive segments separated from each other and facing the first electrode. An RF power supply is configured to apply an RF power to the first electrode to form an RF electric field within a plasma generation region between the first and second electrodes, so as to turn the process gas into plasma by the RF electric field. A DC power supply is configured to apply a DC voltage to at least one of the segments of the second electrode.
US09412557B2	Charged particle beam apparatus and program The movement distance of a second adjustment slider 204 is made shorter than that of a first adjustment slider 205 if the first adjustment slider 205 is positioned in a displayed range, except at both ends thereof, of a set value adjustment axis 203 in a first set value adjustment axis display part 202. The first adjustment slider 205 is kept unmoved while the second adjustment slider 204 alone is moved in the direction of one of both ends of the displayed range if the first adjustment slider 205 is positioned at least at the one of both ends of the displayed range of the set value adjustment axis 203 in the first set value adjustment axis display part 202, if the second adjustment slider 204 is also positioned in the displayed range except at the both ends thereof, and if the first adjustment slider 205 is to be selectively operated by a cursor 220. This structure allows coarse and fine adjustments of set values for operation control to be carried out easily and accurately.
US09412553B2	Transmission X-ray generator An x-ray transmission device includes two surfaces in frictional contact within a low fluid pressure environment provided by a housing substantially opaque to x-rays. Materials of the two surfaces are selected such that the frictional contact generates relative charging between the surfaces. The housing includes a window substantially transparent to x-rays, and an electron target, for example a metal, is on an interior surface of the window. The electron target faces the surface that is relatively negatively charged, such that electrons accelerated from that surface, or accelerated due to the negative charge of that surface strike the electron target to generate x-rays, which may be transmitted through the window.
US09412551B2	Cathode obtaining method and electron beam writing apparatus A cathode obtaining method includes producing a plurality of cathodes each including an electron emission member and a cover part, provided with a gap, which covers a side surface of the electron emission member, measuring an outer dimension of the upper surface of the electron emission member, for each of a plurality of cathodes, measuring an outer dimension of the gap at the same surface as the upper surface of the electron emission member, for each of a plurality of cathodes, calculating an area ratio by dividing the area of the gap, for each of a plurality of cathodes, obtaining an upper limit of the area ratio corresponding to a desired brightness by using a correlation between brightness and the area ratio, and selecting a cathode having the area ratio less than or equal to the upper limit from a plurality of cathodes that have been produced.
US09412547B2	Contactor A contactor includes a contact portion and an actuation portion. The contactor further includes a keeping portion. The keeping portion includes a capacitor structure and uses an electrostatic force between opposite plates of the capacitor structure to keep the contact portion in a contact state or a disconnection state. The electrostatic force generated by an electrostatic latch is used to keep the contactor in a switched-to static state. The contactor has reduced energy consumption in the static state, is convenient to manufacture, and has a low cost.
US09412545B2	Electromagnetic relay An electromagnetic relay includes a contact part including a fixed contact and a movable contact, the movable contact being displaceable in an approaching/separating direction with respect to the fixed contact; a drive part including a coil, a movable core, and a fixed core, the movable core being connected to the movable contact via an axial core, and the fixed core including a first plate member having a through hole through which the axial core is inserted and a second plate member that encapsulates the coil; and a permanent magnet polarized in a direction substantially perpendicular to the approaching/separating direction. The first plate member or the second plate member includes an extension part that extends toward the contact part, the extension part being configured to hold the permanent magnet.
US09412542B2	Particulate and pressure redirection shield for an electric circuit breaker Featured is a particulate and pressure redirection barrier for an electrical breaker as well as a breaker embodying such a barrier. Such a barrier includes first through fifth segments, where the first segment includes a first and second side section and a bottom section that are coupled to each other so as to form a generally U shaped structure. The second segment is coupled to the first side section so it extends outwardly at an angle from the first side section. The third segment is coupled to the second side section so as to extend outwardly and at an angle from the second side section. The fourth segment is coupled to the second segment so as to extend outwardly from and at an angle with respect to the second segment. The fifth segment is coupled to the third segment so as to extend outwardly from and at an angle with respect to the third segment. Such a configuration of the fourth and fifth segments is such that gas flowing along a surface of the second or third segments is redirected at an angle with respect to that surface.
US09412540B2	Switch A small-size switch having an arc runner is provided. The switch includes fixed contacts each of which is bonded with each one end of fixed contactors 6U; movable contacts 10U each of which is bonded with each of movable contactors 9 and each of which can contact with or leave from each of the fixed contacts; an interphase barrier 80 that is disposed so as to partition the movable contacts 10U one by one and that is an insulator; and an arc runner that has an arc extinguish portion 12A and that is disposed so as not to intrude in a space where the interphase barrier 80 and the movable contactor 9 are most closely located.
US09412539B2	Frame-supported circuit breaker having automatic locking function An air circuit breaker with a self-locking function, includes: an air circuit breaker body; wherein the air circuit breaker further includes an input unit for inputting a locking code or an unlocking code; an authentication processing unit for receiving the locking code or the unlocking code from the input unit and outputting a control signal after authenticating; and a locking unit for receiving the control signal from the authentication processing unit and locking or unlocking the air circuit breaker body.
US09412532B2	Portable power source A portable power source includes a main body and a power button. The main body includes a receiving portion. The receiving portion defines a receiving groove and includes a protrusion received in the receiving groove. The protrusion includes a contact switch. The power button includes a button body and a latching arm. The button body pushes the contact switch to turn on/off the portable power source, and the latching arm rebounds the button body away from the contact switch.
US09412526B2	Spring biased slide switch A switch includes: a case including a bottom portion and a side wall; a fixed terminal provided on the bottom portion of the case; a supporting member provided in the case; a movable contact strip supported by the supporting member so as to be pivotable in a vertical direction above the fixed terminal; a resilient member provided between the side wall of the case and the movable contact strip, and configured to urge one end portion of the movable contact strip obliquely upward; and a pressing member provided above the resilient member. The movable contact strip pivots and an opened-closed state between the movable contact strip and the fixed terminal is switched by pressing a center portion of the resilient member downward by the pressing member.
US09412523B2	Enhanced packing of energy storage particles The present application is generally directed to energy storage materials such as activated carbon comprising enhanced particle packing properties and devices containing the same. The energy storage materials find utility in any number of devices, for example, in electric double layer capacitance devices and batteries. Methods for making the energy storage materials are also disclosed.
US09412522B2	Hollow cylindrical capacitor and inverter device The hollow tubular capacitor includes one side electrode connecting portion having an inner peripheral tubular portion and one side surface portion, the other side electrode connecting portion having an outer peripheral tubular portion and the other side surface portion and an electrostatic capacitance portion having one side electrode plate, the other side electrode plate and a dielectric body, wherein the electrostatic capacitance portion is accommodated in an annular space formed at the inner peripheral tubular portion, the one side surface portion, the outer peripheral tubular portion and the other side surface portion in a high density to reduce inside inductance component. The inverter device is formed such that the hollow tubular capacitor and an annular inverter circuit portion having three-phase upper and lower arms are integrally arranged coaxially on the central axis line.
US09412520B2	Multilayer ceramic electronic component A multilayer ceramic electronic component may include: a ceramic body in which a plurality of internal electrodes and a plurality of dielectric layers are stacked in a thickness direction; and an external electrode including an electrode layer disposed on an outer surface of the ceramic body to be connected to the internal electrodes, a conductive resin layer disposed on the electrode layer and containing metal particles and a base resin, and a plating layer disposed on the conductive resin layer.
US09412516B2	Resolver and method of manufacturing the same Provided is a method of manufacturing a resolver having a stator mounted around a rotator and configured to detect a rotational angle of a motor, the method including: forming the stator to have a core with protrusions disposed at a predetermined interval along a rotational direction of the rotator; winding a signal source coil around the protrusions of the core to generate an alternate current (AC) magnetic field when an input voltage signal is applied thereto; and winding a plurality of output signal coils alternately along the rotational direction of the rotator around the protrusions of the core, along the rotational direction of the rotator, to generate induced voltage signals of different phases in response to the AC magnetic field generated by the signal source coil and the rotation of the rotator.
US09412515B2	Communication and control regarding wireless electric vehicle electrical energy transfer A method substantially as shown and described in the detailed description and/or drawings and/or elsewhere herein. A device substantially as shown and described in the detailed description and/or drawings and/or elsewhere herein.
US09412513B2	Wireless power transmission system To improve power transmission efficiency in wireless power feeding by using a magnetic body. A wireless power transmission system 100 feeds power by wireless from a feeding coil L2 to a receiving coil L3 based on a magnetic-field resonance phenomenon between the feeding coil L2 and receiving coil L3. A transmission control circuit 200 supplies AC power to the feeding coil L2 at a drive frequency so as to make the feeding coil L2 feed the AC power to the receiving coil L3. A magnetic body F is disposed between the feeding coil L2 and receiving coil L3. The magnetic body F is disposed in a space between coil surfaces of the feeding coil L2 and receiving coil L3.
US09412503B2	Electronic component including outer electrodes provided on end portions of a surface of an electronic component body In an electronic component, when L0 is a dimension of an electronic component body in a first direction, L1 is a distance between a first outer electrode and a second outer electrode on a first surface in the first direction, and L2 is a dimension of each of the first and second outer electrodes on the first surface in the first direction, 0%
US09412502B2	Method of making a down-hole cable having a fluoropolymer filler layer A system and method for a down-hole cable is provided. The down-hole cable includes an insulated conductor portion. A filler layer abuts and encapsulates the insulated conductor portion, wherein the filler layer is substantially formed with a foamable fluoropolymer. At least one additive is mixed with the foamable fluoropolymer filler layer. An armor shell is applied to the exterior of the foamable fluoropolymer filler layer with the at least one additive. A bond is formed between the foamable fluoropolymer filler layer with the at least one additive and an internal surface of the armor shell.
US09412497B2	Cable An object of the invention is to provide a cable capable of matching exposed dimensions of conductors with a predetermined dimension to perform good processing at the time of distal end processing. In a cable (10) in which a pair of insulated wires (1) each of which is formed by covering a conductor (4) with an insulator (5) is mutually stranded and a periphery of these stranded insulated wires (1) is covered with a sheath (6) made of an inner sheath (2) and an outer sheath (3), the conductor (4) is formed by assembling a plurality of stranded wires (4a) each of which is formed by wholly stranding a plurality of wires (4b), and by further wholly stranding the stranded wires (4a).
US09412484B2	Ultracapacitor with a novel carbon Disclosed is a carbon material that can be useful, for example, in ultracapacitors. Also disclosed are applications and devices containing the carbon material.
US09412483B2	Composite wire and contact element A contact element is provided. The contact element has a composite wire. The composite wire has a core made of steel or a steel alloy, a copper alloy layer surrounding the core and a metallic coating applied to the copper alloy layer. The contact element is configured as a connecting wire, a connection wire, a cable wire, a cable strand, a plug-in pin for plug connectors, a weaving wire, a woven wire mesh, a knitted wire mesh or a spring element.
US09412480B2	Diffraction leveraged modulation of X-ray pulses using MEMS-based X-ray optics A method and apparatus are provided for implementing Bragg-diffraction leveraged modulation of X-ray pulses using MicroElectroMechanical systems (MEMS) based diffractive optics. An oscillating crystalline MEMS device generates a controllable time-window for diffraction of the incident X-ray radiation. The Bragg-diffraction leveraged modulation of X-ray pulses includes isolating a particular pulse, spatially separating individual pulses, and spreading a single pulse from an X-ray pulse-train.
US09412479B2	Method and composition for removing radioactive cesium The present invention intends to provide a method for removing radioactive cesium, or radioactive iodine and radioactive cesium that is simple and low-cost, further does not require an energy source such as electricity, moreover can take in and stably immobilize the removed radioactive substances within a solid, and can reduce the volume of radioactive waste as necessary, and to provide a hydrophilic resin composition using for the method for removing radioactive cesium, or radioactive iodine and radioactive cesium, and the object of the present invention is achieved by using a hydrophilic resin composition containing: at least one hydrophilic resin selected from the group consisting of a hydrophilic polyurethane resin, a hydrophilic polyurea resin, and a hydrophilic polyurethane-polyurea resin each having at least a hydrophilic segment; and a clay mineral dispersed therein in a ratio of at least 1 to 180 mass parts relative to 100 mass parts of the hydrophilic resin.
US09412475B2	Apparatus for transferring a fuel rod for testing Disclosed is a fuel rod testing apparatus for a nuclear fuel assembly. The fuel rod testing apparatus includes a helium leakage testing chamber having a gate so that a fuel rod is horizontally loaded/unloaded and testing whether or not helium leaks from the fuel rod, a fuel rod upward/downward transfer unit that has first and second transfer sections located in front of the gate and horizontally installed apart from each other in order to guide the fuel rod loaded into or unloaded from the helium leakage testing chamber, and that vertically drives the first and second transfer sections, and a main frame that has a upper transfer section disposed in parallel in a lengthwise direction of the fuel rod upward/downward transfer unit and having an inclined face and a lower transfer section installed at a lower portion of the upper transfer section and having an inclined face.
US09412474B2	Method and apparatus for compressing plasma to a high energy state A compressor assembly and the method of using the same which includes an elongated spiral passageway within which a compact toroid plasma, such as a compact toroid plasma structure, can be efficiently compressed to a high-energy state by compressing the compact toroid plasma structure by its own momentum against the wall of the spiral passageway in a manner to induce heating by conservation of energy. The compressor assembly also includes a burn chamber that is in communication with the spiral passageway and into which the compressed compact toroid plasma structure is introduced following its compression.
US09412473B2	System and method of a novel redundancy scheme for OTP A novel redundancy scheme to repair no more than one defect per I/O in a One-Time-Programmable (OTP) memory is disclosed. An OTP memory has a plurality of OTP cells in a plurality of I/Os and at least one auxiliary OTP cell associated with each I/O. At least one volatile cell in each I/O corresponds to the auxiliary OTP cells. At least one Boolean gate to invert the data into and/or out of the main OTP memory in each I/O independently based on the data in the volatile cells. The data in each I/O of the OTP memory can be inverted if no more than one defect per I/O is found. Furthermore, the inversion scheme can be achieved by reading the auxiliary OTP cells and storing into the volatile cells by automatically generating at least one read cycle upon initialization.
US09412471B2	Method of reading data from a nonvolatile memory device, nonvolatile memory device, and method of operating a memory system In a method of reading data from a nonvolatile memory device, a first read operation for memory cells coupled to a first word line is performed by applying a first read voltage to the first word line, a first read retry is performed to obtain an optimal read level regardless or independent of whether data read by the first read operation is error-correctable, and the optimal read level is stored to perform a subsequent second read operation using the optimal read level. Related methods and devices are also discussed.
US09412468B2	Semiconductor devices and semiconductor systems for conducting a training operation The semiconductor device includes a flag signal generator, a reference voltage generator and a first buffer. The flag signal generator generates a flag signal in response to an internal command and an information code. The reference voltage generator receives a set code in response to the flag signal, and generates a reference voltage having a voltage level regulated according to the set code. The first buffer buffers the external signal in response to the reference voltage to generate an internal signal, and generates a calibration code in response to the flag signal.
US09412465B2	Reliable readout of fuse data in an integrated circuit An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses.
US09412460B2	Plural operation of memory device An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data usage in response to a first operation algorithm to read, program and erase data, and for a second pattern of data usage in response to a second operation algorithm to read, program and erase data, respectively. The controller circuitry is coupled to the first and second memory blocks, and is configured to execute the first and second operation algorithms, wherein a word line pass voltage for read operations applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage for read operations applied in the second operation algorithm.
US09412457B2	Semiconductor memory apparatus, data transmission device, and recording method According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value.
US09412456B2	Nonvolatile memory device, programming method of nonvolatile memory device and memory system including nonvolatile memory device Disclosed are a program method and a nonvolatile memory device. The method includes receiving program data to be programmed in memory cells; reading the memory cells to judge an erase state and at least one program state; performing a state read operation in which the at least one program state is read using a plurality of state read voltages; and programming the program data in the memory cells using a plurality of verification voltages having different levels according to a result of the state read operation. Also disclosed are methods using a plurality of verification voltages selected based on factors which may affect a threshold voltage shift or other characteristic representing the data of a memory cell after programming.
US09412455B2	Data write control device and data storage device According to one embodiment, a data transfer control device complying with a communication protocol which executes an update of information from an attachment device in a predetermined area of a system memory, the device includes a receiving part receiving the information from the attachment device, a transferring part transferring the information in the predetermined area, the information from the transferring part overwritten in the predetermined area sequentially, and a determining part inhibiting a transfer of the information in the transferring part to omit the update of the information in the predetermined area.
US09412452B2	Semiconductor device A semiconductor device includes a first memory string and a second memory string. The first memory string includes a plurality of first main memory cells formed on a pipe transistor of a semiconductor substrate and a plurality of first dummy memory cells connected between the first main memory cells and a common source line. The second memory string includes a plurality of second main memory cells formed on the pipe transistor and a plurality of second dummy memory cells connected between the second main memory cells and a bit line. The number of the second dummy memory cells is greater than the number of the first dummy memory cells.
US09412448B2	C-element with non-volatile back-up The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes (Q, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element (202) having a first terminal coupled to the first storage node (Q); a second resistive element (204) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (Rmin, Rmax), wherein a second terminal of the first resistive element (202) is coupled to a second terminal of the second resistive element (204) via a first transistor (210); and a control circuit (232).
US09412444B2	Electronic device An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.
US09412443B2	Processor system having variable capacity memory According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the basic units including one cell transistor and one variable resistance element, a mode selector switching between first and second modes, a read/write of one bit executed in 2n basic units (n is an integer) among the basic units in the first mode, the read/write of the one bit executed in 2m basic units (m is an integer, m≠n) among the basic units in the second mode, and a control circuit which controls the switching between the first and second modes.
US09412440B1	Systems and methods of pipelined output latching involving synchronous memory arrays Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.
US09412439B1	Hybrid TFET-MOSFET circuit design A circuit includes a hybrid switch, which includes a Tunnel Field-Effect Transistor (TFET) having a first source, a first drain, and a first gate. The hybrid switch further includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) connected to the TFET in parallel, with the MOSFET including a second source connected to the first source, a second drain connected to the first drain, and a second gate connected to the first gate.
US09412435B2	Pipeline-controlled semiconductor memory device with reduced power consumption and memory access time A semiconductor device includes a memory cell array including a plurality of memory array basic units. A first bus for transfer of address/control signals, includes a first buffer circuit operating as a pipeline register. A second bus for bidirectional transfer of write/read data, includes a second buffer circuit operating as a pipeline register. A first control circuit sequentially sends the address/control signals on the first bus, and a second control circuit sequentially sends/receives write/read data on the second bus.
US09412430B2	Electronic device and method for fabricating the same An electronic device including a semiconductor memory is provided. The semiconductor memory includes a first electrode, a second electrode crossing the first electrode, and a variable resistance pattern positioned in an intersection region of the first electrode and the second electrode and buried in the first electrode.
US09412429B2	Memory device with multiple voltage generators A semiconductor memory device includes multiple voltage generators. The memory device includes a first voltage generator for generating a first internal voltage based on a first power supply voltage, and a second voltage generator for generating a second internal voltage based on a second power supply voltage that is lower than the first power supply voltage. The first internal voltage is used as a driving voltage of a bit line sense amplifier in a core block including a memory cell array. The second internal voltage that is lower than the first internal voltage is used as a driving voltage of a peripheral circuit block other than the core block.
US09412422B2	Memory device and method for putting a memory cell into a state with a reduced leakage current consumption In various embodiments, a memory device includes at least one memory cell and at least one virtual supply line coupled to the at least one memory cell. The memory device is designed in such a way that a voltage potential present on the virtual supply line is altered after an active access to the memory cell by virtue of a charge stored within the memory device during the active access being re-stored in such a way that a state of the memory cell with a reduced leakage current consumption is achieved.
US09412420B2	Hermetically sealing a disk drive assembly A method for forming a seal for hermetically sealing a hard disk drive assembly. The method includes forming a solder channel within a top cover of a disk drive enclosure and disposing a solder preform on a base of the disk drive enclosure such that the solder preform aligns with the solder channel when the top cover is positioned on the base.
US09412419B2	Hard disk drive module A hard disk drive (HDD) module includes two cartridges for receiving two HDDs. Each cartridge includes a bottom tray and a top cover adjustably connected to the bottom tray. Each top cover includes a top plate located above the corresponding bottom tray. The cartridges are arranged up and down. The bottom tray of the upper cartridge is fastened to the top cover of the lower cartridge.
US09412418B2	In-box quick release access device structure An in-box quick release access device mounting structure includes a rigid holder shell including an accommodation chamber surrounded by a bottom panel and two opposite side panels thereof, a first positioning member and a first locating member located at the bottom panel and defining a mounting space therebetween, a second positioning member and a second locating member respectively located at the two side panels, and a retaining mechanism including a first retaining plate fastened to the first positioning member and adapted for detachably securing a small access device in the mounting space and a second retaining plate fastened to the second locating member and adapted for detachably securing a large access device in the accommodation chamber.
US09412417B2	Persistent group of media items for a media device Improved techniques to utilize and manage a group of media items (or media assets) on a computing device are disclosed. The group of media items can be utilized and managed at a host computer for the host computer as well as a media device (e.g., media player) that can couple to the host computer. One popular example of a group of media items is know as a playlist, which can pertain to a group of audio tracks. One aspect pertains to providing a persistent media device playlist at a host computer. Another aspect pertains to imposing capacity limits to a playlist, such as a media device playlist. Still another aspect pertains to a graphical user interface that enables a user to trade-off storage capacity of a media device between media asset storage and data storage. Yet still another aspect pertains to a graphical user interface that assists a user with selecting media items to fill a group of media items.
US09412414B2	Spatial conform operation for a media-editing application Some embodiments provide a method that receives the addition of a video clip having a first set of spatial properties to a composite video project having a second set of spatial properties. When the first set of spatial properties and the second set of spatial properties are different, the method automatically applies a spatial conform effect to the video clip to conform images of the video clip to the second set of spatial properties. The method receives input to transform images of the video clip as displayed in the composite video project. The method stores the spatial conform effect and the received transform as separate effects for the video clip.
US09412412B2	Logical block protection for tape interchange A two part process is used for modifying records to be written and retrieved from tape devices. A record is appended with a cyclic redundancy check and a string of zeros. Submitting the entire record to tape drives which are logical block protection enabled will result in no change. For drives that are not LBP enabled, the string of zeros at the end of the record is removed. In addition to determining whether a drive is LBP compliant, a determination may be made as to whether a drive is a linear tape open drive from a particular manufacturer. Linear tape open drives may behave similarly as drives which may not be enabled with logical block protection.
US09412408B2	Optical information recording medium having first and second pit row of identical reflectance In a case where (i) a reflectance calculated from a reflected light amount obtained from a longest pit (P1max) or a longest space (S1max) in a first pit row is defined as a first reflectance and (ii) a reflectance calculated from a reflected light amount obtained from a longest pit (P2max) or a longest space (S2max) in the second pit row is defined as a second reflectance, the first pit row is formed such that the first reflectance becomes substantially identical with the second reflectance.
US09412401B2	Data reader magnetic shield with CoFeNiB material A data storage device may be configured at least with a magnetic stack that contacts a magnetic shield. The magnetic stack can be disposed between first and second side shields and having at least one layer constructed of a CoFeNiB material. The magnetic shield may have a synthetic antiferromagnet with a non-magnetic layer disposed between first and second ferromagnetic layers.
US09412400B2	Tunnel magnetoresistance read head with narrow shield-to-shield spacing A tunnel magnetoresistance (TMR) read sensor having a tabbed AFM layer and an extended pinned layer and methods for making the same are provided. The TMR read sensor has an AFM layer recessed from the air bearing surface, providing a reduced shield-to-shield distance.
US09412399B2	Underlayer for reference layer of polycrystalline CPP GMR sensor stack Embodiments disclosed herein generally relate to a magnetic head having an amorphous ferromagnetic reference layer. The ferromagnetic reference layer may have amorphous structure as a result of an amorphous ferromagnetic underlayer that the ferromagnetic reference layer is deposited thereon. The amorphous ferromagnetic reference layer enhances magnetoresistance, leading to an improved magnetic head.
US09412398B2	Shield with uniform magnetic properties for a perpendicular magnetic recording head Depositing a seed layer for a high-moment shield onto a write pole may have a deleterious effect on the magnetic response of the write pole. Instead, an amorphous separation layer may be deposited between the write pole and the seed layer. In one embodiment, the seed layer is formed directly on the amorphous layer. In addition to separating the seed layer from the write pole, the amorphous separation layer permits the seed layer to dictate the crystallographic orientation of the shield which is subsequently deposited on the magnetic head. That is, the amorphous layer provides a substrate that allows the seed layer to have a crystalline structure independent of the layers that were deposited previously. The amorphous separation layer may comprise an amorphous metal—e.g., NiNb or NiTa—or an insulative material—e.g., alumina or silicon dioxide.
US09412397B1	Method of forming a magnetic write head A magnetic write head has a plated coil with narrow pitch and is suitable for writing at high frequencies on magnetic media with high coercivity. The narrow pitch is obtained without such disadvantages as overplating that has adversely affected prior art attempts to produce such narrow pitches. The process that produces the magnetic write head is characterized by an RIE plasma etch using O2/N2 to etch plating trenches into a baked layer of photoresist with the ratio of gases being 5/45 sccm so that a dilute O2 concentration does not create unwanted side etching of the plating trenches. In addition, a Cu seed layer is coated with an insulating layer of Al2O3 which redeposits on the trench sidewalls to inhibit redeposition of any Cu from the seed layer and prevent outward growth of the plated Cu that would result in overplating.
US09412396B2	Voice activity detection/silence suppression system A Voice Activity Detection/Silence Suppression (VAD/SS) system is connected to a channel of a transmission pipe. The channel provides a pathway for the transmission of energy. A method for operating a VAD/SS system includes detecting the energy on the channel, and activating or suppressing activation of the VAD/SS system depending upon the nature of the energy detected on the channel.
US09412390B1	Automatic estimation of latency for synchronization of recordings in vocal capture applications Latency on different devices (e.g., devices of differing brand, model, vintage, etc.) can vary significantly and tens of milliseconds can affect human perception of lagging and leading components of a performance. As a result, use of a uniform latency estimate across a wide variety of devices is unlikely to provide good results, and hand-estimating round-trip latency across a wide variety of devices is costly and would constantly need to be updated for new devices. Instead, a system has been developed for automatically estimating latency through audio subsystems using feedback recording and analysis of recorded audio.
US09412386B2	Orchestrated encoding and decoding Orchestrated encoding schemes facilitate encoding and decoding of data in content signals at several points in the distribution path of content items. Orchestrated encoding adheres to a set of encoding rules that enables multiple watermarks and corresponding applications to co-exist, avoids collisions among watermarks, and simplifies metadata and routing database infrastructure.
US09412385B2	Performing spatial masking with respect to spherical harmonic coefficients In general, techniques are described by which to perform spatial masking with respect to spherical harmonic coefficients. As one example, an audio encoding device comprising a processor may perform various aspects of the techniques. The processor may be configured to perform spatial analysis based on the spherical harmonic coefficients describing a three-dimensional sound field to identify a spatial masking threshold. The processor may further be configured to render the multi-channel audio data from the plurality of spherical harmonic coefficients, and compress the multi-channel audio data based on the identified spatial masking threshold to generate a bitstream.
US09412383B1	High frequency regeneration of an audio signal by copying in a circular manner A method for generating a reconstructed audio signal having a baseband portion and a highband portion is disclosed. The method includes deformatting an encoded audio signal into a first part and a second part and obtaining a decoded baseband audio signal by decoding the first part. The method also includes extracting, from the second part, a noise parameter and an estimated spectral envelope of the highband portion and obtaining a plurality of subband signals by filtering the decoded baseband audio signal. The method further includes generating a high-frequency reconstructed signal by copying in a circular manner a number of consecutive subband signals of the plurality of subband signals and obtaining an envelope adjusted high-frequency signal by adjusting, based on the estimated spectral envelope of the highband portion, a spectral envelope of the high-frequency reconstructed signal. The method also includes generating a noise component based on the noise parameter and obtaining a combined high-frequency signal by adding the noise component to the envelope adjusted high-frequency signal. Finally, the method includes obtaining a time-domain reconstructed audio signal by combining the decoded baseband audio signal and the combined high-frequency signal. The method may be implemented by an audio decoding device comprising one or more hardware elements.
US09412378B2	Device and method for supplying a reference audio signal to an acoustic processing unit Equipment includes a first interface intended to be connected to a sound reproduction device and at least one second interface intended to be connected to at least one microphone, an acoustic processing unit adapted for delivering an audio signal filtered by attenuation or suppression of a reference audio signal from an audio signal received via the second interface. In an initialisation phase, the equipment determines a propagation latency; configures a buffer with a reading-triggering threshold defined according to the determined propagation latency. In a nominal operating phase, the equipment transmits a third audio signal via the first interface, the third audio signal being the reference signal after passing through the buffer.
US09412372B2	Method and system for audio-video integration A method of dictation is described which, after transcription, integrates video into text at locations designated by the user. A user collects audio and visual information using an application that has been installed on the user's mobile device. The user designates, using the application, the desired location of the video files within the audio file. Both the audio and video information are uploaded to a transcription provider. The transcription provider uses transcription software to transcribe the audio files into text, the transcription software being able to identify the transcriptionist as to the location within the audio file each video is to be inserted. The transcribed document with integrated audio and video is then delivered back to the user.
US09412371B2	Visualization interface of continuous waveform multi-speaker identification A method implemented in a computer infrastructure having computer executable code having programming instructions tangibly embodied on a computer readable storage medium. The programming instructions are operable to receive a current waveform of a communication between a plurality of participants. Additionally, the programming instructions are operable to create a voiceprint from the current waveform if the current waveform is of a human voice. Furthermore, the programming instructions are operable to determine one of whether a match exists between the voiceprint and one library waveform of one or more library waveforms, whether a correlation exists between the voiceprint and a number of library waveforms of the one or more library waveforms and whether the voiceprint is unique. Additionally, the programming instructions are operable to transcribe the current waveform into text and provide a match indication display (MID) indicating an association between the current waveform and the one or more library waveforms based on the determining.
US09412370B2	Method and system for dynamic creation of contexts A method and a system for a speech recognition system, comprising an electronic speech-based document is associated with a document template and comprises one or more sections of text recognized or transcribed from sections of speech. The sections of speech are transcribed by the speech recognition system into corresponding sections of text of the electronic speech based document. The method includes the steps of dynamically creating sub contexts and associating the sub context to sections of text of the document template.
US09412364B2	Enhanced accuracy for speech recognition grammars Disclosed herein are methods and systems for recognizing speech. A method embodiment comprises comparing received speech with a precompiled grammar based on a database and if the received speech matches data in the precompiled grammar then returning a result based on the matched data. If the received speech does not match data in the precompiled grammar, then dynamically compiling a new grammar based only on new data added to the database after the compiling of the precompiled grammar. The database may comprise a directory of names.
US09412360B2	Predicting and learning carrier phrases for speech input Predicting and learning users' intended actions on an electronic device based on free-form speech input. Users' actions can be monitored to develop a list of carrier phrases having one or more actions that correspond to the carrier phrases. A user can speak a command into a device to initiate an action. The spoken command can be parsed and compared to a list of carrier phrases. If the spoken command matches one of the known carrier phrases, the corresponding action(s) can be presented to the user for selection. If the spoken command does not match one of the known carrier phrases, search results (e.g., Internet search results) corresponding to the spoken command can be presented to the user. The actions of the user in response to the presented action(s) and/or the search results can be monitored to update the list of carrier phrases.
US09412357B2	Mapping ultrasound transducers Ultrasound transducers may be mapped by varying a focus-affecting parameter and adjusting the parameter so as to improve focus quality. In some embodiments, mapping involves successively varying the phase of one transducer element, or group of elements, with respect to a constant phase of the other transducer elements, and determining the phase at which a tissue displacement in the ultrasound focus is maximized.
US09412353B2	Method for cancelling noise and electronic device thereof An apparatus and method for cancelling a noise of an audio signal in an electronic device is provided. The method includes recording audio signals using a plurality of microphones and changing an audio signal which is introduced into a first microphone during a noise generation interval to an audio signal which is introduced into a second microphone, wherein the first microphone includes one or more microphones which are influenced by the noise among the plurality of microphones.
US09412352B2	Recording audio in association with display content In an ensemble performance, performance lesson or the like, a musical score (display content) is displayed and input audio is recorded. The input audio includes notes, comments or the like uttered by a human player or an instructor. During recording of the input audio is received a user input designating a desired time position on the musical score displayed on the display device. A recording time of the input audio based on a time point at which the user input has been received and the time position on the musical score designated by the user input are stored into a storage device in association with each other. An icon is displayed in association with the time position on the musical score designated by the user input. Once the icon is selected, voice based on the recording time recorded in association with the icon is reproduced to sound the comments, etc.
US09412349B2	Intelligent keyboard interface for virtual musical instrument A user interface for a virtual musical instrument presents a number of chord touch regions, each corresponding to a chord of a diatonic key. Within each chord region a number of touch zones are provided, including treble clef zones and bass clef zones. Each treble clef touch zone within a region will sound a different chord voicing. Each bass clef touch zone will sound a bass note of the chord. Other user interactions can modify or mute the chords, and vary the bass notes being played together with the chords. A set of related chords and/or a set of rhythmic patterns can be generated based on a selected instrument and a selected style of music.
US09412345B2	Adjustable zero fret and method of use on a stringed instrument An apparatus and method of varying the tonal aspects of a string instrument such as an acoustic or electric guitar is disclosed. The apparatus and method employing a unique zero fret assembly. The zero fret assembly includes an upper portion and a lower portion. The lower portion is configured to connect with a fret board, headstock or body of an instrument. The upper portion is configured to engage the lower portion. The upper portion is also configured to receive and support an instrument's strings. The upper portion is selectively movable relative to the lower portion by an operator to change the tonal nature of the instrument.
US09412337B2	Projection displays A locally dimmed display has a spatial light modulator illuminated by a light source. The spatial light modulator is illuminated with a low resolution version of a desired image. The illumination may comprise a series of lighting elements that vary smoothly from one element to another at the spatial light modulator.
US09412336B2	Dynamic backlight control for spatially independent display regions Embodiments of the disclosure describe a tileable display panel including a screen layer to display a unified image, an illumination layer including a two-dimensional array of lamps, and a display layer disposed between the screen layer and illumination layer. The display layer includes a plurality of pixelets each positioned to be illuminated by a corresponding lamp from the illumination layer to project a magnified image sub-portion corresponding to a received subset. The magnified image sub-portions collectively blend together to form the unified image displayed on the screen layer. Embodiments of the disclosure further include illumination layer control logic to determine a brightness value of each of the received subsets of pixel data, and adjust an illumination setting to reduce or increase an illumination output of a lamp in the illumination layer based, at least on part, on the brightness values of the corresponding subset of pixel data.
US09412329B2	Methods and apparatuses for controlling display devices Methods and apparatuses for per display scale factors within a multiple display system are described.In one aspect of the invention, a machine implemented method includes setting a scale factor for each window buffer equal to an extreme scale factor among a plurality of displays. The method further includes transferring data from each window buffer into a corresponding frame buffer for one of the plurality of displays by setting a scale factor of each frame buffer equal to the scale factor of the corresponding display.In one example according to this aspect, the method further includes displaying on a high resolution display and a low resolution display an image, stored in the corresponding frame buffers, with substantially the same physical size even though the displays have different scale factors and pixel densities. Also, the extreme scale factor is one of the largest scale factor or the smallest scale factor.
US09412321B2	Display device to apply compensation data and driving method thereof A display device includes a display panel, a data driver, a gate driver, and a signal controller. The display panel includes a pixel connected to the gate and data lines, and the pixel includes a liquid crystal capacitor. The signal controller obtains compensation data and normal data based on input data for a still image. The signal controller apples the compensation data and normal data to the pixel during different periods of a frame. The compensation data has a value that reduces a difference of operation characteristics of liquid crystal molecules in the liquid crystal capacitor when a data voltage for the display panel changes between different polarities.
US09412319B2	Driving method for liquid crystal device, liquid crystal device, and electronic device A driving method for a liquid crystal device, which has a first electrode, a second electrode, and a third electrode for trapping ions, includes applying AC signals having the same frequency but whose phases in an amount of time corresponding to a single cycle are shifted relative to each other to the first electrode, the second electrode, and the third electrode, respectively, so that the distribution of an electrical field produced between the first electrode, the second electrode, and the third electrode is scrolled from the first electrode to the third electrode over time.
US09412316B2	Method, device and system of displaying a more-than-three primary color image Embodiments of the invention include a method, device and/or system for displaying a more than three primary color (RGB) image. The device (100,200) may include, for example, a driver control module (218) to controllably activate one or more drivers (206,210) of an array of sub-pixel elements of at least four primary colors based on image data representing pixels of the color image in terms of at least three primary colors (RGB). Other embodiments are described and claimed.
US09412313B2	Display apparatus and method of driving the same A display apparatus includes a display panel including n×m array of pixels and which sequentially drives the pixels from pixels in a first row to pixels in an n-th row, a panel driving circuit which sequentially applies first, second, third or fourth image data to the display panel, a backlight unit including a first light source disposed adjacent to the pixels in the first row and a second light source disposed adjacent to the pixels in the n-th row, and a backlight control circuit which divides each of first and second time periods into first, second, third and fourth blinking time periods, and applies a control signal to the backlight unit, where the first time period corresponds to two frames during which the first and second image data are applied, and the second time period corresponds to two frames during which the third and fourth image data are applied.
US09412304B2	Display device and method for driving the same A special mode processor drives a display panel to display an image. When the display panel is configured to operate in a special operation mode, the special operation mode processor determines a pixel block size for blocking the plurality of pixels into a plurality of pixel blocks and determines a first set of on-pixels and a first set of off-pixels. The first set of on-pixels is initially turned on and the first set of off-pixels is initially turned off. A drive history representative value is generated for the first group of pixels that represents a drive time and drive characteristic for the first group of pixels. The drive history representative value is compared with a threshold value. Responsive to the drive history representative value exceeding the threshold value, a second set of on-pixels and a second set of off-pixels are turned on and off respectively.
US09412302B2	Pixel driving circuit, driving method, array substrate and display apparatus A pixel driving circuit, comprises: a line (Data), a first scanning line (Scan1), a second scanning line (Scan2), an enabling control line (Em), a power supply line (S), a light emitting device (D), a driving transistor (DTFT), a storage capacitor (C), a resetting unit (1), a data writing unit (2) and a light emitting control unit (3), and further discloses a pixel driving method, an array substrate and a display apparatus. The pixel driving circuit of the present disclosure solves the problem of non-uniformity of the threshold voltage caused by the manufacturing process and long-time operation of the pixel point driving transistor by means of compensating, so that the current flowing through each pixel point light emitting device is not affected by the threshold voltage, thereby finally ensuring the uniformity of the image display.
US09412301B2	Organic light-emitting display apparatus and pixel An organic light-emitting display apparatus including emitting pixels including drivers for displaying gradation by making a light-emitting device selectively emit light according to a logic level of a data signal transmitted to each of the sub-fields forming a frame, and dummy pixels coupled to a repair line that is coupled to a light-emitting device of a first emitting pixel from among the plurality of the emitting pixels, wherein the dummy pixels include a first dummy driver for making the light-emitting device of the first emitting pixel emit light by charging the repair line when a data signal having a first logic level is transmitted, a second dummy driver for discharging the repair line when a data signal having a second logic level opposite to the first logic level is transmitted, and a boost capacitor coupled to the repair line and for controlling a charging/discharging speed of the repair line.
US09412298B2	Latch circuit of display apparatus, display apparatus, and electronic equipment A latch circuit for outputting data for M pixels present in one line on a display panel in a time-division manner for each pixel, in order to drive each pixel from among the M pixels based on N-bit data, includes M×N 1-bit latch circuits in which N 1-bit latch circuits are arranged in the column direction Y and M 1-bit latch circuits are arranged in the row direction X, each circuit latching 1-bit data. Each 1-bit latch circuit includes a data latch unit circuit that latches data corresponding to any one bit of the N bits at different timings for each row, a line latch unit circuit that simultaneously latches data from the data latch unit circuit in each row, and an output enable element that outputs data from the line latch unit circuit based on an enable signal for selecting any one column.
US09412295B2	Pixel circuit and driving method thereof A pixel circuit including a light emitting element outputting a gray scale based on a current supplied thereto, a first transistor configured to control an amount of current supplied to the light emitting element based on a gray scale data voltage supplied to a gate electrode of the first transistor, a second transistor connected between the gate electrode of the first transistor and an initialization voltage, a third transistor connected between the gate electrode of the first transistor and a first terminal of the first transistor; a fourth transistor connected between the first terminal of the first transistor and the light emitting element, and a fifth transistor connected between a second terminal of the first transistor and a data line. The data line is selectively supplied with the gray scale data voltage and a power supply voltage for light emitting of the light emitting element to the fifth transistor.
US09412289B2	Display unit, drive circuit, drive method, and electronic apparatus A display unit that drives pixels field sequentially includes pixel circuits disposed in a matrix form of rows and columns and a drive control section that causes the pixel circuits to display image frames of input image data such that a single frame of the image frames is displayed in two parts as a first sub-frame and as a second sub-frame. The first and second sub-frames are displayed field sequentially by different portions of the pixel circuits. The first sub-frame is displayed by a first portion of the pixel circuits that are located in a checked pattern, while the second sub-frame is displayed by the remaining pixel circuits.
US09412288B2	Tailgate cover A tailgate cover includes at least one pocket to securely fit over a tailgate. In some embodiments, the tailgate cover includes two or three pockets. The tailgate cover is made of stretchable material such as a stretchable fabric which enables the cover to be stretched securely over the tailgate. To further secure the tailgate cover over the tailgate, any coupling device is able to be used. The tailgate cover is able to include any graphic and/or text.
US09412286B2	Fastening arrangement for an electronic price label A fastening arrangement for an electronic price label includes a holder, into which the electronic price label is placed. The holder can in turn be fastened onto an installation point, such as onto the edge of a shelf. In the fastening arrangement the electronic price label is locked in relation to the holder with a fastening member, which extends through the wall of the holder from the first side of the wall to the second side of the wall and onwards into the electronic price label.
US09412284B2	Contour encryption and decryption A method of encrypting information includes converting an information sequence represented as a strings of bits into a curvilinear coding system, where each element of the curvilinear coding system corresponds to a sub-sequence of successive same-valued bits, converting said curvilinear coding system into a at least one closed curve, and embedding said at least one closed curve in a 2-dimensional pattern. A method for decrypting information includes extracting at least one closed curve from a digitized 2-dimensional pattern, and converting the at least one closed curve into an information sequence represented as a string of bits.
US09412283B2	System, design and process for easy to use credentials management for online accounts using out-of-band authentication The invention provides an easy to use credential management mechanism for multi-factor out-of-band multi-channel authentication process to protect a large number of documents without the need to remember all the document passwords. When opened, the secure document application generates a multi-dimensional code. The user scans the multi-dimensional code and validates the secure document application and triggers an out-of-band outbound mechanism. The portable mobile device invokes the authentication server to get authenticated. The authentication server authenticates the user based on shared secret key and is automatically allowed access to the secure document. The process of the invention includes an authentication server, a secure document application to generate an authentication vehicle or an embodiment (i.e. multi-dimensional bar code) and handle incoming requests, secret keys and a portable communication device with a smartphone application.
US09412277B2	Vehicle cut-in strategy A vehicle system includes a first sensor configured to output a first signal and a second sensor configured to output a second signal. The first and second signals represent movement of a potential cut-in vehicle. The vehicle system further includes a processing device programmed to compare the movement of the potential cut-in vehicle to at least one threshold. The processing device selects the potential cut-in vehicle as an in-path vehicle if the movement exceeds the at least one threshold.
US09412274B2	System and method for providing a distance to target for remote keyless entry A method and system for providing a distance to target vehicle finder function for remote keyless entry is provided. The method and system include enabling a vehicle finder function from a portable device and transmitting a low power signal from the portable device to a vehicle onboard receiver. The method and system further includes determining whether the vehicle onboard receiver receives the low power signal from the portable device and enabling a low power vehicle finding response. The method and system also include transmitting a high power signal from the portable device to the vehicle when it is determined that the vehicle onboard receiver does not receive the low power signal from the portable device, and enabling a high power vehicle finding response when it is determined that the vehicle onboard receiver receives the high power signal from the portable device.
US09412270B2	Wireless vehicle detection system and associated methods having enhanced response time Embodiments of the invention include a wireless vehicle detection systems and associated methods with extended range and battery life. The wireless vehicle detection system can include a plurality of sensor pods in communication with an access point without repeaters. Embodiments of the sensor pod can include a vehicle detector controller adapted to determine the presence of vehicles and a communication controller connected to the vehicle detector and adapted to transmit data 300 feet or more to an access point, which in turns communicates with the base station. To extend the battery life of the sensor pod, the sensor pod can be adapted to detect received communication signal strength and adjust transmitting power based upon the strength to thereby conserve power. Embodiments of the sensor pod can also include a battery connected in parallel to an HLC capacitor to further extend the life of the battery.
US09412262B2	Wireless two-way communication protocol for automated furniture accessory integration A system and method for integrating furniture accessories with automated furniture items is provided. In embodiments, a communication protocol enables a remote device to control an automated furniture accessory coupled to a control component of an automated furniture item. Items of identifying information are provided to a control component based on coupling the automated furniture accessory to the CAN bus of the control component. According to the communication protocol, one or more packets of information are provided to the remote device using a wireless communication device of the control component. The remote device may then be used to control features of the automated furniture accessory, based on wireless communication with the control component. In some embodiments, the firmware of the remote device may be updated to enable the control component to be coupled to updated automated furniture accessories, and enable the remote device to control such accessories.
US09412258B2	Systems and methods for multi-criteria alarming Systems and methods for using multi-criteria state machines to manage alarming states and pre-alarming states of a hazard detection system are described herein. The multi-criteria state machines can include one or more sensor state machines that can control the alarming states and one or more system state machines that can control the pre-alarming states. Each state machine can transition among any one of its states based on sensor data values, hush events, and transition conditions. The transition conditions can define how a state machine transitions from one state to another. The hazard detection system can use a dual processor arrangement to execute the multi-criteria state machines according to various embodiments. The dual processor arrangement can enable the hazard detection system to manage the alarming and pre-alarming states in a manner that promotes minimal power usage while simultaneously promoting reliability in hazard detection and alarming functionality.
US09412257B2	Electronic cassette management system, method of operating electronic cassette management system, and electronic cassette management device A first data taking section takes first detection results from a first wireless tag reader which detects the come and go of an electronic cassette into and out of a first service zone, and also takes second detection results from a second wireless tag reader which detects the come and go of an electronic cassette into and out of a second service zone. A first alert controller drives a first speaker to start an alert when the first alert controller determines on the basis of the first detection results that the electronic cassette has gone out the first service zone. After the start of alerting, the first alert controller stops driving the first speaker to interrupt the alert when first alert controller determines that the electronic cassette has come in either the first service zone or the second service zone.
US09412255B1	Remote monitoring of activity triggered sensors and a customized updating application Monitoring a particular home or place of business for activity may provide a remote subscriber with updated information regarding feedback from sensors at the remote location. One example method of operation may include receiving sensor data from one or more sensors that have been activated at the remote location, identifying a subscriber account associated with the sensor data, matching the sensor data with a predefined sensor identifier stored in the subscriber account, and generating a notification to include the predefined sensor identifier and a time reference indicator associated with a time the sensor data was activated.
US09412254B1	Downed item detector A device for automatically detecting a change in position beyond a reference position is provided. Preferably the change in position results from a change in height of an object. In the preferred embodiment inclinometers detect a change in position resulting from an electric line or other suspended object that has descended from its reference position.
US09412250B2	Alert method and alert system thereof An alert method and an alert system thereof. The alert method includes: detecting, by a turn detector installed on a steering wheel, a first turn and a second turn of the steering wheel in a predetermined period; generating, by a controller, a first alert signal based on the first and second turns; and when receiving the first alert signal, generating, by an alert device, a first alert message.
US09412248B1	Security, monitoring and automation controller access and use of legacy security control panel information A system, method and apparatus for controller functionality for each of security, monitoring and automation, as well as a bidirectional Internet gateway, is provided. Such functionality is provided by virtue of a configurable architecture that enables a user to adapt the system for the user's specific needs. In addition, functionality for gathering configuration information from a previously-installed security system and using that information in a subsequent takeover of that security system is provided.
US09412246B2	Systems and methods for intra-zone detection Systems (100) and methods (1800) for determining where an object or person is located in an EAS detection zone. The methods involve: simultaneously emitting a first signal from a first emitter and a second signal from a second emitter; concurrently detecting the first and second signals during a first period of time by each of a first detector and a second detector; and determining where the object or person is within the EAS detection zone based on a pattern of a signal output from at least one of the first and second detectors which reflects that at least one of the first and second signals is blocked by the object or person during at least one of a second period of time and a third period of time in which the object or person is traveling through the EAS detection zone.
US09412245B2	System and method for visualization of history of events using BIM model A method and apparatus are provided, wherein the method includes the steps of a building information model (BIM) of a security system providing a three-dimensional view of a secured area of the security system, including the physical location of any sensors of the security system, an input device of the security system receiving from a user a starting time and ending time of a time interval of interest, and a processor of the security system displaying the three-dimensional view of the secured area, including a time scale showing the starting time on one end of the time scale and the ending time at an opposing end of the time scale and a respective popup of details for each corresponding sensor of at least some sensors of the security system activated during the time interval of interest, each respective popup graphically connected to the physical location of the corresponding sensor within the three dimensional view.
US09412244B2	Smart sensor line alarm system Embodiments of the present invention are directed to systems and methods for monitoring a status of a plurality of a merchandise display devices for displaying items of merchandise at respective display positions. For example, the method includes monitoring for a change in a preselected characteristic of a circuit defined by an electrical connection between the security devices and a plurality of nodes and between the nodes and an alarm unit. The method also includes determining whether an item of merchandise has been added to or removed from a respective display position based on a change in the preselected characteristic.
US09412243B2	Portable security system A portable alarm system designed for unoccupied unsecured locations, such as construction sites, machinery, campsites and the like. The alarm system defines a continuous monitoring line about the perimeter of the unsecured location using a plurality of wireless sensors attached to a flexible non-stretchable tape suspended between to vertical poles. The system has motion-sensing/detecting capabilities such that any movement of a housing where the microprocessor of the system is located generates audible/visual alarm. Each of the wireless sensors has a magnet and a transmitter positionable within a predetermined distance from the magnet. If the intruder tampers with the tape and increases the distance between the magnet the transmitter, the alarm is activated as well.
US09412241B2	Slot machine game and system with improved jackpot feature Certain embodiments provide a method and system for awarding a progressive prize. The system includes a bank of gaming machines accepting different bets per play as selected by a player. A random number is selected from a predetermined fixed range of numbers that does not change during play of a gaming machine. The player is allotted one or more numbers for each credit bet. The allotted numbers represent a subset of the predetermined fixed range of numbers. A feature game is triggered for the progressive prize based on a numerical comparison between the selected random number and the number(s) allotted to the player. Certain embodiments provide a trigger condition for a feature outcome based on an event having a probability related to credits bet per game at a gaming machine. A probability of success in the feature game may be higher than a probability of success in the base game.
US09412238B2	Method and apparatus for increasing potential payout opportunities in card games Systems, apparatuses and methods for increasing potential payout opportunities using multiple card indicia representing multiple cards. One embodiment involves determining whether any one or more of a plurality of cards of a poker game having multiple poker hands are to be randomly provided with multiple card indicia representing multiple cards, presenting the plurality of cards of the poker hands, including the one or more of the plurality of cards determined to be randomly provided with multiple card indicia, and identifying a plurality of resulting hands for each of the multiple poker hands that include a multiple card indicia, where each of the plurality of resulting hands includes a different subset of a total of the indicia of the other cards in the respective poker hand and any cards provided with multiple card indicia.
US09412236B2	Player initiated multi-player games Some embodiments include a computer-implemented method for enabling a player to configure and initiate multiplayer wagering games. The computer-implemented method can include presenting, on a display device of a wagering game machine, a graphical user interface including social contact icons representing social contacts associated with the player, and a multiplayer wagering game icon associated with a multiplayer wagering game. The method can also include detecting input indicating selection of the multiplayer wagering game icon and the social contact icons. The method can also include transmitting, to the social contacts via a network, invitations to participate in the multiplayer wagering game. The method can also include detecting acceptance of the invitations from at least one of the social contacts, and conducting the multiplayer wagering game involving the player and the at least one of the social contacts.
US09412232B2	Gaming system and method for offering simultaneous play of multiple games Gaming apparatus and methods of conducting a wagering game of chance. A gaming machine is disclosed which is configured for mutually concurrent play of a plurality of games of chance on a single display screen. A method of conducting a wagering activity includes providing a player with a plurality of differing games of chance, at least some of which are mutually concurrently playable on a single screen display of a gaming device and enabling mutually concurrent play of the plurality of differing games of chance on the single screen display. Various other gaming machine configurations and methods of play related to multiple differing games of chance on a single display screen are also disclosed herein. Networked gaming machines are also disclosed.
US09412230B2	Game performance determination by incremental revenue Embodiments of the present invention are directed to methods of determining the performance of a gaming device by analyzing the incremental revenue generated by the gaming device. This method may include identifying an analysis period, recording game performance data for a set of gaming devices and a test gaming device during the analysis period, and comparing the recorded data to historical gaming data for the set of gaming devices. Some examples of this method may also include developing parameters for the analysis period and using those developed parameters to normalize the recorded game data for the analysis period prior to comparing the recorded data to the historical gaming data.
US09412228B2	Handheld wagering game system and methods for conducting wagering games thereupon A gaming system for conducting a wagering game includes a handheld gaming machine configured to play at least one game and a controller. The controller is configured to base eligibility of the handheld gaming machine for a game-related feature at least upon a location of the handheld gaming machine and/or a proximity of the handheld gaming machine to an external device.
US09412224B2	Multi-player gaming machine with lever-actuated spinning wheel A gaming machine of the present invention stores a bet area on which a bet is placed through a gaming terminal and a game value placed as the bet, determines a resulting symbol from a plurality of symbols, rotates the wheel based on an operation of the lever in one of the plurality of gaming terminals, whose lever has been activated, stops the rotation of the wheel so that the pointer points at a symbol arrangement area with the resulting symbol, and awards a payout based on the resulting symbol and the odds set for the bet area in which the bet is placed through the gaming terminal.
US09412223B2	Operation unit and game machine An operation unit has a touch panel that senses a press, and a button plate disposed above the touch panel, and having a plurality of push buttons, each of which protrudes on a side opposite to a side where the touch panel is disposed. The button plate is provided along a surface of the touch panel, and has a base section having apertures at respective positions where the plurality of push buttons are formed, top surface sections, each of which constitutes corresponding one of the plurality of push buttons and serves as an operation surface, and bending deformable sections, each of which connects, in a freely elastically deformable manner, a peripheral section of corresponding one of the top surface sections and an edge of corresponding one of the apertures formed in the base section.
US09412221B2	Gaming machine A gaming machine 300 includes an input device, a lower image display panel 141, and a motherboard 70. The motherboard 70 executes processes of: (a1) displaying a 29-option selection screen showing 29-option bonuses including a door 2 options on the lower image display panel 141; (a2) when the selection of the door 2 options is received by a switch, selectively executing a 2-option game of executing a predetermined game and awarding a character to a player based on the result of the predetermined game or a 1-option game of immediately providing the game character to the player, and (a3) if the 1-option game is executed in (a2) when the selection of the door 2 options is received by the switch, displaying an indication image along with the 29-option selection screen.
US09412220B2	Gaming machine When the game result of a base game in which symbols 501 are rearranged on a lower image display panel 141 is bonus winning, the execution of a first bonus game in which a selection game is executable for a predetermined number of times is allowed, one of a predetermined number of options associated with selectable game results is selected for each time of the selection game in the first bonus game, and a second bonus game is executed after the end of the first bonus game when in the first bonus game the selection game is executed for the predetermined number of times.
US09412217B2	Medication dispensing apparatus having conveyed carriers A medication dispensing cabinet and an associated medication dispensing drawer assembly are provided in order to controllably convey and dispense medication. A medication dispensing cabinet may include a cabinet body, a plurality of drawers disposed within and configured for slidable extension relative to the cabinet body, a conveyor belt disposed within a first drawer and a plurality of bins operably connected to the conveyor belt and configured to receive medication for movement with the conveyor belt. Each bin may includes an openable support surface which, in one embodiment, is biased to open. In addition, the first drawer may define an opening and the conveyor belt may be configured to move a respective bin into alignment with the opening. The support surface of the respective bin may then be permitted to open and the medication carried by the respective bin may be dispensed through the opening.
US09412215B2	Interchangeable and changeable slider blade dispensing apparatus with adjustable saw tooth trough tray This invention relates to the re-design of the original Ideal Dispensing apparatus, U.S. Pat. No. 2,174,712, (1939) and U.S. Pat. No. 2,637,612, (1953). Stated patent design was a single serving, slideable type container dispensing apparatus, manually operated horizontally through slideable guideways that were permanently welded fixed, one size, guideways that included a simple pan/tray for containers, cans and cartons. The new design gives the all-around versatility with the new all metal individual interchangeable and adjustable guideway blades and a saw tooth trough tray that accommodates majority of sizes, and shapes cans, cartons and beverage containers to include neck-less, and tapered designs in todays marketplace. This said new apparatus with new trough tray magnifies a novel and unobvious design combining and optimizing the utilization of space and versatility, with ease of installation and adjustment. This is optimal for changing, adding to the guideway storage and dispensing of said containers regardless of container design.
US09412214B2	Illumination apparatus, image sensor unit, and paper sheet distinguishing apparatus An illumination apparatus includes: a light source that emits light at a plurality of wavelengths; and a rod-like light guide that shapes light emitted by the light source into a line, wherein the light guide is made of a material including a region in which transmittance of wavelengths is not constant, the light source is arranged at one end of the light guide in a longitudinal direction, the light source includes a wavelength of a region in which transmittance of the light guide is not constant, and a reflection surface including reflection member having reflectance differences for the light at a plurality of wavelengths is formed at the other end of the light guide in the longitudinal direction.
US09412213B2	RFID reader Embodiments of the invention relate to the field of RFID (radio frequency identification). Some particularly preferred embodiments relate to a high-Q, so-called “full duplex” (FDX) RFID Reader. An RFID tag reader, the reader comprising: an electromagnetic (EM) field generator for generating an electromagnetic (EM) field for modulation by said tag, said modulation comprising modulated load of said EM field by said tag; a detector system responsive to fluctuations in strength of said EM field at said reader; a negative feedback system responsive to said detector system to provide a control signal for said EM field generator for controlling said EM field generator to reduce said detected fluctuations; and a demodulator responsive to said control of said EM field to demodulate said EM field modulation by said tag.
US09412211B2	System and method for on-vehicle dynamic accident recreation using accident data recording A system and a method for recreating an operation of a crashed vehicle during and/or before the accident. An accident data recorder collects vehicle operation data related to the operation of the crashed vehicle prior to and/or during the accident. A processor may analyze the prior vehicle operation data that may include prior acceleration input data, prior braking input data, and/or prior steering input data and may output vehicle control data to at least one electronic controller based on the prior vehicle operation data. The at least one electronic controller automatically operates the test vehicle on a test surface to recreate an operation of the crashed vehicle during and/or before the accident. At least one electronic controller unit automatically and accurately recreates a response of the crashed vehicle to the prior acceleration input, the prior steering input, and the prior braking input.
US09412207B2	Electronic device, time setting method, time setting system and program An electronic device includes a communication unit that performs communication with an external apparatus; a timekeeping unit that performs timekeeping of time; and a control unit, after completion of a connection with the external apparatus using the communication unit, updates time of the timekeeping unit using time information when being in a state where time can be set by obtaining the time information from the external apparatus.
US09412206B2	Systems and methods for the manipulation of captured light field image data Systems and methods for the manipulation of captured light fields and captured light field image data in accordance with embodiments of the invention are disclosed. In one embodiment of the invention, a system for manipulating captured light field image data includes a processor, a display, a user input device, and a memory, wherein a depth map includes depth information for one or more pixels in the image data, and wherein an image manipulation application configures the processor to display a first synthesized image, receive user input data identifying a region within the first synthesized image, determine boundary data for the identified region using the depth map, receive user input data identifying at least one action, and perform the received action using the boundary data and the captured light field image data.
US09412204B2	Virtual image generating apparatus, virtual image generating method, and recording medium storing virtual image generating program An image generation apparatus, system, and method that include an image recording unit that records at least one image containing photography position information corresponding to a photography position of the image, an input unit for selecting a selected image from the at least one image recorded in the image recording unit, a map-image unit that acquires at least one map image corresponding to the photography position information of the selected image, a direction detection unit that detects a photography direction of the selected image from the photography position information and acquires at least one surrounding map image viewable from the photography position when the selected image was recorded, and a virtual image generation unit that generates at least one virtual image of a scene viewable from the photography position when the selected image was recorded based on the photography position information and the at least one surrounding map image.
US09412202B2	Client terminal, server, and medium for providing a view from an indicated position There is provided a client terminal including a determination unit configured to determine whether an overhead view image is associated with a position indicated by a user, and a display control unit configured to perform control so that the overhead view image is displayed on a display unit in accordance with a determination result obtained by the determination unit.
US09412196B2	Regional compositing A method for regional compositing includes compositing a plurality of video planes and at least one graphics plane. Graphics elements of the at least one graphics plane may be stored into a single graphics plane. A rectangle may be associated to one or more graphics elements of the single graphics plane. A Z-order of the plurality of video planes and the at least one graphics plane may be determined according to rectangular regions defined by rectangles associated with graphics elements of the single graphics plane. A pixel-by-pixel Z-order may be performed based on the determined Z-order of the plurality of video planes and the at least one graphics plane.
US09412194B2	Method for sub-pixel texture mapping and filtering A method for sub-pixel texture mapping and filtering is provided. The method includes the steps of: dividing an area on a source image into a red (R) sub-area, a green (G) sub-area, and a blue (B) sub-area, where the area on the source image is corresponding to a pixel of a destination image presented by a display device; sampling the R sub-area to obtain a R color value, sampling the G sub-area to obtain a G color value, and sampling the B sub-area to obtain a B color value; and rendering R, G, B color components of the pixel of the destination image according to the R color value, the G color value, and the B color value.
US09412187B2	Delayed rendering of content The invention relates to a computer implemented method for preparing content of a document, wherein a document file is received as an input, the content of the document file is parsed, the parsed content data items forming the content of the document file are classified into at least two separate categories. Further, within the method at least one of the following is performed for the classified parsed content data items: rendering the content data items classified in a first category into a raster canvas and storing the rendered content of the raster canvas into a raster image file, generating and storing a meta file comprising at least one preprocessed rendering instruction for at least one content data item classified in a second category. The invention also relates to a system configured to perform the method and a non-transitory computer readable medium storing computer program code.
US09412184B2	Regularized phase retrieval in differential phase-contrast imaging The present invention relates to differential phase-contrast imaging of an object (108). When reconstructing image information from differential phase-contrast image data, streak- like artefacts (502) may occur. The artefacts (502) may substantially reduce legibility of reconstructed image data. Accordingly, it may be beneficial for removing or at least suppressing said artefacts (502). Thus, a method (400) for regularized phase retrieval in phase-contrast imaging is provided comprising receiving (402) differential phase-contrast image data of an object (108); generating (404) reconstructed image data of an object (108) and presenting (406) reconstructed image data of the object (108). The differential phase-contrast image and the reconstructed image data comprise a two-dimensional data structure having a first dimension and a second dimension. Generating reconstructed image data comprises integration of image data in one of the first dimension and the second dimension of the data structure. A gradient operator is determined in the other one of the first dimension and second dimension of the data structure and the data structure is employed for reconstructing image data resulting in a reduction of artefacts (500) within the reconstructed image data.
US09412181B1	System and method for digital image intensity correction The present invention provides a method and apparatus to enhance the image contrast of a digital image device while simultaneously compensating for image intensity inhomogeneity, regardless of the source. The present invention corrects intensity inhomogeneities producing a more uniform image appearance. Also, the image is enhanced through increased contrast, e.g., tissue contrast in a medical image. The method makes no assumptions as to the source of the inhomogeneities, e.g., physical device characteristics or positioning of the object being imaged. In the method, the error between the histogram of the spatially-weighted original image and a specified histogram is minimized. The specified histogram may be selected to increase contrast generally or particularly for accentuation, e.g., on localized regions of interest. The weighting is preferably achieved by two-dimensional interpolation of a sparse grid of control points overlaying the image. A sparse grid is used rather than a dense one to compensate for slowly-varying image non-uniformity. Also, sparseness reduces the computational complexity, as the final weight set involves the solution of simultaneous linear equations whose number is the size of the chosen grid.
US09412173B2	Method for mapping an environment A method for mapping an environment comprises moving a sensor along a path from a start location (P0) through the environment, the sensor generating a sequence of images, each image associated with a respective estimated sensor location and comprising a point cloud having a plurality of vertices, each vertex comprising an (x,y,z)-tuple and image information for the tuple. The sequence of estimated sensor locations is sampled to provide a pose graph (P) comprising a linked sequence of nodes, each corresponding to a respective estimated sensor location. For each node of the pose graph (P), a respective cloud slice (C) comprising at least of portion of the point cloud for the sampled sensor location is acquired. A drift between an actual sensor location (Pi+1) and an estimated sensor location (Pi) on the path is determined. A corrected pose graph (P′) indicating a required transformation for each node of the pose graph (P) between the actual sensor location (Pi+1) and the start location (P0) to compensate for the determined drift is provided. The sequence of estimated sensor locations is sampled to provide a deformation graph (N) comprising a linked sequence of nodes, each corresponding to respective estimated sensor locations along the path. For at least a plurality of the vertices in the cloud slices, a closest set of K deformation graph nodes is identified and a respective blending function based on the respective distances of the identified graph nodes to a vertex is determined. Transformation coefficients for each node of the deformation graph are determined as a function of the 20 required transformation for each node of the pose graph (P) to compensate for the determined drift. Tuple coordinates for a vertex are transformed to compensate for sensor drift as a function of the blending function and the transformation coefficients for the K deformation graph nodes closest to the vertex.
US09412171B2	Adaptive multi-dimensional data decomposition A method of decomposing an image or video into a plurality of components. The method comprises: obtaining (10) an intensity signal of the image or video; and decomposing (30) the intensity signal into a component representing the three-dimensional structure shape of one or more objects in the scene and at least one other component. Also provided is a method of performing an Empirical Mode Decomposition on data in two or more dimensions, using normalized convolution.
US09412170B1	Image processing device and image depth processing method An image depth processing method includes the following steps. A background image and a foreground image in a reference image are obtained according to a depth image corresponding to the reference image. It is noted that the depth value of the background image is larger than the depth value of the foreground image. Meanwhile, the background image is blurred, and then the foreground image and a local image in the blurred background image are blurred. A simulation image is generated according to the background image and the foreground image after blurring the local image and the foreground image.
US09412163B2	Method for detecting and quantifying cerebral infarct A method for detecting a cerebral infarct includes receiving an image of a brain of a subject from a magnetic resonance imaging scanner, wherein the image has a plurality of voxels, and each of the voxels has a voxel intensity. Then, the voxel intensities are normalized, wherein the normalized voxel intensities have a distribution peak, and the normalized voxel intensity of the distribution peak is Ipeak. A threshold is determined, which is the Ipeak+ a value. Voxel having the normalized voxel intensity larger than the threshold is selected, wherein the selected voxel is the cerebral infarct. A method for quantifying the cerebral infarct is also provided.
US09412158B2	Method of configuring a machine vision application program for execution on a multi-processor computer A machine vision system includes a computer with one or more processors and software that has a plurality of tool routines each performing a different image analysis function. A machine vision application program is created by selecting certain ones of the plurality of tool routines to analyze the image. A maximum number of processors on the computer is designated as available for executing a machine vision application, wherein the maximum number may be less than the total number of processors on the computer. When the machine vision application program operates execution of each tool routine is limited to using simultaneously no more than the maximum number of processors.
US09412156B2	Apparatus and methods for encoding, decoding and representing high dynamic range images A data structure defining a high dynamic range image comprises a tone map having a reduced dynamic range and HDR information. The high dynamic range image can be reconstructed from the tone map and the HDR information. The data structure can be backwards compatible with legacy hardware or software viewers. The data structure may comprise a JFIF file having the tone map encoded as a JPEG image with the HDR information in an application extension or comment field of the JFIF file, or a MPEG file having the tone map encoded as a MPEG image with the HDR information in a video or audio channel of the MPEG file. Apparatus and methods for encoding or decoding the data structure may apply pre- or post correction to compensate for lossy encoding of the high dynamic range information.
US09412155B2	Video system with dynamic contrast and detail enhancement A method and system for real time luminance correction and detail enhancement of a video image including the steps of extracting a luminance component from a video image, separating the luminance component into an illumination layer and a scene reflectivity layer, the illumination layer having a dynamic range, compressing the dynamic range of the illumination layer to generate a corrected illumination layer, filtering the reflectivity layer to generate an enhanced reflectivity layer; and combining the corrected illumination layer with the enhanced scene reflectivity layer to generate an enhanced luminance image, is provided. A system for real time luminance correction and detail enhancement of a video image is also provided.
US09412154B2	Depth information based optical distortion correction circuit and method Provided are a depth information based optical distortion correction (ODC) circuit and method. The ODC circuit includes a depth acquisition unit acquiring a depth of an image, a grid generation unit dynamically generating a correction grid corresponding to the depth of the image using depth information of the image and a projection matrix, and a distortion correction unit correcting optical distortion in the image using the correction grid. The corrected image can then be stored, transmitted, or otherwise output. The image can be a single static image or photograph or a frame in a video recording.
US09412153B2	Using depth for recovering missing information in an image An inpainting apparatus and method are described for infilling of blank areas from which an image object or area has been missing, removed, or moved from. Structure regions that reach the edge of the removed object area are identified and then prioritized as to fill order based on depth (distance) from the camera. Then these structure regions are filled in prioritized fill order, followed by remaining (homogeneous) areas to generate the inpainted image. The method may be performed on any desired computer-enabled electronic device, including cell phones, digital cameras, laptops, tablets, personal computers and other processor-equipped electronic devices.
US09412151B2	Image processing apparatus and image processing method This invention improves the image quality of areas that the user want sharply focused. Depth values representing positions in a depth direction of scenes including the photographed object are estimated to generate a depth map. The focus map generation unit, based on the virtual focus parameter 305 and the depth map, generates by an area dividing operation a focus map representing an area to be sharply focused (in-focus area) and an area to be blurred (out-of-focus area). The in-focus area image processing unit places greater importance on the in-focus area in the image processing to generate an in-focus area image. The out-of-focus area image processing unit puts greater importance on the out-of-focus area in the image processing to generate an out-of-focus area image. The image blending unit generates a refocused image by blending the in-focus area image and the out-of-focus area image.
US09412147B2	Display pipe line buffer sharing An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.
US09412146B2	System and method for distributed virtualization of GPUs in desktop cloud Embodiments are provided to enable graphic processing unit (GPU) virtualization for high bandwidth or rate demanding applications, such as 3D gaming, where a client communicates with a host via a virtual desktop infrastructure (VDI). The distributed GPU virtualization allows one or more VMs or comparable hosts or components without GPU access to communicate with a GPU at a different component or physical machine in a data center or a network using remote direct memory access (RDMA). A first physical machine that excludes a GPU starts a remote display driver function to handle a request to render graphics from a client via gateway. A second physical machine that comprises a GPU is instructed to start a render function for the client using the GPU. The render function communicates with the remote display driver function at the first physical machine. The rendered graphics is then sent to the client via the gateway.
US09412143B2	Active images through digital watermarking The present disclosure relates generally to the technological arts of digital watermarking and fingerprinting. One claim recites a method comprising: obtaining digital data representing imagery captured with a camera; storing the digital data at a location in electronic memory; processing the digital data with a processor, said processing comprising generating a digital fingerprint of the imagery; storing the digital fingerprint of the imagery and the location in a storage repository or index; transforming the digital data with digital watermarking upon a request to output the digital imagery to a physical domain, said digital watermarking comprising a plural bit identifier; and associating the plural bit identifier with the fingerprint and location in the storage repository or index. Of course, other combinations, features and claims are disclosed as well.
US09412139B2	Method and system for notarising electronic transactions The invention relates to a system comprising: a first computerized system, or emitter, connected to a communication network; a second computerized system, or receiver, connected to said network; and a server connected to said network. Said server operates as a trusted third party for electronic transactions, is adapted in such a way as to offer a custody service and to vouch for the existence and content of an electronic document sent by the emitter, and communicates with a timestamping entity.The invention also relates to a method according to which the system is used to send a notification and/or contracting request for a receiver and an associated electronic document, from an emitter to said server, and to allow the receiver to securely access said document stored in a repository of the server, the transaction executed being traceable from beginning to end, and repudiation in the origin and destination avoided.
US09412135B2	Check data lift for online accounts Embodiments for extracting data for online account includes systems that receive at least one check images, apply one or more optical character recognition processes to at least a portion of the at least one check image, and convert image based data to text based data. The embodiments further identify check data in the text based data, identify online data from the check data, incorporate at least a portion of the online data into a portion of an online account, and provide the online account portion to a customer.
US09412133B2	System and method for user defined markets for electronic trading A system and method for user defined markets for electronic trading is disclosed. In one embodiment, a technology platform is provided that allows a user to define a new market for electronic trading and automatically generate the new market for live trading. In one embodiment, the new market is automatically tested using a trading simulator that simulates the new market for electronic trading.
US09412131B2	Method and arrangement for specifying services provided by a franking machine In a method for specifying services provided by a franking machine, a program code is loaded into a data processing device via and, a first communication channel to a remote data center, authorization to access the franking machine is requested using an authorization request message. In response, via a second communication channel, data are provided from the remote data center to the franking machine. In response, the franking machine enables access for executing a specification process via a third communication channel via which communication between the data processing device and the franking machine is established using the program code executed by the data processing device. The specification process is executed using the program code to set at least one feature of at least one service provided by the franking machine.
US09412122B2	Method of selecting and purchasing digital objects for subsequent delivery to a third party Disclosed is a method for transferring user data objects, wherein a data providing component provides user data objects. According to the method, the data providing components are called up by a first telecommunication device in order to transfer a selection of certain user data objects to a second telecommunication device. The data providing component transmits a transfer offer message to the second telecommunication device in order to inform the latter on the user data objects that are to be transferred. At least one useful data object is then selected in a second telecommunication device, whereupon the user data object is transferred from the data providing component to the second telecommunication device. The user data object which is transferred to the second telecommunication device is then charged to the first telecommunication device.
US09412118B2	Systems and methods for providing offers using a mobile device A wireless device is enabled to provide offers. The wireless device receives card data for a financial account card and stores the card data in a memory associated with the wireless device. Responsive to using the card data in a transaction at a first merchant location, the wireless device receives transaction line-item data from a computing system associated with the first merchant location. The wireless device determines merchant information for a second merchant location and determines an offer associated with the second merchant location based on the line-item data and the merchant information for the second merchant. The wireless device presents the offer when the wireless device is near the second merchant location.
US09412116B2	Systems, methods and machine-readable media for facilitating provisioning of platforms Systems and method to facilitate provisioning of a plurality of platforms are provided. First information enabling unique identification of a first provider may be processed. The first provider may be matched to a first category. A first set of platform features may be identified. A first set of service modules may be determined. A first definition of a first platform that is configured to interact with the first set of service modules to provide the first set of platform features may be generated. A first plan to provide access to the first platform with the first set of service modules may be generated. A first platform application may be configured to provide the first platform based at least in part on the plan. The configuring may include integrating the first set of service modules into the first platform application using one or more component interfaces.
US09412110B2	Mobile image acquisition A set of conditions associated with monitoring a given environment is received. One or more locations in the given environment are determined, based on at least a portion of the received set of conditions, for which data is to be acquired. The given environment is traversed through the one or more locations. Data at the one or more locations is acquired. The acquired data is stored for subsequent review. One or more of the above steps are performed under control of a processing device at least a part of which is mounted on a mobile platform that is configured to move through the given environment. Determination of the one or more locations in the given environment may further include determining an extended region to be observed.
US09412108B2	Systems and methods for fraud detection by transaction ticket size pattern A method and system for detecting fraud in a payment card network using a pattern of transaction ticket size are provided. The method including receiving transaction information, for a current financial transaction, from at least one of a merchant point of sale (POS) device and a merchant website, the transaction information including a current transaction amount, the transaction information associated with a single payment card cardholder, retrieving a predetermined number of historical transactions for the single cardholder based on the transaction information, and generating a historical spend ticket size pattern based on average ticket size and dispersions for at least one of the same store, similar stores, and relevant merchant categories. The method further including comparing the current transaction amount to the historical spend ticket size pattern and generating a recommendation for approval or decline of the current financial transaction based on the comparison.
US09412105B2	Mobile checkout systems and methods A mobile checkout system and method for completing a purchase transaction to purchase items from an internet merchant. A user browses and selects items for purchase from the merchant through a shopping application or browser. During the processing of the transaction, a checkout application installed on a mobile communication device is launched. The checkout application receives a checkout token created by a checkout server that identifies the purchase transaction. The checkout application uses this token and communicates with the checkout server to cause the checkout server to complete the purchase transaction. When the transaction is complete, the shopping application or browser is relaunched and a results page is displayed.
US09412103B1	Methods systems and computer program products for managing access to customer data Controlling access to customer data. A customer service agent is provided with indirect access to customer data through an intermediate computer such that it is not necessary for the customer service agent to ask questions about the received customer data or receive such data from the customer directly. Secure data access can be used to validate customers and streamline customer interaction and discussions with customer service agents since many questions a customer service agent may ask a customer directly during a discussion are already answered and known to the customer service agent before the customer speaks with the customer service agent. The customer can select which merchants receive customer data, and customer data can be entered manually or acquired by processing images of customer documents or cards such as personal identification or account cards containing information to be used during customer service discussions.
US09412098B1	Systems and methods for daily task optimization A system and method is disclosed for determining an optimized sequence of visits by a consumer to a plurality of merchant locations irrespective of travel distance. The system is configured to receive, from the consumer, errand data including start time and start and finish location and a plurality of merchant locations to visit. The system also generates one or more models for predicting visit durations the merchant locations as a function of time using transaction data and location data associated with a plurality of consumers that previously visited the merchant locations. Based on the generated models, and current and historical travel/traffic information and the errand data, the system generates an optimized sequence of visits for the consumer.
US09412096B2	Techniques to filter electronic mail based on language and country of origin Techniques to detect spam using language and a country of origin of an e-mail may include receiving an e-mail message for a recipient, detecting a country of origin for the e-mail message and detecting a language of the e-mail message. A technique may further include determining a country frequency with which the recipient communicates with the country of origin by e-mail, and a language frequency with which the recipient communicates in the language by e-mail. A technique may assign a first score to the message according to the country frequency, and a second score to the message according to the language frequency. The scores may used to determine whether the e-mail message is spam. Other embodiments are described and claimed.
US09412095B2	Status and time-based delivery services for instant messengers Embodiments of the present invention address deficiencies of the art in respect to unattended status and time-based messaging in an instant messaging (IM) environment and provide a method, system and computer program product for unattended status and time-based messaging in an instant messaging (IM) environment. In an embodiment of the invention, a method for unattended status and time-based messaging in an instant messaging (IM) environment can be provided. The method can include receiving a request from an IM user to queue an unattended status and time-based message, retrieving a recovery trigger for the unattended status and time-based message, and assigning the unattended status and time-based message to a message queue.
US09412093B2	Computer-readable recording medium, extraction device, and extraction method When a second pattern is to be generated by adding an event to a first pattern including events, an extraction program causes a computer to execute the following process based on combinations of events. That is, the extraction program causes the computer to generate the second pattern when the number of occurrence, in the second pattern, of each of the events included in the combinations is not more than a threshold. The extraction program causes the computer to calculate, based on data including a plurality of events, a frequency at which one or more of the generated second patterns occur in the data. The extraction program causes the computer to extract the second pattern having the frequency satisfying a predetermined condition. The extraction program causes the computer to add a new event to the extracted second pattern.
US09412090B2	System, mobile communication terminal and method for providing information A system, a mobile communication terminal, and a method for providing information. The system for providing information includes: a tag configured to store tag information; a mobile communication terminal configured to obtain the tag information using short-range communication and to calculate position information of the mobile communication terminal when the tag information is obtained; and an information providing server configured to receive the tag information and the position information from the mobile communication terminal, extract service address information which provides information for connecting to a service identified by the tag information and based on the position information, and provide the extracted service address information to the mobile communication terminal. The mobile communication terminal is connected to the service based on the service address information.
US09412088B2	System and method for interactive communication context generation An interactive communication, such as a video conference or an audio communication, is established and a user places the interactive communication on hold. Prior to and/or after the interactive communication was placed on hold, context information related to when the interactive communication was placed on hold is gathered. The interactive communication is taken off hold and the context information is presented to the user; thus providing the user with the context of the interactive communication when it was placed on hold.
US09412087B2	System, method, and apparatus for mapping product identification to medication identification A method, system, and corresponding apparatus are provided for mapping product identification to medication identification. In particular, a method may include receiving a product identifier associated with a medication container; comparing the product identifier with a database of product identifier formats; and retrieving a medication identifier from the product identifier in response to the product identifier corresponding to a single product identifier format in the database. Methods may include applying an algorithm to the product identifier in response to the product identifier failing to correspond with a product identifier format in the database and creating a mapped product identifier to a single medication identifier in the database in response to the application of the algorithm to the product identifier resulting in the single medication identifier match.
US09412086B2	Apparatus and method for customized product data management The invention is an electronic identification system that integrates with consumer purchased products for management of data in digital form by way of an interconnected computing system, network, and/or mobile device. The system utilizes a scanning system and coded labels that facilitate a uniform identification of goods within a sales setting or within a household. Such a system would enable the use of SMART technology systems in household appliances, warehouses and retail such that the system implements mobile applications and interfacing through a high-speed network.
US09412085B2	Management of an object A method and associated system for managing an item in a place. The method detects that: (i) the item in the place is being moved, (ii) an operating object inside the place is moving, and (iii) the operating object inside the place and the item in the place are within a previously specified distance of each other. Responsive to the previous detections, it is determined that the operating object does not have a reservation for borrowing the item, from which it is determined that the operating object has illegitimately taken the item, which triggers preventing the operating object from removing the item from the place.
US09412084B2	Service context According to one general aspect, a method may include displaying a user interface associated with the application. The user interface may provide a selection of a business service that is implemented within an Information Technology (IT) environment by at least one server and at least one business application executing on the at least one server. The method may include requesting a service status for the business service based on the selection, and receiving a database result regarding the business service from a database server. The database result may include performance information associated with the business service. The method may include displaying the service status as a user interface element viewable within the user interface of the application. The service status may provide the performance information that has been received within the database result.
US09412082B2	Method and system for demand response management in a network A method and system for controlling demand events in a utility network with multiple customer sites. The value of a demand response parameter threshold for invoking a demand response event is calculated based on the number of available demand response events and the number of opportunities remaining to issue the available demand response events. This parameter represents the utility objectives for using the demand response program (e.g., cost savings, reliability, avoided costs). A current value of the demand response parameter is compared to the threshold value, and a determination is made whether or not to call a demand response event for the current opportunity, or to save the event for a future opportunity based upon this comparison.
US09412081B2	Method and apparatus for recording and reporting agricultural information using a combination of universal product code and lot code Various embodiments of the present disclosure include methods and apparatus for recording and reporting agricultural information using a combination of a universal product code and a lot code. In an example embodiment, apparatus comprises a hand-held device including a display and one or more input devices to sense product identification indicia associated with or affixed to a food product that is grown or raised in an agricultural operation. The product identification indicia comprise a combination of a universal product code and a lot code for the food product. The hand-held device includes at least one processor to determine a machine-readable identification code from the product identification indicia; send the identification code to at least one remote server; receive, from the at least one remote server, agricultural certification information that is associated with the product; and display the certification information on the display in human readable form.
US09412080B2	Method and system for handling conditional dependencies between alternative product segments within a manufacturing execution system ANSI/ISA/95 compliant A system handles conditional dependencies between alternative product segments of a production process modeled within a manufacturing execution system (MES). The system includes data processing units connected to a network and production components. The data processing units run MES software for controlling and monitoring the process. The MES software includes a production modeler embedding time-sensitive dependency information in each product segment to define the start of execution in relation to another product segment. The production modeler embeds in each product segment programmed for alternative execution conditional dependency information and a sequence attribute about the order of evaluation of the specified condition. The MES software, during execution of a product segment preceding alternative executions, checks the condition specified as first in the set of sequence attributes and, if that condition is satisfied, executes the product segment corresponding with that condition, otherwise iterates the check for execution until a condition is satisfied.
US09412071B2	Rules execution platform system and method Methods, mediums, and systems are described for providing a platform coupled to one or more rules engines. The platform may provide runtime rule services to one or more applications. Different rules engines may be used for different types of rules, such as calculations, decisions, process control, transformation, and validation. Rules engines can be added, removed, and reassigned to the platform. When the platform receives a request for services from an application, the platform selects one of the rules engines to handle the request and instructs the selected rules engine to execute the rule. The rules engine may be selected automatically. The platform may be implemented through a service-oriented architecture.
US09412070B2	Automatically deriving context when extracting a business rule A method and associated system for automatically deriving context of a business rule that is being inferred from an information source, such as legacy computer-program source code, a system specification, or a description of a business function or operation. A first generation of context-dependent conditions upon the business rule is identified by analyzing the information source and other, related, sources, and the business rule is modified to account for this first generation of context-dependent conditions. Context-dependent conditions that place constraints upon the previously identified first-generation conditions are then identified and the business rule is further modified to account for this next generation of context-dependent conditions. This process repeats iteratively through multiple generations of identifications, until the business rule has been modified to accommodate all contextual information that may be gleaned from all analyzed information sources. These sources may include extrinsic sources like Web pages, standards, or public documents.
US09412068B2	Distributed factor graph system In a data processing system, a method for implementing a factor graph having variable nodes and function nodes connected to each other by edges includes implementing a first function node and a on a first computer system, the first computer system being in network communication with a second computer system; establishing a network connection to each of a plurality of processing systems; receiving, at the first function node, soft data from a variable node implemented on one of the processing systems, the soft data including an estimate of a value and information representative of an extent to which the estimate is believed to correspond to a correct value; and transmitting, from the first function node to the one of the processing systems, soft data representing an updated estimate of the value.
US09412067B2	Anomaly detection in spatial and temporal memory system Detecting patterns and sequences associated with an anomaly in predictions made a predictive system. The predictive system makes predictions by learning spatial patterns and temporal sequences in an input data that change over time. As the input data is received, the predictive system generates a series of predictions based on the input data. Each prediction is compared with corresponding actual value or state. If the prediction does not match or deviates significantly from the actual value or state, an anomaly is identified for further analysis. A corresponding state or a series of states of the predictive system before or at the time of prediction are associated with the anomaly and stored. The anomaly can be detected by monitoring whether the predictive system is placed in the state or states that is the same or similar to the stored state or states.
US09412066B1	Systems and methods for predicting optimum run times for software samples A computer-implemented method for predicting optimum run times for software samples may include (1) identifying a set of training data that identifies (i) a plurality of static characteristics of at least one previously executed software sample and (ii) an amount of time taken by a software-analysis mechanism to observe a threshold level of run-time behaviors of the previously executed software sample, (2) identifying a plurality of static characteristics of an additional software sample, (3) determining that the static characteristics of the additional software sample and the previously executed software sample exceed a threshold level of similarity, and then (4) predicting an optimum run time for the additional software sample based at least in part on the amount of time taken by the software-analysis mechanism to observe the threshold level of run-time behaviors of the previously executed software sample. Various other methods, systems, and computer-readable media are also disclosed.
US09412064B2	Event-based communication in spiking neuron networks communicating a neural activity payload with an efficacy update Apparatus and methods for event based communication in a spiking neuron network. The network may comprise units communicating by spikes via synapses. The spikes may communicate a payload data. The data may comprise one or more bits. The payload may be stored in a buffer of a pre-synaptic unit and be configured to accessed by the post-synaptic unit. Spikes of different payload may cause different actions by the recipient unit. Sensory input spikes may cause postsynaptic response and trigger connection efficacy update. Teaching input spikes trigger the efficacy update without causing the post-synaptic response.
US09412062B2	RFID apparatus, RFID reader, portion hot-drinks machine and system In various embodiments, a Radio Frequency Identification apparatus includes a coupling body having a metal material and a transponder chip configured to contactlessly transmit data. The transponder chip is physically coupled to the coupling body, has a storage element which stores the data, and has a first electrode which is at a distance from the coupling body. The coupling body is in the form of a second electrode for the transponder chip configured to couple the transponder chip to an external Radio Frequency Identification reader for reading the data.
US09412060B2	Semiconductor device and method for manufacturing the same A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 Ω/cm2 is formed on at least one surface of each structure body.
US09412059B2	Card body, a manufacturing method for an IC card, and the IC card According to one embodiment, a card body includes a card part onto which an IC module is to be mounted, and a bracket part to support the card part. The card part includes a bevel. The bracket part includes a hole, a first bridge part, a second bridge part, a first break-off line, and a second break-off line. The hole is formed at a circumference of the card part. The first bridge part connects the bracket part and the card part. The second bridge part connects the bracket part and the card part. The second bridge part is provided at a farer position from the bevel than the first bridge part. The first break-off line is provided with a first depth at the first bridge part. The second break-off line is provided with a second depth at the second bridge part. The second depth is shallower than the first depth.
US09412058B2	Method for encoding the color of an object in multispectral form by adaptive compression, and associated decoding method The present invention relates to a method for encoding the color of an object in multispectral form by adaptive compression, characterized in that said method comprises the following steps: determining an identifier of the color in the form of a logistics-dedicated code and having a European Article Numbering (EAN), Universal Product Code (UPC), or Domain Name System (DNS) distributed management structure; inserting a marker at the beginning of said code indicating that the code is a color code, as well as the type of storage; and creating a color encoding that can be interpreted by both a human being and a computer by being directly read, in the form of three elements, i.e. a sample of the color or of texture, a name, and a barcode/chip, using said code and the marker, which provides access to the bidirectional spectral reflectance of the color stored either locally or on a network, or both locally and on a network, and having a rendering model that is predetermined by said marker. The present invention likewise relates to an associated decoding method.
US09412055B2	Image forming apparatus that selectively stores print data in a cache memory to a secondary memory device An image processing apparatus that stores print data in a cache memory while preventing performance from being degraded by cache flushing. The image processing apparatus includes a cache for storing print data, and an SD card for storing the print data stored in the cache. A cache controller of a CPU transmits an SD card write request for storing the print data stored in the cache into the SD card to a secondary storage device access controller. When the SD card write request is received after printing of the print data has been normally terminated, the secondary storage device access controller disables execution of the storage processing.
US09412053B1	Method, apparatus and system for projecting light for user guidance Embodiments of an apparatus, system and method for creating light projection solutions for user guidance are described herein. A user may request that projected light be used to assist in a plurality of operations involving objects in the physical space around the user. A user can use voice commands and hand gestures to request that a projector project light or images on or near objects involved in one or more operations. Embodiments of the disclosure perform an image recognition process to scan the physical space around the user and to identify any user gesture performed (e.g., a user pointing at a plurality of objects, a user holding an object); a steerable projector may be actuated to project light or image data based on the user's request and a plurality of operations associated with the objects.
US09412051B1	Neuromorphic image processing exhibiting thalamus-like properties Neuromorphic image processing employs neuromorphic neurons arranged as relay neurons, interneurons and reticular neurons to process image data. A neuromorphic image processing channel includes relay neurons and interneurons to receive spiking input signals. The interneurons provide feed-forward inhibition to the relay neurons. The neuromorphic image processing channel also includes reticular neurons to receive output spiking signals from and to provide feedback inhibition to the relay neurons. A neuromorphic image processing system includes a first neuromorphic image processing (NIP) channel to receive a first set of spiking input signals and a second NIP channel to receive a second set of spiking input signals. The neuromorphic image processing system also includes reticular neurons to receive output spiking signals from and to provide feedback inhibition to both the first and second NIP channels.
US09412049B2	Apparatus and method for recognizing object using correlation between object and content-related information An apparatus and method for recognizing an object using correlation information about an object and content-related information which is generated based on the content-related information. The apparatus includes a data classifier, a data analyzer, a correlation manager, and an object identifier.
US09412046B2	Training image adjustment preferences Some embodiments include a method of operating a computing device to learn user preferences of how to process digital images. The method can include: aggregating a user image selection and a context attribute associated therewith into a preference training database for a user, wherein the user image selection represents a record of the user's preference over at least one of adjusted versions of a base image when the adjusted versions are separately processed by different visual effects; determining a visual effect preference associated based on machine learning or statistical analysis of user image selections in the preference training database, the user image selections representing experimental records corresponding to the visual effects; updating a photo preference profile with the visual effect preference; and providing the photo preference profile to an image processor to adjust subsequently captured photographs provided to the image processor.
US09412044B2	Method of compensation of respiratory motion in cardiac imaging A method (10) for respiratory motion compensation by applying principle component analysis (PCA) on cardiac imaging samples obtained using 2D/3D registration of a pre-operative 3D segmentation of the coronary arteries.
US09412043B2	Systems, methods, and computer program products for searching and sorting images by aesthetic quality A system, method, and computer program product for assigning an aesthetic score to an image. A method of the present invention includes receiving an image comprising a set of global features. The method includes extracting a set of global features for the image. The method further includes encoding the extracted set of global features into a high-dimensional feature vector. The method further includes reducing the dimension of the high-dimensional feature vector. The method further includes applying a machine-learned model to assign an aesthetic score to the image, wherein a more aesthetically-pleasing image is given a higher aesthetic score and a less aesthetically-pleasing image is given a lower aesthetic score.
US09412040B2	Method for extracting planes from 3D point cloud sensor data A method extracts planes from three-dimensional (3D) points by first partitioning the 3D points into disjoint regions. A graph of nodes and edges is then constructed, wherein the nodes represent the regions and the edges represent neighborhood relationships of the regions. Finally, agglomerative hierarchical clustering is applied to the graph to merge regions belonging to the same plane.
US09412037B2	Method and system for image analysis based upon correlation relationships of sub-arrays of a descriptor array A method for processing an image, including: identifying a group of keypoints in the image; for each keypoint, calculating a corresponding descriptor array including plural array elements, each array element storing values taken by a corresponding color gradient histogram of a respective sub-region of the image in the neighborhood of the keypoint; for each keypoint, subdividing the descriptor array in at least two sub-arrays each including a respective number of elements of the descriptor array, and generating a compressed descriptor array including a corresponding compressed sub-array for each of the at least two sub-arrays, each compressed sub-array obtained by compressing the corresponding sub-array by vector quantization using a respective codebook; exploiting the compressed descriptor arrays of the keypoints for image analysis. For each keypoint of the group, the subdividing is based on correlation relationships among color gradient histograms with values stored in the elements of the descriptor array of each keypoint.
US09412032B2	Schedule managing method and apparatus using optical character reader A schedule managing method capable of automatically generating schedule data using data extracted from an image, and an apparatus thereof are provided. The schedule managing method preferably includes: setting at least one recognition region within an image; extracting data from the set recognition region; categorizing the extracted data according to a predetermined categorization rule; and generating schedule data using the categorized data.
US09412029B2	Apparatus for recognizing iris and operating method thereof An apparatus for recognizing iris in an eye is provided. An image collecting unit collects an image of the eye. A control unit detects whether a user wears a contact lens, based on an edge component on the image of the eye.
US09412028B2	Wheel slip or spin notification Described embodiments include a system and method. A digital imaging device is configured to capture images of a region of a contact between a wheel of a terrestrial vehicle and a surface (“contact region”). A correlator is configured to correlate a first digital image of the contact region captured at a first time with a second digital image of the contact region captured at a second time. A kinematics circuit determines an incremental slide or slip of the wheel relative to the surface. A fraction status circuit combines at least two instances of the incremental slide or slip into data indicative of a slide or slip by the terrestrial vehicle relative to the surface. A communications circuit outputs an electronic signal indicative of the data indicative of a slide or slip by the terrestrial vehicle.
US09412026B2	Intelligent video analysis system and method The present disclosure relates to an intelligent video analysis system and method and, more specifically, an intelligent video analysis system and method which provides an event by analyzing data acquired from a camera and a smart device. The an intelligent video analysis system and method system selects information by temporally and spatially matching information received from a camera and a smart device, determines based on the selected information whether a security event-relevant condition is satisfied, generates Customer Relationship Management (CRM) information, and outputs the CRM information and a security event, which is generated from the selected information.
US09412025B2	Systems and methods to classify moving airplanes in airports A sequence of video images is generated of a pavement area of an airport which contains one or more objects. A processor accesses a background model of the pavement area and determines in a current image a single cluster of foreground pixels that is not part of the background model and assigns a first value to each foreground pixel in the cluster to create a foreground mask. The background model is updated by learning new conditions. A convex hull is generated from the foreground mask. A ratio is determined from pixels captured by the complex hull and pixels in the foreground mask. A ratio higher than a threshold value indicates an object not being an airplane and an alert is displayed on a computer display. Images may be thermal images. A surveillance system based on the calculated ratio is disclosed.
US09412024B2	Visual descriptors based video quality assessment using outlier model System and method for identifying erroneous videos and assessing video quality is provided. Feature vectors are generated corresponding to a plurality of frames associated with the one or more videos. The feature vectors are subsequently subjected to anomaly detection to obtain first and second normalized path lengths and normalized anomaly measures. The first and second normalized path lengths and normalized anomaly measures are provided to a regression model to identify the erroneous video.
US09412022B2	Iris identification system and method A method for biometric recognition may be employed on multiple biometrics, including irises and ears. The method includes decomposing the radiometric profile of each line of an image into a plurality of wavelets using a wavelet transform process. A unique signal is calculated using the plurality of wavelets. A template is assembled using the signal and areas of interest in the template are identified. The template is then compared to a second template using the plurality of areas of interest.
US09412021B2	Method and apparatus for controlling transmission of data based on gaze interaction An approach for controlling transmission of data based on gaze interaction. A data transmission determination platform determines one or more gaze metrics for one or more users. The one or more gaze metrics, relate, at least in part, to a level of interaction of each user with an object. The data transmission determination platform then processes and/or facilitates a processing of the one or more gaze metrics, user preference information, propagation information from one or more entities associated with the object, or a combination thereof to determine data to transmit one or more devices associated with at least a subset of the at least one or more users.
US09412019B2	Methods for extracting shape feature, inspection methods and apparatuses Methods for extracting a shape feature of an object and security inspection methods and apparatuses. Use is made of CT's capability of obtaining a 3D structure. The shape of an object in an inspected luggage is used as a feature of a suspicious object in combination with a material property of the object. For example, a false alarm rate in detection of suspicious explosives may be reduced.
US09412014B2	Biometric information process device, biometric information process method, and computer readable medium A biometric information process device includes: a biometric sensor obtaining a plurality of biometric images of a user; a detection portion detecting a surface reflection region of the plurality of biometric images; and a storage portion storing biometric information obtained from biometric images included in the plurality of biometric images, the biometric images having a different surface reflection region from each other.
US09412013B2	Method and apparatus for recognizing hand motion A hand motion recognizing apparatus obtains an image with first resolution including a hand and an image with second resolution higher than the first resolution including the hand, maps the image with the first resolution and the image with the second resolution, extracts a hand position from the image with the first resolution, obtains a hand region corresponding to the hand position from the image with the second resolution mapped to the image with the first resolution, and subsequently estimates a hand motion from the hand region.
US09412011B2	Warning a user about adverse behaviors of others within an environment based on a 3D captured image stream A tactile feedback output device receives one or more warning signals for controlling one or more types of tactile output by the one or more tactile feedback output devices, the one or more warning signals representing that a predicted behavior of a monitored user represents a particular behavior that is potentially adverse and a percentage probability that the predicted behavior is adverse, the monitored user detected within a particular environment monitored by a supervising user, the one or more tactile feedback output devices worn by the supervising user.
US09412008B2	Tracking apparatus and tracking method A tracking apparatus includes an image data acquisition unit, a tracking process unit, a contrast information acquisition unit, a contrast information similarity evaluation unit, and a control unit. The image data acquisition unit acquires image data. The tracking process unit detects a candidate position of a tracking target in image data. The contrast information acquisition unit acquires contrast information at the candidate position. The contrast information similarity evaluation unit evaluates a similarity between contrast information at a position of the tracking target decided in a past frame and current frame. The control unit decides the position of the tracking target in the current frame based on the evaluation of the similarity.
US09412005B2	Use of error image for unmixing artifact removal in linear spectral unmixing A method of removing a potential false positive result in a stained sample. The method includes the steps of: acquiring a spectral image set of a stained sample; performing linear spectral unmixing of the spectral image set to obtain a plurality of rule images; calculating an error image for the stained sample; thresholding at least one of the plurality of rule images, wherein thresholding is based on the error image; and removing a potential false positive result from the at least one of the plurality of rule images based on thresholding.
US09411999B2	Barcode reader having multiple sets of imaging optics The present disclosure provides a barcode reader including a second set of imaging optics having a larger effective depth of field than a first set of imaging optics and requiring a larger amount of time to process a resulting image of a barcode into a decodable format. The barcode reader also includes a processor providing a decoded output based on an image acquired with the second set of imaging optics if an image acquired with the first set of imaging optics is not decodable.
US09411997B1	Systems and methods for tracking subjects A radio frequency identification (RFID) network and methods for tracking subjects in a closed environment includes distributing RFID readers across the environment. Readers have unique reader identifiers and communicate with a computer system. These identifiers and reader locations are stored. The location of subjects bearing passive RFID tags is acquired by reading the unique subject identifiers off the tags and associating these RFID tags with the reader identifiers of the readers making the readings. A subject data store includes the location data of the subjects obtained by the RFID readers and electronic addresses of the subjects. An instruction set data store comprising sets, each set corresponding to one of a plurality of events, is also maintained. In accordance with the instruction set data store, in response to an event, different event messages are sent to different subjects based upon their location in the closed environment and/or their class label.
US09411989B2	Continuously monitored core temperature sensor and method A system that provides notice of a lost signal. A wireless device and a control device employ radio frequency identification (RFID) technology, which uses radio frequency signals to communicate with one another via communication link having a reception range. The control device transmits a signal to the wireless device via the communication link. The wireless device responds by transmitting a return signal via the communication link. The control device processes the return signal to determine if the wireless device is within the reception range, if not, the control device provides an audible, written or visual alarm.
US09411988B2	Detection of a transactional device A terminal includes first and second communication modules for communicating with a personal device for performing transactions, called a transactional device. The first communication module includes a contact reading interface, and the second communication module includes a contact-free reading interface. The terminal also includes a detection module including: at least one transactional device position sensor, delivering an item of data representative of a position of a transactional device relative to the terminal; and at least one control module for controlling at least one communication module of the first and second communication modules, the at least one control module activating the communication module on the basis of the item of data representative of the position of the transactional device.
US09411984B2	Cryptographic processing apparatus, cryptographic processing system, and cryptographic processing method A process mode of either of an encryption process and a decryption process is set for at least one of a plurality of pieces of key data, in association with the key data. Then, a mode specifying command for specifying a process mode in association with key data is received from another apparatus, and if the received process mode and the process mode associated with the key data coincide with each other, the process in the process mode using the key data is permitted.
US09411983B2	Apparatus and method to protect digital content In an embodiment of the present invention, a processor includes content storage logic to parse digital content into portions and to cause each portion to be stored into a corresponding page of a memory. The processor also includes protection logic to receive a write instruction having a destination address within the memory, and if the destination address is associated with a memory location stores a portion of the digital content, erase the page associated with the memory location. If the destination address is associated with another memory location that does not store any of the digital content, the protection logic is to permit execution of the write instruction. Other embodiments are described and claimed.
US09411982B1	Enabling transfer of digital assets Techniques for managing digital assets are described that enable a principal to designate a plurality of users that will gain access and ownership of the principal's account that contains the various digital assets of the principal in the event of a transfer of assets. The account may be a network accessible account that maintains various digital assets of the principal, such as multimedia, applications, virtual machines, data, and others. In the event of a transfer, access to the account can be controlled by a cryptographic secret, where each of the designated users has been provided with a distinct share (part) of the cryptographic secret. A minimum number of shares of the secret are required before access to the principal's account will be granted. The minimum number may be configured by the principal in advance.
US09411981B2	Method and system for activating a portable data carrier The invention relates to a method for activating a portable data carrier (1) in which a first portable data carrier (1) is supplied in an inactive state to a user, after the user has requested the first data carrier (1) with the aid of a second portable data carrier (2) from a central instance, whereby the first and the second data carrier (1, 2) have access to authentication data for mutual authentication. In the method according to the invention a communication connection is set up between the first and the second data carrier (1, 2), via which the first and the second data carrier (1, 2) mutually authenticate each other on the basis of the authentication data and establish a cryptographically secured end-to-end connection. Via this end-to-end connection then the second data carrier (2) activates the first data carrier (1) by transmitting activation data to the first data carrier (1).
US09411978B2	System and method for access control using network verification A system for controlling access includes a computing device, configured to: determine a first identifier associated with a first access point being used by the computing device to access a network; determine first access control data associated with the first identifier and a first application executing on the computing device; and control access to data over the network by the first application based on the first access control data.
US09411976B2	Communication system and method There is provided a system, including a network that is defined by its novel approach to privacy, security and freedom for its users, namely privacy by allowing access anonymously, security by encrypting and obfuscating resources and freedom by allowing users to anonymously and irrefutably be seen as genuine individuals on the network and to communicate with other users with total security and to securely access resources that are both their own and those that are shared by others with them. Functional mechanisms that the system are able to restore open communications and worry-free access in a manner that is very difficult to infect with viruses or cripple through denial of service attacks and spam messaging; moreover, it will provide a foundation where vendor lock-in need not be an issue.
US09411974B2	Managing document revisions Embodiments of the invention relates to tracking changes made to a document, and embedding the changes in the document while limiting access to the embedded changes. A log of the revisions is retained in a revision history, which is stored in an object library of alternative storage. Access to the document with acceptance of the changes is enabled. Markings associated with deletions and additions to the document, the revision history, or an alternative view showing the changes made is limited based upon a security protocol.
US09411967B2	Systems and methods for managing location data and providing a privacy framework A computer-implemented method includes providing a user interface on an internet-protocol (IP) connected mobile device, the user interface configured to receive a user input corresponding to one or more data privacy parameters for geo-location data, and controlling a transferring of geo-location data to and from each of a plurality of mobile applications on the mobile device based on the user input. A change in one or more of the data privacy parameters can change how geo-location data is provided to each of the plurality of applications and can affect location data accuracy, location data reporting frequency, geo-functions, and more. The user interface can be configured to allow a user to view, manage, and delete a personal location history. Furthermore, one or more profiles can be associated with one or more of the plurality of mobile applications, where each of the one or more profiles is assigned individual data privacy parameters.
US09411962B2	System and methods for secure utilization of attestation in policy-based decision making for mobile device management and security Policy-based client-server systems and methods for attestation in managing and securing mobile computing devices. Attestation provides the means to make efficient, secure, and reproducible use of knowledge possessed by trusted expert parties and authorities within the expression and enforcement of policies for controlling use of, and access to, onboard software and hardware, network capabilities, and remote assets and services. Aspects of secure attestation of applications that use shared and dynamically loaded libraries are presented, as well as potential business models for attestation used in such a policy-based system.
US09411960B2	Virus co-processor instructions and methods for using such Circuits and methods for detecting, identifying and/or removing undesired content are provided. According to one embodiment, a virus processing system includes a virus co-processor, a first memory, a general purpose processor (GPP) and a second memory. The first memory is communicably coupled to the co-processor via a first memory interface. The first memory includes a first signature compiled for execution on the co-processor. The GPP is communicably coupled to the co-processor. The second memory is communicably coupled to the co-processor via a second memory interface and to the GPP. The second memory includes a second signature compiled for execution on the GPP. The co-processor is operable to retrieve the first signature stored within the first memory through an instruction cache. The co-processor is operable to retrieve a data segment to be scanned from second memory through a data cache that is separate from the instruction cache.
US09411959B2	Identifying an evasive malicious object based on a behavior delta A security device may receive actual behavior information associated with an object. The actual behavior information may identify a first set of behaviors associated with executing the object in a live environment. The security device may determine test behavior information associated with the object. The test behavior information may identify a second set of behaviors associated with testing the object in a test environment. The security device may compare the first set of behaviors and the second set of behaviors to determine a difference between the first set of behaviors and the second set of behaviors. The security device may identify whether the object is an evasive malicious object based on the difference between the first set of behaviors and the second set of behaviors. The security device may provide an indication of whether the object is an evasive malicious object.
US09411957B2	Method and device for optimizing and configuring detection rule A method and a device for optimizing and configuring a detection rule, where the method includes: a network entity receives network traffic; extracts a packet from the network traffic, and identifies, according to a feature of the packet, protocol related information used in the network; saves the protocol related information and correspondence between pieces of information in the protocol related information to a first learning association table; and matches a corresponding rule from a vulnerability rule base according to the protocol related information to generate a first compact rule set. Through the generated compact rule set in the present invention, subsequent protocol detection is performed only for a protocol threat that may occur in a live network; therefore, content that needs to be detected subsequently is reduced, the detection efficiency is improved, and unnecessary performance consumption is avoided at the same time.
US09411953B1	Tracking injected threads to remediate malware Injected threads are tracked to detect malware that injects malicious code into the address space of a legitimate process. Relationships between threads of processes executing on a client and files stored by the client are mapped to identify files that create threads in executing processes. The address space of a process is analyzed to identify legitimate memory regions in the address space. A suspicious thread referencing a suspicious memory region of the address space outside of the legitimate memory regions is identified. The suspicious memory region is scanned to identify malware. The mapped relationships are used to identify the file that created the thread that referenced the address space in which the malware was identified. The malware in the file is remediated.
US09411949B2	Encrypted image with matryoshka structure and mutual agreement authentication system and method using the same The present invention relates to an encrypted image with a matryoshka structure and a mutual agreement authentication system and method using the same. The encrypted image with a matryoshka structure is used in authentication in an authentication system having a plurality of layers and comprises: a first encrypted image which can be opened by only a server of any one layer of the authentication system; and a second encrypted image which can be opened by only a server of another layer distinguished from the any one layer, wherein any one sealed encrypted image of the first and second encrypted images is embedded and sealed in the other encrypted image.
US09411946B2	Fingerprint password Various systems and methods for authenticating a user are described herein. A system to includes a biometric scanner to scan an input sequence of biometric identifiers; a storage device to store a biometric identifier database; an input module to receive the input sequence of biometric identifiers; an access module to access the biometric identifier database and retrieve a secret sequence of biometric identifiers; a comparator module to compare the input sequence of biometric identifiers to the secret sequence of biometric identifiers to obtain a result; and an authorization module to, based on the result, allow access to a resource provided by the system.
US09411945B2	Image processing apparatus that performs user authentication, authentication method therefor, and storage medium An image processing apparatus capable of an authentication technique which enables appropriate user authentication on an application-by-application basic without requiring users to perform time-consuming operations. A storage unit stores authentication method setting information in which authentication methods for respective ones of a plurality of applications are set. An authentication method determination unit determines an authentication method for use in authentication to be performed before a selected application is executed, based on the authentication method setting information. An authentication unit performs the authentication using the authentication method determined by the authentication method determination unit. The authentication methods include at least a first authentication method that does not require input of authentication information and a second authentication method that requires input of the authentication information.
US09411943B2	Authentication method for authenticating a first party to a second party An authentication method authenticates a first party to a second party, where an operation is performed on condition that the authentication succeeds. If the first party is not authenticated, then if the first party qualifies for a sub-authorization, the operation is still performed. Further, a device that includes a first memory area holding a comparison measure, which is associated with time, and which is also used in said authentication procedure, a second memory area holding a limited list of other parties which have been involved in an authentication procedure with the device, and a third memory area, holding compliance certificates concerning parties of said list.
US09411939B2	Method for producing patient-specific plate A method of making a patient specific surgical orthopedic implant includes obtaining a virtual model of the orthopedic implant that is configured to fit over a particular tissue body, and virtually designing holes of the orthopedic implant.
US09411938B2	System for defining cuts in eye tissue A computer-aided system include a data storage (18) with eye data (181), which defines a three-dimensional model of the eye, and a reference generator (113) for defining and storing a geometric reference in relation to the three-dimensional model of the eye. The system additionally includes a cut surface editor for defining and positioning cut surfaces in the three-dimensional model of the eye based on user instructions. Finally, the system includes a cut pattern generator (117) for, based on the positioned cut surfaces, generating and storing three-dimensional cut patterns for defining tissue cuts to be executed in a human eye by means of femtosecond laser pulses. The generation of a three-dimensional cut pattern permits the user to define tissue cuts made possible by femtosecond laser pulses in a targeted and efficient fashion in the three-dimensional model of the eye without having to undertake manipulations directly on the eye for this purpose.
US09411933B1	Method and system for collection and management of perioperative data Methods and systems for collecting and managing anesthesia perioperative data of a patient are provided. More particularly, a method of the present disclosure can include presenting a dashboard view of a user interface on a display of a computing device. The dashboard view can display a plurality of modules corresponding to the various perioperative periods of a procedure. In response to a user input, the method can access a module in the plurality of modules if it is determined that the user has access to the module, and can present a corresponding module interface.
US09411929B2	Method of determining RNA integrity A method of determining a quantitative measure of the integrity of RNA in a sample, the method comprising: (i) assaying a sample containing instances of an RNA molecule transcribed from a reference gene, at least some of the instances being damaged, to determine quantitative measures of the relative or absolute numbers of intact instances of each of a plurality of segments of the RNA molecule in the sample, the segments having respective different lengths; (ii) based on a relationship between the determined quantitative measures and the respective different lengths of the segments, determining a quantitative measure of integrity of the instances of the RNA molecule in the sample; and (iii) determining the total number of instances of an RNA molecule of interest in a sample by using the quantitative measure of integrity and the length of a corresponding degradation-relevant segment of the RNA molecule of interest.
US09411925B2	Simultaneously viewing multi paired schematic and layout windows on printed circuit board (PCB) design software and tools A method according to one embodiment includes receiving a printed circuit board design in a memory; generating, using a processor, multiple schematic windows of the printed circuit board design; generating, using the processor, multiple layout windows of the printed circuit board design; and outputting the multiple schematic windows of the printed circuit board design simultaneously with outputting the multiple layout windows of the printed circuit board design. A first of the schematic windows is paired with a first of the layout windows, the paired windows depicting representations of a common sub-portion of the printed circuit board design.
US09411916B2	Distributed approach for feature modeling using principal component analysis In one embodiment, techniques are shown and described relating to a distributed approach for feature modeling on an LLN using principal component analysis. In one specific embodiment, a computer network has a plurality of nodes and a router. The router is configured to select one or more nodes of the plurality of nodes that will collaborate with the router for collectively computing a model of respective features for input to a Principal Component Analysis (PCA) model. In addition, the selected one or more nodes and the router are configured to perform a distributed computation of a PCA model between the router and the selected one or more nodes.
US09411912B1	Clock topology planning for reduced power consumption In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.
US09411908B2	Architecture for TCAM sharing Aspects of the disclosure provide a packet processing system. The packet processing system includes a plurality of processing units, a ternary content addressable memory (TCAM) engine, and an interface. The plurality of processing units is configured to process packets received from a computer network, and to perform an action on a received packet. The action is determined responsively to a lookup in a table of rules to determine a rule to be applied to the received packet. The TCAM engine has a plurality of TCAM banks defining respective subsets of a TCAM memory space to store the rules. The interface is configured to selectably associate the TCAM banks to the processing units. The association is configurable to allocate the subsets of the TCAM memory space to groups of the processing units to share the TCAM memory space by the processing units.
US09411907B2	Method and system for performing searches in a multi-tenant database environment Techniques for searching in a multitenant database environment. A graphical user interface is provided that includes a search functionality for searching a database within a multitenant database environment. The multitenant environment includes data for multiple client entities, each identified by a tenant identifier (ID) having one of one or more associated users. Users of the client identities can only access data identified by their tenant ID. The multitenant environment is at least a hosted database provided by an entity separate from the client entities, and provides on-demand database service to the client entities. Suggested search results are provided in response to user-generated search query input. The suggested search results are based on monitored usage patterns corresponding to a user and are refined in response to subsequent user-generated search query input. Search results are provided based on the user-generated search query input and/or a user selection from the suggested search results.
US09411906B2	Suggesting and refining user input based on original user input Systems and methods to generate modified/refined user inputs based on the original user input, such as a search query, are disclosed. The method may be implemented for Roman-based and/or non-Roman based language such as Chinese. The method may generally include receiving an original user input and identifying core terms therein, determining potential alternative inputs by replacing core term(s) in the original input with another term according to a similarity matrix and/or substituting a word sequence in the original input with another word sequence according to an expansion/contraction table where one word sequence is a substring of the other, computing likelihood of each potential alternative input, and selecting most likely alternative inputs according to a predetermined criteria, e.g., likelihood of the alternative input being at least that of the original input. A cache containing pre-computed original user inputs and corresponding alternative inputs may be provided.
US09411905B1	Multi-term query subsumption for document classification In general, embodiments of the present invention provide systems, methods and computer readable media for generating an optimal classifying query set for categorizing and/or labeling textual data based on a query subsumption calculus to determine, given two queries, whether one of the queries subsumes another. In one aspect, a method includes generating a group of determining queries based on analyzing text within a document; receiving a group of classifying queries; and, for each determining query within the group of determining queries, determining whether at least one of the classifying queries is subsumed by the determining query; and updating the group of classifying queries in an instance in which the classifying query is subsumed by the determining query.
US09411891B2	Methods and systems for team searches in a social networking service Techniques for team searches within a social graph are described. Consistent with some embodiments, a search request initiated by a searching member profile is received. The search request includes search criteria. A team membership connection between the searching member profile and a team profile is then detected. Based on the detected team membership connection, profile connections between member profiles and teammates of the searching member profile are identified. The teammates are member profiles with team membership connections to the team profile. Then, matching member profiles are identified by matching the member profiles with the identified profile connection with the search criteria. The matching member profiles are then communicated to the searching member profile.
US09411881B2	System and method for high dynamic range audio distribution A transcoding tool for transcoding an audio stream to be played at a playback device is provided. The transcoding tool comprises a receiving section adapted to receive at least one bit stream comprising an audio stream and metadata associated with the audio stream. The transcoding tool further comprises a processing section connected to the receiving section and adapted to create a processed audio stream based on the audio stream and metadata, and a transmitting section connected to the processing section and adapted to transmit the created processed audio stream to the playback device.
US09411876B2	Methods and devices for storing content based on classification options Methods and devices for storing content are described. In one example embodiment, a method includes: displaying, on a display of an electronic device, a plurality of selectable content classification options for classifying a content item, the selectable content classification options including a selectable option to classify the content item as an action item and a selectable option to classify the content item as an archive; receiving, via an input interface associated with the electronic device, a selection of one of the content classification options; and storing the content item in accordance with the selected content classification option.
US09411873B2	System and method for splitting a replicated data partition A system that implements a data storage service may store data on behalf of storage service clients. The system may maintain data in multiple replicas of partitions that are stored on respective computing nodes in the system. The system may split a data partition into two new partitions, and may split the replica group that stored the original partitions into two new replica groups, each storing one of the new partitions. To split the replica group, the master replica may propagate membership changes to the other members of the replica group for adding members to the original replica group and for splitting the expanded replica group into two new replica groups. Subsequent to the split, replicas may attempt to become the master for the original replica group or for a new replica group. If an attempt to become master replica for the original replica group succeeds, the split may fail.
US09411872B1	Management of application state data Disclosed are various embodiments for synchronizing application state information across devices. More specifically, embodiments of the disclosure are related to generating and storing of application state information. Key-value pairs are stored on a client device and synchronized with an application synchronization service.
US09411871B2	Merging data volumes and derivative versions of the data volumes Responsive to an instruction to collapse a derivative version of an ancestor data volume into the ancestor data volume, it is determined if a characteristic of the derivative version of the ancestor data volume satisfies a criteria relative to a characteristic of the ancestor data volume. If the characteristic of the derivative version satisfies the criteria, the ancestor data volume is merged into the derivative version of the underlying data to form an updated derivative version. The updated derivative version is established as the ancestor data volume.
US09411868B2	Passive real-time order state replication and recovery A system and method for passive real-time order state replication and recovery. Upstream data is received from an upstream system via a reliable transport, the upstream data also received by a supported system. Downstream data is received from the supported system via the reliable transport. Data acknowledgements are received from the supported system acknowledging receipt of the upstream and downstream data. A replicated current order state of the supported system is continuously updated in real-time based on the received upstream data, downstream data and the data acknowledgements. A recovery request is received after the supported system has experienced an outage. The current order state is restored to the supported system by transmitting a recovery message to the supported system containing the replicated current order state.
US09411867B2	Method and apparatus for processing database data in distributed database system A method and apparatus for processing database data in a distributed database system, wherein the distributed database system comprises a plurality of computing nodes communicatively coupled via computer networks, the method comprising: creating a plurality of different data replicas wherein each of the data replicas is created in the following way: sorting the database data according to at least one data attribute; generating a row key based on the at least one data attribute; and using the sorted database data with the row key as the data replica, storing different data replicas in different computing nodes; and creating an index for each of the data replicas according to its row key.
US09411865B2	Apparatus, system and method for data collection, import and modeling A method of and system for data analysis, including interrogating a plurality of computer systems to generate for each computer system at least one dump file, each dump file including configuration and state information; extracting predetermined configuration and state information from the respective dump files; and storing the extracted configuration and state information in a database in a normalized format.
US09411863B2	Device and method for distributed database keyword searching A method performed by a mobile communications device, including: populating a central database on the device with a title for each of a plurality of software modules installed on the device and associating each title with its software module; populating the central database with at least one keyword associated with each of the plurality of software modules and associating each keyword with its software module; receiving at the device a search query; displaying at the device a search result identifying at least one of the software modules installed on the device having either a title or one or more associated keywords matching the search query; and in response to receiving at the device a selection of a software module identified in the search result, activating the selected software module.
US09411860B2	Capturing intentions within online text A method of capturing intentions within online text comprises with a data mining device (105), identifying (block 305) a number of statements of intention within an online forum (110), and with the data mining device (105), extracting (block 310) a number of attributes (240, 245, 250, 255, 260) from the statements of intention. A system (100) for extracting intentions expressed within an online forum comprises a data mining device (105), a forum server (115) comprising a number of online forums (110) communicatively coupled to the data mining device (105), in which the data mining device identifies a number of statements of intention within the online forums (110) and extracts a number of attributes (240, 245, 250, 255, 260) from the statements of intention.
US09411857B1	Grouping related entities Methods, systems, and apparatus, including computer programs encoded on computer storage media, for grouping related entities. One of the methods includes receiving a search request that includes query text that identifies a first entity. A first entity node in an entity graph that represents the first entity is identified. A highest ranked first group of related entity nodes from a ranking of a plurality of groups of related entity nodes is identified, wherein each related entity node in the first group is connected to the first entity node by a respective path from the related entity node through one or more links in an entity graph. A presentation of information associated with one or more entity nodes in the first group of related entity nodes is provided.
US09411850B1	Process for embedded intelligence A system for executing an embedded intelligence process comprises an interface and a processor. The interface is for receiving an input object for a business process associated with an embedded intelligence applet. The processor is for searching a database for a set of objects. The set of objects is based at least in part on the input object. The processor is for determining display information for the embedded intelligence applet based at least in part on the set of objects.
US09411848B2	Comparator A method, a data network arrangement and a computer program product, by means of which a comparator can be implemented in a data network, in which comparator a possibility of online chat can also be utilized. The comparator user stores his evaluation of the properties included in the targets being evaluated in a database in the server in the data network by using a graphic one- or two-dimensional evaluation frame. In the comparator the comparator user's evaluations are compared to property values set for each target being evaluated. During the comparison the comparator analyses the data entered into the comparator by the comparator user against predetermined online chat threshold values. If even one online chat threshold value is exceeded, it is in the comparator according to the invention possible to offer the comparator user an online chat with the service provider's customer servant in order to support the decision-making.
US09411847B2	Tracking changes that affect performance of deployed applications An application monitoring infrastructure that enables application configuration changes on multiple machines across multiple OS types to be tracked by identifying data containers that are to be monitored for changes, detecting a change to a monitored data container, and storing data representative of a changed version of the monitored data container responsive to detecting that the monitored container was changed. The data containers that are to be monitored for changes are identified from templates, and a unique template is provisioned for each of the applications.
US09411845B2	Integration flow database runtime The present disclosure describes methods, systems, and computer program products for providing application integration functionality directly on a relational database according to an implementation. One computer-implemented method includes inserting relational data into a start table of a database, detecting a change in the start table, retrieving the inserted relational data from the start table, processing, using a computer, the relational data using a database integration flow runtime into result data, inserting the result data into an end table of the database, detecting a change in the end table, and retrieving the result data from the end table.
US09411840B2	Scalable data structures The technology is directed to providing sequential access to data using scalable data structures. In some embodiments, the scalable data structures include a first data structure, e.g., hash map, and a second data structure, e.g., tree data structure (“tree”). The technology receives multiple key-value pairs representing data associated with an application. A key includes a prefix and a suffix. While the suffixes of the keys are distinct, some of the keys can have the same prefix. The technology stores the keys having the same prefix in a tree, and stores the root node of the tree in the first data structure. To retrieve values of a set of input keys with a given prefix, the technology retrieves a root node of a tree corresponding to the given prefix from the first data structure using the given prefix, and traverses the tree to obtain the values in a sequence.
US09411838B2	Table organization using one or more queries A method, system and computer program product are provided for reorganizing a database table according to a set of queries. More specifically, the table is reorganized such that random I/O is reduced by more tightly grouping together rows in the table associated with each of the referencing queries. This enables more associated rows from a given table relevant to a query to be read into memory for a given I/O operation.
US09411835B1	Method and system for validating data integrity A method of validating data between a first system and at least one second system, wherein the first and second systems have corresponding data volumes, the method comprising isolating first and second data volumes in the first and second systems respectively, wherein the first and second data volumes comprise the corresponding data volumes; generating a checksum for the first and second data volumes; comparing the checksum between the first and second data volumes; and indicating an error if the checksum between the first and second data volumes is different; and inserting results into a database for reporting, for event monitoring or for statistical analysis.
US09411831B2	Photo clustering into moments In one embodiment, a method includes automatically and without user input grouping one or more images captured by a first user into clusters of particular moments based at least in part on metadata associated with one or more of the images or data determined through analysis of one or more of the images. Each particular moment being associated with a particular geo-location and time. The method also includes, for each of one or more of the clusters, determining curating information corresponding to the cluster based at least in part on the metadata associated with images in the cluster, the data determined through analysis of images in the cluster, or social-graph information associated with images in the cluster; and providing the clusters of images and at least some of the curating information corresponding to them for display on a computing device of the first user.
US09411830B2	Interactive multi-modal image search A facility for visual search on a mobile device takes advantage of multi-modal and multi-touch input on the mobile device. By extracting lexical entities from a spoken search query and matching the lexical entities to image tags, the facility provides candidate images for each entity. Selected ones of the candidate images are used to construct a composite visual query image on a query canvas. The relative size and position of the selected candidate images in the composite visual query image, which need not be an existing image, contribute to a definition of a context of the composite visual query image being submitted for context-aware visual search.
US09411823B1	Handheld medical imaging mobile modality A method of acquiring medical image data for a subject having a subject medical record and subject identifying information includes capturing medical image data related to the subject with a mobile wireless-communication optical-imaging device. The mobile wireless-communication optical-imaging device includes an optical imaging component, an input component, and a wireless two-way communication component. The method also includes providing a program that includes a program includes a request for subject identifying information, providing the subject identifying information in said program, and wirelessly transmitting data derived from the medical image data and the subject identifying information from the mobile wireless-communication optical-imaging device to a second device. The second device is separate from the mobile wireless-communication optical-imaging device.
US09411820B2	Methods and systems for modeling a replication topology Methods and systems for modeling a replication topology involve, for example, representing a plurality of replication components of a replication topology in a first binary matrix using a processor coupled to memory and generating a result matrix based at least in part on the first binary matrix likewise using the processor. Thereafter, also using the processor, replication components of the replication topology may be identified that are either enabled or non-enabled to receive replications from other replication components of the replication topology based at least in part on the result matrix.
US09411816B2	Maintaining channels lists A method is provided for maintaining a list of content channels that a user of a multi-channel content service subscribes to or has followed, and a client device for operation by the user to receive the content. If a list on the user's device has been modified, the device (e.g., an applet provided by the service) informs a synchronization server by uploading the list. The server synchronizes it with a master list and downloads a copy to the device. A channels list includes an entry for each channel the user follows (and possibly channels he has deleted), which includes an index or ordinal position of the channel among all the user's channels, an identifier of the channel (e.g., a URL), identifiers of sub-lists the channel has been assigned to, and a timestamp identifying the last time the entry changed (e.g., when the channel was added, removed, assigned to a sub-list).
US09411809B1	Remote content presentation queues Systems, methods, and computer-readable media are disclosed for generating, storing, and managing play queues remotely from a user device on which content associated with the play queues may be played. A client application executing on a user device may transmit a request to generate a remote play queue to a remote server. The request may include an indication one or more sources for the content and may optionally include an indication of the content to associate with the play queue. The remote server may access metadata associated with a subset of the content of the play queue and transmit the metadata to the client application, thereby allowing retrieval and playback of the content on the user device.
US09411806B2	Optimizing relational database queries with multi-table predicate expressions Responding to relational database queries (for example, SQL queries) in a new way. More specifically, qualifying queries are written (for example, written by a human individual) in a way so that a join operation precedes a row limiting operation. Notwithstanding the fact that the join operation precedes the row limiting operation, when responding to the query, machine logic (for example, software) performs the row limiting operation before the join operation. This can improve time and processing efficiency.
US09411803B2	Responding to natural language queries Disclosed herein are a system, non-transitory computer-readable medium, and method for responding to natural language queries. Keywords likely to appear in a natural language query are determined and each likely keyword is associated with a module. A response to a natural language query comprises information generated by each module associated with a likely keyword appearing in the natural language query.
US09411802B2	Method for labeling semantic role of bilingual parallel sentence pair Methods for Semantic Role Labeling (SRL) of bilingual sentence pairs. Steps in this invention include tokenizing and part-of-speech tagging a bilingual sentence pair, performing word alignments on the bilingual sentence pair, finding word-aligned predicate pairs in the bilingual sentence pair, generating argument candidates for each predicate using monolingual SRL system, and performing joint inference to obtain the SRL results and argument alignment for each predicate pair. This method produces more accurate SRL results on both sides of bilingual sentence pairs. Furthermore, this method also aligns the predicate-argument structures between the sentence pairs.
US09411795B2	Content placement A content placement method includes electronically identifying a placeholder image in an electronic document. The placeholder defines a copy hole. The placeholder image is decoded to discern content selection data. The content selection data is processed to identify content that is inserted into the copy hole.
US09411790B2	Systems, methods, and media for generating structured documents Systems, methods, and media for generating structured documents are provided herein. Methods may include receiving digital source content, the digital source content having source data elements where each source data element includes one or more attributes, determining the one or more attributes for each of the source data elements, tagging each of the source data elements with an identifier based upon their one or more attributes, the identifier defining a function for a particular source data element with a structured document, and generating a structured document from the tagged source data elements.
US09411785B1	Embedding hidden content in unicode A method, apparatus, and system relating to embedding hidden content within a Unicode message and using the hidden content to perform a particular computer action.
US09411782B2	Real time web development testing and reporting system Elements of the geometry of the image of a webpage as rendered on at least one target browser are compared with elements of a baseline geometry of the webpage to determine the differences between elements of the baseline geometry of the webpage and elements of the respective geometries of the image of the webpage as rendered on the at least one target browser. The elements of the image may be determined by a software tool for determining elements of a document geometry, such as a DOM geometry service. Code such as JavaScript may be injected into the webpage for use in determining the elements of the geometry of the image of the webpage. A list of issues that web developers face may be generated and the above differences between respective elements may allow arriving at a solution for at least some of the issues in order to provide testing of webpage information in real time.
US09411780B1	Employing device sensor data to determine user characteristics Techniques are described for determining height, weight, or other characteristics of a user based on processed sensor data. The sensor data may include data collected by sensors on the user's computing device or other computing devices, or data collected by stationary, external sensors. Different types of sensor data may be processed to estimate at least one physical characteristic of the user, such as the user's height, weight, apparel size, age, and so forth. The estimated characteristics may be employed to perform actions based on the user's identity or category, to customize content delivery for the user, or for other purposes.
US09411779B2	Method of dispensing material based on edge detection A dispensing system for depositing material on an electronic substrate includes a frame, a dispensing unit gantry movably coupled to the frame, a dispensing unit coupled to the dispensing unit gantry, a vision system gantry coupled to the frame, and a vision system coupled to the vision system gantry. A controller is configured to manipulate the vision system with the vision gantry system to move to the position defined by a feature, to acquire an image of at least a portion of a feature, to search for an edge of interest along a center of the image, and to return a value indicating an offset of zero (0), which is interpreted as the location that is exactly as expected, and an offset that reflects where the edge of interest intersected that axis location.
US09411776B2	Separation of data and control in a switching device A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path.
US09411775B2	iWARP send with immediate data operations Apparatus, methods and systems for supporting Send with Immediate Data messages using Remote Direct Memory Access (RDMA) and the Internet Wide Area RDMA Protocol (iWARP). iWARP logic in an RDMA Network Interface Controller (RNIC) is configured to generate different types of Send with Immediate Data messages, each including a header with a unique RDMA opcode identifying the type of Send with Immediate Data message, and send the message to an RDMA remote peer using iWARP implemented over an Ethernet network. The iWARP logic is further configured to process the Send with Immediate Data messages received from the RDMA remote peer. The Send with Immediate Data messages include a Send with Immediate Data message, a Send with Invalidate and Immediate Data message, a Send with Solicited Event (SE) and Immediate Data message, and a Send with Invalidate and SE and Immediate Data message.
US09411773B2	First and second data communication circuitry operating in different states Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.
US09411772B2	Multi-protocol serial nonvolatile memory interface An electronic device including a multi-protocol serial nonvolatile memory interface is disclosed. The interface includes: a first line operative to perform functions of a first chip select line when the interface operates as a SPI of the electronic device; a second line operative to perform functions of a second chip select line when the interface operates as the SPI of the electronic device; a third line operative to perform functions of a clock line when the interface operates as either the SPI or an I2C interface of the electronic device, and a fourth line configured to perform functions of a mast-out-slave-in (MOSI) line and a master-in-slave-out (MISO) line when the interface operates as the SPI of the electronic device, the fourth line further operative to perform functions of a serial data line when the interface operates as the I2C interface of the electronic device.
US09411770B2	Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.
US09411767B2	Flash controller to provide a value that represents a parameter to a flash memory An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.
US09411766B2	Single optical fiber KVM extender Single Optical Fiber KVM (Keyboard Video Mouse) systems are provided that comprises of two subsystems: an electro-optical transmitter subsystem and an electro-optical receiver subsystem. The single optical fiber KVM is configured to support all required bi-directional communications.
US09411765B2	Methods of using a peripheral component interconnect express (PCIE) device in a virtual environment Methods of using a peripheral component interconnect express (PCIe) device in a virtual environment are disclosed. Two operating systems operate on a primary device. One operating system acts as a guest in a virtual environment within the primary device. A peripheral device is coupled to the primary device through a wireless connection. In an exemplary embodiment, the wireless connection is a PCIe bridge. The host operating system interfaces directly with the memory elements and hardware of the primary device. The guest operating system interoperates with the memory elements and hardware of the peripheral device. The use of the PCIe wireless link allows the guest operating system to interface with the elements of the peripheral device with relatively little latency.
US09411760B2	System and method for a thin-client terminal system with a local screen buffer using a serial bus In a system and method for a thin-client terminal system having a local screen buffer using a serial bus, a serial bus interface device receives encoded data from a thin-client server system. The serial bus interface device decodes the encoded data according to a serial bus data format and provides the decoded data to a thin-client control system. The thin-client control system distributes the decoded data for processing to a video processing system, an audio processing system, and an input/output control system. The thin-client control system also receives input data from input devices connected to the thin-client terminal system. The input data is processed and encoded according to the serial bus data format for transmission to the thin-client server system.
US09411759B2	Coupling a specialty system, such as metering system, to multiple control systems A metering system configured to couple to multiple specialty systems, such as a control system. At least some of the illustrative embodiments are processing units comprising a processor, a memory coupled to the processor, and a communication port configured to coupled to a backbone communication network of a control system. The memory stores a program that causes the processor to selectively participate (over the communication port) as a processing unit of a control system of a first manufacturer (the control system implements a first proprietary communication protocol between processing units), and to participate (over the communication port) as a processing unit of a control system of a second manufacturer different than the first manufacturer (the control system of the second manufacturer implements a second proprietary communication protocol between the processing units).
US09411754B2	Dynamic frequency memory control A memory controller (40) is adaptable to scaling of a system clock frequency, to enable another device (10) to access a memory (20), and has a part for outputting control signals having some timing characteristics not entirely scalable with scaling of the system clock frequency. In response to an indication of a change in a frequency of the system clock, the memory controller adapts the part autonomously to enable it to output new digital memory control signals synchronized to the changed system clock and which also have the non scalable timing characteristics. This avoids the need for the processor to adapt the memory controller. Hence the adaptation can be carried out more quickly, leading to less disruption to other parts of the system and means the frequency scaling can be carried out more often.
US09411752B2	Conversion device, peripheral device and programmable logic controller An A/D conversion device includes an input-data storage unit storing therein a plurality of digital values obtained after A/D conversion so that each of the digital values is positioned at a fixed address according to a delay amount, a coefficient-data storage unit, a coefficient-data computation unit that, when a digital-filter process performing request is inputted, calculates an order and a filter coefficient based on a filter characteristic set beforehand, arranges calculated filter coefficients in order of delay amount, respectively, and stores the filter coefficients in the coefficient-data storage unit so that each filter coefficient is positioned at a fixed address according to the corresponding delay amount, and a digital-filter computation unit respectively reading a digital value from the input-data storage unit and a filter coefficient from the coefficient-data storage unit for each delay amount and performing a filter computation based on the read values for each delay amount.
US09411751B2	Key formation Key formation techniques are described. In one or more implementations, an input device includes a key assembly including a plurality of keys that are usable to initiate respective inputs for a computing device, a connection portion configured to be removably connected to the computing device physically and communicatively to communicate signals generated by the plurality of keys to the computing device, and an outer layer that is configured to cover the plurality of keys of the key assembly, the outer layer having a plurality of areas that are embossed thereon that indicate one or more borders of respective said keys.
US09411750B2	Efficient calibration of a low power parallel data communications channel A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.
US09411748B2	Secure replay protected storage Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such that it may be protected against user attacks—e.g., replacing the SPI flash memory device or a man-in-the-middle (MITM) attack to modify the SPI flash memory contents on the fly. In the prior art, monotonic counters cannot be stored in SPI flash memory devices because said devices do not provide replay protection for the counters. A user may also remove the flash memory device and reprogram it. Host platforms alone cannot protect against such hardware attacks.Embodiments of the invention enable secure standard storage flash memory devices such as SPI flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and HMAC key logic to create secure execution environments for various components.
US09411741B2	System and method for application level caching The disclosure generally relates to methods and systems for application level caching and more particularly to dynamically applying caching policies to a software application. In one embodiment, an application level caching method, comprising: monitoring, using a utility executed by a processor, run-time data access operations corresponding to an application; identifying, using the processor, at least one characteristic associated with the run-time data access operations; triggering, using the processor, a caching rule based on the at least one characteristic associated with the run-time data access operations; and providing, using the processor, a memory access instruction according to the caching rule.
US09411732B2	Push-based cache invalidation notification In one embodiments, one or more first computing devices receive updated values for user data associated with a plurality of users; and for each of the user data for which an updated value has been received, determine one or more second systems that each have subscribed to be notified when the value of the user datum is updated and each have a pre-established relationship with the user associated with the user datum; and push notifications to the second systems indicating that the value of the user datum has been updated without providing the updated value for the user datum to the second systems.
US09411730B1	Private memory table for reduced memory coherence traffic A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.
US09411726B2	Low power computation architecture An embodiment includes a system, comprising a first memory; a plurality of first circuits, wherein each first circuit is coupled to the memory; and includes a second circuit configured to generate a first output value in response to an input value received from the first memory; and an accumulator configured to receive the first output value and generate a second output value; and a controller coupled to the memory and the first circuits, and configured to determine the input values to be transmitted from the memory to the first circuits.
US09411717B2	Metadata journaling with error correction redundancy Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, user data and associated metadata are stored in a memory. The metadata are arranged as a first sequence of snapshots of the metadata at different points in time during the operation of the memory, and a second sequence of intervening journals which reflect updates to the metadata from one snapshot to the next. Requested portions of the metadata are recovered from the memory using a selected snapshot in the first sequence and first and second journals in the second sequence.
US09411716B2	System and method for controlling automated page-based tier management in storage systems System and method for automated page-based management in storage systems. The system includes host computers, file servers and a storage system having automated page-based management means. The storage system interface receives instructions to change the condition for decision for migration regarding particular parts or the whole volume. The host computer can control execution of the migration performed by the storage system by specifying areas or volumes with the condition via the interface. Highly optimized, appropriate data placement and data relocation in computer system can be achieved when the application, host computer or management computer can recognize or predict the usage of the data or files. The storage system having automated page-based management may include compression/decompression and a control method for the compression and decompression process.
US09411715B2	System, method, and computer program product for optimizing the management of thread stack memory A system, method, and computer program product for optimizing thread stack memory allocation is disclosed. The method includes the steps of receiving source code for a program, translating the source code into an intermediate representation, analyzing the intermediate representation to identify at least two objects that could use a first allocated memory space in a thread stack memory, and modifying the intermediate representation by replacing references to a first object of the at least two objects with a reference to a second object of the at least two objects.
US09411710B2	Automated regression test case selector and black box test coverage tool for product testing A method for testing a computer application includes identifying components of a version of the application, said components including one or more components that are one of new and modified, generating a keyword matrix of the identified application components. A search is performed in a test script repository with respect to components listed as at least one of the first and second dimensions of the matrix. The keyword matrix is populated with test case identification numbers in the search result. Based on the populated keyword matrix, one or more of (a) gaps in test case coverage for the version of the application, and (b) one or more test cases covering the version of the application are identified.
US09411708B2	Systems and methods for log generation and log obfuscation using SDKs This disclosure generally relates to application development platforms, and more particularly to systems and methods for log generation and log obfuscation using software development kits (SDKs). In one embodiment, an application logging configuration method is disclosed, comprising: obtaining, for an application, a developer-specific log generation schema specifying at least a developer-specific set of variables to be logged and associated code line numbers; obtaining a developer-independent log generation schema specifying at least a developer-independent set of variables to be logged and associated code line numbers; extracting the specifications of the developer-specific and developer-independent sets of variables to be logged and associated code line numbers; generating an application logging schema specifying at least a combination of the developer-specific and developer-independent sets of variables to be logged and associated code line numbers; and storing the application logging schema.
US09411706B1	Suggesting candidate removable software dependencies Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generated aggregated dependencies between software elements in a code base. One of the methods includes determining that a cycle exists in the aggregated dependency graph, determining which of the links in the cycle has a lowest weight, and adding a first link in the cycle having the lowest weight to a set of candidate removable links. The links in the set of candidate removable links are classified as candidate removable links, and a user interface presentation is provided that presents the aggregated dependency graph and which visually distinguishes removable links from other links in the aggregated dependency graph.
US09411704B2	Computer systems and methods of detecting AC failure A computer system that includes a power supply unit that generates at least one secondary supply voltage (Vcc) and an auxiliary voltage (Vaux) based on an AC supply voltage (VAC), and a system board electrically connected to the power supply unit, the system board comprising a sequencing microcontroller that selectively activates further components of the system board, the further components comprising a chipset, wherein the sequencing microcontroller is configured to monitor the state of at least one control signal of the power supply unit and/or the system board to detect a failure of the AC supply voltage (VAC) and signal the failure of the AC supply voltage (VAC) to at least the chipset.
US09411694B2	Correcting recurring errors in memory The present disclosure includes apparatuses and methods for correcting recurring errors in memory. A number of embodiments include determining whether a first subset of a group of memory cells has a recurring error associated therewith using a second subset of the group of memory cells, and responsive to a determination that the first subset of the group of memory cells has a recurring error associated therewith, correcting the recurring error using the second subset of the group of memory cells.
US09411691B2	Virtual machine disaster recovery A method, article of manufacture, and apparatus for protecting data. In some embodiments, this includes creating a copy of a backup virtual machine on a deduplicated data storage device, registering the copy with a virtual environment manager, operating a virtual machine based on the copy and storing changes made during operation of the virtual machine to the copy.
US09411689B2	Method and relevant apparatus for starting boot program A method and a relevant apparatus for starting a boot program are provided. The method includes: when a boot request is detected, determining whether a first physical block in a NAND flash is a bad block; reading first boot data stored in the first physical block if the first physical block is not a bad block; determining whether the read first boot data has a data error; re-reading the first boot data from a first backup block when the read first boot data has a data error; determining whether the first boot data that is re-read from the first backup block has a data error; when the first boot data that is re-read from the first backup block has no data error, continuing to process other boot data that needs to be read to start the boot program, until start of the boot program is complete.
US09411688B1	System and method for searching multiple boot devices for boot images In some disclosed implementations, a system-on-chip on a first IC die includes a boot loader circuit configured to search a first boot device, of a plurality of boot devices coupled to and external to the first IC die, for an uncorrupt boot image. The boot loader circuit is configured to search a second boot device of the plurality of boot devices for an uncorrupt boot image, in response to failing to find an uncorrupt boot image in the first boot device. The boot loader is also configured to load a set of instructions included in the uncorrupt boot image into a memory circuit of the SOC, in response to finding an uncorrupt boot image.
US09411682B2	Scrubbing procedure for a data storage system A method is provided for scrubbing information stored in a data storage system where the information is stored as a plurality of encoded fragments across multiple storage devices. The method includes maintaining on a first storage device a list of metadata entries corresponding to values that are stored in the data storage system at an At Maximum Redundancy (AMR) state, verifying that encoded fragments associated with each of the metadata entries are stored on a second storage, verifying that a corresponding metadata entry is stored on the first storage device for each encoded fragment that is stored on the second storage device, and scheduling for recovery any missing encoded fragments and/or any missing metadata entry.
US09411675B2	Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword-to-codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities can be performed.
US09411673B2	Management server, management system, and management method It is provided a management server is configured to store an access log including a monitoring subject ID, or a monitoring item ID when a request for outputting a historical data is inputted, an incident data including a time, a monitoring subject ID, or a monitoring item ID when an incident indicating a failure in the each of the devices; associate the incident data with the access log; update data included in the access log to a string of characters abstracted; generate an abstract access log; identify first abstract access log from the generated abstract access log based on the first incident data when a value indicating first incident data is inputted; identify a condition for the historical data to be outputted based on the first abstract access log and the first incident data; and output the identified condition for the historical data.
US09411668B2	Approach to predictive verification of write integrity in a memory driver A subsystem is configured to apply an offset voltage to a test, or canary, SRAM write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary SRAM circuit. The subsystem then calculates a probability of failure for the actual, non-test SRAM write operation, which is performed by an equivalent driver circuit with zero offset. The subsystem then compares the result to a benchmark acceptable probability figure. If the calculated probability of failure is greater than the benchmark acceptable probability figure, corrective action is initiated. In this manner, actual failures of SRAM write operations are anticipated, and corrective action reduces their occurrence and their impact on system performance.
US09411647B2	Hierarchical routing and interface selection for multi-processor multimode network devices The embodiments simplify the development of applications for current and future wireless communication devices, resolving the deficiencies of current methods by providing a hierarchical routing layer which abstracts the actual proximity of the network connection. An application can request and receive a type of network connection without having to address details of the actual connection established. A hierarchical routing layer is provided within the software architecture of each processor within the computing device. The hierarchical routing layer abstracts the actual proximity of the network connectivity on the modem from the applications using proxy network interfaces. The hierarchical routing layers on each processor cooperate to identify a best network interface for an application network request. The routing layer enables response to an application request for a network interface in a simple manner regardless of whether the network interface is provided on the application host processor or another processor.
US09411644B2	Method and system for work scheduling in a multi-chip system According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to a another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices.
US09411643B2	Method of performing tasks on a production computer system and data processing system A method of performing tasks on a production computer includes retrieving a one task description file stored on a task computer and containing a description of a task on a production computer, transferring the task description file from the task computer to a production computer, causing the production computer to check that the file is associated with at least one task stored on the production computer, performing the task associated with the file in the production computer using the file, if the association check was successful, wherein the task computer has open ports and the production computer keeps the ports closed so that access by a user of a first user group to the task computer is arranged, but access by a user of the group to the production computer is prevented while steps above are performed in a predetermined operating state of the production computer.
US09411637B2	Adaptive process importance A method and apparatus of a device that changes the importance of a daemon process is described. In an exemplary embodiment, the device receives a message from a user process destined for daemon process, wherein the daemon process executes independently of the user process and the first daemon process communicates messages with other executing processes. The device further determines if the first message indicates that the importance of the first daemon process can be changed. If the first message indicates the importance of the first daemon process can be changed, the device changes the importance of the first daemon process. The device additionally forwards the first message to the first daemon process.
US09411632B2	Parallel method for agglomerative clustering of non-stationary data The disclosure is directed to clustering a stream of data points. An aspect receives the stream of data points, determines a plurality of cluster centroids, divides the plurality of cluster centroids among a plurality of threads and/or processors, assigns a portion of the stream of data points to each of the plurality of threads and/or processors, and combines a plurality of clusters generated by the plurality of threads and/or processors to generate a global universe of clusters. An aspect assigns a portion of the stream of data points to each of a plurality of threads and/or processors, wherein each of the plurality of threads and/or processors determines one or more cluster centroids and generates one or more clusters around the one or more cluster centroids, and combines the one or more clusters from each of the plurality of threads and/or processors to generate a global universe of clusters.
US09411618B2	Metadata-based class loading using a content repository An example method of loading classes from a content repository includes storing a set of files in a content repository. The set of files includes a representation of a set of classes. The method also includes extracting first metadata that describes the set of classes and storing the first metadata in a content repository. The method further includes receiving a request including second metadata corresponding to one or more classes of the set of classes. The request is from a repository-class loader executable in a node. The method also includes selecting, based on the second metadata, a class of the set of classes. The method further includes sending the selected class to the repository-class loader for loading into the node.
US09411617B2	System and method for matching synthetically generated inner classes and methods A system and method for transforming name synthesized classes in response to dynamic class updates to existing classes, featuring the ability to provide replacement synthetic names for reloaded name synthesized classes. According to a preferred embodiment, the name synthesized classes are anonymous classes. The method stores and tracks the synthetic names for each name synthesized class as they are loaded or reloaded, intercepting the loading of the classes before being defined in a virtual machine. Then, the method maps the synthetic name of the name synthesized classes for each dynamic class update to replacement synthetic names of previously loaded name synthesized classes. In addition, the concepts of the invention are applicable to other types of name synthesized classes, such as local classes, bridge methods and lambda expressions.
US09411614B2	Input/output devices having reconfigurable functionality Systems and methods provide re-configurable functionality within components of I/O devices without the need of disconnecting the components from each other. For example, in certain embodiments, when certain types of components are connected to each other, certain functionality sets within the components may be activated to provide combined functionality sets between the components. The combined functionality sets may, for example, be preferred functionality sets to be used when the particular types of components are connected to each other. Furthermore, in certain embodiments, functionality activation keys may be physically inserted into (or electronically communicated to) the components of the I/O device to activate certain functionality sets within the component into which the functionality activation key is inserted (or electronically communicated to), as well as within the other components of the I/O device to which the component is connected.
US09411610B2	Server, screen control method, and screen transition method for effectively displaying screens on a terminal device A terminal device, a server, a screen control method, a screen transition method, and a compute program are provided. The terminal device includes a display unit, plural operation units, a storage unit, and a control unit, and communicates with a server for making a transition of a screen on the display unit. The storage unit stores template information associating an operation unit with a transition instruction for instructing screen transition. The control unit receives instruction information representing any of transition instructions, from the server, and validates an operation unit associated with a transition instruction represented by the received instruction information and transmits operation information representing that the validated operation unit is operated, to the server. The control unit receives new instruction information transmitted from the server, and validates an operation unit associated with a transition instruction represented by the new instruction information.
US09411608B2	Method and apparatus for enhancing a hibernate and resume process for a computing device having an external mechanical input component Before hibernating a computing device (102), system software components (116) are notified of an upcoming hibernation process. The notifications are conveyed through an application program interface (API) (114). At least a portion of the system software components (116) can perform one or more pre-hibernation activities to place that system software component (116) in a ready-to-resume state. Each system software component indicates when it is ready for hibernation. Responsive to receiving the indication from each of the system software components (116), the hibernation process can complete. The completed hibernation process creates a snapshot (122) in nonvolatile memory. The snapshot (122) saves state information (124) for each of the system software components (116). The state information (124) is for the ready-to-resume state of the system software components (116). The computing device (102) can be restored after hibernation using a resume process (130), which reads the state (124) information from the snapshot (122).
US09411603B2	Chip and starting method thereof A starting method including, after being powered on, obtaining, by a central processing unit (CPU), a boot image file, where the boot image file includes universal boot code and differentiating boot code, the universal boot code is obtained by compiling a universal part in boot code of different chips, the universal boot code includes a first boot code segment and a second boot code segment; reading the first boot code segment from the boot image file, running the first boot code segment, and reading indication information of the differentiating boot code; reading, from the boot image file, the differentiating boot code according to the indication information of the differentiating boot code, and running the differentiating boot code; and running the second boot code segment, to complete booting of the chip to which the CPU belongs.
US09411600B2	Instructions and logic to provide memory access key protection functionality Instructions and logic provide memory key protection functionality. Embodiments include a processor having a register to store a memory protection field. A decoder decodes an instruction having an addressing form field for a memory operand to specify one or more memory addresses, and a memory protection key. One or more execution units, responsive to the memory protection field having a first value and to the addressing form field of the decoded instruction having a second value, enforce memory protection according to said first value of the memory protection field, using the specified memory protection key, for accessing the one or more memory addresses, and fault if a portion of the memory protection key specified by the decoded instruction does not match a stored key value associated with the one or more memory addresses.
US09411595B2	Multi-threaded transactional memory coherence The disclosure provides systems and methods for maintaining cache coherency in a multi-threaded processing environment. For each location in a data cache, a global state is maintained specifying the coherency of the cache location relative to other data caches and/or to a shared memory resource backing the data cache. For each cache location, thread state information associated with a plurality of threads is maintained. The thread state information is specified separately and in addition to the global state, and is used to individually control read and write permissions for each thread for the cache location. The thread state information is also used, for example by a cache controller, to control whether uncommitted transactions of threads relating to the cache location are to be rolled back.
US09411591B2	Run-time instrumentation sampling in transactional-execution mode Embodiments of the invention relate to implementing run-time instrumentation sampling in transactional-execution mode. An aspect of the invention includes determining, by a processor, that the processor is configured to execute instructions of an instruction stream in a transactional-execution mode, the instructions defining a transaction. Completion of storage operations of the instructions is interlocked to prevent instruction-directed storage until completion of the transaction. A sample point is recognized during execution of the instructions while in the transactional-execution mode. Run-time-instrumentation-directed storing is performed, upon successful completion of the transaction, run-time instrumentation information obtained at the sample point.
US09411590B2	Method to improve speed of executing return branch instructions in a processor An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness.
US09411588B2	Conditional transaction end instruction A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.
US09411587B2	Method of prefetch optimizing by measuring execution time of instruction sequence cycling through each selectable hardware prefetch depth and cycling through disabling each software prefetch instruction A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the instruction sequence of interest when different prefetch instructions are disabled. The tool may hold hardware prefetch depth constant while cycling through disabling different prefetch instructions and taking corresponding execution time measurements. Alternatively, for each disabled prefetch instruction in the instruction sequence of interest, the tool may cycle through different hardware prefetch depths and take corresponding execution time measurements at each hardware prefetch depth. The tool selects a combination of hardware prefetch depth and prefetch instruction disablement that may improve the execution time in comparison with a baseline execution time.
US09411584B2	Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data fields to store a variable second plurality of bits to store a conflict mask having a mask bit for each offset. Responsive to decoding a vector conflict instruction, execution units compare the offset in each data field with every less significant data field to determine if they hold a matching offset, and in corresponding conflict masks in the destination register, set any mask bits corresponding to a less significant data field with a matching offset. Vector address conflict detection can be used with variable sized elements and to generate conflict masks to resolve dependencies in gather-modify-scatter SIMD operations.
US09411582B2	Apparatus and method for processing invalid operation in prologue or epilogue of loop An apparatus for processing an invalid operation in a prologue and/or an epilogue of a loop includes a register file including a first region for storing a data validity value indicating whether data is valid or invalid, and a second region for storing the data; and a functional unit configured to determine whether an operation is valid or invalid based on a value of a first region of each of one or more input sources received from the register file, and output a destination including a value based on the value of the first region of each of the input sources.
US09411576B2	Software version management for executing replacement actions A software version management system comprising a host driver and at least one software module. The host driver comprises migration means to start, stop and replace the software modules on a computer system in response to replacement actions. The system is characterized by the software module being a downgradable software module comprising a compatibility database specifying dependencies between different versions of the software module; the migration means further comprising i) at least a status means to retrieve temporal information from the downgradable software module; ii) at least a downgrading means responsive to a replacement action to downgrade the downgradable software module to a particular downgrade version and to the status means, the downgrading means identifying an intermediate version of the downgradable software module; the host driver comprising restarting means responsive to the report of the completion of the intermediate version to load and start the downgrade version of the software module.
US09411575B2	Systems and methods for quality assurance automation A method and a system for quality assurance automation are described. A system comprises a requirements service to generate requirements artifacts from one or more sources. The requirement artifacts are of a standardized format that is referenced in tested software code. A data provider service standardizes and distributes various types of common test data across multiple business disciplines. An execution service manages test executions across and multiple environments where test software code is installed. An evaluation service analyzes data resulting from the test executions. A reporting service reports the analyzed data.
US09411569B1	System and method for providing a climate data analytic services application programming interface distribution package A system, method and computer-readable storage devices for providing a climate data analytic services application programming interface distribution package. The example system can provide various components. The system provides a climate data analytic services application programming interface library that enables software applications running on a client device to invoke the capabilities of a climate data analytic service. The system provides a command-line interface that provides a means of interacting with a climate data analytic service by issuing commands directly to the system's server interface. The system provides sample programs that call on the capabilities of the application programming interface library and can be used as templates for the construction of new client applications. The system can also provide test utilities, build utilities, service integration utilities, and documentation.
US09411563B2	Notification-based constraint set translation to imperative execution A method is provided for translating sets of constraint declarations to imperative code sequences based on defining an instantiatable object per set, inserting calls to a notification callback mechanism on state modification and defining calls in the constraint context as imperative code sequences that, in response to these callbacks, take actions to maintain these constraints.
US09411562B2	Inter-application transform builder for cloud applications A method, system, and computer program product for customization of flows between software applications. A system implementation commences by associating a first application with a first graphical object descriptor, and by associating a second application with a second graphical object descriptor. A graphical user interface such as an integrated development environment is used to drag/drop the graphical object descriptors and other graphical objects to form logical connections between the first graphical object descriptor and the second graphical object descriptor. The installation of an application is modified (e.g., using a patch), which modification is performed based at least in part on the logical connections. The logical connections between the applications handles inter-application communication such that upon executing the modified first application at least some outputs from the modified first application are processed using the logical connection to produce modified first application results which are in turn received by the second application.
US09411559B2	Resolution of textual code in a graphical hierarchical model of a technical computing environment A device may receive a chart generated via a technical computing environment, where the chart includes a textual portion and a graphical portion, and the graphical portion includes state information. The device may parse the chart into the textual portion and the graphical portion, and may process the textual portion with a textual engine of the technical computing environment to generate textual results. The device may process the graphical portion with a graphical engine of the technical computing environment to generate graphical results, and may combine the textual results with the graphical results to generate chart results. The device may output or store the chart results.
US09411558B2	Systems and methods for parallelization of program code, interactive data visualization, and graphically-augmented code editing A system for providing a computer configured to read an immutable value for a variable; read the value of the variable at a specific timestamp, thereby providing an ability to create looping constructs; set a current or next value of a loop variable as a function of previous or current loop variable values; read a set of all values that a variable will assume; push or scattering the values into unordered collections; and reduce the collections into a single value.
US09411556B1	Template dependency inlining Methods, systems, and apparatus, including computer programs encoded on computer storage media, for inlining software dependencies. One of the methods includes receiving data representing dependencies between software elements in a project, wherein the plurality of software elements includes a first software element that includes a usage of a template parameterized by a type, a second software element that is or occurs within a definition of the template, and a third software element. If the dependencies include a first dependency of the first software element on the second software element, and a second dependency of the second software element on the third software element, the second dependency is removed and a new dependency is generated of (i) the first software element on (ii) the third software element.
US09411554B1	Signed multiplier circuit utilizing a uniform array of logic blocks A signed multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each of the logic blocks is programmable to implement any of four multiply functions of first and second inputs, in which: the first and second inputs are both signed; the first and second inputs are both unsigned; the first input is signed and the second input is unsigned; and the first input is unsigned and the second input is signed. Each logic block includes rows and columns of sub-circuits, e.g., logical AND gates and full adders. One row and one column of each logic block include a programmably invertible AND gate, with the row and column being independently controlled. The ability to program the logic block to perform all four of these functions enables the combination of rows and columns of the logic blocks to build large signed multipliers of virtually any size.
US09411544B2	Printing apparatus and print control method controlling printing based on acquired information relating to conveyance of a print medium There is provided a printing apparatus for conveying a print medium and performing printing on the conveyed print medium, the printing apparatus including a print data acquisition unit configured to acquire print data in which digital watermark information is added to image data, the digital watermark information being used to identify a position of an image of the image data on a print medium, a printing unit configured to print an image on a print medium based on the print data, a conveyance information acquisition unit configured to acquire information relating to conveyance of a print medium, based on information on the position of the image that is obtained by detection of digital watermark information in an image read by a reading unit, and a print control unit configured to control printing by the printing unit, based on the acquired information relating to conveyance.
US09411542B2	Interruptible store exclusive In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.
US09411541B1	Adjustment of volume synchronization Embodiments of the present invention provide systems and methods for adjusting synchronization rates of volumes. Volumes and their copies (i.e., mirrored volumes) provide physical or virtual storage on a data storage medium. Depending on the function (i.e., the purpose) of mirrored volumes, a certain synchronization rate is recommended. Embodiments of the present invention provide systems and methods for an automatic dynamic adjustment of individual synchronization rates by adapting to changes in system workloads in order to avoid degradation of user-driven input/output (IO) and to efficiently achieve nearly 100% synchronization for all mirrored volumes.
US09411540B2	Efficient connection management in a SAS target A method includes pre-configuring a hardware-implemented front-end of a storage device with multiple contexts of respective connections conducted between one or more hosts and the storage device. Storage commands, which are received in the storage device and are associated with the connections having the pre-configured contexts, are executed in a memory of the storage device using the hardware-implemented front-end. Upon identifying a storage command associated with a context that is not pre-configured in the hardware-implemented front-end, software of the storage device is triggered to configure the context in the hardware-implemented front-end, and the storage command is then executed using the hardware-implemented front-end in accordance with the context configured by the software.
US09411538B2	Memory systems and methods for controlling the timing of receiving read data Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.
US09411537B2	Embedded multimedia card (EMMC), EMMC system including the EMMC, and method of operating the EMMC An embedded multimedia card (eMMC), and a method of operating an eMMC, determine whether a vendor mode is to be entered by parsing a command argument of a command received from a host or a pattern of write data received from the host; receive vendor mode attribute information for the vendor mode, based on a result of determining whether the vendor mode is to be entered; and performing a vendor mode operation in the vendor mode based on the vendor mode attribute information.
US09411530B1	Selecting physical storage in data storage systems A method is used in selecting physical storage in data storage systems. A request for allocation of a portion of storage area of a data storage system is received from a requesting entity. The data storage system is comprised of a set of storage entities and a set of data buses for transferring data to and from the set of storage entities. The set of storage entities are organized into a set of logical units. Each logical unit of the set of logical units is subdivided into a set of slices. A slice is selected from a logical unit of the set of logical units for allocation for use by the requesting entity in response to receiving the request for allocation. The selection is based on an optimum value indicating physical location of the logical unit within the set of storage entities during access to data to be stored in the data storage system.
US09411529B2	Mapping between program states and data patterns The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a number of program state combinations L corresponding to a group of memory cells configured to store a fractional number of data units per cell. The mapping can be based, at least partially, on a recursive expression performed in a number of operations, the number of operations based on a number of memory cells N within the group of memory cells and the number of program state combinations L.
US09411528B1	Storage management systems and methods A hardware-based storage node manager enables processing devices to perform file access operations without invoking the file-data access functions of an operating system.
US09411527B2	Storage system and data management method Storage system comprises a second storage apparatus, which is coupled to multiple first storage apparatuses and is of a different type from the first storage apparatuses, and a first control device, which exists either inside or outside of the second storage apparatus. Row of stripes comprising multiple data elements obtained by segmenting a prescribed data unit, and a redundancy code for rebuilding the data elements, is distributively stored in multiple first storage apparatuses, which are more numerous than the total number of stripe data elements, which are either the data elements or redundancy code, in the row of stripes. The row of stripes is configured to enable the rebuilding of the stripe data elements even when a failure has occurred in up to a prescribed allowable number, which is two or more, of the first storage apparatuses storing the stripe data elements of the relevant row of stripes.
US09411525B2	Modular mass storage system A system for storing data includes a rack, one or more data storage modules coupled to the rack, and one or more data control modules coupled to the rack. The data storage modules may include a chassis, two or more backplanes coupled to the chassis, and one or more mass storage devices (for example, hard disk drives) coupled to the backplanes. The data control modules may access the mass storage devices in the data storage modules.
US09411520B2	Method and apparatus for embedded systems reprogramming A reprogramming device is used for reprogramming embedded systems. The reprogramming device comprises a microprocessor, a memory programmed with software to accomplish the reprogramming of distinctly different embedded systems architectures, and one or more hardware devices that facilitate communication over multiple protocols contained in a portable package designed for both one-time and multi-occurrence use scenarios. In some embodiments, the reprogramming device is able to be used to enhance one or more attributes of performance of existing embedded systems through the reconfiguration of internally stored parameters. In some embodiments, the reprogramming device is also to be used to extract and receive information and instruction from existing embedded systems and enable useful presentation of this information. As a result, the reprogramming device is able to be used to adjust and/or monitor the parameters of the on-board diagnostics computer of a vehicle to ensure peak performance and detect errors.
US09411518B2	Method, computer program product and apparatus for accelerating responses to requests for transactions involving data operations Responding to IO requests made by an application to an operating system within a computing device implements IO performance acceleration that interfaces with the logical and physical disk management components of the operating system and within that pathway provides a system memory based disk block cache. The logical disk management component of the operating system identifies logical disk addresses for IO requests sent from the application to the operating system. These addresses are translated to physical disk addresses that correspond to disk blocks available on a physical storage resource. The disk block cache stores cached disk blocks that correspond to the disk blocks available on the physical storage resource, such that IO requests may be fulfilled from the disk block cache. Provision of the disk block cache between the logical and physical disk management components accommodates tailoring of efficiency to any applications making IO requests, and flexible interaction with various different physical disks.
US09411517B2	System software interfaces for space-optimized block devices Interfaces to storage devices that employ storage space optimization technologies, such as thin provisioning, are configured to enable the benefits gained from such technologies to be sustained. Such an interface may be provided in a hypervisor of a virtualized computer system to enable the hypervisor to discover features of a logical unit number (LUN), such as whether or not the LUN is thinly provisioned, and also in a virtual machine (VM) of the virtualized computer system to enable the VM to discover features of a virtual disk, such as whether or not the virtual disk is thinly provisioned. The discovery of these features enables the hypervisor or the VM to instruct the underlying storage device to carry out certain operations such as an operation to deallocate blocks previously allocated to a logical block device, so that the storage device can continue to benefit from storage space optimization technologies implemented therein.
US09411515B1	Tiered-storage design A method, computer program product, and computing system for defining a storage pool for a storage system being designed that includes a plurality of storage tiers. Each storage tier has a different level of performance. A plurality of workloads are defined for the storage system, wherein each of the plurality of workloads includes: a target skew factor, a capacity requirement, and a IOPS requirement. A density function is generated for each of the plurality of workloads based, at least in part, upon the target skew factor for each of the plurality of workloads. A consolidated system loading report is generated based, at least in part, upon the target skew factor for each of the plurality of workloads.
US09411514B2	Method and apparatus for decomposing I/O tasks in a RAID system A data access request to a file system is decomposed into a plurality of lower-level I/O tasks. A logical combination of physical storage components is represented as a hierarchical set of objects. A parent I/O task is generated from a first object in response to the data access request. A child I/O task is generated from a second object to implement a portion of the parent I/O task. The parent I/O task is suspended until the child I/O task completes. The child I/O task is executed in response to an occurrence of an event that a resource required by the child I/O task is available. The parent I/O task is resumed upon an event indicating completion of the child I/O task. Scheduling of any child I/O task is not conditional on execution of the parent I/O task, and a state diagram regulates the child I/O tasks.
US09411512B2	Method, apparatus, and medium for executing a function related to information displayed on an external device A method for controlling an electronic device is provided, including displaying at least one portion of a screen displayed on a first display unit of a first electronic device on a second display unit of a second electronic device, receiving an input related to a first position in the second display unit; identifying a type of an object corresponding to the first position, and executing at least one function based on the type of the object.
US09411506B1	Providing additional functionality for a group messaging application Configurations providing one or more group objects for extending the functionality of a group messaging application. Some example group objects provide functionality for location-sharing, games, events, calendar, photos, videos, money sending, video calling, audio calling, or a map view of one or more participants in a conversation. Each group object can provide contextual content including semantically relevant information with respect to the participants of the conversation. For instance, each conversation participant can modify the included group object(s) in the context of the conversation. A notification can then be provided to the conversation participants. By viewing the conversation in the group messaging application, contextual information from an included group object for the participants in the conversation can be provided.
US09411505B2	Single-handed approach for navigation of application tiles using panning and zooming Unique interactive systems and methods that facilitate single-handed navigation and interaction with applications within a display space on any type of mobile computing device are provided. Embodiments include or employ scalable application tiles corresponding to applications, whereby the application tiles can provide or indicate the current state of the corresponding application. State information provided in each tile can vary as well depending on the current size of the tile. Tiles can be arranged into a plurality of zones such that a user can view one zone at a time and obtain context and information from the application tiles in that zone rather than working with all tiles and all zones simultaneously. The view of the display space can be of the world or all application tiles, zone, or application. Panning and zooming among the zones, application tiles and/or views can also be performed.
US09411496B2	Method for operating user interface and recording medium for storing program applying the same A method for operating a user interface and a recording medium for storing a program applying the same are provided. The method includes following steps. First, a touch generated by touching a touch display using an input tool is detected. Then, whether or not the touch is generated on a specific area of the touch display is determined. Next, whether the position of the touch is changed is determined if the touch is generated on the specific area. The user interface is activated or switched if the position of the touch is changed. Accordingly, a more convenient and intuitive method for operating the user interface is provided and the convenience in using the electronic device is increased.
US09411495B2	Enhancements to data-driven media management within an electronic device A centralized resource manager manages the routing of audio or visual information within a device, including a handheld device such as a smartphone. The resource manager evaluates data-driven policies to determine how to route audio or visual information to or from various input or output components connected to the device, including headphones, built-in speakers, microphones, bluetooth headsets, cameras, and so on. Among the data considered in the policies are connection status data, indicating if a device is connected, routing status data, indicating if a device is permitted to route information to or from a component, and grouping data, indicating logical relationships between various components. Components may be considered inherently routable, automatically mutable, or optionally routable. Numerous other uses exist for such data, including providing simpler and more logical management interfaces.
US09411493B2	Mobile terminal and control method thereof According to an embodiment of the present invention, a mobile terminal includes a touch screen configured to display a user interface of a multi-layered structure, the user interface including at least one layer stack having a plurality of layers, a command input unit configured to receive a command from a user, and a controller configured to display a first layer of a first plurality of layers in the first layer stack on a first zone of the touch screen, display the first plurality of layers in a spread mode in response to a first command to enter the spread mode, and in the spread mode, change a location of the first layer on the touch screen to a second zone of the touch screen and display the first plurality layers of the first layer stack except for the first layer on a third zone of the touch screen.
US09411492B1	Adding information to a contact record In general, the subject matter described in this specification can be embodied in methods, systems, and program products. A display for a particular contact record is presented. The display includes a name for a particular contact and a generic input area. Each of a plurality of contact records identifies a name for a contact, and each of the plurality of contact records is configured to store multiple entries that each include a value and a field type from a plurality of field types. User input of information using the generic input area is received. A field type from the plurality of field types is determined based on matching semantics of the received user input. The determining occurs without receiving user input specifically identifying the matching field type. The determined field type and the received user input is stored as an entry for the particular contact record.
US09411491B2	Method for providing graphical user interface (GUI), and multimedia apparatus applying the same A method for providing a graphical user interface (GUI) to receive a user command on a touch screen, and a multimedia apparatus using the same. The method for providing a GUI includes determining whether an enlargement command for a GUI item is received, and enlarging the GUI item. Therefore, it is possible to enable a user to operate the GUI item more correctly, and to provide the superior visual effect when the GUI item is operated.
US09411490B2	Shared virtual area communication environment based apparatus and methods Improved systems and methods for navigating and interacting in virtual communication environments are described. At least some of these systems and methods provide a framework that includes one or more virtual areas and supports realtime communications between the communicants. At least some of these systems and methods provide an interface that includes navigation controls that enable a user to navigate virtual areas and interaction controls that enable the user to interact with other communicants in the one or more virtual areas.
US09411489B2	Interfacing with a spatial virtual communication environment A spatial layout of zones of a virtual area in a network communication environment is displayed. A user can have a respective presence in each of one or more of the zones. Navigation controls and interaction controls are presented. The navigation controls enable the user to specify where to establish a presence in the virtual area. The interaction controls enable the user to manage interactions with one or more other communicants in the network communication environment. A respective presence of the user is established in each of one or more of the zones on response to input received via the navigation controls. Respective graphical representations of the communicants are depicted in each of the zones where the communicants respectively have presence.
US09411487B2	User interface presentation of information in reconfigured or overlapping containers A graphical user interface provides a display of multiple items of information in a manner such that the user can comprehend the relationship of various items to one another over a wide span. To achieve this result, at least some information containers are allocated a reduced amount of area in which to be viewed by the user. At least one container continues to be displayed in full view, however. In one embodiment, the containers are displayed in an overlapping arrangement. In a column view, for instance, the column containing the object that was last clicked upon, and the column showing the contents of the selected object, can be displayed in full view. The other columns may be only partially visible, due to the overlapping arrangement. However, the user is presented with enough information to comprehend the relationship of objects at different levels. When the user moves a cursor over a container with a reduced viewing area, the display changes to show that container in full view.
US09411476B2	Induction unit, touch detecting assembly and touch sensitive device A touch detecting assembly, a touch sensitive device, and a portable electronic apparatus are provided. The touch detecting assembly (100) comprises: a substrate (1); and a plurality of induction units (2) disposed on the substrate (1) and not intersecting with each other, each induction unit (2) comprising an induction body (20), and a first electrode (21) and a second electrode (22) connected with the induction body (20) respectively. Each induction body (20) has a plurality of empty parts (24), and the plurality of empty parts (24) are arranged in a predetermined pattern to define a current passage (25) for increasing a resistance between the first electrode (21) and the second electrode (22).
US09411475B2	Keyboard A keyboard includes a non-conductive board, a plurality of keyswitches, and a capacitive touch sensing sheet. The plurality of keyswitches is disposed on the non-conductive board. Each keyswitch includes a keycap and a support device. The support device is connected to the keycap and the non-conductive board so as to make the keycap movable between a pressing position and a non-pressing position relative to the non-conductive board. The capacitive touch sensing sheet is disposed under the non-conductive board for providing a cursor signal to a computer device.
US09411474B2	Shield electrode overlying portions of capacitive sensor electrodes An apparatus including: an array of capacitive sensor electrodes including a plurality of distinct capacitive sensor electrodes distributed over a sensing area; conductive traces connected to respective ones of the plurality of distinct capacitive sensor electrodes; and a shield electrode overlying, in the sensing area, conductive traces.
US09411473B2	Touch device and manufacturing method thereof The present disclosure relates to a touch technology, especially to a touch device and a manufacturing method thereof. The touch device comprises a sensing electrode structure, a shielding layer, a plurality of peripheral connection wires and a grounding wire. The shielding layer surrounds the periphery of the sensing electrode structure. The plurality of peripheral connection wires are located under the shielding layer and electrically connected to the sensing electrode structure. The grounding wire is electrically connected to the shielding layer. Thus, in accordance with the present disclosure, the touch device can shield external interference, and the reliability for operation of the touch circuit can be improved.

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