最新美国发明专利第2015-10-20期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09166646B1	Transceiver circuit and method for operating a transceiver circuit Embodiments of transceiver circuits and methods for operating a transceiver circuit are described. In one embodiment, a transceiver circuit includes a feedback loop connected to a bus and a control circuit connected to the bus. The feedback loop includes a tunable low-pass filter. The control circuit is configured to detect a radio frequency (RF) disturbance on the bus and control the bandwidth of the tunable low-pass filter in response to detection of the RF disturbance on the bus. Other embodiments are also described.
US09166642B2	Signal receiving device and signal receiving method A signal receiving device and signal receiving method to pass a desired frequency component of an intermediate frequency signal by using an IF filter without increasing a chip area. The signal receiving device comprises: a mixer to mix a received frequency signal with a local oscillation frequency signal to generate an intermediate frequency signal; an IF filter to pass a predetermined frequency component of the intermediate frequency signal; a controlling part which adjusts, according to a frequency band of the intermediate frequency signal, the frequency band of the IF filter, and adjust, according to a center frequency set in the IF filter that fluctuates with the adjustment, a center frequency of the intermediate frequency signal to be inputted in the IF filter; and a demodulating part to demodulate a frequency component of the intermediate frequency signal outputted after passing through the IF filter.
US09166637B2	Impulse noise mitigation under out-of-band interference conditions An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters allows frequencies higher than the frequency bandwidth of the desired signal, and a second of the two filters allows frequencies lower than the frequency bandwidth of the desired signal. The INMC may compute and store a mean magnitude separately for a first signal response of the first filter and a second signal response of the second filter. The INMC may select the first filter for impulse noise mitigation when the mean magnitude of the second filter is greater than the mean magnitude of the first filter. The INMC may select the second filter for impulse noise mitigation when the mean magnitude of the first filter is greater than the second filter.
US09166636B2	Rejection of RF interferers and noise in a wireless communications transceiver The invention provides a radio receiver or transceiver having one or more low noise amplifiers corresponding to one or more antenna inputs wherein one or more outputs of the one or more low noise amplifiers is/are combined at a single output current summing node, a tunable, shunt notch filter is coupled or connected to the summed output node that allows for the attenuation of a Tx blocker or interferer, an external blocker or interferer or an internal on-chip interferer.
US09166633B2	Systems and methods for interfacing a white space device with a host device Information is communicated from a host device to a receiving device via white space. A white space device is interfaced with the host device. The white space device has at least one port configured to communicatively interface with a host device to receive multimedia content from the host device. The white space device also optionally has a television band engine configured to encode a transport stream containing at least a portion of the multimedia content received from the host device. A transmitter is configured to transmit the transport stream via white space.
US09166630B1	Adaptive radio communications systems and methods An illustrative adaptive radio communications system comprises a cluster of waveform and application processor entities coupled and a plurality of transceivers. The transceivers convert radio frequency (RF) signals into digital in-phase and quadrature (I/Q) data, which is sent to the waveform processor entities via a network fabric. The waveform processor entities perform low-level waveform processing and the application processor entities perform high-level, distributed signal processing. The system and related methods are capable of processing multiple programmable waveforms of varying complexity.
US09166627B2	Combination error and erasure decoding for product codes In one embodiment, a system for combination error and erasure decoding for product codes includes a processor and logic integrated with and/or executable by the processor, the logic being configured to receive captured data, generate erasure flags for the captured data and provide the erasure flags to a C2 decoder, set a stop parameter to be equal to a length of C1 codewords in a codeword interleave used to encode the captured data, and selectively perform, in an iterative process, error or erasure C1 decoding followed by error or erasure C2 decoding until decoding is successful or unsuccessful. In more embodiments, a method and/or a computer program product may be used for combination error and erasure decoding for product codes.
US09166623B1	Reed-solomon decoder A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.
US09166620B2	Method and apparatus for a memory based packet compression encoding Methods and apparatus for wireless communication in a mobile device that includes receiving a transmission data packet and detecting a string of bytes in the transmission data packet that matches a preset string of bytes saved in a memory component. Aspects of the methods and apparatus include replacing the string of bytes of the transmission data packet that has been determined to match the preset string of bytes saved in the memory component with a location pointer, wherein after replacing the string of bytes in the data packet with the location pointer, the data packet comprises the location pointer and a set of literal bytes. Aspects of the methods and apparatus also include generating a compressed transmission data packet by entropy coding the transmission data packet comprising the set of literal-bytes and the location pointer.
US09166613B2	A/D conversion circuit and solid-state imaging device An A/D conversion circuit and a solid-state imaging device are able to reduce current consumption, and two input terminals of a NAND element included in a latch circuit receive a corresponding one of a plurality of clock signals and an enable signal. The enable signal is not input to the NAND element before an end timing of A/D conversion, and is input to the NAND element at the end timing of the A/D conversion and at a timing at which latching is performed. The latch circuit latches no clock signal when the enable signal is not input.
US09166610B2	Converter arrangement and method for converting an analogue input signal into a digital output signal The invention relates to an arrangement and a method for the identification of parameters in a nonlinear model of an analog-to-digital converter (ADC 17) and the use of this information to reduce the nonlinear distortions of the ADC. A parameter estimator determines an AD parameter vector PAD which describes the nonlinearities of the ADC (17). According to the invention the ADC is excited by a perturbed input signal y′A generated by adder 77 which combines the analog input signal yA with perturbation signal s1 provided by generator. The nonlinear system identification uses intermodulation distortion generated in the digital ADC output signal y′D which are not found in the analog input signal yA. A nonlinear AD compensation element compensates based on parameter vector PAD the nonlinear distortion generated by the ADC and generates the linearized output signal yD. Digital control information PP,1 are used to generate the perturbation signal s1 in generator and to remove the perturbation signal the compensation element. The linearized ADC (is the basis for linearizing digital-analog-converters (DAC), amplifiers and other hardware components.
US09166604B2	Timing monitor for PLL Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device.
US09166602B2	Transceiver A transceiver 1 includes a frequency synthesizer 2 configured to generate an output signal 3 for use as a carrier signal for transmission and/or a signal with a channel frequency for reception, wherein the frequency synthesizer is a sub-sampling based frequency locked loop frequency synthesizer. The combination of a FLL and sub-sampling allows to obtain a sub-sample based locked loop with a closed loop response similar to a PLL but with improved settling time and improved suppression of high frequency components of the quantization noise due to the sampling process. The transceiver allows to obtain a frequency synthesizer with improved characteristics with respect to at least one of power consumption, locking characteristic, design optimization characteristics compared to non-sub-sampling PLL based frequency synthesizers.
US09166599B1	Methods and apparatus for building bus interconnection networks using programmable interconnection resources Integrated circuits may include logic regions configurable to perform custom functions. Interconnects may be used to rout signals throughout the integrated circuit. The logic region may be coupled to input selection circuitry for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry may provide direct access to registers inside the logic regions and to the output selection and routing circuitry by bypassing the input selection circuitry and other processing circuitry inside the logic regions. Bus interconnections having logic regions performing register pipelining, wire stitching, and acting as data source/sink stations to get on and off the bus interconnections may be generated by configuring the bypass circuitry and the output selection and routing circuitry appropriately.
US09166598B1	Routing and programming for resistive switch arrays Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.
US09166596B2	Memory interface circuitry with improved timing margins Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe signal in response to activation of the latched data strobe enable signal. The integrated circuit may include counter circuitry that monitors the gated data strobe signal. The counter circuitry may monitor the gated data strobe signal by counting pulses in the gated data strobe signal to produce a counter value. When the counter value reaches a target value, the logic circuitry may block the data strobe signal from passing to the memory controller.
US09166594B2	Flexible, space-efficient I/O circuitry for integrated circuits Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.
US09166593B2	Flexible, space-efficient I/O circuitry for integrated circuits Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.
US09166589B2	Multiple data rate interface architecture Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
US09166586B2	Fuel dispenser input device tamper detection arrangement A system for detecting unauthorized removal or tampering. The system comprises a printed circuit board having tamper-response electronics and a flexible circuit assembly defining a connector portion, a switch portion, and a cable extending between the connector portion and the switch portion. The flexible circuit assembly is coupled with the printed circuit board at the connector portion. The flexible circuit assembly comprises a plurality of layers each comprising a flexible dielectric substrate and a switch disposed in the switch portion. The switch is in electrical communication with the tamper-response electronics of the printed circuit board via a conductive path. The flexible circuit assembly also comprises a tamper-responsive conductor circuit enclosing the conductive path. The tamper-responsive conductor circuit is in electrical communication with the tamper-response electronics of the printed circuit board.
US09166585B2	Low power inverter circuit A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
US09166584B1	Current-encoded signaling An apparatus is disclosed for communication of data signals in a current-encoded format. The apparatus includes a first logic block and a second logic block. The first logic block includes a first voltage-mode logic (VML) circuit configured to provide a first voltage-encoded binary signal and an encoder circuit configured to convert the voltage-encoded binary signal to a current-encoded binary signal. The second logic block includes a decoder circuit configured to receive the current-encoded binary signal from the first logic block and convert the current-encoded binary signal to a second voltage-encoded binary signal. The logic states encoded by the second voltage-encoded binary signal are equal to the logic states encoded by the first voltage-encoded binary signal. The second logic block also includes a second VML circuit coupled to the decoder circuit and configured to receive and process the second voltage-encoded binary signal.
US09166581B2	Electrode device, circuit arrangement and method for the approach and touch detection An electrode device for a capacitive sensor device and a circuit arrangement for a capacitive sensor device for the operation of an electrode device are provided, wherein the electrode device has a first electrode structure with at least one transmitting electrode and at least one receiving electrode, and a second electrode structure with at least one field sensing electrode, wherein the electrode device or the capacitive sensor device can be operated in a first operation mode and in a second operation mode. In addition a method is provided for approach and/or touch detection with a sensor device.
US09166579B2	Methods and apparatuses for shifting data signals to match command signal delay Methods and apparatuses for shifting data signals are disclosed herein. An apparatus may comprise a clock generation circuit, a delay path, and a driver. The clock generation circuit may be configured to receive an input clock signal and generate a plurality of clock signals based, at least in part, on the clock signal. A delay path may be coupled to the clock generation circuit and configured to receive the input clock signal and the plurality of clock signals. The delay path may be further configured to receive a data signal and delay the data signal based, at least in part, on the input clock signal and each of the plurality of clock signals. A driver may be coupled to the delay path and configured to receive the delayed data signal, and may further be configured to provide the delayed data signal to a bus.
US09166574B2	Apparatus and method for providing timing adjustment of input signal An apparatus for providing time adjustment of an input signal includes a coarse timing digital-to-analog converter (DAC), a replica delay element and an interpolator. The coarse timing DAC has multiple delay settings for providing a coarse timing adjustment of the input signal, and outputs a first delayed signal by delaying the input signal by a first delay time corresponding to a selected setting of the multiple delay settings. The replica delay element receives the first delayed signal from the coarse timing DAC and outputs a second delayed signal by delaying the first delayed signal by a predetermined second delay time. The interpolator blends either the input signal and the first delayed signal or the first delayed signal and the second delayed signal for providing a fine timing adjustment of the input signal, and outputs a timing adjusted output signal including the coarse timing adjustment and the fine timing adjustment.
US09166572B2	Semiconductor device, semiconductor system including the semiconductor device, and method for driving the semiconductor system A semiconductor device includes a plurality of pads, a plurality of data input/output units connected with the plurality of pads and enabled in response to a plurality of enable signals, and a group programming unit suitable for grouping the plurality of pads into a number of pad groups in response to a mode register set (MRS) code and group information, and generating a number of groups of enable signals corresponding to the number of pad groups, wherein a number of groups of the data input/output units are sequentially enabled in response to respective groups of the enable signals.
US09166571B2	Low power high speed quadrature generator An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal, a second latch, wherein the first latch and the second latch are configured as a frequency divider, and a logic circuit coupled to each latch, wherein the logic circuits are configured to generate both an in-phase reference output signal and a quadrature output signal.
US09166569B2	Relaxation oscillator A relaxation oscillator is provided in the present invention. The relaxation oscillator includes a R-S latch, a first delay circuit and a second delay circuit. The input terminal of the first delay circuit is coupled to the Q output terminal of the R-S latch, and the output terminal of the first delay circuit is coupled to the reset terminal of the R-S latch. The input terminal of the second delay circuit is coupled to the inversion Q output terminal of the R-S latch, and the output terminal of the second delay circuit is coupled to the set terminal of the R-S latch. When the input terminal of the first delay circuit inputs a first logic voltage, after a delay time, the output terminal of the first delay circuit outputs a second logic pulse. When the input terminal of the second delay circuit inputs the first logic voltage, after the delay time, the output terminal of the second delay circuit outputs the second logic pulse.
US09166568B2	Low power high resolution sensor interface A sensor interface circuit is provided for resolving sensor signals from a plurality of sensors into a digital sensor signal. The sensor interface circuit includes a relaxation oscillator that receives and pre-processes the sensor signals to generate an analog sensor signal. The relaxation oscillator includes one or more dynamic circuits. The sensor interface circuit also includes a monitoring module for receiving the analog sensor signal and generating the digital sensor signal in response thereto. There is also provided a sensor system front-end and a relaxation oscillator.
US09166564B2	Wideband analog bandpass filter A wideband bandpass filter includes an RF input terminal, an RF output terminal, a plurality of electrically tunable coupling capacitors coupled in series between the RF input and output terminals, and a plurality of resonating circuits each including an electrically tunable resonator capacitor coupled to one of the coupling capacitors. At least one resistance is coupled in series between at least one of the coupling capacitors for providing enhanced out of band rejection of the filter.
US09166562B2	Impedance transformation network for improved driver circuit performance This disclosure provides systems, methods and apparatus for reducing harmonic emissions. One aspect of the disclosure provides a transmitter apparatus. The transmitter apparatus includes a driver circuit characterized by an efficiency and a power output level. The driver circuit further includes a filter circuit electrically connected to the driver circuit and configured to modify the impedance of the transmit circuit to maintain the efficiency of the driver circuit at a level that is within 20% of a maximum efficiency of the driver circuit when the impedance is within the complex impedance range. The filter circuit is further configured to maintain a substantially constant power output level irrespective of the reactive variations within the complex impedance range. The filter circuit is further configured to maintain a substantially linear relationship between the power output level and the resistive variations within the impedance range.
US09166555B2	Phase shifter using bulk acoustic wave resonator A phase shifter using a Bulk Acoustic Wave Resonators (BAWR) is provided. The phase shifter using a BAWR may use a property of a phase shift with respect to a frequency of the BAWR, and also use at least one capacitor, at least one inductor, and the like.
US09166554B2	Flexural resonator element, resonator, oscillator, and electronic device A crystal resonator element include a pair of resonating arms extending from a base, the resonating arms includes a groove, a slope portion is formed in a connection portion of the resonating arms to the base so that a distance between the groove and the outer edge of each of the resonating arms increases as it approaches the base from the resonating arms, and a non-electrode region which extends over a range of areas from a connection portion connected to a first side surface formed along the longitudinal direction of the groove and a connection portion connected to a second side surface facing the first side surface with a bottom portion disposed there between and in which excitation electrodes are not formed is provided in the groove in at least a part of the bottom portion positioned in the slope portion.
US09166552B2	Filter and duplexer A filter includes one or a plurality of parallel resonators coupled in parallel and one or a plurality of a film bulk acoustic resonators coupled in series, the film bulk acoustic resonator having a substrate, a lower electrode, a piezoelectric membrane, and an upper electrode, wherein: at least one of the lower electrode and the upper electrode has a thick membrane region having a thickness larger than that of a center portion of a resonance region at an edge of the resonance region, the resonance region being a region where the lower electrode and the upper electrode face with each other through the piezoelectric membrane; and a width of the thick membrane region is smaller than a wavelength of an acoustic wave propagating in a direction crossing a thickness direction of the piezoelectric membrane.
US09166550B2	System and method for using a reference plane to control transmission line characteristic impedance A system for using a reference plane to control transmission line characteristic impedance includes a signal trace located in a multi-layer structure and at least one constant thickness reference plane proximate to the signal trace, the constant thickness reference plane located with respect to the signal trace so as to provide a desired characteristic impedance between the signal trace and the constant thickness reference plane.
US09166547B2	Electronic device and method for adjusting volume levels of audio signal outputted by the electronic device An electronic device includes an audio sensor, an audio output unit, a pulse width modulation (PWM) unit connected to the audio output unit, and a control chip. When the audio output unit outputs the audio signal, the audio sensor detects a volume level of the environment sound. The control chip determines a volume level of the audio signal according to the volume level of the environment sound and preset associations between volume levels of the audio signal outputted by the audio output unit and volume levels of the environment, and determines a duty cycle of the PWM unit according to the determined volume level and the maximum volume level. The control chip then outputs the duty cycle to the PWM unit, to adjust a current volume level of the audio signal outputted by the audio output unit to the determined volume level.
US09166545B2	Circuit for providing a flat gain response over a selected frequency range and method of use An integrated circuit is disclosed. The integrated circuit includes an amplifier and a capacitor array coupled to the amplifier. The capacitor array is configured to be coupled in parallel to an inductor that is external to the integrated circuit, and the capacitor array and the external inductor comprise a tank circuit. The integrated circuit includes a resistor array coupled in parallel with the capacitor array. The resistor array is utilized to provide an overall frequency response of the capacitor array and resistor array that is opposite of a frequency response of the external inductor over a predetermined frequency range.
US09166542B2	High frequency module and portable terminal using same When the frequency bandwidth of a high frequency signal to be amplified is changed, the linearity of a high frequency module deteriorates. A high frequency module has an amplifier circuit including an amplification transistor and a variable impedance circuit, and an output matching network. Based on an amplifying operation, the amplified high frequency signal will contain unwanted signals of secondary distortion components. In a frequency band that generates such unwanted signals of secondary distortion components, the output impedance of the amplifier circuit is changed so that the impedance will not match between the amplifier circuit and the output matching network. The output impedance of the amplifier circuit is changed by controlling the variable impedance circuit.
US09166541B2	Signal processing circuit, resolver digital converter, and multipath nested mirror amplifier A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
US09166539B2	RF signal generation circuit and wireless transmitter A wireless transmitter includes an RF signal generation circuit, a driver amplifier, and a class-D amplifier. The RF signal generation circuit detects an amplitude signal and a phase signal based on a digital baseband signal subjected to orthogonal modulation, thus generating a pulse phase signal which is High in response to the phase ranging from 0° to 180° but is Low in response to the phase ranging from 180° to 360°. The amplitude signal is subjected to sigma-delta modulation in synchronism with the pulse phase signal and further mixed with the pulse phase signal, thus producing an RF pulse signal. The RF pulse signal is input to the class-D amplifier via the driver amplifier, thus outputting a pulse voltage signal based on a reference voltage. Thus, it is possible to achieve a small-size wireless transmitter with good noise/distortion characteristics and high power efficiency.
US09166537B2	Amplifier arrangement An amplifier arrangement for amplifying a radio signal comprising at least a first amplifier module and a second amplifier module is presented wherein a splitter stage for dividing an amplifier stage input signal into several signal portions. The signal portions are amplified in the at least two parallel amplifier modules. A combiner stage combines the separate amplifier output signals into a single amplifier arrangement output signal.
US09166534B2	Tunable loadline A tunable loadline is disclosed. In an exemplary embodiment, an apparatus includes an amplifier configured to output an amplified signal having a selected power level and a first impedance network coupled to receive the amplified signal at an input terminal and generate a first output signal having a first power level at a first output terminal. The first impedance network being configured to load the amplified signal to convert the selected power level to the first power level. The apparatus also includes a second impedance network configured to selectively receive the first output signal and generate a second output signal having a second power level at a second output terminal. The second impedance network being configured to combine with the first impedance network to load the amplified signal to convert the selected power level to the second power level.
US09166527B2	Amplification circuit having optimization of power A Power amplifier circuit comprising an input, an output comprising: means for sensing the input voltage; and a set of n cascode circuits, each comprising a first transistor having a gate, a source and a drain terminal and further comprising a second transistor having gate, source and drain terminal; the source and gate of the first transistor of said cascode circuits being respectively connected to a first reference voltage and to receive the input signal, the drain of said first transistor being connected to the source of said second transistor, the drain of which being coupled to said output. By activating or deactivating one or more of the n cascode circuits, the total size of the amplification components can be adapted to the value of the output power to generate.
US09166525B2	Solar tracker The solar tracker comprises a base (1) and a solar panel (2) having first and second opposite ends (2a, 2b). The first end (2a) can be connected to the base (1) by a first shaft (E1) and the second end (2b) can be connected to the base (1) by a second shaft (E2), such that said solar panel (2) can pivot with respect to the base (1) alternately around the first shaft (E1) and around the second shaft (E2) under the drive of a lifting mechanism. An automatic connection/disconnection device connects the second end (2b) of the solar panel (2) to the base (1) while at the same time disconnecting the first end (2a) of the solar panel (2) from the base (1), and vice versa, every time the solar panel (2) reaches a position parallel to the base (1) for inverting the inclination of the solar panel (2) with respect to the base (1).
US09166524B2	Connecting components for photovoltaic arrays The invention includes an apparatus for mounting a photovoltaic (PV) module on a structure where the apparatus includes a base portion, a stud portion, and a coupling portion. The coupling portion includes a male portion that acts as a spring under load and a clip portion that penetrates the PV module frame to create a grounding bond. The apparatus includes a lower jaw, shaped to pry open a groove, and a key portion that can compress to allow for tolerances. The invention further includes a clip with one or more tabs and one or more teeth. The invention further includes a replacement roof tile which includes a support structure with a horizontal flange, a vertical component, a horizontal component, a flashing with an upper surface and a lower surface, and a tile-shaped metal surface having a curvilinear shape that reflects the shapes of adjacent tiles.
US09166522B1	Solar panel mounting assembly A solar panel mounting assembly for securing a solar panel to a structure with the assembly comprising a mounting block having mounting block partitions forming a cross-shaped pattern that abut the solar panel, a threaded male member extending out of the mounting block, and a mounting plate and fastener cap for securing the solar panel to the mounting block.
US09166520B2	Range switching device A range switching device may switch a shift range despite resetting and restarting of a controller. When the controller is reset and restarted during a switching operation of the shift range and the shift range before or after being switched is a P range, the controller controls a motor to rotate the motor until a range switching mechanism abuts against a first limit position of a movable range of the range switching mechanism and learns a rotation position of the motor as a reference position of the motor. When the shift ranges before and after being switched are the ranges other that the P range, the controller controls the motor to rotate until the range switching mechanism abuts against a second limit position of the movable range and learns the rotation position of the motor as the reference position.
US09166516B2	Motor drive apparatus and vehicle including the same, and method for controlling motor drive apparatus An ECU sets target value of a system voltage based on an electric power loss of a motor generator and an inverter and controls a voltage boost converter. The ECU calculates the target value of the system voltage using a function expression generated, for each operating point of the motor generator, by approximating a loss characteristic which represents change of the electric power loss with respect to change of the system voltage, by a quadratic expression or a linear expression of the system voltage.
US09166515B2	Electrically powered vehicle and method for controlling the same A converter is disposed between a first battery and a power line for transmitting power inputted to and outputted from a motor for traveling. A second battery, on the other hand, is connected to the power line with a relay being interposed therebetween. A control unit controls the relay to be turned on or off in accordance with an operating state of the motor.
US09166506B2	Controlling a multiphase brushless DC motor for staging and driving a remote-control vehicle Control of rotational speed of a motor is provided using an apparatus and method that provides a staging and a driving mode. A processor controls speed of the motor in three different modes to provide different control that is appropriate for different situations. Control-input indications are received by a processor indicating that a stepping mode is selected. In stepping mode, a sequence of commutation states are chosen in succession at a given stepping frequency for a given control selection. In an active-holding mode, the same phase in the commutation sequence is pulsed at low power to hold a motor location. In a closed-loop motor-control mode, the commutation state is sensed and state transition time is controlled relative to neutral timing. These modes may be used to advantage to simulate a drag race. An operator controls a remote-control vehicle in a stepping mode to drive toward a first beam at a drag start line. When the first beam at the start line is broken, but a second beam is not broken, the ESC begins to perform motor control to actively hold the vehicle in position until the race starts. After the race starts, the ESC receives a control-input indication to drive the motor in a closed-loop motor-control mode.
US09166505B1	Protection circuits for motors System and methods are provided for protecting a direct current (DC) motor. A protection system includes: a motor drive component configured to drive a DC motor, a feedback component configured to generate a feedback signal related to motion of the DC motor, and a watchdog circuit configured to output a fault signal to the motor drive component to stop the DC motor in response to the feedback signal indicating abnormal motion of the DC motor. The watchdog circuit includes a hardware watchdog timer configured to be activated in response to one or more control signals and monitor the feedback signal.
US09166502B2	Method for manufacturing an electromechanical transducer The present invention provides a technology for decreasing a dispersion of the performance among electromechanical transducers each having through wiring. A method for manufacturing an electromechanical transducer includes: obtaining a structure in which an insulative portion having a through hole therein is bonded onto an electroconductive substrate; filling the through hole with an electroconductive material to form a through wiring which is electrically connected with the electroconductive substrate; and using the electroconductive substrate as a first electrode, forming a plurality of vibrating membrane portions including a second electrode, which opposes to the first electrode through a plurality of gaps, on an opposite side of the first electrode to the side having the insulative portion, to thereby forming a plurality of cells.
US09166500B2	Power decoupling controller and method for power conversion system A power conversion system is disclosed including a DC bus for receiving DC power, a power converter for converting the DC power to AC power, and a controller. The controller includes an active power regulator for generating a phase angle command signal, a reactive power regulator for generating a voltage magnitude command, and an active power (P) and reactive power (Q) decoupling unit for decoupling interaction between the active and reactive power regulators. The PQ decoupling unit includes an active power compensation element and a reactive power compensation element. The active power compensation element is used for generating a phase angle compensation signal based on a reactive power error signal, to compensate the phase angle command signal. The reactive power compensation element is used for generating a voltage magnitude compensation signal based on an active power error signal, to compensate the voltage magnitude command signal.
US09166498B2	Power converter with non-symmetrical totem pole rectifier and current-shaping branch circuits A hybrid diode-less power converter topology of the present invention converts power from an AC power source to a variable load with high efficiency. The power converter includes a non-symmetrical arrangement of rectifying switches for rectifying an input AC voltage and shaping switches for shaping an input AC current. The shaping switches are operated in Continuous Conduction Mode (CCM) based on an input AC current. Operation of each of the rectifying switches and shaping switches are further controlled wherein a commutation time for the shaping switches is associated with a first voltage rise and fall time (e.g., less than 10 ns), and a commutation time for the rectifying switches is associated with a second voltage rise and fall time (e.g., at least 100 ns), wherein the first voltage rise and fall time is less than the second voltage rise and fall time by a factor of nine or more.
US09166490B2	Driving controller and full-bridge converting circuit The present invention provides a full-bridge driving controller and a full-bridge converting circuit, which have the function of soft switch, to provide a DC output voltage. The present invention employs a resonant unit to oscillate the current flowing through the converting circuit at a resonant frequency. The full-bridge driving controller switches four full-bridge transistor switches at an operating frequency higher than the resonant frequency, so as to achieve the function of soft switch.
US09166489B2	Layouts of multiple transformers and multiple rectifiers of interleaving converter The present invention relates to multi-phase parallel-interleaved converter circuits with each phase having two or more transformers and two or more rectifiers electrically coupled to the two or more transformers, and layouts of the transformers and the rectifiers of the multi-phase parallel-interleaved converter circuits. In the layouts, the multiple transformers and the multiple rectifiers of the multi-phase converters are interleavingly arranged to be symmetrical to common output polarized capacitor(s) so as to ensure the rectifier outputs of each phase relative to the common output polarized capacitors is symmetrical, thereby reducing the output ripples of the current of the output capacitors.
US09166486B2	Power converter using multiple controllers A power converter controller includes a primary controller and a secondary controller. The primary controller is coupled to receive one or more request signals from the secondary controller and transition a power switch from an OFF state to an ON state in response to each of the received request signals. The primary controller is coupled to detect a turn-off condition when the power switch is in the ON state and transition the power switch from the ON state to the OFF state in response to detection of the turn-off condition. The secondary controller is galvanically isolated from the primary controller. The secondary controller is coupled to transmit the request signals to the primary controller and control the amount of time between the transmission of each of the request signals.
US09166484B2	Resonant converter Consistent with an example embodiment, a resonant converter comprises a signalling transformer that is used to transfer information between the secondary winding and primary winding of the converter whilst maintaining mains isolation between the two sides. In the embodiment, according to the disclosure, the use of a signalling transformer (in addition to a switching, or resonant, transformer) eliminates the need for an opto-coupler to transfer information and so allows for the construction of a simpler, more reliable and/or cheaper resonant converter. Other embodiments described herein may be suitable for use in dimmable LED driver applications, for example.
US09166480B2	Insulation-type power factor correction circuit This is an insulation-type power factor correction circuit including a resonance unit configured to accumulate energy of a surge occurring when the first switching element is turned off and to transmit a resonance current generated by resonating the first capacitor and the primary winding of the second transformer from the primary winding of the second transformer to the secondary winding, a rectifier unit configured to rectify a resonance current output from the resonance unit, a smoothing unit configured to regenerate power output from the rectifier unit to an output of the insulation-type power factor correction circuit, and a control unit configured to control a first switching element for each cycle.
US09166477B2	Control circuit for power converter and related control method A control circuit of a power converter includes: a zero current detection circuit for detecting a current flowing between an inductor and a voltage output terminal of the power converter to generate a zero current detection signal; an adjusting circuit for generating an adjustment signal according to the zero current detection signal; a clock signal generating circuit for adjusting a frequency of a clock signal according to the adjustment signal; a periodical signal generating circuit for generating a periodical signal according to the clock signal; an error detection circuit for generating an error signal; and a control signal generating circuit for generating a control signal to control operations of a power switch. If the and amount of pulses generated by the zero current detection circuit satisfy a predetermined condition, the adjusting circuit switches the power converter's operation mode from DCM to CCM.
US09166471B1	3D frequency dithering for DC-to-DC converters used in multi-mode cellular transmitters A circuit and method is disclosed that dithers a switching frequency of a DC-to-DC converter which gets modulated onto an RF carrier such that switching noise is spread over a given bandwidth that is wider than a communications measurements bandwidth. The circuit includes a switching circuitry adapted to transfer energy from a source to a load using a switching signal having a series of switching cycles and a switching frequency. Also included is a control circuitry adapted to generate a pseudo-random value near a beginning of each of the series of switching cycles to determine a maximum switching frequency value based upon the pseudo-random value. The method includes adjusting the switching frequency of the switching signal incrementally from a fixed minimum switching frequency value to the maximum frequency value and vice versa as a function of time during each of the series of switching cycles of the switching circuit.
US09166470B2	Method and circuit for power factor correction A method and circuit for correcting a power factor in an alternating current/direct current power transformer. The circuit has an inductor fed by a rectified AC voltage, and a switch by which the inductor can be charged and discharged by closing and opening the switch, and further has a diode by which the discharge current of the inductor is fed to the output of the circuit. During the discharge phase, a voltage corresponding to the output voltage is measured, and the measured values are stored. It is further determined when the discharge current reaches or crosses the zero line at the end of a discharge phase. Switch-on and switch-off signals for actuating the switch are generated by analyzing the information determined. The switch should not be switched on again until a particular minimum switch-off time has been reached.
US09166468B2	Voltage regulator circuit with soft-start function A voltage regulator circuit includes a soft start module, a pulse width modulation (PWM) module, and a voltage regulator module. The soft start module is used to receive a current feedback voltage corresponding to an input current, and compare the current feedback voltage with a comparison voltage, so as to output a switching signal. The PWM module is used to receive a clock signal and the switching signal, and determine a first PWM signal and a second PWM signal outputted by the PWM module is a high voltage level or a low voltage level according to the clock signal and the switching signal. The voltage regulator module is used to receive and adjust an output voltage corresponding to the first PWM signal and the second PWM signal.
US09166464B2	Magnetic gear device and holding member A magnetic gear device including: an internal rotor and an external rotor in which a plurality of magnetic pole pairs are each placed in a circumferential direction substantially at equal intervals; and a holding member that is placed between the internal rotor and the external rotor and holds a plurality of magnetic materials in the circumferential direction substantially at equal intervals, wherein the number of magnetic materials is a difference between or a total of the numbers of magnetic pole pairs, the holding member includes a plurality of circular rings that hold the magnetic materials, and connecting rods that are placed in the circumferential direction substantially at equal intervals and connect the plurality of circular rings, the plurality of circular rings face each other via the magnetic materials, and each number of magnetic pole pairs is set to have the number of connecting rods as a divisor.
US09166463B2	Linearly deployed actuators A method for making an actuator includes forming a substantially planar actuator device of an electrically conductive material, the device incorporating an outer frame, a fixed frame attached to the outer frame, a moveable frame disposed parallel to the fixed frame, a motion control flexure coupling the moveable frame to the outer frame for coplanar, rectilinear movement relative to the outer frame and the fixed frame, and an actuator incorporating a plurality of interdigitated teeth, a fixed portion of which is attached to the fixed frame and a moving portion of which is attached to the moveable frame, moving the moveable frame to a deployed position that is coplanar with, parallel to and spaced at a selected distance apart from the fixed frame and fixing the moveable frame at the deployed position for substantially rectilinear, perpendicular movement relative to the fixed frame.
US09166461B2	Automotive alternator having a heat dissipating plate To provide a high-quality, high-output, and low-cost automotive alternator by suppressing heat generation through the reduction of current loss in a heat dissipating plate of a rectifier without expanding a space for placing the heat dissipating plate and reducing the cooling performance of the heat dissipating plate. An automotive alternator includes a rectifier, wherein the rectifier is configured such that a heat dissipating plate of positive pole to which the rectifier element of positive pole is mounted is disposed opposite to a heat dissipating plate of negative pole to which a plurality of rectifier elements of negative pole are mounted; wherein the heat dissipating plate of positive pole is made up of a first heat dissipating plate and a second heat dissipating plate, which are made of two different materials.
US09166457B2	Rotating apparatus having rotating electrical machine and reduction device with common rotating shaft The disclosure discloses a rotating electrical machine that is integrally formed with a reduction device having an input shaft to which a roller gear cam is provided and an output shaft to which cam followers configured to sequentially engage with the roller gear cam is provided on an outer periphery, extending along a direction orthogonal to the input shaft, and is configured to employ one of a field system or an armature as a rotator and the other of the field system or the armature as a stator, including a rotating shaft that is fixed to the rotator and integrally formed as a single shaft with the input shaft of the reduction device.
US09166453B2	Split core stator with terminal accommodating resin box A stator of a rotary electrical machine, includes a core unit configured by a plurality of core assemblies each including a laminated steel plate, an insulator, and a coil; a bus ring facing the core unit; and an accommodating box arranged at the insulator, accommodating an end portion of the coil, and including radially inward and outward engaged portions, the insulator including radially inward and outward extending portions, the radially inward extending portion including a radially inward engagement portion about which the accommodating box rotates in a radial direction of the core unit from an initial attachment position to an attached position and which engages with the radially inward engaged portion, the radially outward extending portion including a radially outward engagement portion which engages with the radially outward engaged portion in accordance with the rotation of the accommodating box to move the accommodating box in the radial direction.
US09166444B2	Control circuit and motor device A control circuit has an input terminal for receiving an input voltage, an energy accumulator for storing electric energy from the input terminal and supplying power to an electrical load, and an over-voltage protection unit for lowering the voltage at the input terminal when the voltage at an output terminal of the energy accumulator exceeds a predetermined threshold value. A motor device combines the control circuit with an electric motor as the load.
US09166441B2	Microprocessor controlled class E driver A charger including a class E power driver, a frequency-shift keying (“FSK”) module, and a processor. The processor can receive data relating to the operation of the class E power driver and can control the class E power driver based on the received data relating to the operation of the class E power driver. The processor can additionally control the FSK module to modulate the natural frequency of the class E power transformer to thereby allow the simultaneous recharging of an implantable device and the transmission of data to the implantable device. The processor can additionally compensate for propagation delays by adjusting switching times.
US09166439B2	Systems and methods for forward link communication in wireless power systems This disclosure provides systems, methods and apparatus for forward link communication in wireless power systems. One aspect of the disclosure provides a wireless charging device for providing wireless power to a receiving device. The wireless charging device includes a primary transmit antenna configured to generate a wireless power field. The device further includes a parasitic antenna configured to selectively adjust a coupling between the primary transmit antenna and the receiving device. The device further includes a controller configured to control the selective adjustment of the parasitic antenna so as to communicate with the receiving device.
US09166437B2	Battery pack An apparatus includes a first cell subpack having a plurality of cells arranged in series and a second cell subpack connected in series to the first cell subpack. The second cell subpack includes a plurality of cells arranged in series and at least one cell arranged in parallel with one of the plurality of cells, arranged in series, of the second cell subpack, where the first cell subpack and the second cell subpack use a first voltage rail to provide at least a first voltage level and a second voltage rail to provide a second voltage level, where the first voltage level is different from the second voltage level.
US09166435B2	Universal industrial battery optimization device Improvements in a battery de-sulfating device are disclosed. The improvements including a plurality of capacitive discharge channels selectively activatable by a control board to provide a pulse wave modulated de-sulfating current to a lead-acid battery. The de-sulfating current can be a variable, or harmonic, repeating pattern of about 0.1-1.5 ms ON pulse followed by an about 2-9 ms OFF period which may be applied to the battery at an operator-adjustable peak amperage of about 0-350 amps. The de-sulfation process before, during or after the normal battery charging cycle, or any combination thereof. The temperature of the battery and the specific gravity of the fluid within the battery is measure during the de-sulfating process. The extent of sulfation of the battery may be ascertained by measuring the impedance of the battery.
US09166432B2	Charge circuit A charge circuit includes a current limiting circuit configured to limit a current input from an input terminal; a first transistor connected between an output terminal of the current limiting circuit and a secondary battery; a charge control circuit configured to turn the first transistor on and off to start and stop supply of a charge current to the secondary battery; a second transistor configured to output a current proportional to the charge current flowing through the first transistor; and a charge timer configured to generate clock pulses according to the current output from the second transistor. The charge control circuit is configured to turn off the first transistor to stop the supply of the charge current to the secondary battery when the number of the clock pulses reaches a predetermined number.
US09166426B2	External power supply apparatus of electric vehicle An external power supply apparatus of an electric vehicle, includes: a battery; an inverter configured to convert DC power of the battery to AC power and configured to output the AC power; a first outlet socket disposed in the electric vehicle and through which an output of the inverter is supplied; a relay connected downstream from the first outlet socket as viewed from the inverter; a charging port connected downstream from the relay as viewed from the inverter and exposed to the outside of the electric vehicle; an adapter including a second outlet socket and being to be connected to the charging port; and, when it is detected that the adapter is connected to the charging port, a controlling unit setting the relay to an ON state to allow the output of the inverter to be supplied through the charging port.
US09166422B2	Battery based portable power supply A portable power supply includes a housing, and power circuitry providing an output AC waveform having a first positive voltage step level, a second higher positive voltage step level, a third lower positive voltage step level, a fourth negative voltage step level, a fifth higher negative voltage step level, and a sixth lower negative voltage step level.
US09166416B2	Method for balancing cells in batteries Adjacent battery cells connected in devices are balanced by closing a first circuit to charge an energy storage device from a first battery cell and thereafter simultaneously opening the first isolated switch and closing a second isolated switch to cause the energy storage device to charge a second battery cell. A circuit includes an isolated switch that operates simultaneously to balance battery cells connected in series, and a battery system balances battery modules connected in series, the battery module including battery cells connected in series. The battery cells and modules can be balanced by hierarchical balancing of modules of the battery pack and component cells of the modules.
US09166415B2	AC link bidirectional DC-DC converter, hybrid power supply system using the same and hybrid vehicle In an AC link type boosting device, DC terminals of two voltage inverters are connected each other in series in additive polarity and plural AC terminals of each of the voltage inverters are connected to a transformer. The two voltage type inverters are AC linked to each other via the transformer. An external voltage applied between the DC terminals of the AC link type booster is divided by the voltage-type inverters.
US09166414B2	Battery pack and method of controlling the same A battery pack including a plurality of battery cell groups including a first battery cell group and a second battery cell group, a first switch that is connected to the first battery cell group, a second switch that is connected to the second battery cell group, and a controller configured to selectively control charging and discharging operations of the first battery cell group and the second battery cell group using the first switch and the second switch.
US09166410B1	Line balancing for a three-phase alternating current system System for providing AC line balancing includes a three-phase power source, a monitoring component and a control component. Three AC lines from the three-phase power source are coupled to a first set of loads and a set of transfer switches. Additionally, the set of transfer switches are configured to be coupled to a second set of loads. The monitoring component is configured to detect current provided by the three AC lines to identify the AC lines providing the highest and the lowest levels of currents to the first and second sets of loads. The control component is configured to configure at least one transfer switch in the set of transfer switches to decouple the AC line providing the highest level of current to a load of the second set of loads and couple the AC line providing the lowest level of current to that load.
US09166408B2	Demand response management system and method with VAR support A method for providing VAR support in a power distribution network having a demand response management system can include querying the demand response management system for an inductive device on the power distribution network and power cycling the inductive device to effect reactive power in the power distribution network.
US09166406B2	Power source switching circuit and power source switching system with power source switching circuit A power source switching circuit, includes a first and second contact, a first, second, and third relay. The first contact includes a first normally open main contact and a first normally closed auxiliary contact. The second contact includes a second normally open main contact and a second normally closed auxiliary contact. The first, second, third normally open contacts of the first, second, third relays, connected in series, are connected between three phrase lines of the main power source and the second normally closed auxiliary contact. The second normally closed auxiliary contact is connected to a zero line of the main power source. The first, second, third normally closed contacts, connected in parallel, are connected between three phrase lines of the auxiliary power source and the first normally closed auxiliary contact. The first normally closed auxiliary contact is connected to a zero line of the auxiliary power source.
US09166401B2	Electrostatic discharge protection device An electrostatic discharge (ESD) protection device including a modified lateral silicon-controlled rectifier (MLSCR) and a voltage control circuit is provided. The MLSCR has a first terminal, a second terminal and a control terminal connected to a first P+-type doped region, where the first terminal and the second terminal are electrically connected to a first line and a second line, respectively. The voltage control circuit is electrically connected to the first line, the second line and the control terminal. When an electrostatic pulse is appeared on the first line, the voltage control circuit provides a current path from the first line to the control terminal. When an input signal is supplied to the first line, the voltage control circuit receives a power voltage, and stops providing the current path according to the power voltage.
US09166398B2	Controller providing protection function and frequency-reduction function using a single pin and system using same A controller providing protection function and frequency-reduction function for a power conversion application, including: a voltage sense pin; a current source; a switch having a first end coupled to the current source, a second end coupled to the voltage sense pin, and a control end coupled with a control signal; and a sampling unit having a first node coupled to the voltage sense pin, a second node for providing the control signal, a third node for receiving a PWM signal, a fourth node for providing a first sampled voltage for a protection function, and a fifth node for providing a second sampled voltage for a frequency-reduction function.
US09166397B2	Electronic control device including interrupt wire An electronic control device includes a substrate, a plurality of component-mounted wires, a plurality of electronic components, a common wire, an interrupt wire and a protective layer. The component-mounted wires and the common wire are disposed on the substrate. The electronic components are mounted on the respective component-mounted wires and are coupled with the common wire. The interrupt wire is coupled between one component-mounted wire and the common wire, and is configured to melt in accordance with heat generated by an overcurrent to interrupt a coupling between the component-mounted wire and the common wire. The protective layer covers a surface of the substrate including the interrupt wire and defines an opening portion so that at least a portion of the interrupt wire is exposed.
US09166396B2	Power conditioning, distribution and management A power conditioning, distribution and management system includes a switch circuit that enables coupling of an AC power supply to a load though an overcurrent device. A control circuit switches the switch circuit from a non-conductive state to a conductive state when a supply voltage signal is between first overvoltage and undervoltage thresholds. The control circuit records an overvoltage event and maintains the switch circuit in the conductive state when the supply voltage signal exceeds a second, higher overvoltage threshold and switches the switch circuit to a nonconductive state when the supply voltage signal exceeds a third, highest overvoltage threshold. The control circuit records an undervoltage event and maintains the switch circuit in the conductive state when the supply voltage signal falls below a second, lower under-voltage threshold and switches the switch circuit to the non-conductive state when the supply voltage signal falls below a third, lowest undervoltage threshold.
US09166394B2	Device and method for limiting leakage currents A device including a mechanism detecting a position of a neutral of a power supply source for an electrical energy apparatus, such as a battery charger of an electric or hybrid motor vehicle, and a mechanism connecting a capacitor for limiting leakage currents between the neutral and an electrically conducting structure in which the apparatus is placed. The device can be used to limit leakage current during recharging of an electric or hybrid traction motor vehicle.
US09166386B2	Subsea cable repair There is provided subsea repair apparatus for performing repair of a subsea cable located beneath the sea, said apparatus comprising: an environment capsule capable of providing a substantially water-free environment within the capsule; and repair equipment located within the environment capsule arranged to repair said subsea cable without the need for a person to be located within the environment capsule.
US09166384B2	Switchgear A housing of a switchgear includes: a framework formed by joining vertical frames to depth directional frames and width directional frames, the vertical frames being arranged in a standing condition at four corners of a cuboid shape; at least a left and right pair of intermediate vertical frames each provided at an intermediate portion in the depth direction; and steel partition plates fixed over the whole in the vertical direction of the intermediate vertical frames, the partition plates being provided for separating the front and the back of the intermediate vertical frames. Then, the depth directional frame on the floor side is formed with a fixing hole near a lower portion of the intermediate vertical frame, the fixing hole being provided for fixing the housing to a foundation surface.
US09166380B2	Spark plug electrode material and spark plug A spark plug electrode material containing nickel, silicon, and copper, the electrode material, in the case of proper use, forming a nickel oxide layer made of nickel oxide grains on at least a part of its surface, the grain boundary phase of the nickel oxide grains including silicon and/or silicon oxide.
US09166376B2	Spark plug A spark plug includes a tubular insulator and a tubular metal shell secured to an outer peripheral surface of the insulator by crimping. The tubular metal shell includes: an inner peripheral surface where powder for sealing is filled between the outer peripheral surface and the inner peripheral surface; a tool engagement portion overhanging in a polygonal shape; and a crimped lid disposed at an end portion of the metal shell coupled to the tool engagement portion, the end portion being bent toward the outer peripheral surface of the insulator by crimping. A relationship between a length L and a thickness t satisfies 2.50≦L/t≦3.10, the length L being a length along a shape of the crimped lid from the tool engagement portion to the insulator in a planar surface that passes through the axis, the thickness t being a thickness at an intermediate portion of the crimped lid.
US09166374B1	Laser devices using a semipolar plane An optical device includes a gallium and nitrogen containing substrate comprising a surface region configured in a (20-2-1) orientation, a (30-3-1) orientation, or a (30-31) orientation, within +/−10 degrees toward c-plane and/or a-plane from the orientation. Optical devices having quantum well regions overly the surface region are also disclosed.
US09166373B1	Laser devices having a gallium and nitrogen containing semipolar surface orientation Laser devices formed on a semipolar surface region of a gallium and nitrogen containing material are disclosed. The laser devices have a laser stripe configured to emit a laser beam having a cross-polarized emission state.
US09166370B2	Vertical cavity surface emitting laser, vertical cavity surface emitting laser apparatus, optical transmission apparatus, and information processing apparatus A vertical cavity surface emitting laser includes a first semiconductor multilayer reflector, a resonator, and a second semiconductor multilayer reflector. The first semiconductor multilayer reflector is formed on a substrate and is configured by stacking a high refractive index layer having a relatively high refractive index and a low refractive index layer having a relatively low refractive index. The resonator includes an active layer formed on the first semiconductor multilayer reflector. The second semiconductor multilayer reflector is configured by stacking the high refractive index layer and the low refractive index layer. The resonator includes a pair of spacer layers disposed vertically on the active layer and a resonator extension area formed at one side of the pair of spacer layers. The resonator extension area contains a material in which an energy level with a crystal defect is higher than a general energy level without the crystal defect.
US09166368B2	High power semiconductor laser with phase-matching optical element A semiconductor laser that includes a single mode semiconductor laser coupled to a flared power amplifier is provided, the device including an internal or an external optical element that reinforces the curved wave front of the flared section of the device through phase-matching. By reinforcing the curved wave front via phase-matching, the device is less susceptible to thermal and gain-index coupled perturbations, even at high output powers, resulting in higher beam quality. Exemplary phase-matching optical elements include a grating integrated into the flared amplifier section; an intra-cavity, externally positioned binary optical element; and an intra-cavity, externally positioned cylindrically curved optical element.
US09166364B2	Semiconductor laser mounting with intact diffusion barrier layer A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.
US09166362B2	Cascaded raman lasing system In a Raman system, a primary laser source emits laser light at an initial wavelength, and a seed source emits a multi-wavelength seed laser light. The seed wavelengths correspond to a respective Stokes orders of the primary laser light. The primary laser light and the seed laser light are combined and fed into a Raman gain medium. Stimulated Raman scattering (SRS) causes the primary laser light to be converted into laser light at a selected target wavelength. The seeding of the primary light mediates the conversion process, so as to reduce spontaneous Raman scattering.
US09166359B2	Method and laser oscillator for the generation of a laser beam Method and laser oscillator for the generation of a laser beam—According to the invention with a view to adjusting, inside said laser oscillator (1), the phase of each of the N elementary laser beams (FLE.1, FLE.2, FLE.N) generated on the basis of said laser oscillator (1) in such a way that said elementary laser beams are in phase, the deviation between the phase of an individual elementary laser beam (FLE.1) and the phases of the N−1 other elementary laser beams (FLE.2, FLE.N) is converted into a level of luminous intensity by means of at least one optical filtering element to which at least a part of each elementary laser beam is directed.
US09166356B2	Unstable imaging resonator In one aspect a power amplifier comprises a first plurality of laser disks disposed in a first vertical plane and a second plurality of laser disks disposed in a second vertical plane, opposite the first vertical plane, wherein the plurality of laser disks are disposed in a central horizontal plane, and a first plurality of reflecting mirrors disposed in the first vertical plane and a second plurality of reflecting mirrors disposed in the second vertical plane, wherein a first set of reflecting are disposed in a lower horizontal plane and a second set of reflecting mirrors are disposed in an upper horizontal plane, wherein respective laser disks and reflecting mirrors adjacent along an optical axis are positioned to provide a 1:1 imaging system therebetween. Other aspects may be described.
US09166355B2	Directly driven source of multi-gigahertz, sub-picosecond optical pulses A robust, compact optical pulse train source is described, with the capability of generating sub-picosecond micro-pulse sequences, which can be periodic as well as non-periodic, and at repetition rates tunable over decades of baseline frequencies, from MHz to multi-GHz regimes. The micro-pulses can be precisely controlled and formatted to be in the range of many ps in duration to as short as several fs in duration. The system output can be comprised of a continuous wave train of optical micro-pulses or can be programmed to provide gated bursts of macro-pulses, with each macro-pulse consisting of a specific number of micro-pulses or a single pulse picked from the higher frequency train at a repetition rate lower than the baseline frequency. These pulses could then be amplified in energy anywhere from the nJ to MJ range.
US09166354B2	Method for constructing multi-contact universally jointed power and/or signal connector devices An adjustable at least three-way electrical connector device for signal, power, voice and/or data communication, comprising at least three adjustable electrical connections utilizing a ball and socket type physical connection device, preferably including a weatherproofing gasket, and further including being constructed utilizing deformable printed circuit boards, deformed and embedded in thermosetting plastic material with elastomeric properties, and including methods of construction.
US09166353B1	Large ferrule crimp die The present invention is directed to a crimp die used to deform a ferrule onto a cable. The crimp die operates within multiple tool platforms. The crimp die includes a male die, a female die, and removable tab adapters. The male and female dies each have a mounting portion and an inner crimping surface to deform the ferrule onto the cable. When required by the tool platform, the tab adapters are removably affixed to the male and female dies to secure the dies to the tool.
US09166351B1	Power adapting device A power adapting device has a connecting seat, at least two conductive strips, and an adapter. The connecting seat has a mounting portion with two slots. The at least two conductive strips are mounted in the connecting seat. Each of the at least two conductive strips has a positioning sheet, a conductive sheet obliquely protruding upward from the positioning sheet, an arced sheet protruding down from the positioning sheet, and an engaging sheet protruding down from the arced sheet. The engaging sheet has a semispherical contact. The adapter is electrically connected to the conductive sheets of the at least two conductive strips. With different power adapting devices of different standards using in cooperation with a charger, the charger can comply with different electrical socket standards via the power adapting devices.
US09166350B2	Hybrid electrical connector A connector is disclosed with an insulating body. A plurality of contacts are positioned in the insulating body. The plurality of contacts include a group of first contacts with a first length, and a group of second contacts with a second length less than the first length. Each second contact is positioned in a gap between two adjacent first contacts.
US09166346B2	Retractable interconnect device configured to switch between electrical paths A retractable interconnect device is configurable to operate in an extended mode or a retracted mode. The retractable interconnect device includes a first (e.g., short) electrical path and a second (e.g., long) electrical path. The retractable interconnect device also includes a connector that is electrically coupled to the first electrical path in the retracted mode and that is electrically coupled to the second electrical path in the extended mode.
US09166345B2	Techniques for detecting removal of a connector A system that detects electrical disconnection of one connector from another connector includes a detection circuitry and a protection circuitry. The detection circuitry detects that a plug connector has been electrically disconnected from a corresponding receptacle connector. In response to the detection, the detection circuitry sends a signal to the protection circuitry. In response to the signal, the protection circuitry lowers or terminates power being supplied to a host device via one of the contacts of the plug connector. This helps to prevent shocks/shorts that may be caused by accidental disconnection of the plug connector.
US09166340B2	Connector A connector for disconnecting electrical lines from a module or connecting them to the module includes a first housing part formed as a flap and a second housing part second housing part formed as a base part with an inner and outer sides, and a coding element receptacle for accepting a coding element, which interacts with a mating coding element disposed in the module, wherein the coding element receptacle is integrated into the base part and, looking towards the inner side, bears a first label field, and the base part is formed on the outer side in the area of the coding element receptacle with an opening and a second label field assigned to the opening, and in addition to numbers/letters, the label fields have marking lines disposed such that, when the coding element is plugged in, the markings match markings disposed on the coding element.
US09166339B2	Connector housing having drainage pathways The invention achieves prevention of sink mark and drainage within a hood part. A housing (10) made of synthetic resin has a hood part (17) extending forward from a terminal holding part (11), and a guide wall part (19) having a guide recessed part (15) formed in a back end part of an inner surface. The housing (10) is formed with a longitudinal mold drawing pathway (20) which includes a mold drawing recessed part (21) having a form which recesses a region in front of a region corresponding to the guide recessed part (15) of the outer surface of the guide wall part (19), and a mold drawing port (22) having a form that communicates with the mold drawing recessed part (21) and passes through a back surface wall (18).
US09166337B2	Externally latching I/O housing Embodiments of the invention generally include apparatus for providing a positive locked connection for I/O devices to computing devices. In one embodiment, an external latching apparatus for an Input/Output (I/O) connection is provided. The external latching apparatus includes a main body and at least one latch. The main body includes a first surface configured to abut to an I/O card bracket and a second surface, parallel and spaced apart from the first surface. The at least one latch extends from the main body beyond the first surface. A plurality of parallel slots are formed in the second surface. Each slot is open on a bottom side of the body and is configured to receive a cable of an I/O cable assembly.
US09166333B2	Connector It is an object of the present invention to prevent damages to a contact. A contact 130 having penetrated the substrate 110 is inserted into the female housing 30, and is electrically connected to a female contact 40. When the slider 1 is pressed down ward during this state, the first movable body 70 and the second movable body 80 are pressed down by the slider 1. This causes a lower stage 73 of the first movable body 70 and a lower stage 83 of the second movable body 80 to move below an upper wall 94 of the housing 90, and outer surfaces of the lower stages 73 and 83 no longer contact the upper wall 94. Then, expansion of a spring 120 moves the first movable body 70 and the second movable body 80 away from the contact 130.
US09166331B2	Connector terminal with a resin mold covering its barrel portion connected to a cable conductor A connector terminal (10) includes a terminal main body that includes a barrel portion (21) to which a core wire (12) exposed from an outer cover (13) of an electric cable (11) is electrically connected, and a tab terminal portion (31) that is electrically connected to a mating terminal, and a resin mold (15) that covers the barrel portion (21) and an end portion of the electric cable (11). The connector terminal (10) is inserted in a cavity (52) formed in a housing (51) and then accommodated in the housing (51) so that a rear end portion of the resin mold (15) is arranged in the inside of the cavity (52).
US09166328B2	Connector, in particular an electrical connector A connector is provided having an outer housing, an inner housing and a seal. The seal includes a first sealing device that positioned between the outer housing and the inner housing such that a mating connector receiving gap is provided between an inner side of the outer housing and the first sealing device.
US09166327B2	Circuit board connector system An inline connector is coupled to a first substrate and operable to receive at least one prong. A second receptacle is coupled to a second substrate and operable to receive the prong. A plug having an elongated prong that, when inserted through the first receptacle and into the second receptacle operates to provide electrical connections between the substrates. The substrates may be circuit boards and the receptacle may be mounted along the edges of the circuit board to allow for easier installation. Some embodiments may provide for identical receptacle providing for lower costs and easier installation.
US09166326B1	Electrical connector with contact guard An electrical connector has a plastic body and a blade contact in a terminal cavity in the body. A guard extends across the mouth of the cavity over an adjacent edge of the blade. A physical interlock connection holds the guard on the blade edge to shield the blade and prevent an object inserted into the mouth from contacting the blade.
US09166324B2	Coaxial cable connector structure A coaxial cable connector structure including a sleeve and an annular nut on the front end of the sleeve is presented, wherein an inner tube is disposed inside the sleeve for connecting the coaxial cable, and a spring is disposed between the inner tube and the inner threads on the annular nut, the spring having a first end positioned proximate the bottom of the annular nut and a second end positioned forward of the front end of the inner tube for the end surface of the connection base towards the annular nut to contact the spring and electrically connect the inner tube when the annular nut is at least partially screwed onto the connection base, so that the coaxial cable connector structure can transmit signals when it is not completely screwed onto the connection base, and provide the effect of vibration suppression from the compressed spring having its two ends abutted against the bottom of the annular nut and the end surface of the connection base by the elastic restoring force when the connection base is completely screwed onto the connection base.
US09166316B2	Data storage connecting device A data storage connecting device includes a circuit board, a first connector, a second connector and a third connector. The circuit board has a first connecting end and a second connecting end. The first connector and a second connector are both disposed on the first connecting end and respectively at two sides of a long axis of the circuit board, a location of the second connector connecting with a data storage device being opposite to that of the first connector connecting with another data storage device. The third connector is disposed on the second connecting end for transmitting data from two data storage devices connected to the first connector and the second connector, respectively, via the circuit to a server device, or vice versa.
US09166314B2	Electrcial connector and assemble method of the same An electrical connector includes an insulating housing including a base, a mating tongue and a positioning portion, terminals and a first positioning board. The positioning portion defines first positioning grooves along a bottom face thereof. Each conductive terminal comprises retained portion interfered with the base, mating portions vertical leg portion and connecting portion connecting with the retained portion and the leg portion. The connecting portion comprises a vertical portion and a horizontal portion. The first positioning board is sandwiched between the horizontal portions. The first positioning board defines second positioning grooves, the horizontal portions of first terminals are limited in the first positioning grooves while the horizontal portions of second terminals are limited in the second positioning grooves.
US09166313B2	Power supply contact for installation of printed circuit board A power supply contact is mountable on a base of a device having a geometry for receiving a power supply and for surface installation of a printed circuit board. The power supply contact includes a base plate mountable on the base of the device, a rail extends upwardly from the base plate, a power supply terminal and an adaptor connecting the rail to the power supply terminal. The rail is in electrical contact with the printed circuit board and the power supply terminal is in electrical contact with the power supply when the printed circuit board and the power supply are installed in the device.
US09166308B2	Modular electrical system providing four wire circuit configurations A modular electrical system (230) comprises a number of separate components forming a four-wire system (110). The component set (230) includes receptacle junction blocks (130), two-way connectors (232), four-way connectors (236), two-way jumper cable assemblies (234), and three-way jumper cable assemblies (238). The components of the component set (230) include various configurations of male blade terminals (150) and female terminals (200) located on the individual components so that a number of differing system configurations can be achieved.
US09166306B2	Method of terminating a coaxial cable Passive intermodulation (PIM) and impedance management in coaxial cable terminations. In one example embodiment, a method for terminating a coaxial cable is provided. The coaxial cable includes an inner conductor, an insulating layer, an outer conductor, and a jacket. First, a diameter of the outer conductor that surrounds a cored-out section of the insulating layer is increased so as to create an increased-diameter cylindrical section of the outer conductor. Next, an internal connector structure is inserted into the cored-out section so as to be surrounded by the increased-diameter cylindrical section. Finally, an external connector structure is clamped around the increased-diameter cylindrical section so as to radially compress the increased-diameter cylindrical section between the external connector structure and the internal connector structure, and via a single action, a contact force between the inner conductor and a conductive pin is increased.
US09166304B2	Screwless quick system for connecting a lead connector to a generator of an implantable medical device A screwless quick connection system for connecting a lead connector to a generator of an active implantable medical device is shown and described. The connector head includes a housing receiving a plug of a lead connector. A mechanism for locking the plug into the housing is provided by a U-folded leaf spring. Each branch of the U is provided with a respective hole sized so that the plug passes through the holes on both branches when it is inserted into the housing. The blade is deformable between a free state, in the absence of plug, and a deformed state, with the plug inserted therein. In the free state, both holes are misaligned, while in the deformed state they are aligned. In this way, an edge of both holes exerts by reaction a radial stress force against the smooth outer surface of the plug inserted therein.
US09166303B2	Full tension swaged connector for reinforced cable An improved cable connector includes a connector insert having an axial bore dimensioned to receive the core of a reinforced cable. A connector body has a substantially cylindrical outer surface and a substantially cylindrical cavity. A distal portion of the cavity is dimensioned to receive the connector insert. A second portion of the cavity proximally displaced from the distal portion is dimensioned to receive the conductor strands of the cable. The connector body may be configured with one or more additional portions of the cavity having progressively increasing diameters, the number of such portions depending on the size of the cable. Alternatively, the inner surface of the cavity may have a slight taper. Using a single die, the connector body is compressed with a swaging tool at several axially spaced-apart locations to grip the conductor strands and also to grip the connector insert.
US09166301B2	Travelling wave antenna feed structures Techniques for implementing series-fed antenna arrays with a variable dielectric waveguide. In one implementation, coupling elements with optional controlled phase shifters are placed adjacent each radiating element of the array. To avoid frequency sensitivity of the resulting array, one or more waveguides have a variable propagation constant. The variable waveguide may use certain materials exhibiting this phenomenon, or may have configurable gaps between layers. Plated-through holes and pins can control the gaps; and/or a 2-D circular or a rectangular travelling wave array of scattering elements can be used as well.
US09166294B2	Quad-band PCB antenna A surface mount antenna includes a ground plane, a feed line, and a radiating element. The ground plane extends in a first direction on a first side of a substrate. The feed line extends in a second direction on a second side of the substrate. The radiating element includes a plurality of segments disposed on the first side of the substrate and is configured to resonate in a plurality of frequency modes.
US09166292B2	Antenna structure and wireless communication device using the same An antenna structure includes a feed section, a ground section, a common section, a first radiator, a second radiator, and a third radiator. The common section is electrically connected to the feed section, and the third radiator is electrically connected to the ground section. The first radiator, the second radiator, and the third radiator are all connected to the common section. The second radiator is spaced from the third radiator to allow current to be coupled from the second radiator to the third radiator.
US09166288B2	Beam steering antenna structure Disclosed is a beam steering antenna structure, including two parallel metallic boards, an antenna perpendicularly disposed between the two metallic boards, a plurality of substrates perpendicularly disposed between the two metallic boards and radially disposed around the antenna, and a bias voltage circuit. Each of the substrates has a plurality of metal units cyclically aligned thereon, and each of the metal units includes two metallic regions oppositely disposed and in no contact with each other and a transistor disposed between the two metallic regions for coupling the two metallic regions. The transistors are electrically connected to the bias voltage circuit to thereby control the steering direction of beam radiation by switching the transistors.
US09166282B2	Wearable device assembly having antenna A wrist-worn device monitors movements of a user. A sensor assembly of the wrist-worn device is configured to detect movement of the user and generate sensor data based on the movement detected. A controller connected to the sensor assembly obtains movement data based on the sensor data. An antenna connected to the controller is configured to operate at a desired frequency when a wrist of the user is received by the device such that the movement data is wirelessly transmittable from the wrist-worn device to an electronic device. The antenna may exhibit a different design and configuration depending on the size of the wrist-worn device.
US09166280B2	Antenna device for smartphones and wireless terminals A portable accessory for preventing death grip of a hand-held apparatus and improving radio wave transmission and reception of the hand-held apparatus. The portable accessory includes an inductive signal amplifying circuit including: a radio transmission/radio unit that transmits or receives radio waves; a capacitive coupled unit that is capacitively coupled with an antenna mounted in the hand-held apparatus; and an impedance matching unit that connects the radio wave transmission/reception unit and the capacitive coupled unit and transmits radio waves.
US09166278B2	Communication apparatus The purpose of the present invention is to reduce the cost of a product while ensuring reliability of the product as a wireless transmission/reception apparatus. Provided is communication apparatus (ODU) (1) installed outside, which includes a case that houses a transmission unit for transmitting a signal and a reception unit for receiving the signal, and a waveguide connected to an external antenna and configured to receive/transmit a signal. In the apparatus, the waveguide is formed integrally with the case, and taper (16) is formed in a part of the tube hole of the waveguide.
US09166272B2	Artificial microstructure and metamaterial using the same The present invention provides an artificial microstructure including a first metal wire, a second metal wire parallel to the first metal wire, at least one first metal wire branch and at least one second metal wire branch. The at least one first metal wire branch and the at least one second metal wire branch are distributed in an interlacement arrangement. One end of the at least one first metal wire branch is connected to the first metal wire; the other end is a free end facing towards the second metal wire. One end of the at least one second metal wire branch is connected to the second metal wire, and the other end of the at least one second metal wire is a free end facing towards the first metal wire. The present invention also discloses a metamaterial with the artificial microstructures.
US09166269B2	Retractable dielectric waveguide A rotatable coupler for dielectric wave guides is described. A first dielectric wave guide (DWG) has an interface surface at a one end of the DWG. A second DWG has a matching interface surface at an end of the second DWG. A rotatable coupling mechanism is coupled to the two DWG ends and is configured to hold the interface surface of the first DWG in axial alignment with the interface surface of the second DWG while allowing the interface surface of the first DWG to rotate axially with respect to the interface surface of the second DWG.
US09166266B1	Compact stripline and air-cavity based radio frequency filter A method is proposed for designing compact stripline and air-cavity based (SACB) RF filters, duplexers, and multiplexers. The target frequency band is 600 MHz˜3 GHz. The proposed devices feature both compact size (with 50% size reduction compared to traditional resonator air cavity design) and high power handling capability as well as low insertion-loss. In the SACB filter, striplines and cavities are used to emulate LC resonator (quasi-LC resonator). The combination of striplines and cavities forms a structure that exhibit the performance of an electric resonator circuit of inductor and capacitor (LC). The outside signal will be connected to the striplines, and the ground will be connected to the metal shield which forms the cavity. By controlling the dimensions of the stripline width and length as well as the size of the cavity, the desired filter response is achieved.
US09166265B2	Signal transmission device, filter, and inter-substrate communication device A signal transmission device includes substrates and resonance sections resonating at the predetermined resonance frequency. At least one of the substrates is formed with two or more resonators in the second direction, and the remaining one or two or more of the substrates are each formed with one or more resonators in the second direction, and at least one of the resonance sections is configured by a plurality of resonators opposing one another in the first direction between the substrates, the opposing resonators form a coupled resonator resonating as a whole at the predetermined resonance frequency through electromagnetic coupling in a hybrid resonance mode, and in a state that the substrates are separated away from one another to fail to establish electromagnetic coupling thereamong, the resonators forming the coupled resonator resonate at any other resonance frequency different from the predetermined resonance frequency on the substrate basis.
US09166262B2	Battery pack with cooling passage A battery pack includes battery modules each having a battery cell and a battery case housing the battery cell therein. The battery modules are stacked in a stacking direction so that a cooling passage for allowing a cooling medium to flow is defined between opposed surfaces of adjacent battery cases. One of the opposed surfaces has first ribs projecting toward the other of the opposed surfaces and extending parallel to each other along the one. The other of the opposed surfaces has second ribs projecting toward the one of the opposed surfaces and extending parallel to each other along the other. In the cooling passage, the first ribs and the second ribs intersect each other and end portions of the first ribs and end portions of the second ribs are in contact with each other in the stacking direction.
US09166261B2	Method for reusing secondary battery A method for reusing a secondary battery by reusing unit cells or battery modules constituting reclaimed assembled batteries (or battery packs) to reconstruct a new assembled battery is disclosed. Assembled batteries are reclaimed, and disassembled into battery modules. The battery modules are selected based on battery characteristics such as an open-circuit voltage (OCV) and the like using an absolute acceptable range and a relative acceptable range, and a new assembled battery is rebuilt. The relative acceptable range is an acceptable range which is set for each assembled battery, and is set to have its center at an average value of a battery characteristic distribution.
US09166258B2	Cooling apparatus for vehicle-mountable battery packs A battery pack 10 has a built-in cooling fan to suction outside air through an air cleaner 16 and an air suction port. The battery pack 10 has a combination of the air suction port and a service plug 25 and a combination of the air cleaner 16 and a 12V terminal set 23 arranged at an upside. The air suction port and the service plug 25 are arrayed along a longer side of the battery pack 10, the air cleaner 16, a filter member in the air cleaner 16, and the 12V terminal set 23 being arrayed parallel thereto.
US09166248B2	Manufacturing method of battery pack A manufacturing method of a battery pack includes a restraining process of restraining single cells at a maximum restraint contact pressure Pd of the battery pack in a complete state, after compressing the single cells at a maximum compression contact pressure Pc that satisfies 0.8≦Pd/Pc≦0.9, with respect to the maximum restraint contact pressure Pd; a standing process of then leaving the single cells to stand for a predetermined number of days in an electrically open state; and a short-circuit testing process of then testing for an internal short in the single cells.
US09166245B2	Distributor and fuel cell module having the same A distributor and a fuel cell module including the distributor are disclosed. The distributor is for supplying a fuel or oxidant from a supply tube to a plurality of distribution portions. The distributor includes a buffer portion and a guide portion. The buffer portion has a center for receiving the fuel or oxidant from the supply tube, and a buffer surface extending away from the center. The guide portion defines a first space with a periphery of the buffer portion. The guide portion is radially connected to the plurality of distribution portions about a center axis of the distributor.
US09166243B2	Flow battery with interdigitated flow field A flow battery includes a first liquid-porous electrode, a second liquid-porous electrode spaced apart from the first liquid-porous electrode, and an ion-exchange membrane arranged between the first liquid-porous electrode and the second liquid-porous electrode. First and second flow fields are adjacent to the respective first liquid-porous electrode and second liquid-porous electrode. Each of the flow fields includes first channels having at least partially blocked outlets and second channels having at least partially blocked inlets. The second channels are interdigitated with the first channels. The flow fields provide a configuration and method of operation for relatively thin electrodes with moderate pressure drops and forced convective flow through the liquid-porous electrodes.
US09166242B2	Multi-modal energy harvester An energy harvester comprising: a microbial fuel cell comprising an anode; and a pump comprising a flexible diaphragm that is configured to be flexed by an ambient, renewable energy source such that with each flexing of the diaphragm nutrient-rich media is pumped past the anode.
US09166241B2	Enzyme electrode, and bio fuel cell equipped therewith An enzyme electrode having an electroconductive base member, an oxidoreductase and an electron mediator has at least a portion (a) in which the oxidoreductase is immobilized on the electroconductive base member, and a portion (b) in which the electron mediator is immobilized on the electroconductive base member but the oxidoreductase is not immobilized on the electroconductive base member. A bio fuel cell having the enzyme electrode as at least one of an anode and a cathode allows optimization of a reaction condition of each one of a plurality of reaction steps, including an “enzymatic reaction”, an “electron transfer reaction”, etc. Thus, the bio fuel cell provides high output.
US09166238B2	Advanced controls algorithm for an electronic pressure regulator system with pulsed disturbances A system and method for regulating the pressure within a volume between a pressure regulator and an injector that injects hydrogen gas into the anode side of a fuel cell stack. The method includes delaying a copy of the a pulsed signal that controls the opening and closing of the injector a predetermined period of time and provides a bias signal from a look-up table that is determined by a desired average mass flow of the hydrogen gas flow to the fuel cell stack and the pressure at an upstream location of the hydrogen gas flow from the pressure regulator. The method selects the bias signal as a pressure regulator control signal that controls the pressure regulator when the delayed pulse injector signal is high and selects an arbitrary value at or near zero as the pressure regulator control signal when a delayed pulse injector is low.
US09166234B2	Fuel cell system Disclosed is a fuel cell system in which a hydrogen distribution system is configured in a compact size. High-pressure hydrogen gas from a hydrogen tank is decompressed in an injector and is then supplied to a cell stack manifold. A portion of a high-pressure supply system on the upstream side of the injector is formed as a first within-end-plate flow passage, and a portion of a low-pressure supply system on the downstream side of the injector is formed as a second within-end-plate flow passage. The second within-end-plate flow passage is a recess portion or a groove formed in the end plate and is formed as an open channel flow passage.
US09166225B2	Sodium vanadium oxide anode material for sodium ion secondary battery, preparation method thereof and sodium ion secondary battery having the same There is provided a preparation method of a sodium vanadium oxide-based (Na1+xV1−xO2) anode material for a sodium ion secondary battery synthesized by mixing particles of precursors such as sodium carbonate (Na2CO3) and vanadium oxide (V2O3) and pyrolyzing a mixture in a mixed gas atmosphere composed of 90 mol % of nitrogen gas and 10 mol % of hydrogen gas through a solid-state reaction. The sodium vanadium oxide-based anode material prepared according to the present invention shows a small change in volume caused by an initial irreversible capacity and continuous charge/discharge reactions, and thus it is useful for providing a next-generation sodium ion secondary battery having stable charge/discharge characteristics and cycle performance.
US09166224B2	Lithium titanate, negative electrode including the lithium titanate, and secondary lithium battery containing the electrode A negative electrode for a lithium secondary battery that includes, as a negative active material, a lithium titanate (Li4Ti5O12) compound containing 0.004 parts by weight or less of phosphorous (P) and 0.007 parts by weight or less of potassium (K) based on 100 parts by weight of lithium titanate, a binder, and a conductive agent, and a lithium secondary battery including the negative electrode.
US09166223B2	Negative electrode for lithium-ion secondary battery and lithium-ion secondary battery The negative electrode for lithium-ion secondary battery is used in which a product of tensile strength and thickness of a negative electrode having a negative electrode active material layer containing silicon and silicon oxide as main components is 3.8 to 9.0 N/mm and a value obtained by dividing the product of the tensile strength and the thickness of the negative electrode by a product of tensile strength and thickness of a negative electrode current collector is 1.06 to 1.29.
US09166221B2	Anode and battery with improved charge-discharge efficiency and method manufacturing the same An anode in which an anode active material layer is arranged on an anode current collector. The anode active material layer includes anode active material particles made of an anode active material including at least one of silicon and tin as an element. An oxide-containing film including an oxide of at least one kind selected from the group consisting of silicon, germanium and tin is formed in a region in contact with an electrolytic solution of the surface of each anode active material particle by a liquid-phase method such as a liquid-phase deposition method. The region in contact with the electrolytic solution of the surface of each anode active material particle is covered with the oxide-containing film, to thereby improve the chemical stability of the anode and the charge-discharge efficiency. The thickness of the oxide-containing film is preferably within a range from 0.1 nm to 500 nm both inclusive.
US09166218B2	Electrolyte replenishing system and method A battery system includes a battery including an anode, a cathode, and a liquid electrolyte; and a conduit communicating to the battery an electrolyte liquid having an electrolyte salt density lower than an electrolyte salt density of the liquid electrolyte. The electrolyte may be non-aqueous. The electrolyte may be volatile.
US09166215B2	Battery pack A battery pack of the type that may be used in an electrically-powered vehicle comprises first and second arrays of cells disposed adjacent one another, and a housing enclosing the two arrays. The housing defines a cooling chamber surrounding heat transfer surfaces of the cells, a first manifold sealed from the cooling chamber and collecting gasses generated by the first array, and a second manifold sealed from the cooling chamber and collecting gasses generated by the second array. A tunnel connects the first and the second manifolds to allow passage of any collected gasses from the first manifold into the second manifold, and a discharge opening in the second manifold allows the collected gasses to escape from the housing. An electrically conductive bridge bar extends through the tunnel and connects the first array with the second array.
US09166213B2	Battery cell assembly and method for manufacturing the battery cell assembly A battery cell assembly is provided. The battery cell assembly includes a battery cell housing having first and second side members coupled together defining an interior region, and a battery cell disposed within the interior region. The battery cell assembly further includes a cable carrier assembly coupled to the battery cell housing. The cable carrier assembly includes a carrier member having a first aperture extending therethrough. The carrier member is disposed between first and second end portions of the first and second side members, respectively, and extends outwardly from the battery cell housing. The cable carrier assembly further includes a first cable fixedly held by the carrier member.
US09166205B2	Light-scattering substrate, method of manufacturing the same, organic light-emitting display device including the same, and method of manufacturing the organic light-emitting display device A light-scattering substrate which can be thinned and has improved thermal resistance, a method of manufacturing the same, an organic light-emitting display device including the same, and a method of manufacturing the organic light-emitting display device are disclosed. The light-scattering substrate includes a light-scattering layer composed of a plurality of metal nanoparticles which are attached to at least a surface of a substrate. The metal nanoparticles are formed by agglomeration of a metal on the substrate, and show a surface plasmon phenomenon.
US09166201B2	Method for manufacturing organic light emitting diode display and method for manufacturing touch panel A manufacturing method of an organic light emitting diode (“OLED”) display includes: forming a contact pattern on a panel region of a surface of a board glass, where the board glass includes the panel region, and a peripheral area which surrounds the panel region; contacting the paper glass with a surface of the contact pattern corresponding to the panel region and the surface of the board glass corresponding to the peripheral area; adhering the surface of the board glass corresponding to the peripheral area to a surface of the paper glass; forming an organic light emitting element on the paper glass corresponding to the panel region; and separating the paper glass from the board glass by cutting the paper glass at a position corresponding to an end portion of the panel region adjacent to the peripheral area.
US09166191B2	Display device, method of manufacturing the display device and carrier substrate for manufacturing display device A method of manufacturing a display device includes: preparing a carrier substrate by forming an adhesive layer on a hard glass substrate; forming a flexible substrate on the adhesive layer; forming a thin film transistor and an organic light emitting element on the flexible substrate and encapsulating the organic light emitting element; and separating the carrier substrate and the flexible substrate by irradiating laser light. The adhesive layer is formed on the carrier substrate in such a state that tensile stress is applied. The display device and the carrier substrate are also disclosed.
US09166187B2	Organic light emitting device and power supply device thereof An organic light emitting device including a first substrate, at least an organic light emitting unit, a plurality of first electrode contacts and a plurality of second electrode contacts. The organic light emitting unit is disposed on the first substrate. The first electrode contacts are disposed on the first substrate at a margin of the organic light emitting unit, wherein adjacent two first electrode contacts are spaced by a first interval, and an end of each first electrode contact is electrically connected to the organic light emitting unit. The second electrode contacts are disposed on the first substrate at a margin of the organic light emitting unit, wherein adjacent two second electrodes are spaced by a second interval, an end of each second electrode contact is electrically connected to the organic light emitting unit, and the second interval is different from the first interval.
US09166186B2	Methods of forming organic light emitting structures and methods of manufacturing organic light emitting display devices In a method of forming an organic light emitting structure, a plurality of first electrodes spaced apart from each other is formed on a lower substrate. A first organic layer covering the first electrodes is formed on the lower substrate. A preliminary pixel defining layer is formed on the first organic layer. The preliminary pixel defining layer includes a photosensitive material, and is selectively exposed to light so that the preliminary pixel defining layer and a portion of the first organic layer beneath the preliminary pixel defining layer are transformed into a pixel defining layer and a first organic layer pattern, respectively. An emitting layer is formed on the first organic layer exposed by the pixel defining layer. A second organic layer is formed on the emitting layer. A second electrode is formed on the second organic layer.
US09166183B2	Organic solar cell and method for producing the same An organic solar cell which includes an anode and a cathode that are arranged to face each other, a photoactive layer that is disposed between the anode and the cathode and contains a hole acceptor and an electron acceptor in mixture, and a metal oxide nano thin film layer that is disposed between the cathode and the photoactive layer and contains a metal oxide having an average particle size of 10 nm or less and having a particle size distribution such that 90% by number or more of the particles relative to the total number of the metal oxide particles has a particle size in the range of ±4 nm with respect to the average particle size, and a method for producing an organic solar cell. The organic solar cell has improved efficiency, and increased service life.
US09166180B2	Light emitting device having an organic light emitting diode that emits white light The present invention has an object of providing a light-emitting device including an OLED formed on a plastic substrate, which prevents degradation due to penetration of moisture or oxygen. On a plastic substrate, a plurality of films for preventing oxygen or moisture from penetrating into an organic light-emitting layer in the OLED (“barrier films”) and a film having a smaller stress than the barrier films (“stress relaxing film”), the film being interposed between the barrier films, are provided. Owing to a laminate structure, if a crack occurs in one of the barrier films, the other barrier film(s) can prevent moisture or oxygen from penetrating into the organic light emitting layer. The stress relaxing film, which has a smaller stress than the barrier films, is interposed between the barrier films, making it possible to reduce stress of the entire sealing film. Therefore, a crack due to stress hardly occurs.
US09166178B2	Organic electronic device and dopant for doping an organic semiconducting matrix material An organic electronic device includes a substrate, a first electrode arranged on the substrate, at least a first functional organic layer arranged on the first electrode and a second electrode arranged on the first functional organic layer. The first functional organic layer includes a matrix material and a p-dopant with regard to the matrix material, wherein the p-dopant includes a copper complex containing at least one ligand.
US09166177B2	Ditriphenylene derivative and organic electroluminescent device using the same The present invention discloses a novel ditriphenylene derivative is represented by the following formula (I), the organic EL device employing the ditriphenylene derivative as host material or dopant material of emitting layer can lower driving voltage, prolong half-life time and increase the efficiency. Wherein m, n represent an integer of 0 to 10. X is a divalent bridge selected from the atom or group consisting from O, S, C(R3)(R4), NR5, Si(R6)(R7). Ar1, Ar2, R1 to R7 are substituents and the same definition as described in the present invention.
US09166175B2	Organic electroluminescent materials and devices Novel compounds containing benzothiophene or benzofuran fused to a carbazoles moiety are disclosed. The compounds are substituted such that both an electron donor fragment and an electron acceptor fragment are present within the same molecule. The compounds are capable of exhibiting delayed fluorescence when used in the emissive layer of OLED devices.
US09166168B2	Organic semiconductor polymer, organic thin film transistor, and electronic device An organic semiconductor polymer includes a moiety represented by the following Chemical Formula 1 and a heteroaromatic moiety having at least one of sulfur (S) and selenium (Se). In the Chemical Formula 1, R1, R2, R3a, R3b, R4a, R4b, R5a, and R5b, a1, a2, b1, and b2 are the same as described in the detailed description.
US09166167B2	P-type materials and organic electronic devices There is presently provided compounds of formula (I), which are useful as p-type semiconductor materials and in devices comprising such p-type semiconductor materials.
US09166166B2	Deposition mask, method of manufacturing display apparatus by using the deposition mask, and display apparatus manufactured by the method A deposition mask that prevents the occurrence of defects when forming an encapsulation film or securing a long lifespan of the encapsulation film, a method of manufacturing a display apparatus by using the deposition mask, and a display apparatus manufactured by the method. The deposition mask has a first portion and a second portion, the second portion being thicker that the first portion; at least one opening in the first portion, deposition materials being passed through the opening; and a plurality of through-holes in the first portion adjacent to and surrounding the opening, the through-holes extending from an upper surface to a lower surface of the first portion, light being passed through the opening and the plurality of through-holes to irradiate the deposition materials.
US09166164B2	Method for manufacturing nonvolatile semiconductor storage device and nonvolatile semiconductor storage device A method for manufacturing a nonvolatile semiconductor storage device according to an embodiment includes laminating a first wire extending in a first direction, and a film made into a variable resistance element made of a metallic material, which are laminated in order on a semiconductor substrate, dividing, into a plurality of pieces, the film made into the variable resistance element, in the first direction and a second direction, forming an interlayer insulating film between the plurality of pieces formed by dividing the film made into the variable resistance element in the second direction, and oxidizing the metallic material of the film made into the variable resistance element, and laminating an upper electrode and a second wire extending in the second direction, which are laminated in order on the film made into the variable resistance element and the interlayer insulating film.
US09166162B2	Resistive memory device A resistive memory device includes: a memory cell comprising first and second electrodes and a resistive layer formed therebetween, wherein the resistive layer is formed of a resistance change material; and a strained film formed adjacent to the resistive layer and configured to apply a strain to the resistive layer.
US09166160B1	Resistive random access memory and method of fabricating the same Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.
US09166158B2	Apparatuses including electrodes having a conductive barrier material and methods of forming same Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.
US09166154B2	MTJ stack and bottom electrode patterning process with ion beam etching using a single mask Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.
US09166152B2	Diffusionless transformations in MTJ stacks A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a plurality of magnetic layers including a nonmagnetic spacer layer. The magnetic junction also includes at least one diffusionless transformation layer. The magnetic junction is configured to be switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
US09166150B2	Electric field enhanced spin transfer torque memory (STTM) device Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.
US09166144B2	Magnetic devices having perpendicular magnetic tunnel junction Provided are magnetic memory devices with a perpendicular magnetic tunnel junction. The device includes a magnetic tunnel junction including a free layer structure, a pinned layer structure, and a tunnel barrier therebetween. The pinned layer structure may include a first magnetic layer having an intrinsic perpendicular magnetization property, a second magnetic layer having an intrinsic in-plane magnetization property, and an exchange coupling layer interposed between the first and second magnetic layers. The exchange coupling layer may have a thickness maximizing an antiferromagnetic exchange coupling between the first and second magnetic layers, and the second magnetic layer may exhibit a perpendicular magnetization direction, due at least in part to the antiferromagnetic exchange coupling with the first magnetic layer.
US09166143B1	Magnetic random access memory with multiple free layers The present invention is directed to a magnetic random access memory element comprising a first magnetic reference layer, a first insulating tunnel junction layer, a first magnetic free layer, a first coupling layer, a second magnetic free layer, a second coupling layer, a third magnetic free layer, a second insulating tunnel junction layer, and a second magnetic reference layer formed in sequence. The first and second magnetic reference layers have respectively a first and second fixed magnetization directions that are substantially perpendicular to respective layer planes and are substantially opposite to each other. The first, second, and third magnetic free layers have respectively a first, second, and third variable magnetization directions that are substantially perpendicular to respective layer planes. The second variable magnetization direction may be parallel or anti-parallel to the first and third variable magnetization directions.
US09166140B2	Piezoelectric material, piezoelectric element, and electronic device There is provided a piezoelectric material not containing any lead component, having stable piezoelectric characteristics in an operating temperature range, a high mechanical quality factor, and satisfactory piezoelectric characteristics. The piezoelectric material according to the present invention includes a main component containing a perovskite-type metal oxide that can be expressed using the following general formula (1), and subcomponents containing Mn, Li, and Bi. When the metal oxide is 100 parts by weight, the content of Mn on a metal basis is not less than 0.04 parts by weight and is not greater than 0.36 parts by weight, content α of Li on a metal basis is equal to or less than 0.0012 parts by weight (including 0 parts by weight), and content β of Bi on a metal basis is not less than 0.042 parts by weight and is not greater than 0.850 parts by weight (Ba1-xCax)a(Ti1-y-zZrySnz)O3 (1) (in the formula (1), 0.09≦x≦0.30, 0.025≦y≦0.085, 0≦z≦0.02, and 0.986≦a≦1.02).
US09166139B2	Method for thermally cycling an object including a polarizable material A method of thermally cycling an object includes alternately contacting the object with vapor from each of a first liquid-vapor two-phase system and of a second liquid-vapor two-phase system of a working fluid, each of the systems two-phase including a liquid phase and a separate vapor phase. The first system two-phase is at a higher temperature and pressure than the second system two-phase. The object can include one or more layers of an electrically or magnetically polarizable material. The object can be housed in a chamber thermal and alternately contacted with vapor from the first liquid-vapor two-phase system and the second liquid-vapor two-phase system contained in a first reservoir and in a second reservoir, respectively.
US09166134B2	Light emitting element, backlight module, liquid crystal display device A light emitting element comprises: a printed circuit board, a chip disposed on a first face of the printed circuit board, a first encapsulation body and a second encapsulation body. The first encapsulation body covers the chip, and the second encapsulation body covers a second face of the printed circuit board or a part of the second face of the printed circuit board. A first pipe and a second pipe are extended respectively from two positions of the first encapsulation body and are respectively connected to two positions of the second encapsulation body. Fluid is encapsulated within the first encapsulation body, the first pipe, the second encapsulation body and the second pipe.
US09166132B2	Light-emitting element mounting package having heat radiation route, manufacturing method of the same, and light-emitting element package A light-emitting element mounting package including a first wiring forming a first light-emitting element mounting portion, which is provided on one surface of a substrate to mount a light-emitting element, and a first through wiring having one end and another end, the one end being electrically connected to the first light-emitting element mounting portion so as to be thermally transferable, and the other end protruding from another surface of the substrate.
US09166129B2	Batwing LED with remote phosphor configuration A lens is formed over one or more light-emitting devices disposed over a substrate. The lens includes a trench that circumferentially surrounds the one or more light-emitting devices. The trench is filled with a phosphor-containing material.
US09166128B2	Light-emitting assembly and method for manufacturing the same A light-emitting assembly and a method for manufacturing the same are provided. The light-emitting assembly includes a circuit board with a light-emitting element and a plurality of optical microstructures disposed thereon. The optical microstructures adjacent to the light-emitting element absorb or guide a portion of light emitted from the light-emitting element.
US09166127B2	Light source module Disclosed is a light source module which does not require rigorous adjustments of the light direction and is free from luminance unevenness. Specifically disclosed is a light source module (1) which comprises a light-emitting element (40), and a light direction changing element (10) which is composed of a transparent resin and discharges the light emitted from the light-emitting element (40) toward the lateral direction. The light direction changing element (10) contains not less than 0.01% by weight but not more than 0.1% by weight of a light-diffusing agent (14) per 100% by weight of the transparent resin.
US09166120B2	LED device having improved luminous efficacy There are provided a light emitting diode (LED) device including an LED chip emitting light within a specific wavelength region, a transparent resin layer covering a light emission surface of the LED chip, and a color conversion layer formed to be spaced apart from the LED chip by the transparent resin layer to cover the transparent resin layer and including at least one type of phosphor converting light emitted from the LED chip into light within a different wavelength region, wherein a mean free path of phosphor particles included in the color conversion layer is 0.8 mm or more at a temperature of 5500 K.
US09166117B2	Light emitting device and method for mixing light thereof An exemplary light emitting device includes a blue-green light source and a orange-red light source. The blue-green light source emits blue-green light and the orange-red light source emits orange-red light when they are activated. The blue-green light and the orange-red light are mixed together to obtain white light.
US09166116B2	Light emitting device The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance.
US09166113B2	Light emitting device and method of manufacture A light emitting device includes a conductive support layer, a light emitting structure layer on the conductive support layer, a first transparent conductive layer and a second transparent conductive layer disposed between the conductive support layer and the light emitting structure layer, and an electrode on the light emitting structure layer.
US09166108B2	Semiconductor light-emitting device and method of forming the same A semiconductor light-emitting device has a first principal surface, a second principal surface formed on a side opposite to the first principal surface, and a light-emitting layer. A p-electrode on the second principal surface is in the region of the light-emitting layer and surrounds an n-electrode. An insulating layer on the side of the semiconductor layer surrounds the p-and the n-electrodes. A p-metal pillar creates an electrical connection for the p-electrode, and an n-metal pillar creates an electrical connection for the n-electrode. A resin layer surrounds the end portions of the p-and the n-metal pillars, and also covers the side surface of the semiconductor layer, the second principal surface, the p-electrode, the n-electrode, the insulating layer, the p-metal pillar and the n-metal pillar.
US09166105B2	Light emitting device A light-emitting device includes: a substrate; a first semiconductor layer disposed on the substrate and having a first surface; a rough structure formed in the first semiconductor layer, the rough structure comprising porous structures formed therein and a portion of the porous structures having openings exposed on the first surface of the first semiconductor layer; and an active layer formed on the first semiconductor layer.
US09166102B2	Group III nitride semiconductor light-emitting device including a superlatice layer A Group III nitride semiconductor light-emitting device includes at least an n-type-layer-side cladding layer, a light-emitting layer, and a p-type-layer-side cladding layer, each of the layers being formed of a Group III nitride semiconductor. The n-type-layer-side cladding layer is a superlattice layer having a periodic structure including an InyGa1-yN (0
US09166100B2	Light emitting device Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a light emitting structure having a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers. The active layer includes a plurality of well layers and barrier layers. An outermost barrier layer of the barrier layers includes a plurality of first layers; and a plurality of second layers.
US09166099B2	Graphene light-emitting device and method of manufacturing the same A graphene light-emitting device and a method of manufacturing the same are provided. The graphene light-emitting device includes a p-type graphene doped with a p-type dopant; an n-type graphene doped with an n-type dopant; and an active graphene that is disposed between the type graphene and the n-type graphene and emits light, wherein the p-type graphene, the n-type graphene, and the active graphene are horizontally disposed.
US09166098B2	Nitride semiconductor light emitting device There is provided a nitride semiconductor light emitting device including an active layer of a multi quantum well structure, the nitride semiconductor light emitting device including: a substrate; and a buffer layer, an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer sequentially stacked on the substrate, wherein the active layer is formed of a multi quantum well structure where a plurality of barrier layers and a plurality of well layers are arranged alternately with each other, and at least one of the plurality of barrier layers includes a first barrier layer including a p-doped barrier layer doped with a p-dopant and an undoped barrier layer.
US09166087B2	Wind uplift-resistant photovoltaic roofing elements and photovoltaic roofing systems The present invention relates generally to the photovoltaic generation of electrical energy. The present invention relates more particularly to photovoltaic arrays for use in photovoltaically generating electrical energy. Aspects of the present invention provide a variety of photovoltaic roofing elements and systems that include, for example, interlocking geometries to provide for water handling and integration with conventional roofing materials; wire management features that can protect wiring and associated electrical components from physical and/or environmental damage; and wind clip and ledge features configured to prevent against wind uplift of the photovoltaic roofing elements when installed.
US09166085B2	Method for manufacturing solar cell module provided with an edge space The solar cell module having a preferable edge space that prevents characteristics of a solar cell such as conversion efficiency from being deteriorated without making processes complicated is provided. In a method for manufacturing a solar cell module including a substrate glass, a first layer formed on the substrate glass and a second layer formed on the first layer, the method includes a step of forming a first edge space having a first width by removing the first layer and the second layer by the first width from an end part of the glass substrate and a step of forming a second edge space by removing only the second layer by a second width from the end part of the glass substrate, and the width of the second edge space is larger than the width of the first edge space.
US09166080B2	Transparent electrode for thin film solar cell, substrate having transparent electrode for thin film solar cell and thin film solar cell using same, and production method for transparent electrode for thin film solar cell Disclosed are: a transparent electrode having a zinc oxide film wherein initial characteristics and humidity resistance during long-time use coexist; and a thin film solar cell provided with said electrode. The transparent electrode contains a transparent conductive layer mainly made of zinc oxide. The transparent conductive film preferably has the following characteristics: having surface irregularities; a carrier concentration of 9×1019 cm−3 or less; a crystal structure having a (110) preferred orientation; a ratio of a (110) peak intensity to a (002) peak intensity I(110)/I(002) measured by X-ray diffraction being 50 or more; and a crystallite with a (110) orientation has a size of: 23 nm or more and 50 nm or less, in a planar direction parallel to a substrate; and 30 nm or more and 60 nm or less, in a planar direction perpendicular to the substrate.
US09166079B2	Method of forming contacts for a back-contact solar cell Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.
US09166075B2	Solar cell A solar cell includes a silicon substrate, an aluminum electrode that collects electricity from the rear surface of the silicon substrate, and a silver electrode that extracts output from the aluminum electrode. The aluminum electrode includes an opening formed on the rear surface of the silicon substrate. On a side of the opening is formed a notch that recesses parallel to the direction in which principal stress acts in a plane of the silicon substrate. The silver electrode covers at least the opening and the notch of the aluminum electrode.
US09166072B2	Field-effect localized emitter photovoltaic device Photovoltaic structures are provided with field-effect inversion/accumulation layers as emitter layers induced by work-function differences between gate conductor layers and substrates thereof. Localized contact regions are in electrical communication with the gate conductors of such structures for repelling minority carriers. Such localized contact regions may include doped crystalline or polycrystalline silicon regions between the gate conductor and silicon absorption layers. Fabrication of the structures can be conducted without alignment between metal contacts and the localized contact regions or high temperature processing.
US09166070B2	Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes: an organic substrate; an integrated circuit and a chip part provided on the organic substrate; a molded section including a central portion and a peripheral portion, and forming, as a whole, a concave shape, the central portion sealing the integrated circuit and the chip part on the organic substrate, and the peripheral portion standing around the central portion; and a solid-state image pickup element provided on the central portion of the molded section, the solid-state image pickup element having a top edge that is lower in position in a thickness direction than a top edge of the peripheral portion of the molded section.
US09166064B2	Junction field effect transistor In a high voltage JFET, a p-floating region is provided in the surface layer of an n-drift region, thereby increasing the resistance R of the n-drift region and minimizing the voltage divided at a pn junction. This makes it possible to improve ESD capacity without increasing device size and without making the cutoff current smaller.
US09166061B2	Semiconductor device Provided is a transistor which includes an oxide semiconductor film and has stable electrical characteristics. In the transistor, over an oxide film which can release oxygen by being heated, a first oxide semiconductor film which can suppress oxygen release at least from the oxide film is formed. Over the first oxide semiconductor film, a second oxide semiconductor film is formed. With such a structure in which the oxide semiconductor films are stacked, the oxygen release from the oxide film can be suppressed at the time of the formation of the second oxide semiconductor film, and oxygen can be released from the oxide film in later-performed heat treatment. Thus, oxygen can pass through the first oxide semiconductor film to be favorably supplied to the second oxide semiconductor film. Oxygen supplied to the second oxide semiconductor film can suppress the generation of oxygen deficiency, resulting in stable electrical characteristics.
US09166058B2	Method for manufacturing semiconductor device To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
US09166055B2	Semiconductor device and method for manufacturing the same A transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use, and a semiconductor device including the transistor are provided. In a transistor in which a semiconductor layer, a source electrode layer and a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order over an oxide insulating film, an oxide semiconductor stack composed of at least two oxide semiconductor layers having different energy gaps is used as the semiconductor layer. Oxygen and/or a dopant may be introduced into the oxide semiconductor stack.
US09166053B2	FinFET device including a stepped profile structure A FinFET device and a method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate including a fin structure, the fin structure including a first and a second fin. The FinFET device further includes a shallow trench isolation (STI) feature disposed on the substrate and between the first and the second fins. The FinFET device further includes a gate dielectric disposed on the first and the second fins. The FinFET device further includes a gate structure disposed on the gate dielectric. The gate structure traverses the first fin, the second fin, and the STI feature between the first fin and the second fin and has a longitudinal stepped profile.
US09166049B2	Method to enhance strain in fully isolated finFET structures Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET.
US09166048B2	Lateral/vertical semiconductor device A lateral semiconductor device and/or design including a space-charge generating layer and electrode located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel.
US09166047B2	Switch circuit using LDMOS device The present invention relates to a switch circuit, and more particularly, to a switch circuit that uses an LDMOS (lateral diffusion metal oxide semiconductor) device inside an IC (Integrated Circuit). In the switch circuit that uses the LDMOS device according to an embodiment of the present invention, a gate-source voltage (VGS) of the LDMOS device may be stably controlled through a current source and resistances, the characteristics of a switch may be maintained regardless of the voltages of both terminals (A and B) by using an N-type LDMOS and a P-type LDMOS in a complementary manner, and the current generated by the current source is offset inside the switch without flowing to the outside of the switch.
US09166044B2	Raised epitaxial LDD in MuGFETs Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.
US09166041B2	Semiconductor device and method of manufacturing the same In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.
US09166040B2	Semiconductor device A semiconductor device disclosed herein is provided with: a source electrode; a gate electrode; a drain electrode; a first region of a first conductivity type formed in a range exposed at an upper surface of the semiconductor substrate a second region of a second conductivity type; a third region of the first conductivity type; and a fourth region of the first conductivity type. The fourth region includes: a first drift region formed in a range exposed at the upper surface; a second drift region having a first conductivity type impurity concentration higher than that of the first drift region, and adjacent to the first drift region; and a low concentration drift region having a first conductivity type impurity concentration lower than that of the first drift region. The first drift region is projected to a second region side than the second drift region.
US09166032B1	Non-volatile memory device According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.
US09166027B2	IGBT with reduced feedback capacitance An IGBT includes at least one first type transistor cell, including a base region, a first emitter region, a body region, and a second emitter region. The body region is arranged between the first emitter region and the base region. The base region is arranged between the body region and the second emitter region. The IGBT further includes a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a base electrode adjacent the base region and dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A doping concentration of the first base region section is higher than a doping concentration of the second base region section.
US09166023B2	Bulk finFET semiconductor-on-nothing integration Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin.
US09166022B2	Fin-like field effect transistor (FinFET) device and method of manufacturing same A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.
US09166017B2	Method of manufacturing semiconductor device and semiconductor device Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.
US09166016B1	Semiconductor device and method for fabricating the same Provided is a method for fabricating a semiconductor device including the following steps. A silicon-containing conductive layer is formed on a substrate. Then, a dielectric layer is formed around the silicon-containing conductive layer. A portion of the dielectric layer is removed to expose a first sidewall of the silicon-containing conductive layer. A shielding structure is formed on a partial surface of the silicon-containing conductive layer, and the shielding structure exposes at least the first sidewall. A metal layer is formed on the substrate to cover the silicon-containing conductive layer not covered by the shielding structure. A salicide process is performed to form a silicide layer.
US09166013B2	Nonvolatile memory device and method for fabricating the same A nonvolatile memory device having a plurality of unit cells, each of the plurality of unit cells includes a first transistor suitable for having a fixed threshold voltage, and a second transistor suitable for coupling to the first transistor in parallel and having a variable threshold voltage.
US09166012B2	Semiconductor memory devices including an air gap and methods of fabricating the same Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.
US09166009B2	Semiconductor apparatus and method for making semiconductor apparatus A semiconductor apparatus invention includes a substrate (1), an epitaxial layer (2) formed on the substrate (1), a gate electrode (3), a source electrode (4), and a drain electrode (5) that are formed on the epitaxial layer. The source electrode (4) and the drain electrode (5) each include at least two first divided electrodes that are formed to extend in parallel to each other in a first direction, inter-electrode distances Ps and Pd between the first divided electrodes are greater than or equal to a radius of an abnormal growth portion formed on a surface of the epitaxial layer (2), and widths of the first divided electrodes are less than or equal to the radius of the abnormal growth portion.
US09166006B1	Methods to improve the performance of compound semiconductor devices and field effect transistors Three methods will be described which may be used to improve the performance of compound semiconductor devices and Field Effect Transistors. In the first method, implementation of more than one sheet of 2DEG or high-density electrons in compound semiconductor devices will be described which may be used to improve the performance of compound semiconductor diodes, resistors and transistors. In the second method, implementation of at least one discontinuity in sheet or sheets of 2DEG or high-density electrons will be discussed which can be used to improve the performance of compound semiconductor diodes, resistors and transistors. In the third method, a way to form an electrical connection between an electrode and a sheet of 2DEG or high density electrons will be presented which may be implemented in compound semiconductor devices to reduce the contract resistance between an electrode and a sheet of 2DEG or high-density electrons.
US09166005B2	Semiconductor device with charge compensation structure A semiconductor device is provided. The semiconductor device includes a semiconductor body having a main surface. In a vertical cross-section which is substantially orthogonal to the main surface the semiconductor body includes a vertical trench, an n-type silicon semiconductor region, and two p-type silicon semiconductor regions each of which adjoins the n-type silicon semiconductor region and is arranged between the n-type silicon semiconductor region and the main surface. The vertical trench extends from the main surface at least partially into the n-type silicon semiconductor region and includes a compound semiconductor region which includes silicon and germanium and is arranged between the two p-type silicon semiconductor regions. The compound semiconductor region and the two p-type silicon semiconductor regions include n-type dopants and p-type dopants. An integrated concentration of the n-type dopants of the compound semiconductor region is larger than an integrated concentration of the p-type dopants of the compound semiconductor region.
US09166002B2	N-doped single crystal diamond substrates and methods therefor The disclosure relates to the formation of n-doped single crystal diamond (SCD). In general, a SCD substrate is preferentially anisotropically etched to provide one or more recesses in the SCD substrate, where the recesses are defined by (1 1 1) surface sidewalls resulting from the preferential anisotropic etching process. The recesses generally have a pyramidal shape. N-type doped SCD (e.g., using a phosphorous dopant) is then deposited into the preferentially anisotropically etched recesses. When the SCD substrate is a p-type diamond (e.g., using a boron dopant), the resulting structure can be used as a p-n junction, for example for use in various power electronic apparatus such as diodes, etc.
US09165996B2	Organic light emitting display device and manufacturing method thereof An organic light emitting display device and a method of manufacturing the same are proposed. The organic light emitting display device includes a display unit having a plurality of sub-pixels, each of which includes a pixel electrode and a counter electrode facing each other and a light emitting layer interposed therebetween; an encapsulation substrate, which covers the display unit; and an auxiliary electrode, which is formed on a surface of the encapsulation substrate, which faces the display unit, and is connected to the counter electrode. Using the structure, voltage drop may be effectively reduced by connecting an auxiliary electrode formed on an encapsulation substrate to a counter electrode, thereby improving reliability of an organic light emitting display device employing the same.
US09165993B2	Capacitor device, organic light emitting display apparatus including the capacitor device, and method of manufacturing the organic light emitting display apparatus A capacitor device includes two top capacitor electrodes separated from each other and symmetrical to each other, two intermediate capacitor electrodes symmetrical to each other and respectively overlapping the top capacitor electrodes, a bridge coupling the intermediate capacitor electrodes without overlapping the top capacitor electrodes, and a driving voltage line coupled to the bridge and configured to apply a common voltage to the intermediate capacitor electrodes.
US09165989B2	High-yield fabrication of large-format substrates with distributed, independent control elements A large-format substrate with distributed control elements is formed by providing a substrate and a wafer, the wafer having a plurality of separate, independent chiplets formed thereon; imaging the wafer and analyzing the wafer image to determine which of the chiplets are defective; removing the defective chiplet(s) from the wafer leaving remaining chiplets in place on the wafer; printing the remaining chiplet(s) onto the substrate forming empty chiplet location(s); and printing additional chiplet(s) from the same or a different wafer into the empty chiplet location(s).
US09165988B2	Organic light-emitting display apparatus having dual insulating parts An organic light-emitting display apparatus is disclosed. The organic light-emitting display apparatus includes a substrate; a thin film transistor (TFT) formed on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; a first insulating layer formed on the TFT; a pixel electrode; a second insulating layer formed on the first insulating layer; and an opposite electrode formed on the intermediate layer.
US09165985B2	Organic light-emitting display device An organic light-emitting display device includes a first substrate having transmitting regions and pixel regions separated from each other by the transmitting regions, a plurality of thin film transistors on the first substrate in the pixel regions, a passivation layer covering the plurality of thin film transistors, a plurality of pixel electrodes on the passivation layer and electrically connected to the thin film transistors, the pixel electrodes being in the pixel regions and overlapping the thin film transistors, an opposite electrode in the transmitting regions and the pixel regions, the opposite electrode facing the plurality of pixel electrodes and being configured to transmit light, an organic emission layer interposed between the pixel electrodes and the opposite electrode, and a color filter in corresponding pixel regions.
US09165982B2	Optical films for reducing color shift and organic light-emitting display apparatuses employing the same Optical films, and organic light-emitting display apparatuses employing the same, include a high refractive index pattern layer including a first surface and a second surface facing each other, wherein the first surface includes a pattern having a plurality of grooves. The plurality of grooves each have a curved surface and a depth greater than a width thereof. The high refractive index pattern layer is formed of a material having a refractive index greater than 1. The optical films, and the organic light-emitting display apparatuses, further include a low refractive index pattern layer formed of a material having a refractive index smaller than the refractive index of the material constituting the high refractive index pattern layer. The low refractive index pattern layer includes a filling material for filling the plurality of grooves.
US09165975B2	Solid-state imaging device, method for manufacturing solid-state imaging device, and imaging apparatus A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.
US09165967B2	Semiconductor structure able to receive electromagnetic radiation, semiconductor component and process for fabricating such a semiconductor structure A semiconducting structure configured to receive electromagnetic radiation and transform the received electromagnetic radiation into an electric signal, the semiconductor structure including a semiconducting support within a first surface defining a longitudinal plane, a first zone with a first type of conductivity formed in the support with a second zone with a second type of conductivity that is opposite of the first type of conductivity to form a semiconducting junction. A mechanism limiting lateral current includes a third zone formed in the support in lateral contact with the second zone, the third zone having the second type of conductivity for which majority carriers are electrons. The third zone has a sufficient concentration of majority carriers to have an increase in an apparent gap due to a Moss-Burstein effect.
US09165964B2	Image sensor and image capture apparatus An image sensor in which each pixel includes a first sub-pixel including a first semiconductor layer, a second sub-pixel including a second semiconductor layer having a polarity different from a polarity of the first semiconductor layer, a third semiconductor layer having a polarity equal to the polarity of the first semiconductor layer, and a microlens, and which includes a plurality of pixels in which the first semiconductor is included in the second semiconductor layer, and the second semiconductor layer is included in the third semiconductor layer, wherein a center of gravity position of a light-receiving surface defining the first semiconductor layer is different from a center of gravity position of a light-receiving surface defining both the first semiconductor layer and the second semiconductor layer.
US09165962B2	Solid state imaging device A solid state imaging device includes a semiconductor layer, and a light shielding portion. The semiconductor layer has multiple photoelectric conversion elements. The light shielding portion is provided in the semiconductor layer, and has a light shielding member whose interface with the semiconductor layer is covered by an insulating film. The light shielding portion includes a light shielding region and an element isolation region. The light shielding region is provided in the semiconductor layer on the side close to the light receiving surface of the photoelectric conversion element for shielding light incident on the photoelectric conversion element from a specific direction. The element isolation region is formed to project in the depth direction of the semiconductor layer from the light shielding region toward a portion between the multiple photoelectric conversion elements in order to electrically and optically isolate the multiple photoelectric conversion elements from one another.
US09165960B2	Pixel circuit, active sensing array, sensing device and driving method thereof A pixel circuit, an active sensing array, a sensing device, and a driving method thereof are provided. The pixel circuit includes a sensing transistor, a reset transistor, and a storage capacitor. The sensing transistor is electrically connected to a sensing element and a data line. The reset transistor is electrically connected to a first scan line and the sensing transistor. The storage capacitor is electrically connected to the sensing transistor and a second scan line. During a compensation period, the reset transistor is turned on in response to a first scanning pulse from the first scan line, so that the sensing transistor is connected into a diode configuration, and the storage capacitor charges and discharges to a threshold voltage of the sensing transistor through the sensing transistor having the diode configuration in response to switching of a level of the data line.
US09165955B2	Array substrate and method for manufacturing the same Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.
US09165954B2	Array substrate and method for manufacturing the same, and display device The present invention provides an array substrate and a method for manufacturing the same, and a display device. In the method for manufacturing the array substrate, a one-time patterning process is employed to form a channel region, a source electrode and a drain electrode of the array substrate. Specifically, a channel region, a source region and a drain region that are consisted of a metal oxide layer are formed via a one-time patterning process, and a heat treatment is carried out on the metal oxide layer of the source region and the drain region in hydrogen gas, thereby forming a conducting source electrode and a conducting drain electrode, respectively. By the technical solution of the invention, the manufacturing process of the array substrate can be simplified, and the manufacturing cost of the array substrate can be lowered.
US09165950B2	Anti-static structure of array substrate The present invention provides an anti-static structure of an array substrate, which comprises: an effective region 20 of the array substrate, a gate line shorting bar 30 and a data line shorting bar 40, the effective region 20 of the array substrate is provided with a plurality of parallel gate lines 22 and data lines 24, the gate line shorting bar 30 is electrically connected with one side of the plurality of gate lines 22, the data line shorting bar 40 is electrically connected with one side of the plurality of data lines 24. The present invention only utilizes a gate line shorting bar to short all gate lines and utilizes a data line shorting bar to short all data lines, in order to greatly avoid the abnormal discharge of the plasma generated when the hole is formed cause static damage to the metal overlapping traces of the shorting bar.
US09165945B1	Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.
US09165941B2	Semiconductor memory devices and methods for fabricating the same A semiconductor memory device includes a substrate having a cell region and a peripheral region, a gate stack including a plurality of insulating layers and a plurality of gates alternately stacked on the cell region of the substrate, a stress buffer layer on the gate stack, a vertical channel that extends vertically through the gate stack and is electrically connected to the substrate, a memory layer wrapped around the vertical channel. A bit line electrically connected to the vertical channel may be provided on the gate stack. In a method of fabricating a semiconductor device, the buffer stress layer is formed directly on an upper insulating layer of a stack whose shape is altered to form the gate stack to inhibit warping of the substrate during fabrication of the device.
US09165939B2	Method for fabricating nonvolatile memory device A method for fabricating a nonvolatile memory device includes forming a first insulation layer and a first conductive layer on a substrate including a first region and a second region, forming a first isolation trench in the first region by etching the first conductive layer, the first insulation layer, and the substrate, forming a first isolation layer filled in the first isolation trench, forming a second insulation layer and a conductive capping layer, etching the capping layer and the second insulation layer, forming a second conductive layer, and forming first gate patterns by etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the first region, and forming a second isolation trench in the second region by etching the second conductive layer, the first conductive layer, the first insulation layer, and the substrate.
US09165935B2	Semiconductor devices and methods for manufacturing the same A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars.
US09165934B2	Semiconductor devices including insulating extension patterns between adjacent landing pads and methods of fabricating the same A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.
US09165933B2	Vertical bit line TFT decoder for high voltage operation A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.
US09165931B1	Apparatus for field-programmable gate array with configurable architecture and associated methods An integrated circuit (IC) includes a substrate that is common to the IC and variants of the IC. The IC also includes a first set of interconnect layers fabricated above the substrate. The first set of interconnect layers is used to couple programmable interconnect of the IC to a first circuit in the substrate. The IC further includes a second set of interconnect layers fabricated above the substrate. The second set of interconnect layers is used to differentiate features of the IC from variants of the IC by selectively coupling the programmable interconnect to a second circuit in the substrate.
US09165929B2	Complementarily strained FinFET structure A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.
US09165927B2	Semiconductor device In a semiconductor device, each of a first connection metal member, a second connection metal member, a third connection metal member, and a fourth connection metal member electrically connects a corresponding line to a corresponding one of main electrodes formed on lower surfaces and upper surfaces of first and second semiconductor elements. A cross-sectional area of each of the first connection metal member, the second connection metal member, the third connection metal member, and the fourth connection metal member is larger than a cross-sectional area of a fifth connection metal member that is disposed at a region located outside regions of the first and second semiconductor elements in a plan view.
US09165926B2	Dynamic threshold MOS and methods of forming the same A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.
US09165925B2	Structures and methods for ring oscillator fabrication Structures and methods are provided for fabricating a ring oscillator including a plurality of stages. An example multi-layer structure includes a first device layer, a second device layer, and an inter-level connection structure. The first device layer includes a first transistor structure associated with a first stage of a ring oscillator. The second device layer is formed on the first device layer and includes a second transistor structure associated with a second stage of the ring oscillator. Further, the first inter-level connection structure includes one or more first conductive materials and is configured to electrically connect to the first transistor structure and the second transistor structure.
US09165918B1	Composite semiconductor device with multiple threshold voltages A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.
US09165915B2	Flip-chip hybridization of microelectronic components using suspended fusible resistive connection elements A method of forming a hybridized device comprising forming a first microelectronic component provided, on a surface, with metal balls, and a second microelectronic component provided, on a surface, with connection elements corresponding to said metal balls, and hybridizing the first and second components to attach the metal balls of the first component to the connection elements of the second component. The manufacturing of the second microelectronic component comprises forming a substrate provided with cavities at the locations provided for the connection elements, and forming resistive elements made of fusible metal respectively suspended above the cavities. The hybridizing of the first and second components comprises transferring the first component onto the second component to have the metal balls rest on the suspended resistive elements, and circulating an electric current through the resistive elements to melt said elements.
US09165908B2	On-SOI integrated circuit comprising a triac for protection against electrostatic discharges An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.
US09165905B2	Method for connecting a plurality of unpackaged substrates A plurality of unpackaged substrates connected to one another is disclosed. The stepped structures on and/or in a first main area of a first substrate include a plurality of integrated circuits. The stepped structures run between the integrated circuits. The first conductor tracks extend from at least some contact connections of the respective integrated circuits as far as the stepped structures. The first substrate is connected on the side of the first main area to a further substrate. The first substrate is severed from a second main area opposite to the first main area such that the first substrate is divided into a plurality of substrate pieces. Each substrate piece has one of the integrated circuits. The first conductor tracks are accessible in interspaces between the substrate pieces. The second conductor tracks are formed from the second main area. At least some of the second conductor tracks lead from the second main area over side walls of the substrate pieces as far as the first conductor tracks.
US09165898B2	Method of manufacturing semiconductor device with through hole A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate.
US09165894B2	Cascode cell having DC blocking capacitor A cascode gain stage apparatus includes an input transistor having an RF input node and a transistor output node, an output transistor having a transistor input node and an RF output node, and a DC blocking capacitor connected between the transistor input and transistor output nodes.
US09165893B2	Semiconductor device including coupling conductive pattern A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.
US09165892B2	Electronic component According to one embodiment, an electronic component includes a device having a plurality of electrodes; a lead electrically connected to each of the plurality of electrodes; a first resin body sealing the device and a portion of the lead; and a first conductive body connected to the leads and contactable with a second conductive body.
US09165889B2	Alignment mark definer An alignment mark definer is configured to provide a geometrical definition for an actual alignment structure to be formed at a temporary surface of a substrate based on a desired appearance of the alignment mark and on an expected alteration of an appearance of the actual alignment structure caused by a deposition material deposited on the temporary surface and the actual alignment structure.
US09165884B2	Method for fabricating a semiconductor device with formation of conductive lines A substrate having a first region and second regions disposed on two sides of the first region; a first group of conductive lines extending from the first region to the second regions on the substrate; a second group of conductive lines alternating with the first group of times and extending from the first region to the second regions on the substrate; interlayer insulating layers formed over the substrate; insulating layers formed in first open regions of the interlayer insulating layers and the first group of conductive lines in the second region; and contact plugs contacting second group of conductive line formed in second open regions of the interlayer insulating layer in the second region.
US09165882B2	Power rail for preventing DC electromigration A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.
US09165872B2	Chip scale diode package no containing outer lead pins and process for producing the same A novel chip scale diode package due to no containing outer lead pins is miniaturized like a chip scale appearance to promote dimensional accuracy so that the diode package is so suitably produced by automation equipment to get automated mass production; the produced diode package may contain one or more diode chips to increase versatile functions more useful in applications, such as produced as a SMT diode package or an array-type SMT diode, and the present diode package due to made of no lead-containing material conforms to requirements for environmental protection.
US09165870B2	Semiconductor storage device and manufacturing method thereof According to the embodiment, a semiconductor storage device includes an organic substrate, a semiconductor memory chip, a lead frame, and a resin mold section. The lead frame includes an adhering portion. The organic substrate is singulated to have a shape in which a portion in which the organic substrate does not overlap with the placing portion is larger than a portion in which the organic substrate overlaps with the placing portion, in plan view. The lead frame further includes a first extending portion in the adhering portion that extends to a surface different from a surface of the resin mold section on a side of an insertion direction.
US09165868B2	Semiconductor device A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group.
US09165867B1	Semiconductor device with lead frame contact solder balls and related methods A semiconductor device may include an integrated circuit (IC), and lead frame contact areas adjacent the IC. Each lead frame contact area may have an opening therein. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may also include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires. Solder balls are within the respective opening.
US09165866B2	Stacked dual chip package having leveling projections The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.
US09165865B2	Ultra-thin power transistor and synchronous buck converter having customized footprint A packaged power transistor device (100) having a leadframe including a flat plate (110) and a coplanar flat strip (120) spaced from the plate, the plate having a first thickness (110a) and the strip having a second thickness (120a) smaller than the first thickness, the plate and the strip having terminals (212; 121a). A field-effect power transistor chip (210) having a third thickness (210a), a first and a second contact pad on one chip side, and a third contact pad (211) on the opposite chip side, the first pad being attached to the plate, the second pad being attached to the strip, and the third pad being coplanar with the terminals. Encapsulation compound (130) filling the thickness difference between plate and strip, and spaces between chip and terminals, wherein the compound has a surface (101) coplanar with the plate surface (111) and the opposite surface (102) coplanar with the third pad (211) and the terminals (212; 212a), the distance (104) between the surfaces being equal to the sum of the first (110a) and third (210a) thicknesses.
US09165858B2	Liquid-cooled arrangement having modular power semiconductor modules and at least one capacitor device, and power semiconductor module therefor An arrangement having a cooling circulation, a plurality of modular power semiconductor modules and at least one capacitor, wherein a power semiconductor module has a power electronics switch and a cooling device, which is capable of carrying a flow of a cooling fluid, for cooling the switch, the cooling device having at least one cooling face, and four connection devices for the cooling fluid. The connection devices are arranged in pairs on main sides of the power semiconductor module. The power semiconductor modules have their main sides strung together modularly by connecting corresponding connection devices on successive power semiconductor modules. To this end, at least two successive power semiconductor modules have a capacitor arranged between them which, for its part, is cooled by means of the cooling circulation of the cooling fluid as provided by the arrangement.
US09165855B1	Semiconductor device with die attached heat spreader A packaged semiconductor device has an integrated circuit (IC) die and a heat spreader. The heat spreader has a first portion with holes formed entirely therethrough. The first portion is attached to the die using thermally-conductive adhesive that fills the holes. The holes enable the heat spreader to be attached to the die without placing excess pressure on the IC die that could cause the die to crack.
US09165854B2	Heat dissipation features, electronic devices incorporating heat dissipation features, and methods of making heat dissipation features Electronic devices incorporating a heat dissipation feature include an enclosure, and at least one heat-generating component positioned within the enclosure. The heat dissipation feature is sufficiently coupled to the at least one heat-generating component to facilitate conductive heat transfer from the heat-generating component. The heat dissipation feature includes a plurality of protrusions exposed externally to the enclosure. A thermally insulating material may be disposed on at least a tip portion of at least some of the protrusions. The thermally insulating material is selected to provide a touch temperature that is below a predetermined threshold. In some instances, the thermally insulating material can provide such a touch temperature by selecting the material to include properties for thermal conductivity (k), density (ρ), and specific heat (Cp) such that the product of kρCp results in a value less than a product of kρCp for human skin.
US09165853B2	Closed loop temperature controlled circuit to improve device stability An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.
US09165850B2	Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.
US09165849B2	Electronic device An electronic device is provided wherein the characteristics thereof are prevented from deteriorating. The electronic device (1) is provided with: a chip component (2) having an electronic element (22); a wiring board (3) on which the chip component (2) is mounted with a space therebetween, the space for containing the electronic element (22); a resin layer (4) provided from the surface of the chip component (2) to the surface of the wiring board (3) so as to surround the space; and an inorganic insulating layer (5), which is provided at the resin layer (4) and is positioned at the side of the space. Since entry of water vapor into the space can be reduced not only by means of the resin layer (4) but also by means of the inorganic insulating layer (5), the electronic device (1) having high airtight sealing performance can be provided.
US09165843B2	Systems and methods of automatically detecting failure patterns for semiconductor wafer fabrication processes A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.
US09165842B2	Short tail recovery techniques in wire bonding operations A method of operating a wire bonding machine is provided. The method includes: detecting a short tail condition after formation of a wire bond formed using a wire bonding tool; providing a bond head assembly of a wire bonding machine at an xy location of the wire bonding machine, the bond head assembly carrying the wire bonding tool; lowering the bond head assembly toward a contact surface at the xy location with a wire clamp of the wire bonding machine closed; opening the wire clamp; decelerating the bond head assembly as it is lowered toward the contact surface such that a portion of a wire extends below a tip of the wire bonding tool; closing the wire clamp; and performing a test to determine if an end of the portion of the wire extending below the tip of the bonding tool is in contact with the contact surface.
US09165840B2	Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.
US09165839B2	Plasma protection diode for a HEMT device The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. A first III-V compound layer is disposed over the silicon substrate. A second III-V compound layer is disposed over the first III-V compound layer. The semiconductor device includes a transistor disposed over the first III-V compound layer and partially in the second III-V compound layer. The semiconductor device includes a diode disposed in the silicon substrate. The semiconductor device includes a via coupled to the diode and extending through at least the first III-V compound layer. The via is electrically coupled to the transistor or disposed adjacent to the transistor.
US09165838B2	Methods of forming low resistance contacts Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.
US09165837B1	Method to form defect free replacement fins by H2 anneal Methods of forming a defect free heteroepitaxial replacement fin by annealing the sacrificial Si fin with H2 prior to STI formation are provided. Embodiments include forming a Si fin on a substrate; annealing the Si fin with H2; forming a STI layer around the annealed Si fin; annealing the STI layer; removing a portion of the annealed Si fin by etching, forming a recess; forming a replacement fin in the recess; and recessing the annealed STI layer to expose an active replacement fin.
US09165831B2	Dice before grind with backside metal A method including forming a plurality of dicing channels in a front side of a wafer; the plurality of dicing channels including a depth at least greater than a desired final thickness of the wafer, filling the plurality of dicing channels with a fill material and removing a portion of the wafer from a back side of the wafer until the desired final thickness is achieved, where a portion of the fill material within the plurality of dicing channel is exposed. The method further including depositing a metal layer on the back side of the wafer; removing the fill material from within the plurality of dicing channels to expose the metal layer at a bottom of the plurality of dicing channels, and removing a portion of the metal layer located at the bottom of the plurality of dicing channels.
US09165830B1	Array substrate and method of fabricating the same, and liquid crystal display device An array substrate, a method of fabricating the same, and a liquid crystal display device are disclosed. The method comprises: sequentially forming a first transparent conductive material layer, an insulation material layer, a semiconductor material layer and a photoresist layer on a substrate base and forming patterns including a gate line, a gate, a gate insulation layer, a semiconductor layer and a first transparent electrode by patterning process; forming a passivation layer and forming a source via and a drain via connected to the semiconductor layer in the passivation layer; sequentially forming a second transparent conductive material layer and a source-drain metal layer and forming patterns including a source, a drain and a second transparent electrode by patterning process, the gate insulation layer is formed only on the gate and the gate line, the source and the drain include stacked second transparent conductive material layer and source-drain metal layer.
US09165828B2	Semiconductor device comprising a fuse structure and a method for manufacturing such semiconductor device A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.
US09165819B2	High linearity SOI wafer for low-distortion circuit applications According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
US09165816B2	Method for singulating a component composite assembly A method relates to separating a component composite into a plurality of component regions, wherein the component composite is provided having a semiconductor layer sequence comprising a region for generating or for receiving electromagnetic radiation. The component composite is mounted on a rigid subcarrier. The component composite is separated into the plurality of component regions, wherein one semiconductor body is produced from the semiconductor layer sequence for each component region. The component regions are removed from the subcarrier.
US09165815B2	Wafer processing sheet Provided is a sheet for processing a wafer. The sheet can exhibit excellent heat resistance and dimensional stability, prevent breakage of a wafer in response to residual stress due to excellent stress relaxation properties, inhibit damage to or dispersion of the wafer due to application of a non-uniform pressure, and also exhibit excellent cuttability. The sheet can effectively prevent a blocking phenomenon from occurring during wafer processing. For these reasons, the sheet can be useful for processing a wafer in various wafer preparation processes such as dicing, back-grinding and picking-up.
US09165814B2	Electrical connector, electrical connection system and lithographic apparatus An electrical connector comprises a high voltage pad and a high voltage plate. When connected to another electrical connector, the two plates, which are at the same voltage as the pads, form a region of high voltage in which the field is low. The pads are positioned in that region. An electrostatic clamp of an EUV lithographic apparatus may have such a pad and plate, for connecting to the electrical connector. By placing the interconnection in a low field region, triple points (points of contact between a conductor, a solid insulator and a gas) may be present in that region.
US09165808B2	Metal organic chemical vapor deposition device and temperature control method therefor The present invention provides a metal organic chemical vapor deposition device and a temperature control method therefor. The device comprises: a chamber; a susceptor which is installed inside the chamber to allow rotation therein, wherein at least one substrate is settled thereon; a plurality of heaters which heat the susceptor, wherein the temperature is independently controlled; a gas sprayer which is positioned in the upper part of the susceptor, and sprays gases of group III and V toward the susceptor; a plurality of temperature detection sensors which are positioned in the upper part of the susceptor, and measure the temperature of heating regions heated by each heater; and a controller which retains temperature setting values necessary for the heating regions, and controls the temperature of the heating regions by comparing sensing temperature values detected by each temperature detection sensor with the setting values necessary for the heating regions. According to the present invention, the metal organic chemical vapor deposition device and the temperature control method therefor can uniformly apply necessary temperature ramping to the entire substrates during process by effectively adjusting the temperature conditions essential for every epitaxial process in the metal organic chemical vapor deposition device, which carries out the process by changing the temperature up to 1200° C. from room temperature. Therefore, the invention improves process efficiency and deposition uniformity.
US09165807B2	Substrate treating apparatus with vertical treatment arrangement including vertical blowout and exhaust units A substrate treating apparatus includes a treating block including a plurality of cells arranged one over another. Each cell has treating units for treating substrates and a single main transport mechanism for transporting the substrates to the treating units. Each cell also has a blowout unit for supplying a clean gas into a transporting space of the main transport mechanism and an exhaust unit for exhausting gas from the transporting space. The blowout unit and the exhaust unit are arranged one over the other in the transporting space to separate the transporting space of each cell from that of another cell.
US09165804B2	Methods of cooling process chamber components Methods for cooling process chamber components are provided herein. In some embodiments, a method of cooling a process chamber component may include reducing a power provided to a heater disposed proximate a surface of the process chamber component to reduce an amount of heat provided to the component by the heater; providing a coolant to coolant channels disposed within the process chamber component using a pulsed flow having a duty cycle until the process chamber component reaches a temperature that is less than or equal to a predetermined magnitude above a temperature of the coolant; and after the process chamber component reaches the temperature less than or equal to the predetermined magnitude above a temperature of the coolant, reducing the duty cycle of the pulsed flow of the coolant to zero.
US09165802B2	Methods for cleaving a bonded wafer structure Apparatus and methods for mechanically cleaving a bonded wafer structure are disclosed. The apparatus and methods involve clamps that grip the bonded wafer structure and are actuated to cause the bonded structure to cleave.
US09165800B2	Liquid processing method, liquid processing apparatus and storage medium Disclosed is a liquid processing method which includes holding the substrate by a holding part, rotating the substrate held by the holding part through a rotation driving part, and supplying a chemical liquid to a holding part-side surface of the substrate by a chemical liquid supply part. After the supply of the chemical liquid, rinsing liquid droplets are generated and supplied between the holding part and the substrate by supplying gas toward the holding part-side surface of the substrate from a gas supply part and, at the same time, supplying a rinsing liquid toward the holding part-side surface of the substrate from a rinsing liquid supply part. After the supply of the rinsing liquid droplets, the gas supply is halted and a rinsing liquid is additionally supplied to the holding part-side surface of the substrate from the rinsing liquid supply part.
US09165794B1	Partial glob-top encapsulation technique A electronic device includes: a circuit board; a semiconductor device, disposed on the circuit board; a cover material, disposed above the semiconductor device; a plurality of bonding wires, respectively connected between a plurality of first contact pads of the semiconductor device and a plurality of second contact pads of the circuit board; a first encapsulant, formed by a first material, arranged to encapsulate a plurality of second bonds formed by electrically connecting the bonding wires to the second contact pads; and a second encapsulant, formed by a second material that is different from the first material, arranged to encapsulate a plurality of first bonds formed by electrically connecting the bonding wires to the first contact pads.
US09165788B2	Post-deposition soft annealing The methods and apparatus disclosed herein concern a process that may be referred to as a “soft anneal.” A soft anneal provides various benefits. Fundamentally, it reduces the internal stress in one or more silicon layers of a work piece. Typically, though not necessarily, the internal stress is a compressive stress. A particularly beneficial application of a soft anneal is in reduction of internal stress in a stack containing two or more layers of silicon. Often, the internal stress of a layer or group of layers in a stack is manifest as wafer bow. The soft anneal process can be used to reduce compressive bow in stacks containing silicon. The soft anneal process may be performed without causing the silicon in the stack to become activated.
US09165787B2	Electronic devices having semiconductor memory units and method for fabricating the same The disclosed technology provides an electronic device and a fabrication method thereof. An electronic device according to an implementation of the disclosed technology may include: a first interlayer insulating layer formed over a substrate; first and second contact plugs passing through the first interlayer insulating layer to contact the substrate and alternately arranged to cross each other; a variable resistance element formed over the first interlayer insulating layer and coupled to the first contact plug; a second interlayer insulating layer formed over an entire structure including the first interlayer insulating layer; a third contact plug passing through the second interlayer insulating layer so as to be coupled to the variable resistance element, and a fourth contact plug passing through the second interlayer insulating layer so as to be contacted to the second contact plug; and conductive lines coupled to the third contact plug and the fourth contact plug, respectively.
US09165783B2	Method of patterning a low-k dielectric film Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.
US09165781B2	Composition for forming pattern reversal film and method for forming reversal pattern There is provided a silicon-containing composition for forming a pattern reversal film that can be reworked by an organic solvent that is normally used for the removal of resist patterns. A composition for forming a pattern reversal film, characterized by comprising: polysiloxane; an additive; and an organic solvent, wherein the polysiloxane has a structural unit of Formula (1) and a structural unit of Formula (2): (where R1 is a C1-8 alkyl group), and (where R2 is an acryloyloxy group or a methacryloyloxy group; and n is an integer of 2 to 4), and the additive is an organic acid having at least two of a carboxy group and/or a hydroxy group; and a pattern reversal film and a method for forming a reversal pattern by use of the composition.
US09165779B2	Flat SiC semiconductor substrate Methods for manufacturing silicon carbide wafers having superior specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR). The resulting SiC wafer has a mirror-like surface that is fit for epitaxial deposition of SiC. The specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR) of the wafer are preserved following the addition of the epitaxy layer.
US09165778B2	Systems and methods for chemical mechanical planarization with photoluminescence quenching Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system for performing chemical-mechanical planarization includes: a polishing pad configured to support an article for chemical-mechanical planarization (CMP), wherein the article includes a CMP stop material, a polishing head configured to perform chemical-mechanical planarization on the article, a light source configured to provide an incident light, a polishing fluid including a plurality of luminescent particles capable of emitting a fluorescent light in response to the incident light, a fluorescence detector configured to detect the intensity of the fluorescent light, and at least one processor coupled to the fluorescent detector and the polishing head, wherein the at least one processor is configured to control the polishing head based on the detected fluorescent light.
US09165776B2	Dry etching method There is provided according to the present invention a dry etching method for a laminated film, the laminated film being formed on a substrate and having a laminated structure in which silicon layers and insulating layers are laminated together with a hole or groove defined therein in a direction perpendicular to a surface of the substrate, the dry etching method comprising etching, with an etching gas, parts of the silicon layers appearing on an inner surface of the hole or groove, characterized in that the etching gas comprises: at least one kind of gas selected from the group consisting of ClF3, BrF5, BrF3, IF7 and IF5; and F2. It is possible by such a dry etching method to prevent non-uniformity of etching depth between the silicon layers.
US09165774B2	Semiconductor device and method of manufacturing the same A semiconductor device includes a plurality of transistors formed over a substrate, a support body including a horizontal portion and protrusions, wherein the horizontal portion covers at least one of the transistors, and the protrusions are formed over the horizontal portion and located between the transistors, and conductive layers and insulating layers alternately stacked over the support body and protruding upwardly along the sidewalls of the protrusions.
US09165771B2	Pulsed gas plasma doping method and apparatus A method and apparatus for doping a surface of a substrate with a dopant, with the dopant being for example phosphine or arsine. The doping is performed with a plasma formed primarily of an inert gas such as helium or argon, with a low concentration of the dopant. To provide conformal doping, preferably to form a monolayer of the dopant, the gas flow introduction location is switched during the doping process, with the gas mixture primarily introduced through a center top port in the process chamber during a first period of time followed by introduction of the gas mixture primarily through peripheral or edge injection ports for a second period of time, with the switching continuing in an alternating fashion as the plasma process.
US09165767B2	Semiconductor structure with increased space and volume between shaped epitaxial structures A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.
US09165765B1	Method for patterning differing critical dimensions at sub-resolution scales Techniques include a plasma oxidation treatment to modify a material to a predetermined thickness around a mandrel or spacer or other structure. This plasma oxidation is then followed by a chemical oxide removal treatment. With only a portion of the structures being oxidized, or by selective masking a portion of oxidized structures, the chemical oxide removal treatment essentially shrinks only a portion of the structures, thereby yielding structures having differing critical dimensions which can function as etch masks to transfer patterns into one or more underlying layers. Accordingly, structures having differing critical dimensions can be fabricated at sub-resolution scales.
US09165763B2	Coating treatment method A substrate is rotated at a first rotation number (first step). The rotation of the substrate is decelerated to 1500 rpm that is a second rotation number and the substrate is rotated at the second rotation number for 0.5 seconds (second step). The rotation of the substrate is further decelerated to a third rotation number and the substrate is rotated at the third rotation number (third step). The rotation of the substrate is accelerated to a fourth rotation number and the substrate is rotated at the fourth rotation number (fourth step). A resist solution is continuously supplied to a center portion of the substrate from a middle of the first step to a middle of the third step.
US09165762B2	Method of depositing silicone dioxide films A method of forming silicon dioxide films using plasma enhanced chemical vapor deposition (PECVD) uses tetraethyl orthosilicate (TEOS), oxygen or a source of oxygen, and hydrogen as precursors. The method can be carried out at low temperatures in a range of 125 to 175° C. which is useful for manufacturing wafers with through silicon vias.
US09165761B2	Method for manufacturing semiconductor device, method for processing substrate, substrate processing apparatus and recording medium There is provided a method for manufacturing a semiconductor device, including forming a thin film containing a specific element and having a prescribed composition on a substrate by alternately performing the following steps prescribed number of times: forming a first layer containing the specific element, nitrogen, and carbon on the substrate by alternately performing prescribed number of times: supplying a first source gas containing the specific element and a halogen-group to the substrate, and supplying a second source gas containing the specific element and an amino-group to the substrate, and forming a second layer by modifying the first layer by supplying a reactive gas different from each of the source gases, to the substrate.
US09165760B2	Cleaning composition and cleaning method using the same A cleaning composition is provided. The cleaning composition includes at least one polyamino-polycarboxylic acid or at least one salt thereof, at least one solvent, at least one substituted or non-substituted phenethylamine and water. The solvent is selected from a group consisting of glycols.
US09165757B2	Stroboscopic device with flash discharge tube having conductive film on outer periphery A stroboscopic device includes a flash discharge tube with a conductive film on its outer periphery, a conductive reflector into which the flash discharge tube is inserted, and a heat-resistant conductive medium laminated on a part of the conductive film of the flash discharge tube. The reflector is electrically connected to the conductive film of the flash discharge tube via the conductive medium. This achieves the stroboscopic device with long service life and high reliability by preventing or suppressing occurrence of spark.
US09165756B2	Ultraviolet discharge lamp apparatuses with one or more reflectors Apparatuses are disclosed which include a discharge lamp configured to emit ultraviolet light, a power circuit configured to operate the discharge lamp, and a reflector system configured to redirect ultraviolet light emitted from the discharge lamp. In some embodiments, the apparatuses include a support structure containing the power circuit and supporting the discharge lamp. In some of such embodiments, the reflector system is configured to redirect ultraviolet light propagating away from the support structure to a region exterior to the apparatus and which is between approximately 2 feet and approximately 4 feet from a floor of a room in which the apparatus is arranged. In other embodiments, the reflector system may be additionally or alternatively configured to redirect ultraviolet light propagating away from the support structure to encircle an exterior surface of the apparatus. In any case, the reflector system may, in some embodiments, include a repositionable reflector.
US09165751B1	Sample atomization with reduced clogging for analytical instruments An aerosol is produced by flowing a liquid sample through a gas-assisted nebulizer. The liquid exits from an outlet into a coaxial flow of gas. The outlet includes a sharp edge that inhibits or prevents accumulation of precipitates from the liquid, thereby reducing or eliminating clogging, which is particularly useful for a samples containing high concentrations of dissolved particles. The aerosol may be introduced into a plasma such that molecules are broken into atoms. The atomization may be followed by an analysis such as by optical emission spectrometry or mass spectrometry.
US09165750B2	High purity copper—manganese alloy sputtering target A high purity copper-manganese alloy sputtering target containing 0.05 to 20 wt % of Mn and, excluding additive elements, remainder being Cu and unavoidable impurities, wherein the target contains 0.001 to 0.06 wtppm of P and 0.005 to 5 wtppm of S, and further contains Ca and Si, and a total content of P, S, Ca, and Si is 0.01 to 20 wtppm. The incorporation of appropriate amounts of Mn as well as Ca, P, Si, and S in copper improves the machinability that is required in the stage of producing a target to facilitate the manufacture (workability) of the target, improves the smoothness of the target surface, and inhibits the generation of particles during sputtering. Thus, provided is a high purity copper-manganese alloy sputtering target which is particularly useful for improving the yield and reliability of semiconductor products that progress toward miniaturization and integration.
US09165749B2	Arc source and magnet configuration The invention relates to an arc source with a target (1) having a target front face (2) for the vacuum vaporization of the target material, a target backside with a cooling plate (4), a central target region (Z) as well as a target margin. The arc source further comprises a magnet configuration (8, 9) with an inner magnet system (8) and/or an outer magnet system (9) for the generation of a magnetic field in the proximity of the target front face. At least one of the magnet systems (8) is herein radially poled and effects alone or in connection with the particular other magnet system that the field lines of the magnetic field extend here substantially parallel to the target front face (2).
US09165744B2	Apparatus for treating ion beam An ion beam scanning assembly includes a set of scanning electrodes defining a gap to accept an ion beam and scan the ion beam in a first plane, and a multipole electrostatic lens system comprising a plurality of electrodes arranged along a portion of a path of travel of the ion beam bounded by the pair of scanning electrodes, the multipole electrostatic lens system configured to shape the ion beam in a direction perpendicular to the first plane.
US09165739B2	Method for manufacturing flat display According to one embodiment, a method for manufacturing a flat display includes applying a dot-like adhesive coating pattern in a region to be bonded on the surface of one of a display panel and a protective plate after forming a wall pattern along the outer circumference of the region to be bonded.
US09165729B2	Keyboard device A keyboard device is located in an accommodating space of a housing having first openings and a second opening. The keyboard device includes a flexible body and a transparent liquid. The flexible body is located in the accommodating space, and includes a main body, first pressing portions, patterns, and a second pressing portion. The first pressing portions are respectively located in the first openings. The patterns are located on the main body or the first pressing portions and are respectively exposed through the first openings. The second pressing portion is located in the second opening. The main body, and the first and second pressing portions have an enclosure space therein. The transparent liquid is located in the enclosure space. When the second pressing portion is pressed, the first pressing portions expand to protrude from the first openings, such that the patterns are enlarged.
US09165727B2	Power-down electrical locking protection device for underground explosion protection frequency converter A power-down electrical locking protection device for an underground explosion protection frequency converter comprises a reversing control part and a locking control part. The reversing control part comprises a reversing handle (1), a sector plate (2) of a reversing switch, and an isolated reversing switch (3). The locking control part comprises a locking button (4), a locking positioning plate (5), and an auxiliary control point (6). The reversing handle (1) is fixedly connected to the sector plate (2). The reversing handle (1) is connected to the isolated reversing switch (3). The locking button (4) is fixedly connected to the locking positioning plate (5). The locking button (4) is connected to the auxiliary control point (6). A positioning stud (7) is fixed outside a cupboard door (8). The locking button (4) is electrically connected to a PLC module and a power supply. The isolated reversing switch (3) is connected to a discharge resistor. The power-down electrical locking protection device for an underground explosion protection frequency converter has the following advantages: the discharge time does not need to be calculated manually and the usage is stable and safe.
US09165724B2	Change-over structure between moving contact and static contact of tap selector A change-over structure disposed between a moving contact and a static contact of a tap selector includes an insulation changer base plate, static contacts which are fixed on the insulation changer base plate in at least one column at intervals, the inner ends of the static contacts are electrically connected to respective tap windings of a transformer, rotation shafts, each comprising moving contacts that are evenly distributed on each of the rotation shafts and are electrically connected to each other, and arc-shaped conductors corresponding to the static contacts in at least one column. Each of the arc-shaped conductors and outer ends of the static contacts are disposed at the same circumference with a center of one of the rotation shafts as a circle center. When one of the moving contacts is changed over between the two static contacts, another moving contact is electrically connected to the arc-shaped conductor.
US09165721B2	Inkjet-printed flexible electronic components from graphene oxide An electrical component includes an inkjet-printed graphene electrode. Graphene oxide flakes are deposited on a substrate in a graphene oxide ink using an inkjet printer. The deposited graphene oxide is thermally reduced to graphene. The electrical properties of the electrode are comparable to those of electrodes made using activated carbon, carbon nanotubes or graphene made by other methods. The electrical properties of the graphene electrodes may be tailored by adding nanoparticles of other materials to the ink to serve as conductivity enhancers, spacers, or to confer pseudocapacitance. Inkjet-printing can be used to make graphene electrodes of a desired thickness in preselected patterns. Inkjet printing can be used to make highly-transparent graphene electrodes. Inkjet-printed graphene electrodes may be used to fabricate double-layer capacitors that store energy by nanoscale charge separation at the electrode-electrolyte interface (i.e., “supercapacitors”).
US09165720B2	Conductive polymer/porous carbon material composite and electrode material using same The purpose of the present invention is to provide: an electric double-layer capacitor, a lithium ion secondary battery, and a lithium ion capacitor, each of which has excellent cycle characteristics; an electrode material which is capable of providing the electric double-layer capacitor, the lithium ion secondary battery, and the lithium ion capacitor; and a composite which is used in the electrode material. The composite of the present invention is a composite produced by compositing from 0.5 to 5 parts by mass of nitrogen atom-containing conductive polymer per 100 parts by mass of porous carbon material. The composite of the present invention is a composite where the peak area ratio (nitrogen/carbon ratio) of peak area derived from nitrogen atoms to peak area derived from carbon atoms in the spectrum by X-ray photoelectron spectroscopy becomes 0.005 to 0.05.
US09165719B2	Method for sealing a liquid within a glass package and the resulting glass package A method for sealing a liquid within a glass package and the resulting sealed glass package are described herein where the sealed glass package can be, for example, a dye solar cell, an electro-wetting display or an organic emitting light diode (OLED) display.
US09165716B2	High capacitance single layer capacitor A high capacitance single layer ceramic capacitor having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and a top or bottom surface and a metallization pad electrically isolated from the metallization side and the top or bottom surface by a castellation or a via or separated by a dielectric insulating band positioned between the electrodes around the perimeter of the ceramic body and separating the top and bottom surfaces.
US09165708B2	Thin film coil and electronic device having the same A thin film coil and an electronic device having the same. The thin film coil includes a substrate; and a coil pattern including a first coil strand and a second coil strand formed respectively on opposite surfaces of the substrate, wherein the first coil strand formed on one surface of the substrate includes at least one path that passes through the other surface of the substrate.
US09165707B2	Multiphase power converters having shared magnetic core sections A multiphase power converter includes a plurality of subconverters and a control circuit. Each subconverter has an input circuit, an output circuit, and a magnetic core coupling the input circuit to the output circuit. The magnetic core of at least one of the plurality of subconverters has a core section that is shared by the magnetic core of another one of the plurality of subconverters. The control circuit is configured to operate the input circuits of the plurality of subconverters with different phases. The magnetic cores may be cores of a transformer, a coupled inductor, etc.
US09165704B2	Superconducting magnet apparatus with cryogen vessel In a superconducting magnet apparatus, at least one superconducting winding and an outer vacuum chamber are provided. A thermal radiation shield is located between the superconducting winding and the outer vacuum chamber. A cryogen vessel is positioned within the thermal radiation shield and within the outer vacuum chamber. The superconducting winding is positioned outside of the cryogen vessel. A refrigerator is operable to cool the cryogen vessel to a liquid cryogen temperature and to cool the at least one thermal radiation shield to an intermediate temperature between the liquid cryogen temperature and a temperature of the outer vacuum chamber. A substantial portion of an outer surface of the cryogen vessel has a thermal emissivity at the liquid cryogen temperature which is greater than an average surface emissivity of the superconducting winding by at least 0.1.
US09165697B2	Peroxide crosslinked resin composition and electric wire and cable using same A peroxide crosslinked resin composition includes a base polymer (A) including 50 to 90% by mass of a first copolymer component (a1) including one of or a mixture of two or more first ethylene α-olefin copolymers having a density of 0.864 to 0.890 g/cm3, a melt flow rate (MFR) of 1 to 5 g/10 min, and a melting point of not higher than 90 degrees Celsius, and 10 to 50% by mass of a second copolymer component (a2) including one of or a mixture of two or more second ethylene α-olefin copolymers having a melt flow rate (MFR) of not smaller than 30 g/10 min, and a melting point of 55 to 80 degrees Celsius, an inorganic filler (B) added in a ratio of from 80 parts to 150 parts by mass with respect to 100 parts by mass of the base polymer (A), and a peroxide crosslinker (C).
US09165696B2	Transparent electrode laminate According to one embodiment, the transparent electrode laminate includes a transparent substrate and an electrode layer which is formed on the transparent substrate and includes a three-dimensional network of metal nanowires. The electrode layer includes a first conductive region and a second conductive region adjacent to the first conductive region. Surfaces of the metal nanowires in the first conductive region are reacted to form reaction products. Surfaces of the metal nanowires in the second conductive region are unreacted. The second region has conductivity higher than that of the first conductive region and an optical transparency.
US09165695B2	Copper alloy wire and method for producing the same The zirconium content of the alloy composition of a copper alloy wire is 3.0 to 7.0 atomic percent; and the copper alloy wire includes copper matrix phases and composite phases composed of copper-zirconium compound phases and copper phases. The copper matrix phases and the composite phases form a matrix phase-composite phase fibrous structure and are arranged alternately parallel to an axial direction as viewed in a cross-section parallel to the axial direction and including a central axis. The copper-zirconium compound phases and the copper phases in the composite phases also form a composite phase inner fibrous structure and are arranged alternately parallel to the axial direction at a phase pitch of 50 nm or less as viewed in the above cross-section. This double fibrous structure presumably makes the copper alloy wire densely fibrous to provide a strengthening mechanism similar to the rule of mixture for fiber-reinforced composite materials.
US09165694B2	Nanowire apparatuses and methods Aspects of the present disclosure are directed to apparatuses and methods involving nanowires having junctions therebetween. As consistent with one or more embodiments, an apparatus includes first and second sets of nanowires, in which the second set overlaps the first set. The apparatus further includes a plurality of nanowire joining recrystallization junctions, each junction including material from a nanowire of the first set that is recrystallized into an overlapping nanowire of the second set.
US09165679B2	Post package repairing method, method of preventing multiple activation of spare word lines, and semiconductor memory device including fuse programming circuit Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing additional information with respect to the reprogrammed fail address; and activating a second spare line and inactivating the first spare line, referring to the additional information.
US09165676B2	Shift register, driving method thereof and flat panel display device A shift register includes a plurality of stages each having a pull-up transistor, a pull-down transistor and a flip-flop, the plurality of stages outputting high level output voltages sequentially for one horizontal period in response to at least one clock signal and a start signal, and an AH control circuit connected to input terminals and output terminals of the plurality of stages to control output signals of all the stages into a high level for one frame.
US09165655B2	Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings, a voltage generating circuit configured to generate control voltages of different voltage levels, and a control circuit configured to control application of control voltages to the word lines and the back gate line. A control voltage applied to the back gate line may be varied depending on how far a selected word line is from the back gate line, and a control voltage applied to unselected word lines may be varied depending on how far the unselected word line is from the selected word line.
US09165653B2	Determining sector status in a memory device The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased.
US09165651B2	Nonvolatile semiconductor memory device and control method thereof A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on.
US09165649B2	Systems and methods of shaping data A method of shaping data includes receiving data represented as a first set of bits, where each bit of the first set of bits corresponds to a logical value. A first write current to write a first logical value to a storage element is less than a second write current to write a second logical value to the storage element. The method also includes applying a shaping operation to generate a second set of bits, where a proportion of bits having the first logical value is larger for the second set of bits than for the first set of bits. The method also includes writing the second set of bits to the memory.
US09165648B1	Resistive memory devices, circuits and methods having read current limiting A memory device, comprising: read circuits coupled to a plurality of memory elements programmable between at least two different resistance states, the read circuits generating output values based on resistance states of selected memory elements in a read operation; and current limit circuits that limit a current flow through each memory element to less than a program threshold current; wherein the program threshold current corresponds to a current that flows through a memory element being programmed to cause its resistance to change to a resistance between that of two different resistance states.
US09165637B2	Volatile memory device and a memory controller A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.
US09165633B2	Carbon nanotube memory cell with enhanced current control A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant. The common node can be constant at a source voltage if a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) is used in the CNT memory device, or the common node can be constant at a supply voltage if an n-channel MOSFET is used in the CNT memory device.
US09165626B2	Self-reference magnetic random access memory (MRAM) cell comprising ferrimagnetic layers MRAM cell comprising a magnetic tunnel junction comprising a storage layer having a net storage magnetization being adjustable when the magnetic tunnel junction is at a high temperature threshold and being pinned at a low temperature threshold; a sense layer having a reversible sense magnetization; and a tunnel barrier layer between the sense and storage layers; at least one of the storage and sense layer comprising a ferrimagnetic 3d-4f amorphous alloy material comprising a sub-lattice of 3d transition metals atoms providing a first magnetization and a sub-lattice of 4f rare-earth atoms providing a second magnetization, such that at a compensation temperature of said at least one of the storage layer and the sense layer, the first magnetization and the second magnetization are substantially equal. The disclosed MRAM cell can be written and read using a small writing and reading field, respectively.
US09165624B2	Semiconductor integrated circuit with switch to select single or multiple chips A semiconductor integrated circuit includes: a first interface block configured to transmit and receive signals within the same chip; a second interface block configured to transmit and receive signals to and from different semiconductor chips; and a switching block configured to select a signal path in which the signal transmission and reception of the first interface block is not performed through the second interface block, in response to a chip structure signal.
US09165622B2	Address detection circuit and memory device including the same An address detection circuit may include one or more address storage units, an initialization unit suitable for deleting an address stored in an address storage unit having a value greater than N, wherein the value is obtained by dividing a respective total input number that addresses have been inputted after the corresponding address is stored by a respective input number corresponding to the stored address, a detection unit suitable for detecting an address having an input number that is a reference number or more from the addresses stored in the one or more address storage units, and a selection unit suitable for selecting an address storage unit in which an address is not stored and storing an input address in the selected address storage unit.
US09165618B2	Semiconductor memory device for conducting monitoring operation to verify read and write operations A semiconductor memory device includes, in part, a first data I/O block and a second data I/O block. During a write operation, the first data I/O block transmits input data supplied through a first pad to a first global I/O line, and further generates a write internal signal. The second data I/O block transmits the write internal signal to a second pad in response to a monitor enable signal. During a read operation, the first data I/O block supplies data from the first global I/O line to a first pad, and further generates a read internal signal. The second data I/O block transmits the read internal signal to the second pad in response to a monitor enable signal.
US09165613B2	Sample-and-hold current sense amplifier and related method A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.
US09165611B2	Wiring structures for three-dimensional semiconductor devices Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction.
US09165607B2	Mounting structure for component of electronic device A portable electronic device having an outer housing, a component, and a shock-absorption assembly is disclosed. A shock-absorption assembly located within the outer housing and coupled to the component can include one or more elements adapted to dampen a mechanical shock to the component. The shock-absorption assembly elements can be mounted to corners and/or edges of the component. Shock-absorption assembly elements can include a first portion comprising protrusions that provide initial damping of the mechanical shock and a second portion comprising an elastic block that provides final damping of the mechanical shock.
US09165606B2	Electronic device An electronic device includes a housing with a carrier therein. The carrier includes a recess with a restricting portion therein. An access unit is disposed in the recess. An elastic member is connected to the access unit and engaged with the restricting portion to restrict the access unit in the recess. A fixed member is connected to the access unit. A movable member is movably disposed on the carrier, including a first contact portion and a second contact portion. When an external force is exerted on the movable member along a first direction, the first contact portion pushes the elastic member along the first direction to deform and separate from the restricting portion, and the second contact portion pushes the fixed member to move along a second direction perpendicular to the first direction, such that the access unit can be removed from the housing.
US09165605B1	System and method for personal floating video Systems and methods for providing a user with a floating video of a subject are provided. The systems and methods generate a floating video by removing background pixels of a primary video using a background image/video, where the user records the primary video and the background image/video. The floating video may be generated on a recording device of the user and/or a remote server. Further, the user and/or the remote server may host the floating video.
US09165603B2	Method and apparatus for grouping video tracks in a video editing timeline A method and apparatus for grouping video tracks in a video editing timeline comprises displaying a plurality of video tracks in a video editing timeline; receiving a selection of video tracks to be grouped from the plurality of video tracks that are displayed; displaying the video tracks selected for grouping as a single video track in the video editing timeline; and applying an indicator identifying the video tracks as grouped in the video editing timeline.
US09165602B2	Information storage medium storing multi-angle data and method and apparatus for reproducing the multi-angle data An apparatus and method for reproducing multi-angle data in a seamless manner, even during a change of angle, and an information storage medium on which the multi-angle data is recorded. AV data divided into clips, which are recording units, is recorded on the information storage medium. Additional information regarding jump points is recorded on a space of the information storage medium other than where the clips are recorded. The apparatus for reproducing the multi-angle data includes a reading unit which reads data from the information storage medium, and a reproducing unit which reproduces the data read by the reading unit by searching for and reproducing clips corresponding to the read data when the read data is multi-angle data, and, if there is an angle change command, reproducing clips for a new angle from a jump point of the clip for the new angle.
US09165600B2	High density timing based servo format A product according to one embodiment includes a magnetic recording tape having opposite ends and at least one servo track, a longitudinal axis of the magnetic recording tape being defined between the ends. The at least one servo track has a plurality of first magnetic bars and a plurality of second magnetic bars. A width of each of the at least one servo track is defined in a direction perpendicular to the longitudinal axis of the magnetic recording tape between sides of the servo track, the sides of each servo track extending along ends of the first magnetic bars. Lengths of the second magnetic bars between outermost ends thereof are less than the width of the associated servo track.
US09165596B1	Magnetic recording disk drive with multiple preamplifiers and common transmission line with impedance compensation A disk drive has multiple preamplifiers (preamps) connected to the system-on-a-chip (SOC) by a common transmission line with resistors between the preamps and the SOC. Each preamp includes a read resistor at the output of each read amplifier, and a write resistor at the input of each write driver. The resistors may be programmable resistors located in the preamps. The read resistors are at the source of the signal to the transmission line and the write resistors are at the termination of the signal from the transmission line. The read and write resistors provide impendence matching with the transmission line and the SOC when one of the preamps is selected as active, which enables the SOC to operate seamlessly with a common transmission line connected to all preamps.
US09165594B2	Spindle motor and disk drive apparatus A spindle motor includes a stationary portion with a shaft, a circular plate portion, a wall portion, and a plate portion. The plate portion has a flat plate portion and an annular convex portion. The sleeve includes an annular portion, an outer side cylindrical portion, and an inner side cylindrical portion. The inner side cylindrical portion and an upper radial dynamic pressure groove array are superimposed in a radial direction. The upper radial dynamic pressure groove array includes a plurality of upper spiral grooves that is inclined in one direction with respect to an axial direction and a plurality of lower spiral grooves that is inclined in another direction opposite to the one direction. A lower end of the upper spiral grooves is positioned farther on an upper side than an upper surface of the annular portion.
US09165589B1	Voice coil motor with lateral attraction force A voice coil motor with a lateral attraction force comprising a magnetic device, a lens carrier, a base, a plurality of guide posts, a set of surface coil and a guiding magnetic plate. The first contact structure and the second contact structure of the magnetic device are contacted the plurality of guide posts respectively. There is at least one contacting point between the first contact structure and one of the plurality of guide posts, and there are at least two contacting point between the second contact structure and the other of the plurality of guide posts.
US09165587B2	System and method for dual-sided sputter etch of substrates A system is provided for etching patterned media disks. A movable electrode is utilized to perform sputter etch. The electrode moves to near or at slight contact to the substrate so as to couple RF energy to the disk. The material to be etched may be metal, e.g., Co/Pt/Cr or similar metals. The substrate is held vertically in a carrier and both sides are etched serially. That is, one side is etched in one chamber and then in the next chamber the second side is etched. An isolation valve is disposed between the two chambers and the disk carrier moves the disks between the chambers. The carrier may be a linear drive carrier, using, e.g., magnetized wheels and linear motors.
US09165583B1	Data storage device adjusting seek profile based on seek length when ending track is near ramp A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of tracks, and a load/unload ramp. When seeking the head a seek length from a starting track to an ending track, control circuit is configured to adjust a seek profile when the seek length is greater than a first threshold and the ending track is within a second threshold of the load/unload ramp.
US09165582B1	Thermal assisted magnetic recording head utilizing uncoupled light A thermal assisted magnetic recording head has a magnetic head slider having an air bearing surface that is opposite to a magnetic recording medium, a core that can propagate laser light as propagating light, a plasmon generator that includes a generator front end surface facing the air bearing surface, and a main pole facing the air bearing surface, and a laser light generator that supplies the laser light to the core. The plasmon generator generates near-field light (NF light) at the generator front end surface to heat the magnetic recording medium. The main pole includes a main pole end surface that faces the air bearing surface and that is positioned in the vicinity of the generator front end surface, and emits a magnetic flux to the magnetic recording medium from the main pole end surface. At least a portion of the laser light that is not coupled with the plasmon generator thermally deforms the air bearing surface so that a part of the air bearing surface positioned closer to the leading side than the generator front end surface and the main pole end surface in the down track direction protrudes toward the magnetic recording medium.
US09165580B2	Disk drive head suspension tail with stiffened edge alignment features A head gimbal assembly for a disk drive includes a flexure tail terminal region having flexure bond pads in electrical communication with the head. Each of the flexure bond pads includes a widened region of a corresponding one of a plurality of electrical traces in a conductive layer, and a discontinuous bond pad backing island in a structural layer that overlaps the widened region. The flexure tail terminal region also includes a plurality of discontinuous edge stiffener islands in the structural layer that do not overlap the widened region of any flexure bond pad, and that are disposed no more than 50 microns from one of the two opposing longitudinal outer edges of the flexure tail terminal region. At least one of the plurality of discontinuous bond pad backing islands is disposed no more than 50 microns from one of the two opposing longitudinal outer edges.
US09165578B2	Swage mount for hard disk drives A swage mount is provided for attaching a head suspension assembly to a head actuator arm for a hard disk drive. The swage mount has a flange body with a thickness for providing clearance from the underlying disk. The swage mount may have a tip for in-plane movement. The tip may be ‘T’ shaped. The tip has a thickness that is greater than the thickness of the flange body for withstanding out-of-plane loads and for enhancing performance of the hard disk drive, for example, during reading/writing of data using the head. Mass properties of the swage mount, the twisting/bending yield load, modal frequency responses, and other performance metrics are analyzed to design the dimensions of the swage mount having favorable in-plane compliance and superior out-of-plane robustness.
US09165575B2	Side shield reader with a shield exciting coil In one embodiment, an apparatus includes at least one read head, each read head including a magnetoresistive (MR) read element, having a lower shield layer, an underlayer positioned above the lower shield layer, an antiferromagnetic (AFM) layer positioned above the underlayer, a magnetization pinned layer positioned above the AFM layer, an insulating layer positioned above the magnetization pinned layer, and a magnetization free layer positioned above the insulating layer, magnetic side shields positioned on both sides of the MR read element in a cross-track direction, and at least one shield excitation coil configured to excite magnetization of the side shields. In another embodiment, a method for forming a read sensor includes forming a MR read element, forming magnetic side shields on both sides of the MR read element in a cross-track direction, and forming at least one shield excitation coil configured to excite magnetization of the side shields.
US09165573B1	Method for controlling camber on air bearing surface of a slider A method of a parting a slider from a slider bar is disclosed. The method includes receiving a slider bar comprising a plurality of sliders and having an air bearing surface (ABS) side and a back side opposite to the ABS side and parting at least one slider from the slider bar with a cutter, wherein the cutter enters the slider bar at least in part on the backside and exits the slider bar at least in part on the ABS side and the ABS side is facing away from the cutting direction by a predetermined acute angle.
US09165572B2	Head gimbals assembly, method for manufacturing thermal-assisted magnetic recording and manufacturing equipment of thermal-assisted magnetic recording Embodiments of the present invention generally relate to a HAMR head. The HAMR head includes an anti-reflecting (AR) coating on a side opposite (e.g., a flex side) of the air bearing surface (ABS). The anti-reflective coating may include one or more anti-reflective layers. The anti-reflective coating reduces the amount of light reflected back towards a light source unit. A shading layer may be disposed on the anti-reflective coating and may function as a contact electrode as well as reducing stray light escaping from the laser, thus reducing the amount of stray light reaching the ABS.
US09165567B2	Systems, methods, and apparatus for speech feature detection Implementations and applications are disclosed for detection of a transition in a voice activity state of an audio signal, based on a change in energy that is consistent in time across a range of frequencies of the signal. For example, such detection may be based on a time derivative of energy for each of a number of different frequency components of the signal.
US09165566B2	Indefinite speech inputs Embodiments are disclosed that relate to the use of speech inputs including indefinite quantitative terms as computing device inputs. For example, one disclosed embodiment provides a method of operating a computing device, the method including receiving a speech input comprising an indefinite quantitative term, determining a definite quantity corresponding to the indefinite quantitative term, and applying the definite quantity to an action performed via the computing device in response to the speech input.
US09165560B2	Methods for watermarking media data Methods are provided for encoding watermark information into media data containing a series of digital samples in a sample domain. The methods involves: dividing the series of digital samples into a plurality of sections in the sample domain, each section comprising a corresponding plurality of samples; processing the corresponding plurality of samples in each section to obtain a single energy value associated with each section; grouping the sections into groups, each group containing three or more sections; for each group, assigning a nominal bit value according to a bit assignment rule, assigning a watermark bit value and comparing the watermark bit value to the nominal bit value. If the nominal bit value and the watermark bit value do not match, modifying one or more energy values of one or more corresponding sections in the group where re-application of the bit assignment rule would assign the watermark bit value to the group.
US09165559B2	Method and apparatus for frequency domain watermark processing a multi-channel audio signal in real-time Digital audio signal watermarking in real-time is difficult in an environment that has limited processing power. According to the invention, the channels in a data block-based audio multi-channel signal are prioritized with respect to watermarking importance, whereby the channel priority can change for different input signal data blocks. For a current input signal block, the most important channel is watermarked and the required processing time is determined. If this required processing time is shorter than a predefined application-dependent threshold, the next most important channel is marked and the additionally required processing time is determined, and so on. Due to the block-based nature of the audio watermarking including block overlap/add and due to the sensitivity of the resulting audio quality against blocking artifacts, several problems are solved in order to lead to acceptable performance and quality.
US09165554B2	System and method for robust access and entry to large structured data using voice form-filling A method, apparatus and machine-readable medium are provided. A phonotactic grammar is utilized to perform speech recognition on received speech and to generate a phoneme lattice. A document shortlist is generated based on using the phoneme lattice to query an index. A grammar is generated from the document shortlist. Data for each of at least one input field is identified based on the received speech and the generated grammar.
US09165547B2	Localization of a wireless user equipment (UE) device based on audio masking A scheme for localizing a wireless user equipment (UE) device's relative position with respect to a spatial configuration based on audio signatures received via a multi-channel audio system, e.g., an audio system of a vehicle or home entertainment system. The wireless UE device is configured to capture the audio signatures masked within a background audio signal received from a head unit. The wireless UE device includes a persistent memory module having program instructions for processing the background audio signal including the masked signatures, which may comprise either channel-specific pseudo-random noise (PN) sequences or single-frequency tones, in order to compute time delays or power levels associated with the speaker channels. A localization module is configured to estimate the wireless UE device's relative position based on the time delays or power levels.
US09165545B2	Pickup for stringed instrument A pickup for engagement to the body of an instrument having metal strings, such as a guitar in position proximate to the strings. The pickup features a coil having loops of wire wound around a recess having a magnetic member therein which projects a magnetic field to magnetize the strings. The electrical current in said coil wire induced by a movement the strings generates a first electrical signal from said first end of the coil wire and corresponding AC second electric signal from said second end of the coil wire. One or a plurality of tap wires engaged to the coil wire at tap points, provide additional individual electronic signals which may be mixed, or may be communicated individually to an amplifier or mixing component.
US09165544B2	Electronic cymbal An electronic cymbal, comprising: an annular portion in an annular shape having predetermined rigidity; a central portion having predetermined rigidity, located on an inner circumferential side of the annular portion and configured separately from the annular portion; a sensor portion comprising a first sensor that detects displacement of the central portion; a support supporting the sensor portion while swingably maintaining the central portion; and an interposed member formed of a film, installed between a lower surface of the central portion and the sensor portion while elastically deformably supported by the support, wherein by displacing the central portion from a motionless state, the sensor portion is pressed by an outer circumferential part of the central portion via the interposed member.
US09165539B2	Multiple contiguous closed-chambered monolithic structure guitar body A chambered electric guitar body according to an illustrative embodiment of the present invention includes at least five contiguous closed chambers enclosed in the assembled monolithic top and bottom parts comprised of a generally solid material such as a metal. The autonomous dimensions of the chambers, cubic volumes, and thickness as well as the density of the material, allow customization of shape and guitar performance. This is accomplished by using the method provided to produce the monolithic structures using digital technology, CAD and CNC machining to achieve desired specifications.
US09165531B2	System for detecting display driver error when failing to receive a synchronization signal and method thereof A system performs a method for detecting display driver error. The method includes sending a first command signal to a display driver to operate according to a first operating state that includes the display driver sending a synchronization signal, and monitoring for the synchronization signal during a first time period after sending the first command signal. The method further includes sending a second command signal to the display driver to operate according to a second operating state that includes the display driver withholding sending the synchronization signal, and monitoring for the synchronization signal during a second time period after sending the second command signal. In addition, the method includes detecting a display driver error based on results of the monitoring during at least one of the first or the second time periods.
US09165530B2	Three-dimensional image display apparatus A signal processor converts an input 3D image signal into a signal in which a left-eye signal and right-eye signal are rearranged temporally alternately. A driver of a liquid crystal display element includes a sub-frame data generator configuring all the sub-frames with step bit pulses and generating sub-frame data by using a drive gradation table in which the last sub-frame reaches a drive state when a drive gradation is “1” and the number of sub-frames reaching the drive state is increased one by one toward ahead of a sub-frame which has already reached the drive state, every time the drive gradation is increased by one. The liquid crystal display element is driven by the driver. An illumination optical system causes illumination light to enter into the liquid crystal display element. A projection lens projects modulated light emitted from the liquid crystal display element.
US09165529B2	Stereoscopic image display apparatus and a stereoscopic image display system having the same A stereoscopic image display system includes a three-dimensional (3D) image signal generator, a display panel, a timing controller, a data driver, and a gate driver. The 3D image signal generator generates left-eye data and right-eye data on the basis of an image signal outputs the left-eye data and the right-eye data to the timing controller. The timing controller outputs the left-eye data and the right-eye data having a first frequency to the data driver in a first mode and outputs left-eye frame data and right-eye frame data having a second frequency to the data driver in a second mode. Two pixels, which are respectively connected to an i-th gate line and an (i+1)th gate line among the gate lines and to a same data line among the data lines, are operated with the same driving time in the first and second modes.
US09165528B2	Display systems for reducing power consumption and methods for driving the same A display system may include a system board configured to compare image signals of a current and previous frame and configured to output the image signals of the current frame and a comparison result; a display panel configured to receive data signals in response to gate signals and configured to include pixels for displaying images corresponding to the data signals; a timing controller configured to output image signals and control signals; a gate driving unit configured to provide the gate signals to the pixels in response to the control signals; and/or a data driving unit configured to store the image signals provided from the timing controller and configured to convert the image signals into the data signals in response to the control signals, the data signals being provided to the pixels.
US09165527B2	System for display of images using extended greyscale bit-depth on standard display devices A system enhances reduced resolution grey scale luminance data for display on a monitor. An interface receives a pixel grey scale luminance value represented by a first number of bits exceeding a display monitor input bit length. A data processor indicates a difference comprising the number of bits. In response to the difference, the data processor derives R, G, B pixel luminance values by adjusting one or more of the R, G, B pixel luminance values to provide corrected R, G, B pixel luminance values representing the grey scale luminance value and at least one of the corrected R, G, B pixel luminance values is different from remaining ones of R, G, B pixel luminance values. The data processor outputs the corrected R, G, B pixel luminance values for display on R, G, B channels of the monitor.
US09165526B2	Subpixel arrangements of displays and method for rendering the same An apparatus including a display and control logic is provided. In one example, the display includes an array of subpixels having a subpixel repeating group tiled across the display in a regular pattern. The subpixel repeating group comprises n rows of subpixels and n columns of subpixels. Each row of the subpixel repeating group comprises n types of subpixels. Each column of the subpixel repeating group comprises the n types of subpixels. Subpixels along each diagonal direction of the subpixel repeating group comprise at least two types of the n types of subpixels. The control logic is operatively coupled to the display and is configured to receive display data and render the display data into control signals for driving the array of subpixels of the display.
US09165524B2	Display device and driving method thereof A display device prevents breakage due to overheating of a data driver and a signal controller. The display device includes a display panel including a plurality of gate lines, a plurality of data lines and pixels connected to the gate lines and the data lines. A gate driver supplies a gate signal to the gate lines. A data driver supplies a data signal to the data lines. A signal controller controls the gate signal and the data signal. The signal controller includes a data converter converting a gray value of image data when a difference in the gray value of the image data of two adjacent pixels connected to the same data line among the plurality of data lines is greater than or equal to a first threshold value.
US09165522B2	Method for pixel gradation extension, drive method and apparatus for charging time of pixel capacitance The present invention relates to a method of extending a pixel gray scale. The secondary gray scale levels with different charging times and the same gray scale voltage are formed by controlling a charging time of the gray scale voltage of every primary gray scale level and refining the level, wherein, the gray scale voltage of the every secondary gray scale level is the same as that of the corresponding primary gray scale level, and its charging time corresponds to the secondary gray scale level. The primary gray scale level of the display pixel of the liquid crystal panel is extended by using this method and the disadvantage of the imperfect display brought forward by the control method using frame rate in the prior art is overcome. The present invention further provides a drive method of controlling the pixel charging time and a drive apparatus thereof, which realizes the pixel gray scale extension by controlling the charging time of the pixel capacitance. It overcomes the disadvantage that a grid strip may be formed visually using the characteristic of the visual retention and the visual inertia of the human eyes while largely increasing the number of colors that can be displayed.
US09165521B2	Field sequential liquid crystal display device and driving method thereof To improve the image quality of a liquid crystal display device. In the liquid crystal display device, writing of an image signal and the turning on the backlights are not sequentially performed in the entire pixel portion but are sequentially performed per specific region of the pixel portion. Thus, it is possible to increase the frequency of input of an image signal to each pixel of the liquid crystal display device. Accordingly, deterioration of display such as color break generated in the liquid crystal display device can be suppressed, and the image quality can be improved.
US09165512B2	Method for reducing double images A method for reducing double images of a frame is disclosed. The frame is divided into a plurality of regions. The method includes generating a plurality of output enable (OE) signals, which are utilized to respectively adjust a plurality of conduction durations of a plurality of gate lines of the corresponding regions. The OE signals are outputted to a gate driver for generating a plurality of scan signals of the corresponding regions. The gate lines, which correspond to the regions, are driven by the gate driver according to the scan signals.
US09165508B2	Display apparatus using reference voltage line for parasitic capacitance, electronic apparatus using the display apparatus and driving method of the display apparatus A display apparatus includes: a plurality of pixel circuits 6; a reference voltage source for supplying a reference voltage to a reference voltage line 4; a first switch for connecting the reference voltage source to the reference voltage line 4; a data line 5 for supplying a data voltage to the pixel circuit, wherein the pixel circuit 6 includes a light emitting element, a driving transistor M1 having a source connected to an anode of the light emitting element, a holding capacitor CS having one end connected to a gate of the driving transistor M1 and having the other end connected to the source of the driving transistor M1, a second switch for connecting the gate of the driving transistor M1 to the data line 5, and a third switch for connecting the source of the driving transistor M1 to the reference voltage line 4.
US09165502B2	Display device and electronic device including display device Objects are to provide a display device the power consumption of which is reduced, to provide a self-luminous display device the power consumption of which is reduced and which is capable of long-term use in a dark place. A circuit is formed using a thin film transistor in which a highly-purified oxide semiconductor is used and a pixel can keep a certain state (a state in which a video signal has been written). As a result, even in the case of displaying a still image, stable operation is easily performed. In addition, an operation interval of a driver circuit can be extended, which results in a reduction in power consumption of a display device. Moreover, a light-storing material is used in a pixel portion of a self-luminous display device to store light, whereby the display device can be used in a dark place for a long time.
US09165500B2	Pixel circuit, organic light emitting display device, and method of driving the pixel circuit A pixel circuit includes an OLED having a cathode coupled to a power source voltage, a first transistor having a second electrode coupled to an anode of the OLED, and a gate electrode coupled to a gate control-line, a second transistor having a second electrode coupled to a first electrode of the first transistor, a third transistor having a first electrode coupled to another power source voltage, a second electrode coupled to a first electrode of the second transistor, and a gate electrode coupled to a gate control-line, a fourth transistor having a first electrode coupled to a gate electrode of the second transistor, a second electrode coupled to the anode of the OLED, and a gate electrode coupled to a scan-line, and a capacitor coupled between the gate electrode of the second transistor and the second electrode of the third transistor.
US09165498B2	Organic light emitting display and power supply for the same An organic light emitting diode (OLED) display including: a display unit including pixels; and a power supply unit including: an output terminal; a reference terminal having an insulated output; and a bias circuit generating a first power source voltage from a received input voltage and supplying a second power source voltage to the reference terminal wherein the first power source voltage and the second power source voltage are voltages driving the plurality of pixels, wherein the bias circuit supplies the second power source voltage to the reference terminal and the plurality of pixels and is referenced to a ground voltage, and wherein a current flowing to the pixels flows to the reference terminal. In the OLED display, one power supply may be used as a power supply powering electroluminescence (EL), and thereby a cost of the OLED display may be reduced and a power efficiency may be improved.
US09165495B2	Crosstalk compensation method and display apparatus using the same The present disclosure provides a crosstalk compensation method and a display apparatus using the same. The method includes: configuring a compensation range with the compensation range set between the maximum gray level and the minimum gray level; establishing a look-up table to record compensation values for each gray level in the compensation range; determining whether the gray level of a first color sub-pixel on the display panel is set within the compensating range. When it is determined that the gray level of the first color sub-pixel is set within the compensation range selects a compensating value for configuring an initial gray level of an adjacent second color sub-pixel to a correction gray level. When it is determined that the gray level of the first color sub-pixel is set outside the compensation range, maintains the gray level of the second color sub-pixel at the initial gray level.
US09165491B2	Display device having multiple viewing zones and converting horizontally-arranged RGB subpixel data for output on square-shaped vertically-arranged RGB subpixels A display device having multiple viewing zones includes a display panel including a plurality of pixels in a matrix form, each pixel including red, green and blue sub-pixels arranged in a vertical direction; and a light guide panel guiding a first image emitted from the pixels in first columns among the plurality of pixels to a first viewing zone and a second image emitted from the pixels in second columns among the plurality of pixels to a second viewing zone, wherein the first column is adjacent to the second column.
US09165488B1	Support device for a post A support device for a hollow traffic marker utilizing a base having a foot positioned at the ground surface. A boss extends from the base and includes a cavity. A first spacer is held within the boss cavity by a fastener. A flexible sleeve positioned over the outer surface of the boss a hollow traffic marker connected to a second spacer by a fastener lies within the flexible sleeve. A gap within the flexible sleeve separates the first and second spacers.
US09165487B2	LED backlight system for cabinet sign A backlighting system for a cabinet sign may include a plurality of panels. Each panel includes a plurality of light emitting diodes (“LEDs”) attached to the panel. The diode has a box sign depth factor of less than about 1.4. An integrated circuit may also be located on the panel. A wire physically connects adjacent panels.
US09165486B2	Back plate for use with a backlight module, a backlight module using the same, and the manufacturing method thereof A back plate for use with a backlight module, a backlight module using the same, and the manufacturing method thereof are provided. The back plate includes a plate body and a side wall. The side wall extends out from the edge of the plate body and includes a wall body and a bending part, wherein the thickness of the wall body is less or equal to 0.12 mm. The bending part is formed by bending a plurality of bending sheets outward from the top of the wall body, wherein the thickness of each bending sheet is less or equal to 0.12 mm. The backlight module includes the back plate and a light source module, wherein the light source module is disposed on the plate body and adjacent to the inner side of the side wall.
US09165484B2	Multi-symbol indication apparatus A multi-symbol indication apparatus, may include a plurality of light sources, each of the light sources emitting light of a single color, a plurality of filter units, each of the filter units installed above the light sources with different height each other and reflecting light of the single color corresponding to the relevant light source, wherein a symbol may be carved on each of the filter units, and a display cover installed above the filter units.
US09165474B1	System and method for limiting computer usage The present invention involves a system and method for limiting access to computers by an individual; and a system and method for rewarding an individual with computer access.
US09165470B2	Autonomous convoying technique for vehicles A method of autonomously convoying vehicles traveling along a route with a leader vehicle being in communication with at least one follower vehicle. The at least one follower vehicle receives a communication relating to a target offset position and route data. Tracking data is generated and derived from on-board sensing devices of the at least one follower vehicle that includes a traveled path of the leader vehicle sensed by the at least one follower vehicle. The route data is compared to the tracking data for identifying accuracy between the route data relative to the tracking data. An adjusted target offset position and a set of trajectory points that provides a trajectory path of travel from a current position of the at least one follower vehicle to the adjusted target offset position are determined based on the accuracy between the route data and the tracking data.
US09165469B2	Systems and methods for coordinating sensor operation for collision detection A collision detection system of a land vehicle may be configured to coordinate sensor operation with one or more other sensing systems of one or more other land vehicles. The coordination may comprise configuring the other sensing systems. In some embodiments, the coordination comprises forming a multistatic sensor comprising one or more emitters and/or one or more receivers. The collision detection system may be configured to receive detection signal(s) emitted by one or more of the other sensing systems. The coordination may further comprise directing detection signals of the multistatic sensor. The collision detection system may use sensor data acquired by use of the coordinated sensing system(s) to generate a collision detection model.
US09165459B2	Radio control transmitter A transmitter for controlling a target to be controlled having a motor, the transmitter includes: a start-up manipulation member to control starting and stopping of the motor; a rotational speed control manipulation member to control a rotational speed of the motor according to an operation amount; a control unit to generate the steering signal such that the motor is rotated according to the operation amount of the rotational speed control manipulation member when the operation amount of the rotational speed control manipulation member is equal to or greater than a preset start position while the start-up manipulation member is in a start-up state; and a transmitting unit to transmit the steering signal.
US09165451B1	Alarm assembly An alarm assembly includes a receiver that is positionable in a vehicle. The receiver emits an audible alarm if the temperature inside the vehicle exceeds a predetermined level when the vehicle is occupied. A temperature sensor is operationally coupled to the receiver. The temperature sensor senses ambient temperature of the receiver's environment so the receiver emits the audible alarm. An occupant sensor is operationally coupled to the receiver. The occupant sensor is positionable beneath a child seat in a vehicle to communicate occupancy of the vehicle to the receiver. A bracelet is operationally coupled to the receiver. The bracelet may be worn by a child inside the vehicle so the bracelet communicates occupancy of the vehicle to the receiver. A collar is operationally coupled to the receiver. The collar may be worn by a pet inside the vehicle so the collar communicates occupancy of the vehicle to the receiver.
US09165449B2	Occupant egress prediction systems, methods and devices A method comprises determining a person's level of risk for developing an adverse condition; selecting a care protocol based on the level of risk; displaying a proposed configuration of a person support structure corresponding to the care protocol for a caregiver to approve; and upon approval by the caregiver, implementing the configuration.
US09165447B2	Smart charm anti-theft alarm system An anti-theft system that has a first component that is an attractive and light-weight smart charm that uses an accessory attachment device to attach to a wearable accessory such as a bracelet or necklace, an item of clothing, or user. The system has a second component that is an object monitor for attaching or combining with a mobile object, such as a wallet or purse. The smart charm and object monitor communicate proximity information between each other, and set off a perceptible alarm through one or more sensory alert mechanisms when the separation distance between the smart charm and object monitor exceeds a threshold alert criterion.
US09165446B2	Anti-theft security device and perimeter detection system A security tag in accordance with an embodiment of the present invention includes a housing, a membrane operable for attachment to merchandise, wherein the housing is connected the membrane, a monitoring device operable to monitor whether a party removes or attempts to remove the housing from the membrane and an alarm operable to emit a tamper signal when the monitoring device indicates that a party has removed or attempted to remove the housing from the membrane in an unauthorized condition. A security system in accordance with an embodiment of the present invention includes a security tag operable for connection to merchandise to be secured, a monitoring device operable to monitor whether a party removes or attempts to remove the security tag from the merchandise and an alarm operable to emit a tamper alarm signal when the monitoring device indicates that a party has removed or attempted to remove the security tag from the merchandise in an unauthorized condition.
US09165444B2	Light socket cameras Security systems can be used to detect a visitor. The security system can include a camera that is configured to take a video of the visitor. As well, the security system can be configured to transmit the video of the visitor to a remote computing device. The video of the visitor can be displayed on the remote computing device. The security system can be attached to a light socket.
US09165435B2	Gaming device having advance game information analyzer This concept is directed to methods of operating a gaming device to analyze game information that is part of a gaming event having a player interaction in advance of the player interaction to make a determination about the game play. These methods may be used for a variety of gaming devices such as slot machines, video keno devices, video poker machines, electronic table games, internet gaming terminals, etc. In each type of gaming device, these operation methods evaluate future game information during game play to determine one of multiple manners by which the game play will continue. These continuation manners may include changing the speed of game play, determining display characteristics of the game and outcome, providing tips or information to the player about the future game information, automatically initiating a subsequent game, or otherwise altering an aspect of the game play parameters in response to the evaluated game information.
US09165432B2	Fast action baccarat A gaming station that includes a plurality of player gaming units is provided. Each player gaming unit may include a betting area on a surface of a trapdoor. Such a trapdoor may support one or more chips in the betting area when the trapdoor is closed. When the trapdoor opens, the chips fall into an internal chip collection area. The player gaming unit may further include an adjustable screen. When the screen is in the closed position, the screen serves to block a player at the player gaming unit from accessing the betting area. When the screen is in the open position, the player is allowed to access the betting area. The gaming station may further include a sliding float for holding a plurality of chips. Such a sliding float may be movable past the plurality of player stations.
US09165431B2	Gaming system player terminal adapted for hot swapping between remote live table games Table game tournament systems can include player terminal(s), electronic gaming table(s), and/or a remote server. A player terminal can have an outer housing, a controller located therewithin or thereabout, input and output component(s), and a communications interface to an outside gaming network having other functionally similar gaming device(s), gaming table(s), and a remote server. The controller and/or server can facilitate providing tournament information to a player, which information can include whether the player would qualify for the next tournament round, who is the most serious opponent to the player, and/or the chip difference therebetween. A terminal can also facilitate asynchronous and individually paced tournament play, switching between different tournament tables on demand, and play of other non-tournament table games thereat simultaneously with the play of the table game tournament. Portable computing devices can be used as player terminals and can permit players to play in actual or practice play-along modes.
US09165429B2	Method and apparatus for gaming machines with a tournament play bonus feature A gaming method and device includes a game, at least one non-qualifying outcome in the game, and at least one qualifying outcome in the game, wherein a player qualifies for a multi-player tournament to be held in the future when the player achieves the at least one qualifying outcome.
US09165427B2	Wagering game with multiple bonus triggering feature and bonus accrual feature In one aspect, there is provided a method of conducting a wagering game which includes the steps of conducting a plurality of basic wagering games and enabling a bonus game in response to a bonus triggering outcome achieved in any of the basic wagering games. The method also includes deferring the enabled bonus game to permit play after completion of play of the plurality of basic wagering games.
US09165426B2	System and method for attending a recorded event in a metaverse application A metaverse system and method for allowing a user to attend a recorded past event in a metaverse application. The metaverse system includes a client computer, a metaverse server, and a time travel engine. The client computer interfaces with the metaverse application. The metaverse server records an event environment of a past event in a metaverse application. The time travel engine serves, in response to a request from a user, a playback of the recorded event environment to the client computer to allow the user to attend and to observe the recorded event environment.
US09165424B2	Thin client support for a gaming machine A gaming machine, such as a video slot or video poker machine, may be configured to request a thin client game from a game server for presentation within a thin client. The outcome of the thin client game is determined by the game server. The gaming machine is also configured to execute a thick client game determined by the gaming machine. Indications of the outcomes of the thin and thick client games may be provided to a data collection device.
US09165423B2	Integrating social networking and wagering systems A wagering game system and its operations are described herein. In embodiments, the operations can include connecting a social network account with a wagering game player account, wherein the wagering game player account is associated with a wagering game session, and wherein the social network account is associated with a social networking session via a venue for a social network. The operations can further include detecting a first event from a first of the social networking session and the wagering game session; and after detecting the first event, causing a second event to occur for a second of the social network session and the wagering game session.
US09165417B2	Method and system for the protection of voting options for remote voting The method includes using a voting computer to represent the user selected voting options gathered by a voting application running in the voting computer, using an element that has a machine readable format such as a barcode, recording then the element in a physical media using a printing device connected to the voting computer, so that it is suitable to be delivered by the user using a physical channel such as a postal service to the electoral officers. Once the delivered physical media is received by the intended destination (e.g., election officials), the method introduces the step of reading the element information contained in the physical media using a reading device connected to a retrieving computer. Finally, the method introduces a process for generating a physical ballot in the retrieving computer using the information delivered by the voter and a printing device.
US09165415B2	Method and apparatus for access authentication using mobile terminal An access authentication method and apparatus in which access authentication is performed using positional data associated with access information data.
US09165414B2	Method and system for predicting performance of an aircraft Methods and systems for operating an avionics system on-board an aircraft are provided. A plurality of signals representative of a current state of the aircraft are received. A future state of the aircraft is calculated based on the plurality of signals representative of the current state of the aircraft. An indication of the future state of the aircraft is generated with the avionics system on-board the aircraft.
US09165410B1	Building a three-dimensional composite scene The capture and alignment of multiple 3D scenes is disclosed. Three dimensional capture device data from different locations is received thereby allowing for different perspectives of 3D scenes. An algorithm uses the data to determine potential alignments between different 3D scenes via coordinate transformations. Potential alignments are evaluated for quality and subsequently aligned subject to the existence of sufficiently high relative or absolute quality. A global alignment of all or most of the input 3D scenes into a single coordinate frame may be achieved. The presentation of areas around a particular hole or holes takes place thereby allowing the user to capture the requisite 3D scene containing areas within the hole or holes as well as part of the surrounding area using, for example, the 3D capture device. The new 3D captured scene is aligned with existing 3D scenes and/or 3D composite scenes.
US09165406B1	Providing overlays based on text in a live camera view Approaches are described for rendering augmented reality overlays on an interface displaying the active field of view of a camera. The interface can display to a user an image or video, for example, and the overlay can be rendered over, near, or otherwise positioned with respect to any text or other such elements represented in the image. The overlay can have associated therewith at least one function or information, and when an input associated with the overlay is selected, the function can be performed (or caused to be performed) by the portable computing device.
US09165398B2	Analysis of food items captured in digital images Data analysis of a food item based on one or more digital images of the food item is disclosed. In one embodiment, the method comprises displaying, on a display unit of the smart device, first and second digital images of a meal, where the first digital image is captured before the second digital image. The method also comprises determining a volume of each food item in the first digital image and a volume of each food item in the second digital image by analyzing the first digital image and the second digital image using a digital image processing technique. The method further comprises generating, on the display unit, an amount of intake for the meal based on a difference between the volume of each food item in the first digital image and the volume of each food item in the second digital image.
US09165393B1	Measuring stereoscopic quality in a three-dimensional computer-generated scene A computer-implemented method for measuring the stereoscopic quality of a computer-generated object in a three-dimensional computer-generated scene. The computer-generated object is visible from at least one camera of a pair of cameras used for creating a stereoscopic view of the computer-generated scene. A set of surface vertices of the computer-generated object is obtained. A stereoscopic transformation on the set of surface vertices is computed to obtain a set of transformed vertices. A translation vector and a scale vector are computed and applied to the set of transformed vertices to obtain a ghosted set of vertices. The ghosted set of vertices is approximately translational and scale invariant with respect to the set of surface vertices. A sum of the differences between the set of surface vertices and the set of ghosted vertices is computed to obtain a first stereo-quality metric.
US09165387B2	Graphing device and method To display patient information, a computing device receives a set of diagnostic values for a patient, a processor of the computing device compares the set of diagnostic values with a set of predetermined normal values, and a video image is displayed having a graphical depiction of the diagnostic values in comparison to the related normal values. The related set of normal values is displayed at a predetermined region of the video image and the set of diagnostic values is displayed on the video image in relation to the certain region of the normal values. Varying levels of relative health of the patient are indicated according the placement of an icon relative to areas of the graphical depiction of the diagnostic values. The video image is a plurality of concentric circles with the diagnostic values being displayed relatively closer to a center of the display in response to the diagnostic values being relatively closer to the values of the related normal values.
US09165386B2	Magnetic resonance imaging device, and method for generating magnetic susceptibility enhanced image There is provided a technique for obtaining a magnetic susceptibility-weighted image in which contrast difference of a tissue of interest and a surrounding tissue can be emphasized regardless of the positional relationship of the B0 direction and the imaging slice. A phase image is converted into a susceptibility map not depending on the B0 direction, and then a weighting image used for weighting is generated by using the susceptibility map. The weighting image to be generated is for emphasizing contrast of a tissue of interest and a surrounding tissue depending on the purpose. Then, by multiplication of the weighting image and an absolute image, a magnetic susceptibility-weighted image in which the magnetic susceptibility difference is emphasized depending on the purpose is obtained.
US09165378B2	Acquisition of color calibration charts The present disclosure related to acquisition of color calibration charts. In at least some examples herein, an image of a calibration color chart is processed. A lighting condition of the color calibration chart may be automatically determined.
US09165373B2	Statistics of nearest neighbor fields In embodiments of statistics of nearest neighbor fields, matching patches of a nearest neighbor field can be determined at image grid locations of a first digital image and a second digital image. A motion field can then be determined based on motion data of the matching patches. Predominant motion components of the motion field can be determined based on statistics of the motion data to generate a final motion field. The predominant motion components correspond to a motion of objects as represented by a displacement between the first and second digital images. One of the predominant motion components can then be assigned to each of the matching patches to optimize the final motion field of the matching patches.
US09165370B2	Image processing apparatus, image processing method, and computer-readable recording device An image processing apparatus includes a probability value calculator that calculates, based on color feature data of a pixel included in an image, respective probabilities that the pixel belongs to a specific area and a non-specific area; a weighted edge intensity calculator that calculates a weighted edge intensity between neighboring pixels based on pixel values and color feature data of the pixel included in the image and a neighboring pixel of the pixel; an energy function creator that uses the probabilities and the weighted edge intensity to create an energy function expressed by a result of an area determination of the pixel; and an area divider that divides the image into the plurality of areas based on the energy function.
US09165367B2	Depth estimation system for two-dimensional images and method of operation thereof A method of operation of a depth estimation system includes: calculating focus measures for positions on a two-dimensional image; generating a depth map for the two-dimensional image based on fitting the focus measure through a Gaussian function; generating a three-dimensional image from the depth map and the two-dimensional image; and processing the three-dimensional image on a storage unit for displaying on a device.
US09165366B2	System and method for detecting and displaying airport approach lights A vehicle display system displays approach lights acquired by a vision system overlaid on, and aligned with, a stored synthetic approach light symbol. A stored approach light type that corresponds to the target runway may be verified to match the acquired approach lights. A synthetic approach light symbol that corresponds to the approach light type is chosen and aligned with the approach lights for display.
US09165365B2	Method and system for estimating attitude of camera In a method of estimating a camera attitude, based on the past-detected position of a marker and an appropriate camera attitude provided during current frame imaging, the position of the maker to the current frame is approximately predicted. Through extraction of points which are near the predicted marker position (marker neighboring points), a group of points are obtained. An attitude of the camera (rotation matrix and translation matrix) which optimizes an estimation function is obtained for re-estimating the camera attitude, where the estimation function needs, as its condition, a distance between the marker neighboring points included in the point groups and an estimation plane on which the marker is positioned. The point groups include many points extracted from the neighborhood of the marker, so that the preliminarily estimated approximate camera attitude can be corrected and estimated with higher accuracy even in an environment with occlusion.
US09165363B2	Image diagnostic device and image correction method Provided is an image diagnostic device with which it is possible to correct location misalignment of an image capture subject, and to improve the reliability of the result of the correction, in time series image data. An image diagnostic device may include an input part (13) which receives image data input; a correction unit (14) which computes a correction vector which denotes location misalignment of an image capture subject, and selects image data used with an image correction unit; an image correction part (20) which carries out a correction process on the image data based on the correction vector and creates corrected image data; a control part (21) which controls the correction unit and the image correction part; a memory (22) which stores the corrected image data and measurement data as stored data; an output unit (23) which outputs the stored data externally; a display unit (24) which displays the stored data; and an external input device (30) where an operator makes an input operation.
US09165359B2	High-throughput single-cell imaging, sorting, and isolation The invention provides a method and apparatus for isolating individual target cells. The apparatus includes a body structure comprising a main channel, a collection channel, and a waste channel fluidly coupled at a first fluid junction. A plurality of trapping channels intersect the collection channel, each trapping channel having a diameter at a location adjacent to the intersection of the trapping channel with the collection channel that is less than a diameter of an individual target cell. The apparatus also includes an imaging system configured to image individual target and non-target cells within the main channel, thereby producing imaging data; a processor configured to perform real-time, multivariate analyses of the imaging data; and a directing system configured to direct the individual target cells. A pressure source is in fluid communication with one or more of the collection channel, the waste channel, the first side channel, and the second side channel.
US09165356B2	Defect inspection method and defect inspection device A defect inspection method for inspecting a defect on a semiconductor wafer, using plural inspection methods includes: merging hot-spot coordinates as coordinates on the semiconductor wafer, designated by a user, or coordinates where a systematic defect can occur, with detected defect coordinates on the semiconductor wafer, acquired from inspection information, after information indicating the type of coordinates are added thereto; deciding an inspection sequence of the coordinates merged with each other; and defect inspection for executing selection using the information indicating the respective types of the coordinates merged with each other, and executing an inspection by selecting an inspection method for every coordinates to be inspected.
US09165354B2	Method of analyzing photolithography processes Methods of analyzing photolithography processes are provided. The methods may include obtaining an image from a pattern formed on a wafer and obtaining dimensions of the image. The methods may further include converting the dimensions into a profile graph and then dividing the profile graph into a low-frequency band profile graph and a high-frequency band profile graph.
US09165353B2	System and method for joint degradation estimation and image reconstruction in magnetic resonance imaging A magnetic resonance imaging (MRT) method for jointly estimating an image degradation and reconstructing an image of a subject in which that image degradation is mitigated is provided. The MRI system is operated to acquire multiple different k-space data sets that are acquired with different acquisition parameters so as to modulate the image degradation to be estimated. Using an iterative process, the image degradation is estimated while jointly reconstructing an image in which the estimated image degradation is mitigated.
US09165350B2	Image sharpening method and image processing device An image sharpening method and an image processing device are provided. The method includes: obtaining a plurality of pixels in an image; calculating a first weight of a high pass filter and a second weight of a first filter according to the pixels, and the first filter is a convolution of the high pass filter and a low pass filter; generating a sharpening filter according to the high pass filter, the first weight, the first filter and the second weight; and executing a sharpening operation on the pixels according to the sharpening filter. Accordingly, a sharpened image has better vision effects.
US09165349B2	Apparatus for generating diagnosis image, medical imaging system, and method for processing image An apparatus for generating a diagnosis image includes a local contrast characteristic calculator configured to calculate local contrast characteristics of radiation image data of a low-energy sub-band from radiation image data generated by radiation having at least two energy bands passing through a subject; a local contrast characteristic applier configured to apply the calculated local contrast characteristics to radiation image data of a full-energy band generated by the radiation having at least two energy bands passing through the subject; and a diagnosis image generator configured to generate a diagnosis image of the subject based on the radiation image data of the full-energy band to which the local contrast characteristics have been applied.
US09165348B2	Stochastic rasterization with selective culling Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.
US09165346B2	Method and apparatus for reducing image noise Embodiments of the present invention provide a method and an apparatus for reducing image noise. The method includes decomposing an original image into a luminance channel image and at least one chrominance channel image, and calculating a weighted average value of each pixel of the luminance channel image and the chrominance channel image by using luminance information, to correct each pixel of the luminance channel image and the chrominance channel image. By virtue of the embodiments of the present invention, it is possible to effectively avoid color dispersion at edges of images, to achieve easy implementation, and to effect low cost.
US09165345B2	Method and system for noise reduction in video systems A system and method of image processing is provided, including implementing adaptive pixel replacement techniques or reducing noise. The method includes obtaining a data map of an image frame, wherein the data map comprises good pixels and bad pixels at locations associated with the data map. The method also includes assigning different techniques to the bad pixels, wherein a first technique is assigned to a first bad pixel and a second technique is assigned to a second bad pixel. The method further includes adjusting information associated with the bad pixels for a chosen technique for each of the bad pixels.
US09165342B2	Image data processing apparatus and method for writing an image data into a memory An image data processing including a storage unit for storing a first pixel block and a second pixel block taken from image data in which pixels are arranged in a first direction and a second direction, and a writing module for writing the first pixel block and the second pixel block stored in the storage unit into a memory, wherein the first pixel block and the second pixel block are arranged one adjacent to the other along the first direction, and the number of pixels arranged in the first direction in each block is equal to an access unit data length of the memory multiplied by a natural number m1, and the writing module writes pixel data equal in length to the access unit data length, and representing pixels contiguously arranged along the first direction across the first and second pixel blocks, into the memory in a single access operation.
US09165340B2	Image display system, image display method, image display program, and computer-readable recording medium storing said program The image display system includes a calculation unit, a specifying unit, a generation unit and a transmitting unit. Upon change of a zoom level of a current image not containing position information to a specified value on a user terminal, the calculation unit calculates a display range of an object represented by the current image after change in zoom level. The specifying unit refers to data of a different image of the object and specifies a part of the different image indicated by the display range calculated by the calculation unit. The different image has a different resolution from the current image. The generation unit generates a next image representing the part specified by the specifying unit using the data of the different image. The transmitting unit transmits the next image to the user terminal for switching from the current image to the next image.
US09165339B2	Blending map data with additional imagery In one aspect, a map is provided for display by one or more computing devices. The map includes one or more polygons. The one or more computing devices receive a zoom request for viewing the map. The one or more computing devices then determines whether a visual threshold has been reached based at least in part on the zoom request. When the visual threshold has been reached, the one or more computing devices identify a polygon of the one or more polygons. The one or more computing devices then provide for display alternate imagery corresponding to the polygon on the map.
US09165338B2	Method, device and computer-readable storage medium for panoramic image completion A method for panoramic image completion is disclosed. The method includes: acquiring a panoramic image; obtaining a projected image by mapping pixels of the panoramic image onto a polar coordinate system, wherein a long side component of the pixel coordinate of the pixels is corresponding to the polar angle of the polar coordinate system and a short side component of the pixel coordinate of the pixels is corresponding to a radial coordinate of the polar coordinate system; acquiring an incomplete region of the projected image, and obtaining a completed image by completing the incomplete region; and obtaining a completed panoramic image by inverse mapping the pixels of the completed image according to the polar coordinate system. Furthermore, a device for panoramic image completion is also disclosed. The above method and device for panoramic image completion take account of the perspective curvature of the panoramic image, to improve the degree of restoration.
US09165337B2	Command instruction management Techniques are described for writing commands to memory units of a chain of memory units of a command buffer. The techniques may write the commands, and if during the writing, it is determined that there is not sufficient space in the chain of memory unit, the techniques may flush previously confirmed commands. If after the writing, the techniques determine that there is not sufficient space in an allocation list for the handles associated with the commands, the techniques may flush previously confirmed commands.
US09165336B2	Method and apparatus for checking a security feature of a value document A method includes checking a specified security feature of a value document which is present in a specified security-feature region of the value document. The security feature includes captured pixel data which describe spatially resolved with a specified optical spatial resolution, an optical image at least of the security-feature region of the value document, and there are captured ultrasound data which describe an ultrasonic property of the value document at least in the security-feature region, spatially resolved with a specified ultrasonic spatial resolution. The ultrasonic spatial resolution is lower than the optical spatial resolution. From the pixel data there are established first reduced-resolution pixel data for reduced-resolution pixels of the first reduced-resolution image which describe a reduced-resolution optical image at least of the security-feature region of the value document, whose optical spatial resolution corresponds to the ultrasonic spatial resolution.
US09165323B1	Biometric transaction system and method A system for enabling identity verification of an individual in a transaction between the individual and an entity that utilizes a data processing system, an entity device, and an individual device. The individual registers with the data processing system biometric data taken from the individual and data pertaining to an individual device. The entity registers with the data processing system entity identifying information. Once the individual and entity agree on a transaction, the entity notifies the data processing system of the pending transaction and requests verification of the individual's identity. The individual communicates to the data processing system individual biometric data. The data processing system compares the biometric data from the individual with registered biometric data. The data processing system forwards a result of the comparison to the entity and upon a successful comparison, may forward any requested information regarding the individual to the entity.
US09165322B2	Digital downloading jukebox system with user-tailored music management, communications, and other tools A digital downloading jukebox system including a mechanism for delivering custom services to a recognized user, including services for creating playlists, communicating with others, accessing other features, etc. is provided. In some exemplary embodiments, after a user is recognized, the jukebox system allows users to access a special front-end via the Internet or on an actual jukebox. Then, the user may, for example, create playlists, share songs with friends, send messages to friends, and access other value-added content. Other exemplary embodiments allow users to become certified, charging them for services without requiring constant inputting of coinage or credit card information. Such a system preferably learns about networks of friends, and enables managers to send similar messages to regular customers and/or others known to the system.
US09165321B1	Optimistic receipt flow An online electronic wallet system and method provide secure storage and transmission of payment instrument information for use in completing online purchases initiated from a client device. A payment instrument's verification code is stored in an encrypted form in local storage on a client device and retrieved and re-encrypted along with other payment instrument information stored on the system using a merchant-specific key. An API library is used to integrate the online electronic wallet system with a registered merchant's purchase flow, including the ability to ensure receipt of an electronic receipt prior to communicating payment instrument information to a merchant server.
US09165317B2	Methods, systems, and products for managing digital content A dynamic repository (either storing digital data content or pointers to stored digital data content) works in conjunction with a plurality of interfaces to manage digital content and digital rights policies associated with one or more users. Digital rights policies are unique to each user and such policies define access to digital content in the repository. The user's digital rights policy indicates the level of access a user has to digital content in the repository (e.g., the policy could indicate that the user has authorized access to a particular file for a period of seven days). The interfaces linked with the content repository are used to access and manipulate the digital data content (based upon each user's digital rights policy) and the digital rights policies stored in the content repository. The interfaces include: (a) one or more authentication interfaces for authenticating users, (b) one or more digital rights management (DRM) interfaces allowing users to add, delete, or edit the digital rights policies, (c) one or more data access interfaces allowing users to selectively access digital data content as defined by their individual digital rights policy, (d) one or more browsing interfaces allowing users to selectively browse said digital data content, or a (e) one or more content manipulation interfaces allowing said users to add, delete, or edit said digital data content.
US09165310B2	Method and apparatus for intelligent street light advertisement delivery A system includes a vehicle processor configured to communicate with an intelligent street light to receive advertisements pertaining to local businesses. The processor is also configured to store a plurality of received advertisements. The processor is further configured to sort the advertisements based on one or more user factors. Also, the processor is configured to determine an appropriate time for advertisement delivery and deliver the advertisements at the appropriate time.
US09165307B2	System, method and computer program product for templated export of content Embodiments disclosed herein provide systems and methods for a templated export. In one embodiment, a method may include determining an export template responsive to a first user action, the first user action indicating a delivery endpoint. The method may further include preparing an asset for delivery to the delivery endpoint utilizing the export template. The asset may include zero or more files. The export template may include predetermined configuration and delivery parameters particular to the delivery endpoint. The prepared asset may be communicated to the delivery endpoint without any further user action.
US09165306B2	Method and system for generating and sharing customized portable consumer devices A method for receiving and presenting user-generated designs and sets of terms for portable consumer devices. The method provides for allowing a first person to create a customized design for a portable consumer device, and share the design with other consumers via a host site. Similarly, the method provides for allowing a first person to create and share a customized set of terms for the portable consumer device. Methods for receiving and distributing feedback for customized designs and sets of terms are included.
US09165298B2	Remote synchronization of pin-pad records with a central transactions database A method of remotely synchronizing pin-pad terminals involves a gateway receiving from an acquirer server an authorization code for a transaction authorized using one of a plurality of pin-pad terminals, and saving in a database particulars of the authorized transaction. Each terminal has a memory storing particulars of at least one authorized transaction authorized using the terminal, and a running total value of all transactions authorized using the pin-pad terminal. The gateway receives a request to close out all the saved transactions and receives from one of the terminals an authorization request message requesting authorization for an additional transaction. In response, the gateway closes in the database all the saved transactions authorized using the one terminal, and responds to the authorization request message by providing the one terminal with a remote synchronization command commanding the one terminal to clear the running total from the memory.
US09165295B2	Automated card information exchange pursuant to a commercial transaction In general, embodiments of the present invention relate to a card and associated methods for automated information (static and dynamic) exchange pursuant to a commercial transaction. In a typical embodiment, the card (e.g., a credit card, a debit card and/or a smart card) comprises an energy component for providing power to the card and a back display (e.g., positioned on the back or magnetic strip side of the card) for displaying card information being used in the commercial transaction. Upon display, a terminal (e.g., a point of sale terminal) will scan/read the card information and generate a corresponding source validation code (SVC). An imager positioned on the back of the card will scan/read the SVC and card validation code (CVC) logic on the card will generate a CVC based on the SVC (e.g., based on a validation result of the SVC). A biometric reader positioned on a front side of the card will take a biometric reading from a user of the card and corresponding user validation code (UVC) logic will generate a UVC based on the biometric reading. The underlying commercial transaction can then be validated (e.g., by a server associated with the terminal or by validation logic on the card itself), a validation result can be displayed on a front display (e.g., positioned on the front side of the card).
US09165293B2	Systems and methods for waveform transmission of transaction card data A device and method for waveform transmission of transaction card data to a merchant point-of-sale device are provided. The device includes a memory device for storing data, a processor, and a transmitter. The device is programmed to receive transaction card data that mimics data stored within a magnetic stripe associated with a transaction card, convert the transaction card data to a first data file for storage within the memory device, transmit the first data file to the transmitter, and transmit a first waveform from the transmitter to the POS device, wherein the first waveform includes changes in a magnetic field that represent the transaction card data.
US09165291B1	Payment transaction by email Disclosed is a technology for seamless initiation of a financial service, such as a payment transaction, by sending a communication message. The disclosed technology can be used, for example, to send payment from a person (e.g., a consumer) to another over e-mail without requiring any sign-up or login procedure. In at least one embodiment, the technology includes receiving a service request email generated by a native email application on a consumer's device, verifying the email using information included in the email, and initiating the service as requested based on the information. Various embodiments of the disclosed technology enable a simplified payment transaction system for ordinary consumers without the hassle of having to sign up, to remember a user account and a password, and to login for sending or receiving every payment transaction, while not sacrificing the essential security feature of authenticating the user for every payment transaction.
US09165290B2	Sharing notes in online meetings Notes may be shared in an online meeting with online meeting attendees through a software application associated with organizing an online meeting, for example, online meeting software, calendaring software, note-taking software, or the like. Notes may be created and/or shared before, during, and/or after the online meeting by meeting attendees. Meeting attendees may be notified when notes are shared for the online meeting. Notes may be shared with items of the software application associated with organizing the online meeting. For example, notes may be shared in online meeting software with the online meeting. Notes may be shared among items of different software applications, for example, notes shared in the online meeting software may be automatically shared with a calendar item in a calendaring software application.
US09165289B2	Electronic meeting management for mobile wireless devices with post meeting processing A device management system includes a meeting support system that is configured to generate and transmit a plurality of electronic meeting invitations to a plurality of mobile wireless devices that correspond to a plurality of meeting participants and receive responses indicating whether the plurality of participants will attend the electronic meeting. The device management system receives identification data that identifies one or more documents or information that will be made available to the plurality of participants. The meeting support system determines whether the plurality of participants is authorized to access the one or more electronic documents or information. If any of the participants are not authorized to access any of the electronic documents or information, the meeting support system notifies the meeting organizer. The device management system may also include a meeting session management system that is configured to share information among the plurality of mobile wireless devices.
US09165287B2	Apparatus and method for augmenting digital educational content with social learning tools A non-transitory computer readable storage medium includes executable instructions to display electronic content, associate a subset of the electronic content with a comment from a user and submit the subset of the electronic content and the comment to a forum accessible by a plurality of users.
US09165286B2	Electronic process-driven collaboration system A business process-driven collaboration system embeds collaboration resources and tools directly into existing business processes and applications. The system provides a service layer connected to an existing business process management (BPM) service to embed collaboration resources into the process, and in particular, into the user interface of the existing business applications. The system provides an interface layer providing rapid enhancement of the existing business applications.
US09165285B2	Shared attachments When an outgoing communication sent to one or more recipients contains a supported attachment type, a shared workspace that contains a shared version of the original attachment is provisioned. A modified version of the original outgoing communication is delivered to internal recipients including both a link to the shared document and the original attachment.
US09165283B2	Method and system to process a request to create a collaborative task Embodiments include a system for providing an identification of a collaborative task. The system may include a communication unit and a processing unit. The communication unit may be configured to receive a request of a user to create the collaborative task and send task metadata to a further system. The processing unit may be configured to generate the task metadata. The task metadata may be a part of the collaborative task and identifying the collaborative task as a part of a process.
US09165281B2	System and method for enabling electronic presentations A system and method is provided for enabling collaborative electronic presentations and annotation of graphic information. The method includes the operation of taking a snapshot of an active application. A snapshot can be initiated by a user accessible snapshot control. The snapshot of the active application can be transferred to the electronic whiteboard in response to activation of the snapshot control. A further operation is storing the snapshot in a whiteboard sheet of the electronic whiteboard. Each loaded snapshot may be stored in a separate whiteboard sheet in order to provide a plurality of whiteboard sheets. Another operation can be enabling graphical annotation of the plurality of whiteboard sheets in the whiteboard annotation area by the user.
US09165279B2	System and method for calibration and mapping of real-time location data A method of mapping the location of at least one object in three dimensional space, relative to an initial point in three dimensional space by an EIR terminal which contains a microprocessor, memory, a scanning device, a motion sensing device, and a communication interface. The method includes scanning a signal of decodable indicia located at a pre-defined area of a physical object, locating the decodable indicia within this signal, decoding the decodable indicia into a decoded message. The decoded message is an identifier for said physical object, which is then displayed. After receiving an interface command, the EIR terminal is placed in mechanical contact with the pre-defined area of the physical object and a first spatial position is stored as a point of origin in the EIR terminal.
US09165275B2	Method and apparatus for identifying redeployed distributed generator components A method and apparatus for identifying a redeployment of a distributed generator component, at least a portion of the method being performed by a controller comprising at least one processor. In one embodiment, the method comprises obtaining a first identification (ID) for a first component of a distributed generator (DG) and a second ID for a second component of the DG; generating an association between the first identifier and the second identifier, wherein the association identifies a relationship between the first and the second components; and comparing the association to a plurality of documented associations to determine whether the association has changed.
US09165273B2	Externalizing enterprise workspaces using content plug-in The present disclosure describes methods, systems, and computer program products for externalizing an enterprise workspace to business applications. One computer-implemented method includes indicating data within an application to be included in a new module, initiating a command to create the new module using the indicated data, transmitting the command to create the new module to an external server, receiving from the external server a list of available enterprise workspaces for adding the new module, selecting at least one available enterprise workspace from the list of available enterprise workspaces, transmitting the selected enterprise workspace to the external server, and receiving a confirmation of the new module creation.
US09165272B1	System for monitoring a plurality of tagged assets on an offshore asset A system for monitoring a plurality of tagged assets on at least one offshore asset, by creating a customer profile and a library of survey set ups and storing information from independent survey set ups mounted on or proximate to the offshore asset on the administrative data storage. The system includes creating a library of tagged assets for the offshore asset using at least one independent survey set up, wherein each tagged asset has an icon with a hyperlink to a library of images. The system includes identifying placement locations on offshore assets and forming an executive dashboard for display on at least one client device, wherein a virtually positioned icon positioned on an image of the tagged assets presents a hyperlink to the library of survey set ups for that tagged asset, thereby enabling toggling from the image to the library of survey set ups.
US09165270B2	Predicting likelihood of customer attrition and retention measures The present invention relates to a system and method for customer retention. Historical transaction and customer data may be received from stores. Likewise, recent customer transaction data may be received from the stores. The transactions are linked to each customer. Attriters, historical customers who discontinued shopping, are identified. Next, risk factors for attrition may be identified by examining the attriters' transaction history for commonalities. From the risk factors a loss model may be generated. The loss model may be used, in conjunction with current transaction data, to generate the likelihood of loss for each of the current customers, which may then be reported. Retention measures may be generated for each customer by comparing the customer's transactions to the loss model and the risk factors. The retention measures may be outputted to the stores, and a price optimization system. Likewise, the retention measures may be validated by comparing actual customer loss to the loss model.
US09165262B2	Automatic generation of assent indication in a document approval function for collaborative document editing A method for generating an assent indication in a document approval and review function can include loading a document for editing in a document editor and determining a set of authors for the document. The method also can include modifying a title of the document to include an identity of at least one of the authors in the set. Finally, the method can include changing a visual appearance in the title of an identity of the assenting author responsive to one of the authors in the set assenting to a publication of the document.
US09165261B2	Apparatus and method for performing accounting in wireless communication system An apparatus and method for processing accounting in a wireless communication system are provided. The method includes creating an accounting data base (DB) for a mobile station (MS), determining whether a state transition of the MS occurs, if the state transition of the MS occurs, updating state information in the accounting DB, and transmitting the accounting information including the state information to an accounting server.
US09165259B2	Personalized activity stream discovery system, method, and device A personalized activity stream system, method, and device delivers a recommendation that is contextualized basis a selected item in an activity stream and that is personalized for a recommendation recipient consistent with an inference of the recommendation recipient's interests. Contextualization and personalization may be based on an automatic analysis of usage behaviors and/or content. The recommendation may be informed by an inference of an expertise level, and an explanation for the recommendation may be delivered to the recommendation recipient. The recommendation may be in accordance with an automatically determined geographic location associated with a location-aware portable device, as well as environmental conditions proximal to the portable device.
US09165258B2	Generating training documents A method of generating training documents for training a classifying device comprises, with a processor, sampling from a distribution of words in a number of original documents, and creating a number of pseudo-documents from the distribution of words, the pseudo-documents comprising a similar distribution of words as the original documents. A device for classifying textual documents comprises a processor; and a memory communicatively coupled to the processor, the memory comprising a sampling module to, when executed by the processor, determine the distribution of words in a number of original documents, a pseudo-document creation module to, when executed by the processor, create a number of pseudo-documents from the distribution of words, the pseudo-documents comprising a similar distribution of words as the original documents, and a training module to, when executed by the processor, train the device to classify textual documents based on the pseudo-documents.
US09165257B2	Typing assistance for editing Apparatus and methods are disclosed for providing feedback and guidance to touch screen device users to improve the text entry user experience and performance. According to one embodiment, a method comprises receiving a text entry, receiving input on a touch screen in the form of a first single touch input located over a word of previously entered text, and presenting the user with one or more suggestion candidates indicated possible replacement words related to the selected word. The user can then select one of the suggestion candidates using a second single touch input to replace the selected word with a word associated with the selected suggestion candidate.
US09165255B1	Automatic sequencing of video playlists based on mood classification of each video and video cluster transitions A given set of videos are sequenced in an aesthetically pleasing manner using models learned from human curated playlists. Semantic features associated with each video in the curated playlists are identified and a first order Markov chain model is learned from curated playlists. In one method, a directed graph using the Markov model is induced, wherein sequencing is obtained by finding the shortest path through the directed graph. In another method a sampling based approach is implemented to produce paths on the digraph. Multiple samples are generated and the best scoring sample is returned as the output. In a third method, a relevance based random walk sampling algorithm is modified to produce a reordering of the playlist.
US09165254B2	Method and system to predict the likelihood of topics The present invention relate to a method and system to predict the likelihood of data topics that may occur from data sources. The likelihood of the data topics may be predicted over other dimensions of time or over other dimensions. In the present invention, a topic means a defining characteristic, usually represented as a data element, of a single feature, activity, subject, behavior, event or an aggregation of such defining characteristics.
US09165249B2	Information processing apparatus, information processing method, and program Provided is an information processing apparatus including: a reward estimator generating unit using action history data, which includes state data expressing a state of an agent, action data expressing an agent's action, and a reward value expressing a reward of the action, as learning data to generate, through machine learning, a reward estimator estimating the reward value from inputted state data and action data; an action selecting unit preferentially selecting an action not included in the action history data but with a high estimated reward value; and an action history adding unit causing the agent to perform the selected action and adding to the action history data the state data and action data for the action and the action's reward value in association with each other. The reward estimator is regenerated when a set of state data, action data, and the reward value is added to the action history data.
US09165247B2	Using global and local catastrophes across sub-populations in parallel evolutionary computing A parallel genetic algorithm computing process tracks forward progress of a first sub-population across generations thereof. The first sub-population is one of a plurality of sub-populations that form a population of candidate solutions to an optimization problem. At a current generation of the first sub-population, it is determined that forward progress of the first sub-population fails a set of one or more forward progress criteria. In response to determining that the forward progress of the first sub-population fails the set of one or more forward progress criteria at the current generation, a local catastrophe is invoked on the current generation of the first sub-population. The first sub-population is re-populated after the local catastrophe is invoked. The first sub-population is re-established after re-populating while constraining migration to the first sub-population.
US09165246B2	Neuristor-based reservoir computing devices A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.
US09165244B2	Structural to functional synaptic conversion Computer-implemented methods, software, and systems for determining functional synapses from given structural touches between cells in a neuronal circuit are described. One computer-implemented method for determining functional synapses from predetermined synapses of connections between two cells in a neuronal circuit, includes determining, from the predetermined synapses, the functional synapses by leaving a portion of the connections unused, e.g. for activation by plasticity mechanisms.
US09165243B2	Tensor deep stacked neural network A tensor deep stacked neural (T-DSN) network for obtaining predictions for discriminative modeling problems. The T-DSN network and method use bilinear modeling with a tensor representation to map a hidden layer to the predication layer. The T-DSN network is constructed by stacking blocks of a single hidden layer tensor neural network (SHLTNN) on top of each other. The single hidden layer for each block then is separated or divided into a plurality of two or more sections. In some embodiments, the hidden layer is separated into a first hidden layer section and a second hidden layer section. These multiple sections of the hidden layer are combined using a product operator to obtain an implicit hidden layer having a single section. In some embodiments the product operator is a Khatri-Rao product. A prediction is made using the implicit hidden layer and weights, and the output prediction layer is consequently obtained.
US09165240B2	Coupling in and to RFID smart cards A dual interface (DI) smart card (100) comprising a chip module (CM), a module antenna (MA), a card body (CB) and a card antenna (CA) having two windings (D,E) connected with reverse phase as a “quasi-dipole”. Capacitive stubs (B,C) connected with an antenna structure (A) of the module antenna (MA). The module antenna (MA) overlaps only one of the windings (D or E) of the card antenna (CA). The card antenna (CA) may be formed from one continuous wire. Ferrite (156) shielding the module antenna (MA) from contact pads (CP) and for enhancing coupling between the module antenna (MA) and the card antenna (CA). The card antenna (CA) may be disposed substantially only in a top half portion of the card body (CB).
US09165239B2	Electromagnetic-coupling-module-attached article An electromagnetic-coupling module including a radio IC chip and a feeder circuit board on which the radio IC chip is mounted and a feeder circuit including a resonant circuit having a predetermined resonant frequency is attached to an article. The article has a radiation element that radiates a transmission signal supplied from the feeder circuit of the electromagnetic-coupling module via electromagnetic coupling and that supplies a received reception signal to the feeder circuit via the electromagnetic coupling.
US09165238B2	Methods for manufacturing RFID tags and structures formed therefrom Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices.
US09165236B2	Method for manufacturing smart cards This invention relates to a smart card (1) manufacturing method that makes it possible to reduce the thickness of the said smart card and directly obtain a final 3FF or 4FF format. The smart card manufacturing method comprises steps for depositing resin forming a first protective coat (11) over the electronic element assembly with a surface greater than the required smart card format and depositing a second protective coat with a format larger than the required card format on the first protective coat. The second protective coat is fixed to the first protective coat by curing the first protective coat, and then the assembly obtained in that way is cut to the required format.
US09165235B2	Method and apparatus for protecting information in magnetic strip and RFID cards from fraudulent scanning A device for preventing unwanted electromagnetic inquiry of an electronic card storing information thereon by the transmission of a rogue interrogating signal from an RFID skimmer proximate the electronic card. The device comprises a first and a second conductive material layer each operating to detune an antenna associated with the electronic card or to detune front end resonant circuits associated with the electronic card, and one or more third material layers having a greater thickness than the first and second layers and disposed between the first and second layers, the one or more third material layers providing electromagnetic shielding against radio frequency signals emitted from the electronic card.
US09165231B2	Image recognition in passive RFID devices Passive RFID devices are disclosed that perform image recognition. The device includes an antenna, circuitry, and a camera. The antenna receives a radio frequency (RF) signal from a RFID reader. The circuitry stores image data for objects that is used for image recognition. To operate, the circuitry derives power from the RF signal. With the power derived from the RF signal, the camera captures an image. The circuitry then identifies an object in the captured image based on the image data for the objects, and outputs information for the identified object, such as to the RFID reader.
US09165223B2	Compensation for optical brighteners of print media to facilitate calibration of a printing system Systems and methods are provided for compensating for optical brighteners found in print media while calibrating a printer. The system is able to determine reflectance values for a print medium, to determine reflectance values for a colorant applied to the print medium, and to alter the determined reflectance values for the colorant based on the reflectance values of the print medium. The system is further able to calibrate a printer that applied the colorant to the print medium based on the altered reflectance values.
US09165221B2	Image forming system, data processing apparatus, image forming apparatus, recording medium and display method When an image formation instruction for created document data is received, image data for a preview image corresponding to the document data is generated, the preview image based on the image data is displayed on a display, and an image is formed using data for image formation based on the image data for the preview image.
US09165220B2	Image object recognition based on a feature vector with context information Examples disclosed herein relate to image object recognition based on a feature vector with context information. A processor may create an expanded feature vector related to a first area of an image including context information related to the first area. The processor may determine the presence of an object in the image based on the feature vector and output information about the determined object.
US09165218B2	Distance-based image analysis An image analyzer (120) aggregates image samples (140) into a cluster (170) based on the image samples (140) being classified from a subset of image metrics applied to a reference sample (130). The image analyzer (120) generates an image quality output (150) by analyzing a distance (180) from the cluster (180) relative to another cluster.
US09165217B2	Techniques for ground-level photo geolocation using digital elevation Techniques for generating cross-modality semantic classifiers and using those cross-modality semantic classifiers for ground level photo geo-location using digital elevation are provided. In one aspect, a method for generating cross-modality semantic classifiers is provided. The method includes the steps of: (a) using Geographic Information Service (GIS) data to label satellite images; (b) using the satellite images labeled with the GIS data as training data to generate semantic classifiers for a satellite modality; (c) using the GIS data to label Global Positioning System (GPS) tagged ground level photos; (d) using the GPS tagged ground level photos labeled with the GIS data as training data to generate semantic classifiers for a ground level photo modality, wherein the semantic classifiers for the satellite modality and the ground level photo modality are the cross-modality semantic classifiers.
US09165212B1	Person counting device, person counting system, and person counting method A person counting device according to embodiments of the present invention counts the number of persons passing through a doorway based on an imaged image in which the surroundings of the doorway are imaged. The person counting device includes a moving line acquirer that acquires a moving line for each person detected from the imaged image, a person counter that counts the persons that have passed through the doorway based on the moving line, and a display information generator that generates display information which represents the number of persons that have passed through the doorway based on the counting results of the person counter. The person counter detects an interruption of the moving line in the vicinity of the doorway, determines a similarity between the background image of the doorway and the person image, and includes a deemed counter that deems that the person has passed through the doorway.
US09165205B2	Image processing device generating character image and background image on the basis of connected pixel group In an image processing device, an edge image generation part detects an edge in an original image and generates an edge image constituted from the detected edge. A connected pixel extraction part extracts connected pixel groups in the edge image. A binary image generation part classifies the connected pixel groups under respective colors of the connected pixel groups, and generates a character image for each color. A background image generation part generates a background image of the original image based on the character image so that a pixel value at the position of the character image in the original image is set by an average value of the pixel values in the original image with regard to at least a portion of pixels around a rectangle circumscribing the connected pixel groups. An image compression part compresses respective image data of the character image and background image by different compression manners.
US09165199B2	Controlled human pose estimation from depth image streams A system, method, and computer program product for estimating human body pose are described. According to one aspect, anatomical features are detected in a depth image of a human actor. The method detects a head, neck, and trunk (H-N-T) template in the depth image, and detects limbs in the depth image based on the H-N-T template. The anatomical features are detected based on the H-N-T template and the limbs. An estimated pose of a human model is estimated based on the detected features and kinematic constraints of the human model.
US09165196B2	Augmenting ADAS features of a vehicle with image processing support in on-board vehicle platform Systems and methods directed to augmenting advanced driver assistance systems (ADAS) features of a vehicle with image processing support in on-board vehicle platform are described herein. Images may be received from one or more image sensors associated with an ADAS of a vehicle. The received images may be processed. An action is determined based upon, at least in part, the processed images. A message is transmitted to an ADAS controller responsive to the determination.
US09165190B2	3D human pose and shape modeling Methods, devices and systems for performing video content analysis to detect humans or other objects of interest a video image is disclosed. The detection of humans may be used to count a number of humans, to determine a location of each human and/or perform crowd analyses of monitored areas.
US09165188B2	Systems and methods for mobile image capture and processing In various embodiments, methods, systems, and computer program products for processing digital images captured by a mobile device are disclosed. Myriad features enable and/or facilitate processing of such digital images using a mobile device that would otherwise be technically impossible or impractical, and furthermore address unique challenges presented by images captured using a camera rather than a traditional flat-bed scanner, paper-feed scanner or multifunction peripheral.
US09165185B2	Optical character recognition of text in an image according to a prioritized processing sequence A computer-implemented method for providing a text-based representation of a region of interest of an image to first is provided that includes a step of identifying text zones within the image, each text zone including textual content and having a respective rank assigned thereto based on an arrangement of the text zones within the image. The method also includes determining a processing sequence for performing optical character recognition (OCR) on the text zones. The processing sequence is based, firstly, on an arrangement of the text zones with respect to the region of interest and, secondly, on the ranks assigned to the text zones. The method further includes performing an OCR process on the text zones according to the processing sequence to progressively obtain a machine-encoded representation of the region of interest, and concurrently present the machine-encoded representation to the user, via an output device, as the text-based representation.
US09165184B2	Identifying matching images The disclosure concerns face recognition systems. The aim is to identify candidate matching images to a probe image. There is provided methods, software and computer system to select (22, 24) a method of matching images from two or more methods of matching images based on an underlying resolution (20) of the probe image (8). Comparing two images of differing resolutions is common in surveillance environments. To alleviate this degradation, the method advantageously dynamically selects the most appropriate matching method for a probe image. The disclosure also provided methods to determine the underlying resolution of a probe (8) or gallery image (14).
US09165183B2	Estimating apparatus, method thereof, and computer program product therefor An estimating apparatus configured to estimate a correct attribute value is provided. The estimating apparatus extracts feature quantities from an image including a person, calculates a first likelihood of the feature quantity for respective attribute classes; calculating second likelihoods for the respective attribute classes from the first likelihoods for the respective attribute classes; specifies the attribute class having the highest second likelihood; calculates an estimated attribute value of the specific attribute class and estimated attribute values of selected classes by using the feature quantity; and applies the second likelihood on the estimated attribute value of the specific attribute class as a weight, applies the second likelihoods on the estimated attribute values of the selected classes as a weight and add the same, and calculates a corrected attribute value of the specific attribute class.
US09165180B2	Illumination sensitive face recognition Systems and methods for face recognition are provided. In one example, a method for face recognition includes receiving a user image and detecting a user luminance of data representing the user's face. An adaptive low pass filter is selected that corresponds to the user luminance of the user's face. The filter is applied to the user image to create a filtered user image. The filtered user image is projected to create a filtered user image representation. A filtered reference image representation that has been filtered with the same low pass filter is selected from a reference image database. The method then determines whether the filtered reference image representation matches the filtered user image representation.
US09165179B1	Feature reduction based on local densities for bundle adjustment of images Methods, systems, and computer program products are provided for determining camera parameters and three dimensional locations of features from a plurality of images of a geographic area. These include, detecting features in the plurality of images where each of the images cover at least a portion of the geographic area, comparing the detected features between respective ones of the images to determine a plurality of matched features, selecting a subset of the plurality of matched features and determining the camera parameters and the three dimensional positions of one or more of the detected features using the selected subset. The respective matched features are selected depending on a quantity of other matched features in proximity to the respective matched features.
US09165175B2	Finger sensing apparatus performing secure software update and associated methods A finger sensing apparatus may include a finger sensor having an integrated circuit (IC) substrate, an array of finger sensing elements on the IC substrate, and secure software update circuitry on the IC substrate. In addition, the finger sensing apparatus may include a host platform external from the finger sensor and hosting software associated with the finger sensor. The host platform may cooperate with the secure software update circuitry to authorize an attempted software update.
US09165169B2	Method for data communication between a base station and a transponder A method for data communication between a base station and at least one transponder by a high-frequency electromagnetic carrier signal is disclosed, onto which information packets are modulated, whereby each information packet has a header section, a middle section, and an end section and whereby the middle section has a data field for the transmission of data and/or address information and a protection field placed thereafter for the correction of errors in the transmission of the data and/or address information, whereby after the data field the base station inserts at least one control field, by which the protection field following the inserted control field can be changed in such a way that the duration of an information packet is set variably. The invention relates further to a base station for carrying out this method, to a data communication system containing a base station and at least one transponder in communicative wireless contact with the base station.
US09165168B2	Magnetic Card Reader In order to perform processing of analyzing card data in an appropriate amount of time depending on the number of tracks actually present on a magnetic stripe with use of a single demodulation circuit, the single demodulation circuit produces, based on magnetic data read by a magnetic head, a single common card running signal obtained by ORing card running signals of tracks present on the magnetic stripe of the magnetic card, a clock signal of each track present on the magnetic stripe, and a data signal of each track present on the magnetic stripe. A card running signal generation circuit generates, based on the common card running signal and the clock signal of each track, an individual card running signal of each track present on the magnetic stripe. A data analysis processing unit determines, based on presence or absence of the individual card running signal, presence or absence of a track on the magnetic stripe to perform processing of analyzing the data signal only for the track determined to be present on the magnetic stripe.
US09165163B2	Secure delivery of processing code An apparatus may comprise a secure portion of a chip and an external memory device. The secure portion of the chip may be configured to receive an encryption key, and the memory device may be configured to receive an encrypted processing code. The secure portion of the chip may be configured to verify the encrypted processing code by decrypting the encrypted processing code using the encryption key. A non-secure portion of the chip may be configured to write the encrypted processing code on the memory device while the memory device is coupled to the chip. The encryption key may be associated with an identifier of the chip.
US09165161B2	Setting options for publishing calendar Selectively shared and filtered personal information collections are provided. Personal information collections include calendars, task lists, address books, and other collections of information that may be provided by personal information manager (PIM) software. Personal information collections published on a server may be limited on a user-by-user basis as to who may access the collections. Furthermore, collections may be automatically filtered based on a rolling window of dates, reducing file size and maintaining privacy of items outside the rolling window.
US09165158B2	Encryption key management using distributed storage of encryption-key fragments An encryption key fragment is divided into a number of encryption key fragments. Requests to store different ones of the encryption key fragments are transmitted to different computer memory storage systems. An individual request to store an encryption key fragment includes one of the encryption key fragments and bears an access control hallmark for regulating access to the encryption key fragment.
US09165157B2	Methods and apparatus facilitating access to storage among multiple computers Multiple computers in a cluster maintain respective sets of identifiers of neighbor computers in the cluster for each of multiple named resource. A combination of the respective sets of identifiers define a respective tree formed by the respective sets of identifiers for a respective named resource in the set of named resources. Upon origination and detection of a request at a given computer in the cluster, a given computer forwards the request from the given computer over a network to successive computers in the hierarchical tree leading to the computers relevant in handling the request based on use of identifiers of neighbor computers. Thus, a combination of identifiers of neighbor computers identify potential paths to related computers in the tree.
US09165156B2	Role-based access control modeling and auditing system A role-based access control (RBAC) modeling and auditing system is described that enables a user to access and/or create security roles that can be applied to users of a first software application. When a security role having a particular set of permissions has been accessed or created, the system can present a simulated user interface (UI) that indicates information that can be viewed and/or actions that can be performed by a user to whom the security role has been assigned when interacting with the first software application. The system may further provide “run as” functionality that enables a simulated UI to be generated for a particular user and that can display the security role(s) associated with the particular user. The system may be embodied in a second software application, such as a tool that is associated with the first software application.
US09165155B2	Protecting the integrity and privacy of data with storage leases Storage leases specify access restrictions and time periods, restricting access to their associated data during the storage lease time period. Storage leases may be assigned to individual data storage blocks or groups of data storage blocks in a data storage device. A data storage device may include any arbitrary number of different storage leases assigned to different portions of its data storage blocks. Storage lease-enabled devices may provide security certificates to verify that data access operations have been performed as requested and that their storage leases are being enforced. Storage lease-enabled devices compare storage lease information for data units with the current time using a clock isolated from access by storage clients or time certificates from one or more trusted time servers. Storage leases may be used in combination with backup applications, file systems, database systems, peer-to-peer data storage, and cloud storage systems.
US09165151B2	Systems, methods, and devices for encrypted data management Key management for and automount of encrypted files, including recovering a master vault key file from an encoded vault key file, storing the vault key file within a previously mounted crypto key management virtual drive so as to provide a secure scratch pad area for temporary storage of the master vault key file. An open and mount module may then invoke a file mounting procedure by providing the vault key file name and a path corresponding to the crypto key management virtual drive to a virtual drive mounting module. The method of passing the vault key file to the file mounting utility module may comprise passing command line arguments equal to a pathname and filename to the file mounting utility.
US09165146B2	Content management device and content management method Provided is a content management device for protecting a content of a provider. A content management device 800 deletes one or more contents shared with and held by a user of another device. The content management device 800 comprises: a sharing unit 801 configured to distribute the contents to the user and thereby share the contents with the user; and a switching unit 802 configured to switch a method of the deletion to another method according to a time elapsed from the distribution.
US09165143B1	Image file generation and loading A method relating generally to loading a boot image is disclosed. In such a method, a header of a boot image file is read by boot code executed by a system-on-chip. It is determined whether the header read has an authentication certificate. If the header has the authentication certificate, authenticity of the header is verified with the first authentication certificate. It is determined whether the header is encrypted. If the header is encrypted, the header is decrypted.

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