最新美国发明专利第2013-06-25期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

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US08472576B2	Jammer canceller for power-line communication An apparatus to process an input signal received via a power line in a power line communication system includes a jammer remover and a jammer detector. The jammer remover removes interference resulting from transmission of electricity and the input signal over the power line from the input signal. The jammer remover generates a jammer-canceled signal using an adaptive filtering procedure. The jammer detector is coupled to the jammer remover to detect the interference.
US08472574B2	Receiver and method of receiving A receiver recovers data from Orthogonal Frequency Division Multiplexed (OFDM) symbols, the OFDM symbols including sub-carrier symbols carrying data symbols and sub-carrier signals carrying pilot symbols. The receiver includes a Fourier transform processor arranged in operation to receive a time domain digital version of the OFDM symbols and to form a frequency domain version of the OFDM symbols, from which the pilot symbol sub-carriers and the data symbol bearing sub-carriers can be recovered, and a detector arranged in operation to recover the data symbols from the data bearing sub-carriers of the OFDM symbols.
US08472573B2	Automatic gain control with out of band blocking signal compensation One embodiment of the present subject matter includes a method of receiving an input signal. The method, in various embodiments, includes detecting a peak of the input signal and detecting an envelope of the input signal. In various embodiments, the peak and envelope are used to identify out-of-band blocking signals and to adjust gain control. The method also includes comparing the peak to a first threshold Tp and comparing the envelope to a second threshold Te. In the method, if the peak is above the first threshold and the envelope is below the second threshold, then ignoring the input signal. If the envelope is above the second threshold, the method includes applying automatic gain control to decode information encoded in the input signal.
US08472571B2	Direct detection of wireless interferers in a communication device for multiple modulation types Direct detection of wireless interferers in a communication device for multiple modulation types. One or more radios implemented within a communication device is/are operative to receive and process wireless communications. A wireless communication signal is processed to extract symbols there from. Various symbols groups are processed in accordance with correlation processing to identify potential interferers (e.g., other communication devices using common portions of frequency spectra). Alternatively, matched filter processing (e.g., using a Barker matched filter in some embodiments) operates on the various symbol groups to identify some potential interferers. Various combinations of correlation processing and matched filter processing may be employed in other instances (e.g., using any of a desired means of comparison, combining, etc.) in considering interferers identified in accordance with each of these two means. Also, re-identification and re-characterization of possible interferers may be performed subsequently to remove or re-admit frequency spectra for use in communications.
US08472563B2	Signal processing apparatus, signal processing method and storage system A signal processing apparatus includes a first baseline wander correcting unit, provided in a processing path in which a predetermined processing is performed on an input signal, which corrects baseline wander by a feedforward and a second baseline wander correcting unit, provided anterior to the first baseline wander unit, which corrects the baseline wander by a feedback control. The first baseline wander correcting unit derives an amount of baseline wander. Further, it calculates a value corresponding to an average value of the amount of derived baseline wander and fine-adjusts a correction amount of baseline. Then it corrects the baseline wander by using the fine-adjusted baseline amount. The second baseline wander correcting unit calculates a value corresponding to an average value of the amount of baseline wander derived by the baseline wander derivation unit and coarse-adjusts a correction amount of baseline, and corrects the baseline wander by using the coarse-adjusted baseline amount. The fine correcting by the first baseline wander correcting unit and the coarse correcting by the second baseline correcting unit ensure efficient correction of baseline wander.
US08472556B2	Amplifier device and predistortion control method This invention relates to an amplifier device and a predistortion control method. The amplifier device comprises a predistortion unit, a predistortion control unit, and an amplifier unit, of which the predistortion control unit controls the predistortion unit in accordance with a signal fed back from the amplifier unit. The predistortion control method comprises determining power of a left side lobe of two side lobes of a frequency spectrum of the signal fed back from the amplifier unit; determining power of a right side lobe of two side lobes of a frequency spectrum of the signal fed back from the amplifier unit; determining a cost function in accordance with the power of the first and right side lobes, and controlling the predistortion unit in accordance with the cost function.
US08472554B2	Signaling of mixture combination sets Systems and methods for conveying and determining modulations schemes employed by co-scheduled users are disclosed. In addition, methods and systems for designing signaling schemes that convey such information are also disclosed. In accordance with one method, an index is received and a table of indices in which the received index denotes a plurality of different sets of modulation schemes is referenced. Further, one or more modulation schemes of at least one co-scheduled user is determined based on the referencing. In addition, data signals are received and are processed by utilizing the one or more modulation schemes.
US08472553B2	Channel estimation for wireless systems without matrix inversion In various embodiments, techniques are provided to determine channel characteristics of various communication systems such as OFDM systems or systems using a plurality of transmit antennas by using various sets of training symbols that produce zero cross-correlation energy. Channel communication can accordingly be simplified as the zero cross-correlation property allows for channel estimation without a matrix inversion.
US08472552B2	Digital linear transmitter architecture A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (ΔΣ) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ΔΣ DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.
US08472551B2	Three phase and polarity encoded serial interface A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.
US08472547B2	Parameterized codebook with subset restrictions for use with precoding MIMO transmissions One aspect of the teachings herein relates to signaling codebook restrictions, to restrict the precoder recommendations being fed back from a remote transceiver, so that precoder selections made by the remote receiver are restricted to permitted subsets of overall precoders within a defined set of overall precoders, or to permitted subsets within larger sets of conversion precoders and tuning precoders, for the case where the overall precoders are represented in factorized form by conversion and tuning precoders. As a non-limiting example, these teachings advantageously provide for precoder restrictions in LTE or LTE-Advanced networks, where ongoing development targets the use of larger, richer sets of precoders, and where the disclosed mechanisms for determining, signaling, and responding to subset restrictions provide significant operational advantages.
US08472546B2	Method of data transmission in multiple antenna system A method of data transmission includes determining the number of layers, generating mapping symbols by mapping modulation symbols for a first codeword and modulation symbols for a second codeword to each layer, and transmitting the mapping symbols through a plurality of antennas. At least one of the first codeword and the second codeword is mapped to at least 3 layers and the number of layers is larger than 3.
US08472545B2	Method and system for managing precoding in a multi-user wireless communications system Operating a wireless communications system that supports multi-user multiple-input multiple-output (MU-MIMO) communications between a base station and multiple mobile stations involves generating a channel estimation, predicting a future channel estimation from the channel estimation, precoding data in response to the predicted future channel estimation, and transmitting the precoded data.
US08472543B2	Method and system for predicting channel quality index (CQI) values for maximum likelihood (ML) detection in a 2×2 multiple input multiple output (MIMO) wireless system Aspects of a method and system for predicting CQI values for ML detection in a 2×2 MIMO system are presented. In one aspect of the system, a CQI value for a MIMO communication system may be computed based on a computed channel realization by reverse mapping the computed channel realization to a corresponding CQI value. Based on the computed CQI value, a coding rate may be selected. The coding rate may be selected from a lookup table, wherein the computed CQI value is utilized as an index to the lookup table. The reverse mapping may utilize a function, which is computed using radial basis function networks. In another aspect of the system, a joint mutual information value may be computed for the MIMO communication system. The joint mutual information value may be computed based on a Shannon mutual information value and a matched filter mutual information value.
US08472542B1	Method, apparatus, and system for signal transmission Embodiments of the present invention provide a method, an apparatus, and a system for signal transmission. The method includes: obtaining, by a base station, a high-power precoding matrix and a low-power precoding matrix according to channel quality information, precoding a corresponding high-power signal stream according to the high-power precoding matrix respectively to obtain a first signal stream, precoding a corresponding low-power signal stream according to the low-power precoding matrix respectively to obtain a second signal stream, superimposing the first signal stream and the second signal stream to obtain one or more superimposed signal streams and transmitting the one or more superimposed signal streams to user terminals; decoding, by the user terminals, the received one or more superimposed signal streams by using receiving matrices, and obtaining signal streams that the user terminals need. The embodiments of the present invention are applicable to signal transmission in a Multiple-Input Multiple-output system.
US08472541B2	Signal processing under attenuated transmission conditions Signal processing under attenuated transmission conditions. Within an orthogonal signal space, the number of orthogonal signals that are used to transmit information from a transmitter to a receiver is reduced and the transmitted power of each of the now remaining orthogonal signals is modified; this may involve increasing the power of all of the remaining orthogonal signals equally or alternatively modifying them individually. The same modulation used before the reduction may also be used afterwards; within communication systems having multiple transmitter-receiver paths, this will ensure that the communication system's throughput and efficiency will remain unchanged even when one (or more) transmitter-receiver paths are highly attenuated. In addition, robust mode operation is provided for ranging and registering of transmitter devices when entering the communication system. In addition, the unused orthogonal signals may be employed to support interference cancellation of those orthogonal signals that are used to transmit information.
US08472538B2	Method and apparatus for delay spread estimation Methods for calculating a delay spread estimate in an OFDM-receiver are described, along with computer program products and electronic apparatuses for performing the methods. The methods comprise determining a position of an FFT-window in relation to one or more OFDM-symbols of a received OFDM-signal and using the determined position to obtain a first OFDM-symbol from the received OFDM-signal. An FFT is applied to the first OFDM-symbol to produce an FFT-output signal. A frequency dependent phase rotation component of the FFT-output signal is determined and removed from the FFT-output signal. A number of zero-crossings of at least one of a real component and an imaginary component of a transfer function of a channel, over which the received OFDM-signal has been transmitted, derived from the FFT-output signal where the frequency dependent phase rotation component has been removed is determined, and a delay spread estimate is calculated based on the determined number of zero-crossings.
US08472536B2	Method of controlling in a wireless communication system having multiple antennas A method of controlling interference in a wireless communication system is disclosed. A method for controlling interference by a transmitter of a wireless communication system with multiple antennas comprises generating a base codebook subset including at least one precoding matrix selected from a base codebook; transmitting a base codebook subset indication, which represents the at least one precoding matrix included in the base codebook subset, to a receiver; and precoding data using the base codebook subset or the base codebook.
US08472531B2	Error concealment for MPEG decoding with personal video recording functionality Error concealment for motion picture expert group (MPEG) decoding with personal video recording functionality. Error concealment of MPEG data may take place within various components within playback, recording, reading and writing data systems. The error concealment may be provided within existing systems whose components may not be capable of accommodating errors within MPEG data. In certain embodiments, the available data that contain no errors is maximized to conceal those portions of the data that do include errors. Various layers may be accommodated while performing error concealment, including the MPEG transport stream layer, the video layer, and the audio layer.
US08472529B2	Estimating complexity of video frames for encoding Complexity for a video frame after a special event is estimated and used for encoding the frame. The complexity for a key frame of a special event is estimated based on its intra activity and a complexity of a previously encoded key frame in the video stream prior to the special event. The complexity for a dependent frame after a special event is estimated based on a motion estimation cost for the dependent frame and a complexity of a previously encoded dependent frame prior to the special event.
US08472528B2	Method for marking a digital image with a digital water mark The invention relates to a method for marking a digital document, especially a digital image, with a digital watermark for the purpose of manipulation recognition while inserting an integrity information and at least one multibit message.
US08472525B2	Method and apparatus for encoding/decoding motion vector Provided are methods and apparatuses for encoding and decoding a motion vector. The method of encoding the motion vector includes: selecting, as a mode of encoding information about a motion vector predictor of the current block, a first mode in which information indicating the motion vector predictor from among at least one motion vector predictor is encoded or a second mode in which information indicating generation of the motion vector predictor based on blocks or pixels included in a previously encoded area adjacent to the current block is encoded; determining the motion vector predictor of the current block according to the selected mode and encoding the information about the motion vector predictor of the current block; and encoding a difference vector between the motion vector of the current block and the motion vector predictor of the current block.
US08472524B2	Motion compensated frame rate conversion with protection against compensation artifacts A system to interpolate between a number of images for the purpose of frame rate conversion may include a motion vector interpolator, a motion compensation module, and a protector. The motion vector interpolator may segment a motion vector into portions based on temporal distances of a target image from each of the number of images. The motion compensation module may generate at least two motion compensated values for a pixel in the target image based on the portions of the motion vector. The protector may choose a motion compensated value for the pixel in the target image when the motion vector is accurate and may choose a pixel value from one of the number of images when the motion vector is not accurate.
US08472518B2	Video-information encoding method and video-information decoding method A video-information encoding apparatus and decoding apparatus with a guarantee of a fixed processing time. By limiting the amount of data to be input into/output from a CABAC encoding unit and decoding unit on a unit-of-encoding basis, such as one picture, slice, macroblock or block, and by encoding uncompressed video data, it is possible to provide a video-information encoding apparatus and decoding apparatus with a guarantee of a fixed processing time. Thereby, an apparatus with a guarantee of the processing time can be mounted.
US08472514B2	Adaptive spectral enhancement and harmonic separation A circuit and method perform adaptive spectral enhancement at a frequency ω1 (also called “fundamental” frequency) on an input signal y which includes electromagnetic interference (EMI) at an unknown frequency, to generate a fundamental-enhanced signal φ1 (or its complement). The fundamental-enhanced signal φ1 (or complement) is thereafter used in a notching circuit (also called “fundamental notching” circuit) to generate a fundamental-notched signal y−φ1. The fundamental-notched signal y−φ1 is itself enhanced to generate a harmonic-enhanced signal φ2 that is used to notch the fundamental-notched signal y−φ1 again, in one or more additional notching circuits that are connected in series with the fundamental notching circuit. The result (“cascaded-harmonic-notched” signal) is relatively free of EMI noise (fundamental and harmonics), and is used as an error signal for an adaptation circuit that in turn identifies the fundamental frequency ω1. Use of a cascaded-harmonic-notched signal as the error signal improves speed of convergence of adaptation.
US08472513B2	TX back channel adaptation algorithm Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e.g., a slicer) as the quantifier input signal to quantify the quantifier input signal to one of multiple digital values. The channel distorted signal may be further adjusted by summing the channel distorted signal with the output of a Decision Feedback Equalizer (DFE) filter to create a DFE corrected signal which then becomes the quantifier input signal. An error signal is determined by finding the difference between the scaled quantifier decision and the quantifier input signal. The pre/post cursor coefficient values that adjust the effects of the pre/post cursor taps of the FIR filter are updated as a function of the error signal and at least two quantifier decision values, and update coefficient values, may be sent over a communications back-channel to the FIR filter.
US08472510B2	Receiver and method for equalizing received signal A receiver includes a discrete Fourier transform unit, a frequency-domain equalizer, an inverse discrete Fourier transform unit, a time-domain equalizer and an output circuit. The discrete Fourier transform unit is utilized for performing a discrete Fourier transform operation upon a received signal to generate a frequency-domain signal. The frequency-domain equalizer is utilized for equalizing the frequency-domain signal to generate an equalized frequency-domain signal. The inverse discrete Fourier transform unit is utilized for performing an inverse discrete Fourier transform operation upon the equalized frequency-domain signal to generate a first equalized time-domain signal. The time-domain equalizer is utilized for equalizing the received signal to generate a second equalized time-domain signal. The output circuit is utilized for generating a third equalized time-domain signal according to the first equalized time-domain signal and the second equalized time-domain signal.
US08472509B2	Multimode multicarrier mode system and method of communication over the same An alternative approach to coping with the ever increasing demand for faster communications hardware is to design modems that are capable of operating its speeds at a higher data rate than a speed required for a single port of the standard communication rate for that modem. Basically, by utilizing a resource manager, that directs the data in and out of the various portions of the modem in an orderly manner, keeping track of which of the ports is being operated at any given point in time, a standard single port modem can be reconfigured, for example, at an over clocked rate, to manipulate the data input and output of a modem.
US08472507B2	Low power radio communication system A method significantly reduces the average power for radio communication in a communication system, such as a system that has applications requiring low communication latency. The method may use a low power radio communication circuit (e.g., a non-heterodyne receiver) to wait for a communication request, taking advantage of the low power consumption of the radio communication circuit. Subsequent to receiving and validating the communication request, the communication system may switch to a more efficient—but higher power—communication circuit. Thus, effective communication is achieved without making undesirable tradeoffs, such as reduced sensitivity.
US08472504B2	Method for optimizing an acquisition of a spread-spectrum signal from a satellite by a mobile receiver A method for optimizing an acquisition phase of a spread-spectrum signal by a mobile receiver includes searching for a trend path having the maximum energy for different frequency assumptions and among all the positive trend paths of frequencies between initial and final instants marking the beginning and the end of a coherent signal integration.
US08472503B2	Method and apparatus for performing frequency synchronization A method and apparatus for performing frequency analysis of sub-epoch correlations to estimate an unknown frequency of a received signal is provided. The method includes forming a sequence of correlation values from a plurality of correlations performed over a period less than a repeating period of a code, and analyzing the sequence of correlation values to estimate the frequency that is used to receive a signal comprising the code.
US08472501B2	Human body communication apparatus for non-contact communications and human body communication method for non-contact communications in the same using frequency selective baseband Provided are a human body communication apparatus for non-contact communications using a frequency-selective baseband and a human body communication method for non-contact communications in the same. The human body communication apparatus may be useful to perform stable communications between users by reducing interference induced from other communication apparatuses without affecting interference between the users since data are transmitted/received between communication apparatuses adjacent to a human body by spreading and despreading the data using only spreading codes of a limited frequency band (frequency-selective baseband) in which an inductive electromagnetic field formed by an antenna shows the most effective characteristics.
US08472497B2	Millimeter wave beaconing with directional antennas A wireless device comprises a code-assignment module configured for assigning Golay codes to be used for spreading, a spreading module configured for spreading data with the Golay codes to produce a signal, wherein the Golay codes are randomly used to spread the data, and a transmitter configured for transmitting the signal. The wireless device may transmit a first beacon signal via a set of quasi-omni beam patterns, and a second beacon signal via a set directional beam patterns. The first beacon signal has a first transmission rate that is higher than the second beacon signal's the transmission rate. Extended Golay codes having zero periodic cross-correlation may be generated from a Golay code and a set of short sequences. A data block transmitted by the wireless device may comprise Golay codes and data portions, wherein every data portion is between two Golay codes and every Golay code is between two data portions.
US08472495B2	Laser device and method of manufacture thereof A laser device includes a substrate, a lower cladding layer on the substrate, an active layer on the lower cladding layer and having a disordered portion spaced from an end face of a resonator of the laser device, an upper cladding layer located on the active layer, and a diffraction grating located in a portion of a layer lying above or below the active layer, with respect to the substrate. The disordered portion intersects a boundary between a diffraction grating section, in which the diffraction grating is located, and a bulk section, in which no diffraction grating is located.
US08472494B2	Semiconductor laser silicon waveguide substrate, and integrated device A semiconductor laser includes: a first portion, made from a silicon-containing material, including an optical waveguide, a first diffraction grating including a phase shift, and a second diffraction grating; a second portion including a light-emitting layer made from a material different from that of the first portion; a laser region including the first diffraction grating, and the optical waveguide and the light-emitting layer provided in a position corresponding to the first diffraction grating; and a mirror region including the second diffraction grating, and the optical waveguide and the light-emitting layer provided in a position corresponding to the second diffraction grating.
US08472493B2	Hybrid laser coupled to a waveguide A method for introducing light into a waveguide formed on the upper surface of a microelectronics substrate, by means of a distributed feedback laser device formed by the association of an SOI-type structure having a portion forming said waveguide, of a stack of III-V semiconductor gain materials partially covering the waveguide, and of an optical grating, wherein the grating step is selected so that the optical power of the laser beam circulates in a loop from the III-V stack to the waveguide.
US08472490B2	Semiconductor optical element and integrated semiconductor optical element A semiconductor optical element and an integrated semiconductor optical element suppressing leakage current flow through a burying layer. A mesa-stripe-shaped laminate structure includes a p-type cladding layer, an active layer, and an n-type cladding layer. A burying layer on a side of the laminated structure includes, a first p-type semiconductor layer, a first n-type semiconductor layer, an Fe-doped semiconductor layer, a second n-type semiconductor layer, a low carrier concentration semiconductor layer, and a second p-type semiconductor layer. The Fe-doped semiconductor layer is not grown on a (111)B surface of the first p-type semiconductor layer and of the first n-type semiconductor layer. The second n-type semiconductor layer is not grown on a (111)B surface of the first p-type semiconductor layer, of the first n-type semiconductor layer, and of the Fe-doped semiconductor layer.
US08472488B2	Algorithm to drive semiconductor laser diode An algorithm to drive a semiconductor laser diode (LD) is disclosed. The algorithm assumes that the modulation current to keep the extinction ratio in constant has temperature dependence represented by an exponential function under the average output power of the LD is kept constant by an auto-power-control (APC). When a tracking error exists and the approximation by an exponential function is turned out in failure, the algorithm adds a correction to the exponential function determined by a difference between a practically measured modulation current and another modulation current calculated from a value determined for a bared LD.
US08472487B2	Photonic integrated circuit having variable length mach-zehnder modulators A photonic integrated circuit (PIC) having multiple Mach-Zehnder (MZ) modulators with different lengths is provided. The modulator lengths are selected to provide optimal performance for each optical path provided on the PIC.
US08472486B1	Seeded raman amplifier for applications in the 1100-1500 nm spectral region A method of generating high-power laser output in the 1100 to 1500 um spectral region having a controllable linewidth. A Raman amplifier comprised of one or more nested pairs of fiber Bragg grating cavities tuned to the 1st, 2nd, . . . N−1st order Stokes wavelengths is seeded with both the desired Nth order Stokes output wavelength and the corresponding zeroth-order Stokes pump wavelength. As the pump wavelength propagates through the apparatus, it is sequentially converted to the 1st, 2nd, . . . N−1st order Stokes wavelengths in the nested fiber Bragg grating cavities. The desired Nth order Stokes output wavelength is then amplified by the N−1st Stokes order as it propagates through the nested fiber Bragg grating cavities. The linewidths of various Stokes orders can be controlled through adjusting resonant bandwidths of the fiber Bragg grating cavities by offsetting, through heating, the reflectivity bandwidths of each pair of cavity gratings.
US08472483B2	Systems, apparatus, methods and computer program products for providing ATSC interoperability Systems, apparatus, methods and computer program products are provided for causing a dataframe to be emitted at an air interface of an antenna. A memory stores a transmission to antenna delay value (TAD). An offset calculator calculates an offset value based on an epoch of a global timebase generator and the transmission to antenna delay value (TAD). An interface controller in communication with the offset calculator communicates a segment synchronization signal and a field synchronization signal based on the offset value.
US08472481B2	DTV transmitting system and method of processing data in DTV transmitting system A DTV transmitting system includes two pre-processors. The first pre-processor codes high-priority enhanced data for forward error correction (FEC) and expands the FEC-coded data. The second pre-processor codes low-priority enhanced data for FEC and expands the FEC-coded low-priority enhanced data. The DTV transmitting system further includes a data formatter generating enhanced data packets including the pre-processed data, a multiplexer multiplexing the enhanced data packets with main data packets, an RS encoder RS-coding the multiplexed data packets, a data interleaves interleaving the RS-coded data packets, and a block processor which codes each block of enhanced data in the interleaved enhanced data packets and bypasses the interleaved main data packets.
US08472479B2	Data transmission method, data transmission apparatus, data reception apparatus, and packet data structure A data transmission apparatus for sequentially transmitting data in units of packets each containing transmission data to the receiving end. The apparatus including a reception unit receiving the transmission data as an input signal, a packet formation unit receiving the transmission data, and forming an uncompressed packet in which predetermined transmission data is stored as uncompressed data, and a compressed packet in which at least a portion of transmission data that follows the predetermined transmission data is compressed and stored as compressed data. The apparatus also including a reference information management unit holding and managing as reference information related to the uncompressed packet, and a transmission unit transmitting the packets formed by the packet formation unit. The packet formation unit forming compressed data to be stored in a compressed packet, based on the transmission data of the uncompressed packet and the reference information.
US08472478B2	Communication system and encoding method having low overhead A communication system processes blocks of input data that include control words and a packet of information words are received. The packet has a start preceded by ones of the control words and an end followed by others of the control words. When the block consists exclusively of information words, a one bit block header having a first sense is appended to the block to form a frame. When the block does not consist exclusively of information words, the block is condensed to accommodate a TYPE word, the TYPE word is generated and inserted into the block and a one bit block header is appended to the block to form the frame. When the block does not consist exclusively of information words the one bit block header has a second sense, opposite to the first sense. Use of a one bit block header reduces overhead. Forward error correction is also utilized.
US08472477B2	SAF synchronization layer packet structure and server system therefor Provided is a Simple Aggregation Format (SAF) synchronization packet structure including a SAF synchronization packet header and a SAF synchronization packet payload and multiplexing diverse element streams which include a scene description elementary stream. The SAF synchronization packet header includes time information related to an access unit included in the SAF synchronization packet payload, and the SAF synchronization packet payload includes header information on the access unit and payload information indicating the access unit. Since the present invention can multiplex diverse elementary streams effectively and simply into one data stream, synchronized data transmission is possible. Since the present invention accommodates a synchronization layer packet of the MPEG-4 system, it can be easily integrated with the MPEG-4 system and utilize the advantage of the MPEG-4 synchronization layer packet such as the concept of an access unit or a degradation priority.
US08472475B2	System and method for retransmission and fragmentation in a communication network A system and method for fragmented transmission and retransmission in a communication network. According to various embodiments of the disclosed method and apparatus, a method for fragmenting a protocol data unit for transmission from a source node in a communication network includes the operations of determining a plurality of subpackets in which to send the protocol data unit having one or more service data units; creating a data unit header for a first of the plurality of subpackets; identifying one or more fragments for inclusion in the first of the plurality of subpackets; creating an aggregation subheader for the first of the plurality of subpackets, wherein the aggregation subheader comprises data identifying the one or more fragments; and concatenating the data unit header, one or more fragments and aggregation subheader to build the first of the plurality of subpackets.
US08472472B2	Wireless terminal and method of data communication therein A wireless terminal and a method of data communication between such wireless terminals includes a first wireless terminal determining whether a second wireless terminal is located within a preset distance, the first wireless terminal determining whether the first wireless terminal is tilted at more than a preset slope and the first wireless terminal transmitting a preset packet of data to the second wireless terminal where it determines that the second wireless terminal is located within the preset distance from the first wireless terminal and the first wireless terminal is tilted at more than the preset slope.
US08472471B2	Method and apparatus for transmitting control information The present invention relates to a wireless communication system. More particularly, the present invention relates to a method and apparatus for transmitting uplink control information in the event that a plurality of cells is constructed, wherein the method comprises the following steps: receiving a PDCCH and/or a PDSCH; generating acknowledgement information on the PDCCH and/or PDSCH; and, if acknowledgement information transmission timing and channel state information transmission timing collide with each other, dropping the channel state information and transmitting only the acknowledgement information, or transmitting the acknowledgement information and the channel state information together in accordance with a predetermined condition.
US08472468B2	Communication apparatus, communication method, and communication system A physical frame is constructed, the physical frame including a medium access control super-frame payload which in turn includes a plurality of medium access control frames. With respect to the constructed physical frame, virtual carrier sense information is set in the plurality of medium access control frame so that a result of carrier sense is identical to another by virtual carrier sense based on the plurality of medium access control frames in the medium access control super-frame payload. The physical frame in which the virtual carrier sense information has been set is transmitted to a destined communication apparatus.
US08472467B2	Wireless device and methods for opportunistic scheduling in a contention-based wireless network Embodiments of a wireless device and method for channel access are generally described herein. In some embodiments, the wireless device is configured to measure channel quality and set a backoff delay for channel access based on the channel quality. Shorter backoff delays are set for better channel quality and longer backoff delays are set for poorer channel quality.
US08472465B2	Method and an apparatus for determining the radio frame structure of time division duplex system A method for determining the radio frame structure of a Time Division Duplex system is disclosed, which comprises: configuring, by the network side, the radio frame structure used for service transmission as containing two half-frames each of 5 ms, wherein each half-frame consists of eight service time slots of 0.5 ms and one special time slot field of 1 ms, two consecutive service time slots form a subframe of which the length is 1 ms, and the special time slot field contains a DwPTS, a GP and an UpPTS; determining the lengths of the DwPTS, the GP and the UpPTS in the special time slot field according to the requirements of the coverage range, and determining the radio frame structure used for service transmission. By reconfiguring the radio frame structure, the invention can flexibly support different coverage ranges, enhance the flexibility of satisfying different service requirements, and implement the coexistence of two types of TDD systems.
US08472463B1	Devices, systems, and/or methods for managing wireless networks Certain exemplary embodiments comprise a method that can comprise wirelessly transmitting a thin Beacon message from an Access Point in a wireless local area network cell. The thin Beacon message can be transmitted during a superframe subsequent to a Beacon message. The thin Beacon message can be transmitted at a predetermined thin Beacon time interval. The time period between consecutive Beacon and/or thin Beacon messages can be divided further into a thin CFP and a thin CP.
US08472457B2	Method and apparatus for queuing variable size data packets in a communication system Variable size data packets are queued in a communication system by generating from each data packet a record portion of predetermined fixed size containing information about each packet and storing only data portions of the packets in independent memory locations in a first memory. The record portions are only stored in one or more managed queues in a second memory having fixed size memory locations equal in size to the size of the record portions. The first memory is larger than the second memory; and the memory locations in the first memory are arranged in blocks having a plurality of different sizes. The memory locations are allocated to the data portions according to the size of the data portions.
US08472455B2	System and method for traversing a treelet-composed hierarchical structure A method for performing node traversal operations of a treelet-composed hierarchical structure includes allocating a queue for each of the plurality of treelets, each queue operable to store ray-states entering a respective one of the treelets. The method additionally includes determining that a ray-state exits a first treelet of the hierarchical structure and enters a second treelet of the hierarchical structure. The method further includes forwarding the ray-state entering the second treelet to a processing element for processing therein, wherein the queue allocated to store ray-states entering the second treelet is bypassed.
US08472454B2	Relay-server arranged to carry out communications between communication terminals on different LANS A technique of carrying out communications between communication terminals on different LANs while realizing reductions in the burden of account control and suppression in load on a server includes first and second relay servers on first and second LANs issuing a registration request to a SIP-server, respectively. A first communication terminal on the first LAN issues a registration request to the first relay server while a second communication terminal on the second LAN issues a registration request to the second relay server. The first and second relay servers exchange account information about the registered communication terminals with each other. When the first communication terminal generates communication data addressed to the second communication terminal, the first relay server selects the second relay server as a relay based on the exchanged account information to relay the communication data. Then, the second relay server relays the communication data to the second communication terminal.
US08472453B2	Terminal capabilities set exchange between heterogeneous endpoints In one embodiment, a method includes receiving at a protocol translator a first message from a first endpoint to a second endpoint. The first message includes a list of media capabilities of the first endpoint. The method also includes transmitting from the protocol translator a second message to the second endpoint including a media capabilities request header and receiving at the protocol translator a response message from the second endpoint. The response message includes a response header including a list of the media capabilities of the second endpoint.
US08472452B2	Lookup cluster complex A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.
US08472447B2	IP multicast snooping and routing with multi-chassis link aggregation Aggregation Switches connected via a virtual fabric link (VFL) are each active and able to perform at least limited IP multicast snooping. The resulting IP multicast snooping information is maintained internally within each Aggregation Switch and shared substantially in real-time therebetween via the VFL.
US08472444B2	Method and apparatus for handling traffic in a data communication network A method and apparatus for offloading data traffic routing from one NI (network interface) to another. The NI receives data traffic, and that portion of the data traffic that must be L3 routed is passed to the CPU of the NI though a token bucket meter or equivalent metering device that selectively designates a portion of the routing traffic to another NI for routing. The portion of the traffic designated corresponds to the capacity of the CPU and offloading a portion of the data traffic helps to reduce the number of packets that are discarded when a CPU is overloaded. The threshold for determining when and in what quantity the data traffic should be offloaded is either statically or dynamically set, and in the latter case may be updated automatically when traffic levels and, in some implementations, other considerations require.
US08472443B2	Port grouping for association with virtual interfaces In one embodiment, an apparatus includes a port channel manager for receiving information identifying switches connected to a group of physical ports at a network device and creating subgroups each comprising the physical ports connected to one of the switches. The apparatus further includes a virtual interface agent for assigning a virtual interface connecting a virtual switch to a virtual machine, to one of the subgroups. Traffic received from the virtual machine on the virtual interface is transmitted to one of the switches on one of the physical ports in the assigned subgroup. A method for grouping ports for association with virtual interfaces is also disclosed.
US08472441B2	Multicast communication apparatus and method for receiving and forwarding data via a network among a plurality of nodes A multicast communication apparatus for receiving and forwarding data via a network among a plurality of nodes. The apparatus has: a receiving section that receives the data from a source node; a routing table that stores route information of the data including the source node and a destination node of the data; a forwarding section that forwards the data to a next destination node according to the route information of the routing table; a hop length table that includes a hopping number of the data forwarded from the source node to the next destination node; and a mixing processing section that performs mixing processing of data received from another node. The mixing processing section performs the mixing processing according to the hopping number in the hop length table.
US08472435B2	System and method of wireless device activity messaging A method and system of reachability indication between a wireless device and at least one push server, the method comprising the steps of: sending device status information from the wireless device to the at least one push server; and receiving the status information at the at least one push server; wherein the at least one push server is enabled to selectively start and stop serving the wireless device on the basis of the status information. The method further comprises sending status information to a packet data serving node that stores a list of push servers associated with a wireless device, and having the packet data serving node forward the status information to the push server. The system and method further includes selectively starting and stopping the serving of the wireless device by the push server during a voice call.
US08472430B2	VoIP packet prioritization A method and system for prioritizing data packets relating to a conversation over a VoIP communication channel is provided. An individual client or a service provider may specify priority information corresponding to incoming conversations. When several calling clients send data packets to one called client, the predefine priority information of the called client may be exchanged as part of contextual information. Based on the predefined priority information, priority levels are assigned to the received data packets. Subsequently, an existing communication channel may be terminated, interrupted, altered, and/or suspended in order to transmit data packets with higher priority than other data packets. A new communication channel may be established for a two-way communication, or a one-way communication between two clients. In this manner, the highest priority conversation among several incoming conversations, such as an emergency broadcast message or communication, can be ensured to reach to a client without a delay.
US08472427B1	Packet exchange arbitration for coexisting radios The present specification describes techniques for packet exchange arbitration. In some embodiments, a request is maintained to an arbiter at least until a packet exchange has been communicated and/or at least until a time-sensitive packet is communicated. In some other embodiments, a grant of a request is delayed at least until the communication of an isochronous packet.
US08472426B2	Real-time wireless communication method for guaranteeing quality of service in wireless personal area network Provided is a real-time wireless communication method for guaranteeing quality of service in a wireless personal area network (WPAN). When real-time data transmitted in a time slot of a current superframe has an error, a terminal, which was designated as a coordinator from among a plurality of terminals in a WPAN, allocates a time slot for retransmitting the real-time data to a next superframe and retransmits the real-time data in the allocated time slot of the next superframe. Therefore, quality of a real-time communication service in a WPAN can be guaranteed.
US08472425B2	System, method and apparatus for an efficient information broadcast in a multi-carrier wireless network Embodiments of an apparatus, system and method are described for a base station. Notification from a mobile station in a network may be received. A multi-carrier advertisement with a base station multi-carrier configuration may be sent. The base station multi-carrier configuration may include at least one carrier index associated with a carrier frequency operated on by the base station. Other embodiments are described and claimed.
US08472422B2	Method and system for avoiding hanging PDP contexts A method and system for avoiding hanging Packet Data Protocol (PDP) contexts in a General Packet Radio Service (GPRS) network. A time-out period is included in a request message to create a PDP context. The request message is transmitted from a first GPRS Support Node (GSN) to a second GSN. The second GSN receives the request message and transmits a response message to the first GSN. If the second GSN is unable to create the PDP context within the time-out period, the response message informs the first GSN that creation of the PDP context has been aborted. A Network Service Access Point Identifier (NSAPI) may be included in the response message so that the first GSN may request the second GSN to delete the request for creating the PDP context after a N3-T3 timeout of the first GSN has expired.
US08472421B2	Method and system for avoiding hanging PDP contexts A method and system for avoiding hanging Packet Data Protocol (PDP) contexts in a General Packet Radio Service (GPRS) network. A time-out period is included in a request message to create a PDP context. The request message is transmitted from a first GPRS Support Node (GSN) to a second GSN. The second GSN receives the request message and transmits a response message to the first GSN. If the second GSN is unable to create the PDP context within the time-out period, the response message informs the first GSN that creation of the PDP context has been aborted. A Network Service Access Point Identifier (NSAPI) may be included in the response message so that the first GSN may request the second GSN to delete the request for creating the PDP context after a N3-T3 timeout of the first GSN has expired.
US08472413B2	Protocol for wireless networks A wireless transmission method includes providing a commanding node and a plurality of sub-networks. Each of the sub-networks includes at least one responding node. Time slots are assigned to the sub-networks such that time slots assigned to each sub-network are interleaved in time with time slots assigned to at least one other sub-network. Within each time slot, at least one acknowledgement packet is transmitted from the at least one responding node before a command packet is sent from the commanding node within the time slot. Each at least one acknowledgement packet indicates whether or not a most recent command packet from the commanding node was correctly received by the responding node.
US08472411B2	Methods and systems for multi-user detection in CDMA-based common channels and computer program products thereof Methods for multi-user detection in a CDMA-based channel for use in a base station receiver are provided. Signals, each including a CDMA code, are received. Correlation operations are performed on CDMA codes of received signals respectively to obtain corresponding first correlation values. CDMA codes are divided into first and second code groups according to a threshold and corresponding first correlation values. An interference cancellation procedure is performed on received signals to remove signals corresponding to first code group therefrom and to obtain a removed signal. Correlation operations are performed on CDMA codes of removed signal to obtain corresponding second correlation values. Each first correlation value is subtracted from a corresponding second correlation value and compared with a threshold to generate a comparison result. Whether CDMA codes within first code group are correct are determined according to comparison results, wherein the threshold is dynamically adjusted according to comparison results.
US08472405B2	System and method for handling over a user equipment (UE) from a packet-switched network to a circuit-switched network A system and method for handing over a User Equipment (UE) from a Packet-Switched network to a Circuit-Switched network. A Generic Access Network Controller (GANC) receives a registration message from the UE with a temporary UE identity (GUTI) and uses the GUTI to identify a Mobility Management Entity (MME) controlling a connection with the UE. The GANC informs the MME whether the UE is registered to use Circuit Switched over Long Term Evolution (CS over LTE) signaling using a Generic Access Network (GAN). If so, the MME selectively directs to the GANC, handover signaling relating to the handover of the UE. If not, the MME selectively directs the handover signaling to a Mobile Switching Center (MSC). If the UE changes to a new MME, the new MME is informed whether the UE is registered to use CS over LTE using the GAN.
US08472404B2	Mobile communication method and radio base station A mobile communication method according to the present invention includes the steps of: (A) calculating, at the radio base station (eNB1), an estimated neighbor radio base station parameter, on a basis of load information acquired from a neighbor radio base station (eNB2), the estimated neighbor radio base station parameter being supposed to be used in the neighbor radio base station (eNB2); and (B) notifying, from the radio base station to (eNB1) the neighbor radio base station (eNB2), the estimated neighbor radio base station parameter.
US08472401B2	Relay station and method of operating relay station in multi-hop communication system A replay station and a method of operating the relay station in a multi-hop communication system are provided. A method of operating a relay station of a multi-hop communication system includes monitoring a delay of the relay station, determining whether the monitored delay exceeds a predetermined threshold, and controlling the relay station to be handed over to another upper relay station that is different from a connecting upper relay station.
US08472399B2	Ranging channel structures and methods To facilitate ranging between mobile terminals and a base station in a wireless communication network employing orthogonal frequency division multiplexing (OFDM) for uplink data communications, a periodic ranging channel for use by a mobile terminal is defined. The channel specifies a plurality N of blocks of sub-carrier frequencies of an OFDM frequency band which are non-contiguous within the OFDM frequency band. The channel also specifies a time slot within an OFDM subframe which spans one or more OFDM symbol periods. A ranging transmission is periodically sent as a spread signal across the specified N blocks of sub-carrier frequencies within the specified time slot. The duration of the ranging transmission may be less than a duration of the OFDM subframe. A notional grid of tiles representing time and frequency resources associated with the subframe may facilitate channel definition. A similar approach may be used to define an initial access channel for initial access transmissions.
US08472392B2	Access point for providing WLAN virtualization, WLAN virtualization system and method of providing access to wireless communication network The present invention relates to a WLAN virtualization system which is capable of efficiently separating a Basic Service Set (BSS) into a plurality of virtual BSSs in a Time Division Multiplexing (TDM) manner. The WLAN virtualization system includes an Access Point (AP) for providing a plurality of vBSSs, and a plurality of stations corresponding to the vBSSs provided by the AP. Each of the vBSSs is operated on a superframe basis, the superframe being scheduled by a beacon frame transmitted from the AP. The superframe includes the beacon frame, one contention-free period, and one contention period. The CPs of the vBSSs include intervals which do not overlap each other. The vBSSs can be classified into any groups designated by a service provider based on certain criteria such as physical layer, QoS, security level, or network access authority, and times can be allocated to superframes at different rates or frequencies.
US08472387B2	Point to point radio bearers for a broadcasting service A method for establishing a connection between user equipment (UE) and an associated network includes receiving at the UE a notification indicating either a start of a broadcast service or an availability of the broadcast service, such that the notification comprises an identifier which identifies the broadcast service. The method further includes receiving at the UE a setup message which establishes a point-to-point radio bearer between the UE and the network, such that the setup message comprises the identifier which is used to identify that the radio bearer carriers the broadcast service.
US08472383B1	Group management in multiuser communications A method in a receiving device that receives data from a plurality of transmitting devices via a shared wireless communication channel includes selecting a group of two or more transmitting devices from the plurality of transmitting devices for simultaneous transmission of respective data to the receiving device, so that each transmitting device in the group of transmitting devices transmits the respective data to the receiving device at a nominal power level of the transmitting device, and receiving the respective data from each in the group of transmitting devices simultaneously via the shared wireless communication channel.
US08472377B2	Management of session control signaling for multicast/broadcast services The invention relates to a method for distributing control signaling for session control of a multicast or broadcast service within a mobile communication network. Furthermore the invention also provides a base station, mobile terminal and communication system to perform the proposed method. In order to reduce the number of signaling connections for the service, the invention proposes to avoid the initial distribution of session control signaling in the entire mobile communications network or service area. Rather than providing service related control signaling connections upon session start, the control signaling connections are set up in response to service requests of the mobile terminals requesting the service. According to one further aspect, the mobile terminals send the service requests based on service announcements available at the mobile terminals, i.e. in contrast to conventional implementations, the mobile terminals do not await a notification of the access network on the availability of the service within the cell.
US08472376B2	Handling multiple user interfaces in an IP multimedia subsystem A method of operating an Internet Protocol Multimedia Subsystem (IMS) network having a plurality of user interfaces. A terminal agent is interposed between a plurality of Session Initiation Protocol (SIP) User Agents and a Serving Call/Session Control Function (S-CSCF) of the IMS network. The terminal agent registers its contact address with the S-CSCF on behalf of the plurality of SIP User Agents and emulates a single SIP User Agent to the S-CSCF.
US08472371B1	Roaming support for wireless access subscriber over fixed IP access networks The claimed subject matter provides for systems and methods that facilitate a transfer of a portion of a service-level policy agreement associated with a home wireless access network to a fixed internet protocol (IP) access network. An authentication component can authenticate a subscription of a multi-mode device across different network architectures. A policy component can provide at least a portion of a service-level policy agreement to enable or disable services or policies associated with a multi-mode device at the fixed IP access network on a per session basis.
US08472368B2	Method and arrangements in a communication system Methods and arrangements in a network node and mobile terminal, respectively, in a wireless communication system supporting aggregation of component carriers. The method in a network node involves, when resources on at least two downlink component carriers are being assigned to a mobile terminal at the same time, allocating (908) control information bits not related to power control in a bit field, which is normally used for power control in a message on a physical downlink control channel associated with one of said at least two downlink component carriers. The method in a mobile terminal involves, using control information bits not related to power control obtained from a bit field, which is normally used for power control in a message on a physical downlink control channel associated with one of said at least two downlink component carriers, for locating information related to downlink or uplink transmissions.
US08472365B2	Method and system for acknowledgement and retransmission of multicast data in wireless local area networks A method and apparatus are described including multicasting a plurality of data units and multicasting a request for acknowledging receipt of the plurality of data units, receiving signals responsive to the request. Also described are a method and apparatus including receiving a multicast request to acknowledge receipt of data, determining if a response to the request is required, determining status of the data, preparing the response based on the determining acts and transmitting the response.
US08472364B2	Evolved multimedia broadcast/multicast service base station, user equipment and methods thereof The present invention provides a user equipment (UE), comprising: first receiving means for receiving on a first carrier information for determining a second carrier and a Multimedia Broadcast/Multicast Service (MBMS) notification; second receiving means for receiving Radio Bearer (RB) configuration information and MBMS scheduling information on the second carrier determined from the information; and control means for generating an MBMS scheduling template based on the received RB configuration information and MBMS scheduling information, wherein, the second receiving means receives MBMS data based on the MBMS scheduling template.
US08472361B2	Method of generating repeated data package transmission Repeated data packets are generated from a first Bluetooth enabled device to a second Bluetooth enabled device to facilitate radio direction finding of the first device by the second device. A communication connection is established between the first and second devices in accordance with a Bluetooth protocol stack and in response to receiving at the second device a data packet transmitted by the first device the second device transmits an NACK data packet to the first device, whereby the first device is cause to retransmit said data packet, and causing the second device to process at least one of the transmitted data packet and the retransmitted data packet in accordance with a radio direction finding algorithm. The communication connection preferably comprises a remote name request.
US08472360B2	Mobile communication method and mobile station A mobile communication according to the present invention includes a step A of causing the mobile station to judge whether or not the mobile station is allowed to go into a standby mode in a cell corresponding to a predetermined pilot channel when the mobile station detects a predetermined operation made by a user and a step B of causing the mobile station to enter the standby in the cell when the mobile station judges that the mobile station is allowed to be in the standby mode in the cell.
US08472358B2	Method and apparatus in a telecommunication system Method and apparatus in a communication unit employing a wireless TDD or half duplex FDD transmission arrangement when communicating with a data sending party, for scheduling feedback reports for data blocks in received receive (RX) sub-frames, in transmit (TX) sub-frames available for transmission. An obtaining unit in the communication unit receives allocation parameters for the connection where the number of required feedback reports is greater than the number of allowed feedback reports. A scheduling unit in the communication unit then schedules feedback reports in available TX sub-frames according to a predetermined spreading rule also known by the data sending party, dictating that the feedback reports are spread out or distributed evenly over the available TX sub-frames. In this way, the number of feedback reports in a TX sub-frame can be reduced.
US08472356B2	System and method for managing communication links A system and method for managing a communication link between a consumer electronic device adapted for two-way, wireless communications with at least one peripheral. The communication link is managed using a controller that is associated with the consumer electronic device that functions to assign communication slots to the peripheral to facilitate communications between the peripheral and the consumer electronic device.
US08472354B2	Method and system for providing custom call waiting An approach for providing custom call waiting with media messaging is disclosed. A request is received from a first voice station to establish a voice communication session with a called party station. A detection is made that the called party station is currently in communication with a second voice station. A content designated from a call-waiting condition for presentation to a caller is retrieved. The content to either the first voice station or the second voice station is retrieved in response to a user input from the called party device.
US08472350B2	Bank aware multi-bit trie Embodiments of the invention include a method performed by a bank aware mtrie control module for distributing a plurality of mtrie levels across a plurality of memory banks. The bank aware mtrie control module identifies the plurality of memory banks present and identifies one or more mtrie blocks in one or more mtrie levels, each mtrie block is an array of mtrie nodes associated with an mtrie level. The bank aware mtrie control module stores each mtrie block in one of the plurality of memory banks, all mtrie nodes in a given mtrie block are stored in the same memory bank. For each subsequent mtrie level, the bank aware mtrie control module ensures that each of the mtrie blocks in that mtrie level is stored in one of the plurality of memory banks other than the memory bank storing mtrie blocks of an immediately previous mtrie level.
US08472349B1	Determining mean opinion scores (MOS) for variable bit rate audio streams Systems and methods for determining mean opinion scores (MOS) for variable bit rate (VBR) audio streams transmitted over VoIP networks are described. In an embodiment, a method may include monitoring a communication over a network and detecting portions of the communication including packets having a different packet payload sizes. The method may also include deriving bit rates corresponding to those portions. The method may then include calculating MOS values for each portion based on the derived bit rates, and calculating an overall MOS value for the communication based upon each individual MOS value averaged according to a distribution of packets having the different packet payload sizes.
US08472343B2	Method and apparatus for use in a network A decentralised method is disclosed of deciding a common configuration parameter in a network. The network comprises at least one node designated to perform the method. In the method, a designated node makes a local decision relating to the configuration parameter in dependence upon information relating to its local operating environment (M3). The designated node sends its local decision to other designated nodes, if any, and receives corresponding local decisions made by other designated nodes, if any (M4). Following such receipt, the designated node makes a common decision relating to the configuration parameter in dependence upon its local decision and the received local decisions (M5). The common decision is made using a decision algorithm common to the designated nodes.
US08472340B1	Network interface with autonegotiation and cable length measurement A network device including a transceiver module, an autonegotiation module, and a cable length estimator. The transceiver module is configured to communicate with a second network device via a wire medium. The autonegotiation module is configured to i) detect a selector field of the second network device, ii) transmit, in response to the selector field of the second network device matching a first predetermined value, a first base page to the second network device via the transceiver module, and iii) transmit, in response to the selector field of the second network device matching a second predetermined value, a second base page to the second network device via the transceiver module. The cable length estimator is configured to, in response to the selector field of the second network device matching the second predetermined value, determine a physical length of the wire medium.
US08472338B2	Efficient transmission of data to multiple network nodes An improved method, system, and computer program product for efficient transmission of data to multiple network nodes is disclosed. A method for transmitting a data block over a network from a first sending node to a first set of recipient nodes, comprises, in the first sending node, a) dividing the first set of recipient nodes into a subset of selected nodes, selected according to scoring criteria associated with each recipient node, and a subset of unselected nodes, b) assigning at least one of the unselected nodes to at least one selected node according to scoring criteria associated with the respective selected nodes, c) transmitting to each selected node a packet including the data block and a list of the nodes assigned to the selected node.
US08472337B2	Variation of up link resources in a cellular system The invention discloses a method (300) for a cellular system (100) with a first node (110) which controls traffic to and from users (120) in a cell (130). Traffic between the users (120) and the first node (110) comprises user resources and control resources, with uplink traffic, comprising channels sent in data frames (200). Each data frame comprises a number of resource blocks (1, 2, 3, 4), and each uplink channel is allotted an amount of resource blocks in each data frame. At least part of the traffic between the users and the first node is divided (305) into first and second groups, and a cell's usage of the first and second group is monitored (310). The amount of resource blocks which is allotted to one of the uplink channels in a cell (130) is varied (315) depending on the cell's usage of these two groups.
US08472334B2	Method for self organizing network operation The present invention relates to wireless cellular telecommunication networks and, in particular, to control and management of self organizing wireless cellular telecommunication network. A method for network planning and frequency optimization in LTE networks by determining the optimal base station configuration parameters, comprises a base station initialization, an initial base station configuration, an iterative measurement procedure, an optimization process, a verification of operation, and a periodical maintenance procedure.
US08472326B2	System and method for monitoring interlayer devices and optimizing network performance A system and method is disclosed for monitoring and optimizing interlayer network performance that includes determining at the data link layer of a network device whether there is degradation in transmission performance over at least one link in the network using network performance information data and if so, the system and method communicates from data link layer of the network device to a second layer of the network device information regarding the degradation in transmission performance associated with the at least one link in the network. The system and method optimizes, at the second layer of the network device, network performance to overcome the degradation in the transmission performance associated with the at least one link in the network.
US08472324B1	Managing route selection in a communication network A system, method and computer-readable medium for the determination of a transit route by a computing system distinct from a router are provided. By pre-determining routes for content within a routing environment, routers on the network forward communications according to the pre-determined route. Specifically, by distributing at least some of the route calculations functionality and/or routing entries storage/maintenance from router components (e.g., edge routers), the processing and memory requirements of such router components within the routing environment can be reduced. In one aspect, the distribution of at least a portion of the routing calculation function and routing entry storage/maintenance within a routing environment facilitates the use of lower-capability, cheaper commodity-based routers.
US08472321B2	Method for managing data transfer services on a network The present invention relates to a method for managing traffic transfer services on a network. One of the present methods determines priority reference ensuring to retrieve bandwidth greater than necessary bandwidth, if current available bandwidth is not sufficient for a new connection, and selected selects a combination of in-service connections whose priority is not higher than the determined priority reference such that the selected combination is able to return the necessary bandwidth and the number of connections in the selected combination is smallest as well. The connections pertaining to the selected combination are pre-empted to permit access of the new connection to the network.
US08472320B2	Jitter buffer control A method of controlling an adaptable jitter buffer in accordance with the present invention detects a context description of data handled by the adaptable jitter buffer. Thereafter it is determined whether the detected context description is equal to a predetermined context description. If not, jitter buffer adaptation proceeds as normal. Otherwise it is determined whether the current target buffer depth is too low for the detected context description. If not, the target buffer depth is frozen to the current value. Otherwise it is increased and frozen at a higher value that is compatible with the detected context description.
US08472316B2	Utilization of data links Control of a data packet buffer in a communication system and a data packet queue in a transmission link are shown. The queue stores a plurality of received data packets that are intended for transmission over a wireless interface. Selected packets are discarded from the queue without the selected packets having been transmitted. A packet is selected for discarding depending on at least the length of time the packet has been stored in the queue. The discarding of a selected packet is effectuated on condition that at least a predetermined time period has elapsed since a previous discarding of a packet has taken place. Such a solution is advantageous in that, for varying transmission bandwidth conditions in the transmission link, it is possible to achieve good link utilization and throughput, while at the same time enabling a low end-to-end delay for packets transmitted in the link.
US08472314B2	Network-based dedicated backup service A system and method for providing alternate dedicated connections are described. A primary dedicated connection may be configured to connect a first network and a second network, and a second dedicated network-based connection, which may include a point-to-point protocol (PPP)/layer 2 tunneling protocol (L2TP) tunnel, may be configured to automatically connect the first network and the second network when the primary dedicated connection fails.
US08472312B1	Stacked network switch using resilient packet ring communication protocol A stacked switch using a resilient packet ring protocol comprises a plurality of switch modules coupled to one another in a ring topology and each having a plurality of external terminals for interfacing with external devices. Each switch module includes an external interface for communicating with the external terminals, the external interface configured to communicate using a communication protocol; and an internal interface for communicating with other switches, the internal interface using a resilient packet ring (RPR) protocol. Advantages of the invention include the ability to flexibly create a high performance stacked switch with advanced features.
US08472311B2	Systems, methods, and computer readable media for providing instantaneous failover of packet processing elements in a network Systems, methods, and computer program products for providing instantaneous failover of packet processing elements in a network are disclosed. According to one aspect, the subject matter described herein includes a system for providing instantaneous failover of packet processing elements in a network. The system includes a plurality of packet processing elements for processing packets in a network and a packet distribution module for maintaining information about the operating status of each element of the plurality of packet processing elements, for maintaining information about packet flows being processed by the packet processing elements, and, for each packet flow, assigning one of the plurality of packet processing elements as the primary element for the packet flow and assigning another of the plurality of packet processing elements as the secondary element for the packet flow. The packet distribution module routing packets to the packet processing elements according to the operating status of the packet processing elements that have been assigned to the packet flow with which the packets are associated.
US08472305B2	Network coding-based data processing method and system The present disclosure provides a network coding-based data processing method and system. The method includes: receiving modulated data packets, the modulated data packets including: a first data packet modulated by using a first constellation map, a second data packet modulated by using a second constellation map, and a third data packet modulated by using a third constellation map; where the first constellation map, the second constellation map, and the third constellation map are capable of minimizing the bit error rate of received signals, and a bit stream transmitted in the third data packet is an Exclusive-OR result of a bit stream transmitted in the first data packet and a bit stream transmitted in the second data packet, that is, c=a⊕b; and obtaining original transmitted data from the received data packets.
US08472304B2	Carrier allocation and time sharing for OFDMA/TDMA networks A method allocates bandwidth to channels in an orthogonal frequency division multiple access and time division multiple access (TDMA) network. The network includes a master device (master) communicating with a set of slave devices (slaves). The master defines a set Ψm of logical indices ν of a set of N physical subcarriers for a set of M data streams to be allocated to a set of Nd logical data subcarriers according to Ψm={ν\|ν=iM+m, i=0,1,2, . . . , d−1}, where d=Nd/M. The set of N data subcarriers is mapped to the set of Nd logical subcarriers according to the logical indices, and the data subcarriers are allocated to the logical subcarriers.
US08472302B2	Recording device and optical oscillator device A recording device that records information in an optical recording medium includes: a self excited oscillation semiconductor laser including a saturable absorber section to apply a bias voltage and a gain section to inject a gain current, and also emitting a laser light to record the information in the optical recording medium; a reference signal generation unit generating a master clock signal and also supplying an injection signal synchronized with the master clock signal to the gain section of the self excited oscillation semiconductor laser; and a recording signal generation unit generating a recording signal based upon the master clock signal and also applying the recording signal to the saturable absorber section of the self excited oscillation semiconductor laser as the bias voltage.
US08472299B2	Optical element and optical pickup device using the same An optical element which has optical steps each providing a phase difference to transmitted light and has low light amount loss and a high efficiency is provided. The optical element includes a symmetry axis, a plurality of optically functional surfaces which are ring-shaped regions around the symmetry axis, and a plurality of wall regions connecting the optically functional surfaces to each other. The optically functional surfaces and the wall regions constitute the optical steps. On a cross-section taken by, as a cutting plane, a plane including the symmetry axis, the contour line of each wall region is substantially parallel to a light beam which is incident on the optically functional surface on the outer side and passes near the wall region. The maximum value of the angle between the symmetry axis and the light beam passing near the wall region is equal to or more than 25 degrees.
US08472290B2	Apparatus and method identifying disc type A method and apparatus identifying a type of a recordable disc according to whether a land pre-pit (LPP) is formed on the disc. The apparatus includes an RF (radio frequency) amplifier amplifying light reflected by the disc to a predetermined value; an LPP signal detector detecting an LPP (Land Pre-Pit) signal from output signals of the RF amplifier; and a system controller identifying a type of the disc according to whether the LPP signal is detected by the LPP signal detector. Since a disc type is discriminated and operational conditions of a disc drive are adequately set during an early stage of a disc driving period, a lead-in time of a disc can be reduced.
US08472281B2	Noise suppression by adaptive speed regulation of towed marine geophysical streamer A method for towing marine geophysical sensor streamers in a body of water includes moving a towing vessel at a selected speed along the surface of the body of water. At least one geophysical sensor streamer is towed by the vessel at a selected depth in the water. A velocity of the streamer in the water is measured at at least one position along the streamer. The selected speed of the towing vessel is adjusted if the measured velocity exceeds a selected threshold.
US08472280B2	Alternate page by page programming scheme An alternate page by page scheme for the multi-state programming of data into a non-volatile memory is presented. Pages of data are written a page at a time onto word lines of the memory. After all of the pages of data are written to a first level of resolution onto one word line, the memory goes back to the adjacent word line (on which all of the pages of data have previously been written the first level of resolution) and refines the accuracy with which the data had been written on this preceding word line. This can reduce the effects on the data of capacitive coupling between the word lines.
US08472270B2	Apparatus and method for testing one-time-programmable memory An apparatus and method of testing one-time-programmable memory limits current through a one-time-programmable memory to less than a threshold amplitude, where the memory has a fuse configured to blow upon receipt of a signal having the threshold amplitude. The method also uses blow signal assertion circuitry to attempt to assert a blow signal to the fuse. When not defective, blow signal assertion circuitry is configured to permit the low amplitude signal to flow through the fuse when the fuse is not blown and the blow signal is asserted. The method then produces an output signal having a success value if the limited current flows through the fuse, and a failure value if the current does not flow through the fuse.
US08472269B2	Redundancy control circuit and memory device including the same A redundancy control circuit includes an address fuse circuit and a first circuit. The address fuse circuit includes a plurality of first fuses. Each of the first fuses is configured to be cut based on a result of comparing a number of bits of a defective input address having a first logic level with a number of bits of the defective input address having a second logic level. The address fuse circuit is configured to generate a first address using the first fuses based on a cutting operation that depends on the result of comparing. The first circuit is configured to output either the first address or a second address that is an inverted address of the first address as a repair address, wherein a logic level of each of bits of the repair address is the same as that of the defective input address.
US08472267B2	Late-select, address-dependent sense amplifier Sense amplifiers in a memory may be activated and deactivated. In one embodiment, a processor may include a memory. The memory may include a number of sense amplifiers. Based on a late arriving address bit of an address used to access data from the memory, a sense amplifier may be activated while another sense amplifier may be deactivated.
US08472264B2	Semiconductor memory device A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a shape of a matrix along a plurality of parallel bit lines and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier which detects a voltage or a current of the bit line and decides the read data from each of the memory cells; a clamping transistor connected between the sense amplifier and the bit lines to determine a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer.
US08472263B2	Mode-register reading controller and semiconductor memory device A semiconductor memory device may include a mode-register reading controller and a mode register. The mode-register reading controller generates a control signal for loading data into an input/output line in response to an enable signal, during a mode-register reading operation. The control signal is generated in response to a mode-register read signal when there is a reset command is input. The mode register loads the data into the input/output line in response to the control signal.
US08472261B2	Reading devices for memory arrays A reading device for a memory array is provided. The memory array comprises memory cell columns. The reading device comprises first sensing amplifier groups, a second sensing amplifier group, and an output unit. Each first sensing amplifier groups selectively generates a first sensing output signal. The second sensing amplifier group generates a second sensing output signal. The output unit selectively outputs one of the second sensing output signal and the first sensing output signals according to a page address signal. In a reading operation period, the reading device reads data from a column group to the first sensing amplifier groups. In the reading operation period, when the page address signal indicates an initial input address, initial address data read from the specific column set corresponding to the initial input address among the column group is transmitted to the second sensing amplifier group to generate the second sensing output signal.
US08472260B2	Semiconductor memory apparatus and method for discharging wordline thereof Various embodiments of a semiconductor apparatus having a discharge technology are disclosed. In one exemplary embodiment, the semiconductor apparatus may include a plurality of lines in which a selected line is driven by a first control voltage and an unselected line is driven by a second control voltage with a level lower than the first control voltage. The apparatus may also include a discharge control unit configured to form a discharge current path between a discharge node of the selected line and a common discharge node of the unselected line and induce a predetermined voltage difference between the discharge node and the common discharge node; and a common discharge unit configured to discharge current flowing through the discharge current path.
US08472259B2	Non-volatile semiconductor memory device A non-volatile semiconductor memory device according to an embodiment includes a data write portion, the data write portion includes, in a write loop, a first operation mode of sequentially performing a program operation and a first verify operation, and a second operation mode of sequentially performing the program operation, the first verify operation, and a second verify operation, and the data write portion includes, in the first verify operation, precharging a bit-line connected to the first memory cell and a bit-line connected to a second memory cell adjacent to the first memory cell and verifying data of the first memory cell, then in the second verify operation, when the write to the second memory cell is completed, without precharging the bit-line connected to the second memory cell, precharging the bit-line connected to the first memory cell and verifying data of the first memory cell.
US08472258B2	Semiconductor nonvolatile memory device An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
US08472257B2	Nonvolatile memory and method for improved programming with reduced verify A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
US08472253B2	Semiconductor memory device A semiconductor memory device includes: a memory-cell array provided between a first region and a second region, and including a plurality of memory cells; a first row decoder and a second row decoder; a first power line provided in the first region; a second power line provided in the first region; a first power-supply circuit configured to supply the first voltage to the first power line and to the second power line; a first switching circuit; and a second switching circuit. In a write operation, the first switching circuit connects the first power line and the first power-supply circuit to each other whereas the second switching circuit disconnects the second power line and the first power-supply circuit from each other.
US08472251B2	Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (greater than 80%) between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.
US08472246B2	Method of programming a multi-bit per cell non-volatile memory A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data.
US08472243B2	Storage apparatus Disclosed herein is a storage apparatus including a cell array configured to include storage devices arranged to form an array. Each of the storage device has: a storage layer for storing information as the state of magnetization of a magnetic substance; a fixed-magnetization layer having a fixed magnetization direction; and a tunnel insulation layer sandwiched between the storage layer and the fixed-magnetization layer. In an operation to write information on the storage layer, a write current is generated to flow in the layer-stacking direction of the storage layer and the fixed-magnetization layer in order to change the direction of the magnetization of the storage layer. The cell array is divided into a plurality of cell blocks. The thermal stability of the storage layer of any particular one of the storage devices has a value peculiar to the cell block including the particular storage device.
US08472242B2	Magnetoresistive effect memory A magnetoresistive effect memory of an aspect of the present invention including a magnetoresistive effect element including a first magnetic layer having an invariable magnetization direction, a second magnetic layer having a variable magnetization direction, and an interlayer provided between the first magnetic layer and the second magnetic layer, and a reading circuit which passes a pulse-shaped read current through the magnetoresistive effect element to read data stored in the magnetoresistive effect element, wherein the pulse width of the read current is shorter than a period from an initial state to a cooperative coherent precession movement of magnetizations included in the second magnetic layer.
US08472239B2	Nanowire mesh FET with multiple threshold voltages Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
US08472238B2	Variable resistance nonvolatile storage device with oxygen-deficient oxide layer and asymmetric substrate bias effect The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt
US08472232B2	Self-identifying stacked die semiconductor components A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.
US08472229B2	Array-based integrated circuit with reduced proximity effects An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.
US08472228B2	Array-based integrated circuit with reduced proximity effects An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.
US08472224B2	Adjustable write bins for multi-level analog memories Selecting bins in a memory by receiving a target cost for performing writes at an analog memory that is capable of storing a range of values. Possible bins that may be created in the range of values and a cost associated with each possible bin are determined. Each possible bin includes one or more of the values. A group of bins are identified, the group of bins are among the possible bins with associated costs that are within a threshold of the target cost. A maximum number of bins are selected from the group of bins that have non-overlapping values. The selected bins are stored along with the values of the selected bins utilized to encode and decode contents of the analog memory.
US08472221B1	High voltage rectifier using low voltage CMOS process transistors A high voltage full wave rectifier circuit having complementary serially connected low voltage MOSFET stacks provides high voltage rectifier capability. The MOSFET stacks are coupled to a pair of cross coupled MOSFETs that provide a full wave rectified output voltage. The state of the MOSFETs in the MOSFET stacks is controlled by resistors coupled between the rectifier output and a time varying input signal. The resistance values of the resistors are selected to maintain operation of the stacked MOSFETs below their breakdown voltages. A pair of diodes is connected between ground and the MOSFET stacks. A plurality of diode connected MOSFETs are connected between the rectifier output and the resistors to establish bias voltages on the gates of the MOSFETs in the MOSFET stacks to control operation of the rectifier during input voltage cycles. A voltage doubler circuit is also described where low voltage MOSFETs are utilized in a novel configuration to provide high voltage doubling capability.
US08472215B2	Grid-tie inverter for interconnecting AC voltage to electric power grid According to one embodiment, a grid-tie inverter includes: a inverter performing pulse width modulation for a DC voltage; a first capacitor circuit connected to an input side of the inverter so as to form a neutral point; a second capacitor circuit connected to an output side of the inverter so as to form a neutral point; a common mode current bypass channel formed by connecting the neutral points of the first capacitor circuit and the second capacitor circuit; a grounded capacitor provided between the bypass channel and a ground; a first common mode choke coil unit including a common mode choke coil at least one of between the first capacitor circuit and the inverter and between the inverter and the second capacitor circuit; and an output filter converting a pulse width-modulated voltage outputted from the inverter into a sine AC voltage.
US08472213B2	Extending pulse width modulation phase offset Extending pulse width modulation phase offset when generating phase shifted groups of pulse width modulation (PWM) signals is accomplished with a separate phase counter that is independent of the time-base counters used in traditional PWM generation circuits and that is prevented from being retriggered until an existing duty cycle has completed. This is accomplished with a phase offset counter, a phase comparator and a circuit that is triggered via a master time base for overall synchronization of the multi-phase PWM signal generation.
US08472212B2	Resonant converting device, and control module and method for controlling a resonant converter A method for controlling operation of a resonant converter is to be implemented by a control module that generates a drive signal for controlling a power switch of the resonant converter to thereby control an output voltage and an output current provided by the resonant converter to a load. The method includes: (A) configuring the control module to determine if the load is operating in a first mode or a second mode; (B) configuring the control module to generate the drive signal according to the output voltage when the control module determines that the load is operating in the first mode; and (C) configuring the control module to generate the drive signal according to the output current when the control module determines that the load is operating in the second mode.
US08472209B2	Device having anti-demolition functions A device having anti-demolition functions includes a housing and an electronic apparatus. The housing includes a first cover and a second cover. The first cover has a first connection part disposed thereon. The electronic apparatus is disposed in the housing and is fixed on the second cover. The electronic apparatus includes a first block, a second block and a join part. The second block has a second connection part disposed thereon, wherein second connection part fastens first connection part when first cover is engaged with second cover. The join part connects first block and second block, and has at least one circuit wire passing there through, wherein when the first cover and the second cover are separated from each other, the join part is separated from at least one of the first block and the second block, such that the at least one circuit wire forms an open circuited status.
US08472204B2	Advanced mezzanine card for hosting a PMC or XMC A card assembly is disclosed comprising a carrier host card, an interposer printed wiring board (PWB) situated between the carrier host card and a hosted card, wherein the carrier host card and the interposer printed wiring board (PWB) are configured to have a space there-between. The card assembly further comprising a customized front panel including a first cutout for the carrier host card and a second cutout for said hosted card.
US08472202B1	System for connecting electrical cables to a printed circuit board An electrical communication system includes a printed circuit board (PCB) having first and second ground plates and a plurality of signal vias and a plurality of ground vias extending between and through the first and second ground plates. Each of the plurality of signal vias are electrically connected to a respective conductive trace on a surface of the PCB. Cables connect to the PCB at a right angle, with a connector attached to an opposite side of the PCB. Each cable has two signal wires and a ground wire extending therefrom. The two signal wires define a differential pair. The signal wires are symmetrical with respect to the ground wire. Each of the signal wires electrically connects to a respective one of the plurality of signal vias. The ground wire connects to one of the plurality of ground vias. The cables are offset with respect to one another on the first and second ground plates and within the PCB.
US08472200B2	Locking mechanism for a housing to hold a plug-in module Locking mechanism (1) and a housing (2) equipped with one such locking mechanism, to hold a plug-in module (5), and a modular system (3) which comprises a housing and a plug-in module, wherein the locking mechanism (1) has an actuating mechanism (4) for unlocking of the plug-in module. The invention is characterized in that the actuating mechanism (4) is connected to a lifting mechanism (6) in order to lift a plug-in module (5) held in the housing (2) when unlocking.
US08472198B2	Data center with cable management structure A data center includes a housing and a number of server units arranged in the housing. Each server unit includes a server module and a cable management member. The first ends of a number of cables are connected to the back panel of the server module. The cable management member includes a bottom plate, a front plate, and two side plates. A number of connectors are set on the front plate. The second ends of the cables are connected to the connectors. The cable management member is fixed to one side of the server module. The cables are received in a space formed between the bottom plate and the server module. The cable management member includes a first clipping portion and a second clipping portion formed at opposite sides. The housing includes a number of rails, which can slide between the first and second clipping portions.
US08472196B2	Power module A power module includes a first heat sink, first and second power chips, a thermo-conductive insulating layer, a lead frame and a molding compound. The first heat sink has a first area and a second area. The first power chip is disposed in the first area. The thermo-conductive insulating layer is disposed in the second area. The second power chip is disposed on the heat sink through the thermo-conductive insulating layer. The lead frame is electrically connected to at least one of the first and second power chips. The molding compound covers the first and second power chips, the thermo-conductive insulating layer and a portion of the lead frame. The first heat sink is electrically connected to at least one of the first and second power chips. Because the first power chip is not disposed on the first heat sink through the thermo-conductive insulating layer, the cost can be reduced.
US08472189B2	Fireproof enclosure An enclosure comprises a thermal barrier (42) for protecting a heat sensitive component (40). The thermal barrier includes at least one endothermic layer (48, 54, 58) that includes water gelled with a thickening agent, absorbed onto a cellulose-comprising fabric or paper. The endothermic layer is sandwiched between layers comprising metal foil or sheet (49, 52, 56).
US08472187B2	Display apparatus A display apparatus of present invention includes a tabular display unit having a display screen for displaying an image and a support section constituted by a bent stick member. One end of the support section is inserted into a hole arranged on a back surface of the display unit from a lower side, and the support section is arranged between a placement surface and a lower end of the display unit, whereby the support section supports the display unit from the lower side.
US08472186B2	Tablet computer case and associated methods Tablet computer cases and associated methods are disclosed and described. In one embodiment, a tablet computer case may include a first panel configured to releasably engage and hold a tablet computer of a predetermined size and shape, a second panel having a keyboard a hinge rotatably attaching the two panels, and a communication connector that allows the keyboard to communicate with the tablet computer.
US08472185B2	Package and assembly having a computer housing, an article, and the package An assembly includes an article, and a computer housing including left and right sidewalls cooperatively defining an accommodating space and an opening for communicating the accommodating space with an external environment, and a positioning member provided on one of the sidewalls. Each sidewall includes a slide rail. A package is mounted removably in the accommodating space via the opening, is connected slidably to the slide rails of the sidewalls, and is positioned within the accommodating space through the positioning member. The package includes two interconnected cover parts cooperatively defining a receiving space for receiving the article and a communicating hole for communicating the receiving space with the external environment, and a handgrip to mount removably the package in the accommodating space. Each cover part includes a stop member abutting against the article to prevent escape of the article from the receiving space via the communicating hole.
US08472184B2	Industrial computer capable of dust prevention and resistant to vibration A dust-free and anti-vibration industrial computer. The industrial computer has a case sealed from the outside, a heat diffusion fin assembly mounted on the outer surface of the case, and a circulation pipe for allowing a heat generating component and at least a heat diffusion fin to be communicated with each other, or a heat pipe for transferring heat between the heat generating component and the heat diffusion fin. The heat generating component can be cooled in a state in which dust is prevented from being produced within the case.
US08472183B1	Rack-mounted computer system with front-facing power supply unit A data center includes a row of one or more racks. Computer systems are mounted in the racks. A cold aisle is on a first side of the rack row and a hot aisle is on the second side of the rack row. An air handling system moves air from the cold aisle on the first side of the row of racks through computer systems in at least one of the racks and exhausts air from the computer systems into the hot aisle on the second side of the row of racks. The computer systems include input/output connectors, power input connectors, and power supply air inlets on the first side (cold-aisle side) of the row. One or more power rack power distribution units are provided on the first side (cold-aisle side) of the row.
US08472182B2	Apparatus and method for facilitating dissipation of heat from a liquid-cooled electronics rack Apparatus and method are provided for facilitating cooling of one or more components of an electronics rack. The apparatus includes a liquid-cooled structure associated with the electronic component(s) to be cooled, and a liquid-to-air heat exchanger coupled in fluid communication with the liquid-cooled structure via a coolant loop to receive coolant from and supply coolant to the liquid-cooled structure. The heat exchanger is disposed external to the electronics rack within a cool air plenum of the data center containing the rack, and the plenum is coupled to a cool air source providing cooled air to the data center. Cooled air of the cool air plenum passes across the heat exchanger and cools coolant passing through the heat exchanger, which dissipates heat from the coolant passing therethrough to the cool air passing across the heat exchanger to facilitate liquid cooling of the electronic component(s) associated with the liquid-cooled structure.
US08472179B1	Actuation mechanism for vertical insertion, retention and extraction of an electronic component An electronic device includes a bay for a removable component with a vertical axis of insertion and removal. The component is inserted upwardly in the electronic device with aid of an actuation mechanism. For example, the actuation mechanism may include a lever and a horizontal support member sized to hold the bottom side of the component. Rotation of the lever translates the support member in the vertical direction to smoothly lift the component into a seated position in which connectors in the component and the electronic device are coupled. The actuation mechanism may include a latch to hold the component securely in the seated position. Rotation of the lever in the opposite direction lowers the support member. The actuation mechanism may include one or more tabs on the horizontal support member or elsewhere that pull the component during removal to overcome the unmating force of the connectors.
US08472176B2	Integrated power adapter system for portable computers An integrated power adapter system for a portable computer may include a power adapter for providing power to the portable computer, extractable elements for connection to an external socket, and a dissipation grid for reducing the temperature of the cover screen. The power adapter system may be a slim power adapter system being removable from and integrated with the cover screen of the portable computer.
US08472175B2	Folding electronic device with swivel function A folding electronic device includes a first case, a second case, and a hinge element. The hinge element includes a shaft, a swing member, a toothed gear, and a spring clip. When the first case opens up at an about 180 degree angle relative to the second case from a folded position, the central projection of a spring clip engages with one tooth of the toothed gear, the first case may rotate relative to the second case under the horizontal direction or the vertical direction from any angle between about 0 and 180 degrees.
US08472173B2	Electric apparatus An electric apparatus is provided in which it is possible to connect a signal line to multiple key panels which are rotatably attached to a main body chassis. The electric apparatus has multiple first hinges and multiple second hinges. The first hinge rotatably attaches a panel to the second hinge. Further, the second hinges are rotatably attached to a main body of the electric apparatus. The multiple second hinges are rotatably connected.
US08472169B2	Cable clamp, circuit board and computer enclosure using the cable clamp A cable clamp mounted to a circuit board to bind cables, the cable clamp includes a clamp member to clamp the cables, and a fixable member extending from the clamp member to be fixed to the circuit board.
US08472168B2	Package structure A package structure for packaging a portable electronic device is provided. The package structure includes a base portion, a supporting portion and a connector. The supporting portion is connected to the base portion. The supporting portion includes a first fixing element and a second fixing element, wherein when the package structure is in a supporting state, the supporting portion is folded and standing upright, the first fixing element is detachably connected to the second fixing element, and the portable electronic device is supported by the supporting portion. The connector is disposed on the supporting portion, wherein the portable electronic device is connected to the connector.
US08472167B2	High current clamping connector There is disclosed an apparatus including a chassis configured to accept a plurality of blades. The chassis may contain a backplane assembly may include a backplane bus bar configured to provide electrical power to the plurality of blades and a power supply configured to deliver electrical power through a power delivery bus bar. A clamp may be disposed to force the power delivery bus bar into electrical contact with the backplane bus bar.
US08472164B2	Stacking type electrochemical cell having quasi-bipolar structure Provided is a stacking type quasi-bipolar electrochemical cell having a reliable, easy-to-manufacture, and simple structure. The electrochemical cell includes: an electrode including a current collector, and positive and negative active material layers disposed at both sides of the current collector and spaced apart from each other with a current collector extension part being located therebetween, wherein a polarity of the electrode is used as an opposite polarity in a neighboring cell; an electrode assembly formed by stacking a plurality of electrodes including the electrode; and an electric connection part connecting some of the electrodes of the electrode assembly which are included in the same series, the electric connection part connecting the some electrodes in parallel.
US08472163B2	Negative electrode current collector for heterogeneous electrochemical capacitor and method of manufacture thereof A current collector for use in an electric double layer electrochemical capacitor having a sulfuric acid electrolyte. The current collector uses a conducting carbon (e.g., graphite foil) basis with p-type conductivity. A protective film covers at least a portion of the graphite foil basis. The protective film is comprised of a conducting composite material made with a conducting carbon and a conducting organic polymer with p-type conductivity. The protective film is grown on the current collector basis such that it preferably fills the pores of the current collector basis. A lug portion of the current collector basis may be protected with an insulating polymer material.
US08472162B2	Multilayered electrochemical energy storage device and method of manufacture thereof An energy storage device comprising one or more cells, wherein each cell is defined by a pair of electrodes and a separator placed therebetween, wherein each cell is bounded by two current collectors, the geometric form and size of said separator being identical to the form and size of said current collectors, and wherein in each cell, one electrode is printed on one of said two current collectors and the other electrode is printed on one face of the separator, the two electrodes being electronically insulated by means of said separator, and wherein the peripheral region of the separator, which surrounds the electrode printed thereon, is sealed.
US08472159B2	Method to charge toner for electrophotography using carbon nanotubes or other nanostructures In accordance with the invention, there are systems and methods to impart an electrostatic charge to particles. An exemplary method can include providing a plurality of particles to be charged and providing a plurality of nanostructures disposed over a first electrode array, the first electrode array including a plurality of electrodes spaced apart. The method can also include providing a multi-phase voltage source operatively coupled to the first electrode array and applying a multi-phase voltage to the first electrode array to create a traveling electric field between each electrode of the first electrode array, thereby causing electron emission from the plurality of nanostructures and forming a plurality of charged particles. The method can further include transporting each of the plurality of charged particles using the traveling electric field onto a surface.
US08472158B2	Protective device A protective device including a substrate, a conductive section and a first auxiliary medium is provided. The conductive section is supported by the substrate, wherein the conductive section comprises a metal element electrically connected between first and second electrodes. The metal element serves as a sacrificial structure having a melting point lower than that of the first and second electrodes. The first auxiliary medium is disposed between the metal element and the substrate, wherein the first auxiliary medium has a melting point lower than that of the metal element. The first auxiliary medium facilitates breaking of the metal element upon melting.
US08472156B2	Method and device for supervising the sensitivity of a protection function A method and a device for supervising the sensitivity of a protection function in an electrical power system including a metering device for measuring values of a feature, said protection function being configured to initialize an action based on a test value and a threshold value for the feature, wherein said test value is either a measured value or derived from the said measured values, the device includes a computing unit configured to receive the test values and, repeatedly during the operation of the protection function, to calculate a mean value and a deviation of the test values, to determine the probability of a false action based on the calculated mean value, the threshold value and the calculated deviation, and to indicate that the sensitivity is too high when the probability of a false action exceeds a first limit value for the probability of a false action.
US08472148B2	Self-aligned double flux guided TMR sensor A magnetic head according to one embodiment includes an array of sensor structures formed on a common substrate. Each sensor structure further comprises: a magnetic tunnel junction sensor spaced from a media-facing surface of the head; and a flux guide between the media-facing surface of the head and the sensor, the flux guide guiding magnetic flux from a magnetic medium adjacent the media-facing surface to the sensor. Additional systems and methods are also presented.
US08472146B2	Current perpendicular magnetoresistive sensor with a dummy shield for capacitance balancing A perpendicular magnetic read head having a balanced capacitive coupling with the substrate. The read head includes a magnetoresistive sensor with first and second magnetic, electrically conductive shields separated from a substrate by a layer of non-magnetic, electrically insulating material. A dummy magnetic shield is formed on the non-magnetic electrically insulating layer and is electrically connected with the second magnetic, electrically conductive shield. The dummy shield is formed to have a capacitive coupling with the substrate that matches the capacitive coupling of the first magnetic, electrically conductive shield with the substrate.
US08472145B2	Arm coil assembly, arm flexible cable assembly and disk drive unit with the same An arm coil assembly includes a drive arm having at least two grounding pins formed on a mounting region thereof and a voice coil fixed on the tailing end of the drive arm for controlling the drive arm. The grounding pins are provided for electrically connecting with a flexible printed cable assembly by extending through at least two mounting holes formed on the flexible printed cable assembly. Each grounding pin has a slot formed thereon to clamp the flexible printed cable assembly. The arm coil assembly of the present invention having grounding pins with slot structure to clamp the flexible printed cable assembly which is mounted on the drive arm to form an arm flexible cable assembly, thus, the flexible printed cable assembly can be pre-mounted onto the arm coil assembly without using any additional fixtures or tools, therefore simplifying the mounting process and reducing the manufacturing cost thereof. The invention also discloses an arm flexible cable assembly and a disk drive unit including the same.
US08472134B2	Air bearing surface overcoat with soft intermediate film, and methods of producing the same In one embodiment, a magnetic head includes at least one magnetic head element for reading from and/or writing to a magnetic medium, the element having an air bearing surface (ABS) facing toward a magnetic medium, an adhesive film including silicon nitride above the ABS having a characteristic of being formed under a water vapor partial pressure, and a protective film above the adhesive film, the protective film including carbon. Also, in another embodiment, a method includes forming an ABS of a magnetic head, the ABS being a surface of the magnetic head which is closest to a magnetic medium when in use, forming an adhesive film above the ABS of the magnetic head, the adhesive film being formed under a water vapor partial pressure, and forming a protective film above the adhesive film, the protective film including carbon.
US08472131B1	Disk drive including a filter component with coarse and fine sections There is provided a disk drive including a disk drive base, a disk rotatably coupled to the disk drive base, and a spindle motor attached to the disk drive base and configured to support the disk for rotating the disk with respect to the disk drive base. The disk drive further includes a filter component. The filter component includes a filter housing coupled to the disk drive base, and a filter element disposed within the filter housing for filtering disk rotation induced airflow. The filter element includes a coarse section and a fine section. The coarse section has a porosity greater than a porosity of the fine section.
US08472130B2	Track-dependent data randomization mitigating false VFO detection A method for randomizing data to mitigate false VFO detection is described. In one embodiment, such a method includes simultaneously receiving multiple input data streams. Each input data stream is associated with a different track on a magnetic tape medium. The input data streams are simultaneously scrambled to produce multiple randomized data streams. The input data streams are scrambled such that different bit patterns are produced in the randomized data streams even where corresponding bit patterns in the input data streams are identical. The randomized data streams are simultaneously written to their associated data tracks on the magnetic tape medium.
US08472129B1	Forearm engaging telescoping microscope with claw The forearm engaging telescoping microscope with claw is a hand tool that provides for magnification of an object resting on a ground surface while an end user is standing in an erect posture, and which does not have to bend over to view the magnified object. A telescoping hand tool includes means for engaging a forearm at a first end whereas a microscope in perpendicular arrangement extends from a second end. The telescoping hand tool can adjust in overall length to accommodate different sizes as needed of the end user. A claw is provided adjacent to the magnifying lens, and extends in an opposing direction. The forearm engaging means is comprised of a handle that is grabbed by a hand of the end user and arm braces that engage around said forearm.
US08472126B2	Zoom lens A zoom lens includes, in the order from the object-side to the image-side thereof, a first lens group of a negative refractive power, a second lens group of a positive refractive power, and a third lens group of a positive refractive power. The first lens group includes, in the order from the object-side to the image-side thereof, a first lens of negative refractive power, and a second lens of positive refractive power. The second lens group includes, in the order from the object-side to the image-side thereof, a third lens of positive refractive power, a fourth lens of negative refractive power, and a fifth lens of negative refractive power.
US08472119B1	Image waveguide having a bend An optical apparatus having a waveguide that includes a bend, a first segment and a second segment operatively coupled at the bend, the first and second segments each including a pair of reflective surfaces being substantially parallel and opposing each other. An in-coupling region receives light into the first segment of the waveguide, and an out-coupling region allows the light to exit the second segment of the waveguide. A light filtering region disposed near the bend between the first segment of the waveguide and the second segment of the waveguide will selectively filter light transmitted from the first segment of the waveguide to the second segment of the waveguide.
US08472117B2	Lens array and 3-dimensional display apparatus including the same A lens array according to an exemplary embodiment of the present invention includes: a first upper lattice plate including a plurality of first upper lattices; a first lower lattice plate including a plurality of first lower lattices; a first membrane disposed between the first upper lattice plate and the first lower lattice plate; a transparent liquid filled in the first lower lattice plate; and a hydraulic pressure controller positioned in the first lower lattice plate, wherein the first upper lattice and the first lower lattice are engaged with each other, thereby forming a plurality of first regions.
US08472116B2	Apparatus for combining light from a plurality of coherent light sources An apparatus for combining coherent light from a plurality of coherent light sources is provided. The apparatus includes a plurality of light guides, each including: a first mirror at an entrance face, including an aperture for admitting light therein from a respective one of the plurality of coherent light sources; and a second partially-reflective mirror at an exit face. The apparatus further includes a second stage light guide, for combining emitted light exiting the plurality of light guides, including: a second stage entrance face and a second stage exit face, the second stage entrance face for receiving the emitted light from each the exit face of the plurality of light guides; and a third mirror, at the second stage exit face, for reflecting the light back towards the second mirror, the third mirror including an exit aperture for the light to exit the second stage light guide.
US08472115B2	Anistropic dye layer, coordination polymer for anistropic dye layer and polarization element, and polarization control film, polarization control element, multi-layer polarization control element, ellipse polarization plate, light emission element, and method for controlling polarization properties employing the anistropic dye layer An anisotropic dye layer containing a coordination polymer is disclosed. The a polarization control film containing an oriented dichroic dye in which light absorption spectrum of a molecule is reversibly changed by charge passing are disclosed.
US08472099B2	Scanning optical apparatus A scanning optical apparatus includes: a light source; a first optical element configured to convert light emitted from the light source into a beam of light; a second optical element configured to convert the beam of light having passed through the first optical element into a linear image extending in a main scanning direction; a deflecting mirror configured to deflect the beam of light having passed through the second optical element in the main scanning direction; and a third optical element configured to convert the beam of light having been deflected by the deflecting mirror into a spot-like image and focus it on a target surface to be scanned. The third optical element is a single lens having a pair of opposite lens surfaces, and each of the pair of lens surfaces is aspheric in a main scanning plane to satisfy the formula:  ( 1 - S k ⁡ ( y 1 , y 2 ) f t ⁡ ( y 1 , y 2 ) ) · h ⁡ ( y 1 , y 2 )  < r e ⁢ min 2 .
US08472089B2	Rotor imaging system and method with variable-rate pixel clock The technology disclosed relates to handling varying pixel overlaps long a first axis as a scanning head sweeps a curved path that is not parallel to the first axis. In particular, we teach use of a variable frequency pixel clock to produce equally spaced pixels along the first axis as a rotor arm scans a curved path that is not parallel to the first axis. The pixel clock has a varying frequency that varies approximately sinusoidally with the position of the scanning head relative to the first axis.
US08472087B2	Office machine with both platform-type scanning mode and feeder-type scanning mode An office machine with both platform-type scanning mode and feeder-type scanning mode. The office machine includes a reciprocally movable scanning module arranged on upper side of the office machine for scanning documents placed on a platform. The office machine further includes a sheet-feeding path positioned under a bed. The sheet-feeding path has at least one position where the documents passing through the sheet-feeding path can be scanned by the scanning module.
US08472085B2	Image processing device, additional information providing method, and computer-readable storage medium An image processing device provides a detection result of additional information added to each of pages which constitute a document. The image processing device includes an input part which inputs image data of each page of a document. A detection part generates a page detection result of additional information added to the image data, the page detection result being generated on a page basis and indicating a result of detection of the additional information for each page. A detection result output part outputs an outline result indicating an outline of the page detection results for the respective pages on a document basis, together with an identifier of the document associated with the outline result.
US08472084B2	Image processing apparatus optimizing information and control method thereof An image processing apparatus and a control method thereof. Information of image processing parameters, such as halftoning, edge emphasis, color correction, and gamma correction, is inserted into the document to be printed in the form of the watermark during the printing work. Thus, when the user wants to copy the printed document, the information of the image processing parameters used for printing the document is optimized suitable for the copy by detecting the watermark inserted into the printed document, thereby improving the quality of the copy. The method includes inserting first information of image processing parameters, which are used to print the document, into the document when printing the document, and optimizing second information of image processing parameters to be used for copying the document using the first information of image processing parameters inserted into the document when copying the document.
US08472081B2	Color screen sets A method for designing a screen set for color halftoning includes selecting a screen set that includes at least two screens. The screens are applied to a uniform color image so as to form a set of corresponding colorant halftones. The colorant halftones are superposed to form a color halftone. A spatial frequency spectrum of the color halftone is calculated. Maxima of the spatial frequency spectrum that occur at two effective frequencies are identified, the two effective frequencies being located in two adjacent quadrants of a complex spatial frequency space. A magnitude of each effective frequency is compared with a predetermined frequency magnitude. The screen set is accepted for future application for color halftoning only if both effective frequency magnitudes are greater than the predetermined frequency magnitude. Relating computer program product and data processing system are also disclosed.
US08472078B2	Image processing apparatus for determining whether a region based on a combined internal region is a table region An image processing apparatus includes a region segmentation unit configured to perform region segmentation based on a black pixel connected region in a document image, a selection unit configured to select a processing target region from regions segmented by the region segmentation unit, an internal region combining unit configured to generate a combined internal region by combining internal regions which are included in the regions selected by the selection unit and satisfy a predetermined condition, a table region determination unit configured to determine whether a region based on the combined internal region obtained by the internal region combining unit is a table region, and an extraction unit configured to extract the region determined by the table region determination unit as a table region.
US08472077B2	Image processing method for fast fill-in of a figure and computer readable medium therefor An image processing method includes steps of acquiring a first two-dimensional parallelogram image, creating a second two-dimensional parallelogram image by dividing the first image into two figures by a line along a predetermined scanning direction and joining together respective sides of the two figures corresponding to an upper base and a lower base of the first image, calculating a value w representing a numerical number of pixels constituting an upper base or a lower base of the second image and a value h representing a numerical number of pixels in a height direction of the second image, securing a w×h two-dimensional memory space, writing pixel values on each scanning line of the second image, sequentially in a scanning order, onto a corresponding scanning line of the two-dimensional memory space, and storing supplementary information of the second image in association with the two-dimensional memory space.
US08472074B2	Printing apparatus and printing method, and program therefor having first form data and second form data The objective of the present invention is to provide a printing apparatus that can avoid difficulty in the folding of a print sheet that has been printed using clear toner. In order to achieve this objective of the present invention, a printing apparatus includes a storage unit for storing data which indicates positions to be printed by using a transparent color material on a print sheet according to a registration instruction and a synthesizing unit for synthesizing image which is printed by using non-transparent color material based on contents data and image which is printed by using transparent color material based on form data stored in the storage unit on a print sheet according to a synthesis instruction.
US08472072B2	Method for improving printing quality and related printing system A method for improving printing quality is disclosed. The method includes an application device transmitting an original image including a plurality of printing pixels to a driving device, the driving device setting the plurality of printing pixels as a plurality of first printing dots, the driving device detecting an edge of the original image, the driving device setting a plurality of second printing dots according to a plurality of neighboring pixels corresponding to the edge, and the driving device generating an image to be printed according to the plurality of first printing dots and the plurality of second printing dots.
US08472070B2	Image forming apparatus An image forming apparatus includes a first determination section which determines at least one of a position and a density of a mark; a correction section which corrects at least one of an image forming position and an image formation density of a formation section; a second determination section which determines whether a related element which affects the determination result by the first determination section satisfies a set condition; and a control section which controls the formation section to form a mark based on a mark element including at least one of: a width in the moving direction of the object; a width in a direction perpendicular to the moving direction; a density; a distance with an adjacent mark in a pattern; and a number of marks in the pattern, which is increased when the second determination section determine that the related element satisfies the set condition.
US08472068B2	Image processing apparatus, image processing system, and program An image processing apparatus includes a receiving unit that receives all image data of pages that are imposed; an input unit that inputs the number of pages in vertical and horizontal directions and a page opening direction; a calculation unit that calculates a division number on the basis of the number of pages and the page opening direction; an all image data dividing unit that divides the all image data into divided image data on the basis of the division number; and an acquisition unit that acquires a bind width and a back width from the all image data, wherein the printing position of the divided image data is corrected by calculating a margin from the bind width, the back width, a length of the print sheet, a length of the divided image data, and the number of pages of the divided image data in a correction direction.
US08472057B2	Information processing apparatus, and information processing method A client is used in an environment in which a printing method for causing a device to print printing data via a print server coexists with a printing method for transmitting print data to the device without the intervention of the print server for printout. If it is determined that a printer driver to be set up on the local printer is a newer version than that of a printer driver for a network printer and is shared therewith, a printer driver to be set up on the local printer is set up, and setting processing regarding a printer driver on the print server so as to cause the network printer to operate normally is performed.
US08472049B2	Image forming system, image forming apparatus, and job management program An image forming system for communicably connecting a data processor and an image forming apparatus can include a registration unit for registering a print job based on a print request, a printing unit for conducting print processing based on a print job registered in the registration unit, an authentication unit for, when the print job is a locked job with an unlocking condition, prohibiting print processing of the locked job until the unlocking condition is fulfilled, and a prohibition unit for prohibiting print processing of a normal job, which is registered in the registration unit after registration of the locked job, without the unlocking condition.
US08472048B2	Job control method, computer readable medium, and job control system A job control method includes: acquiring, from electronic information accepted, set information set for each setting item contained in the electronic information; setting the set information, which is acquired in the acquiring step, for an usable state in the job within a job item contained in a plurality of job items whose executing procedure are preset, the plurality of job items including a first job item and a second job item; and changing the set information, which is used in the job within a first job item, into an unusable state in the job within a second job item to be executed after the first job item has been executed.
US08472042B2	Image forming apparatus which forms an image based on print data described in a page description language The present invention provides a technique for reducing image quality deterioration and suppressing print performance reduction. A raster image processor (RIP) generates intermediate data by interpreting PDL data, and stores it in a memory. In a case where the memory area overflows in the middle of intermediate data generation and storage processing on the print data for one page, rendering is executed based on the intermediate data. In accordance with JPEG XR, tile division is performed. An encoding parameter indicative of lossless-encoding or lossy-encoding is determined in accordance with each tile, and encoding is executed. The encoded image data is stored in a background image memory area as a background image of intermediate data that will subsequently be generated. When subsequent intermediate data generation is completed, rendering is executed, the rendered image is synthesized with the image saved as a background image, then the data is outputted.
US08472040B2	Host apparatus, image forming apparatus, and diagnosis method for image forming apparatus A host apparatus, an image forming apparatus, and a diagnosis method for the image forming apparatus, the diagnosis method including: storing a printing image generated from print data according to a printing command; and generating a diagnosis image for the printing image based on the stored printing image and a defect image corresponding to a predetermined defect of the image forming apparatus.
US08472036B2	Controlling program and controlling method There is described a controlling method to be employed in a printing system that includes: a plurality of image forming apparatuses, each of which is capable of assigning a name to setting information in regard to a printing operation and also capable of registering the setting information in association with the name thereof; and a specific apparatus to be coupled to the plurality of image forming apparatuses. The method includes: acquiring plural sets of setting information, each of which is the setting information registered in each of the plurality of image forming apparatuses in association with the name thereof; determining whether or not at least two of the names assigned to the plural sets of setting information are cognominal; and displaying a message, indicating a fact that the same name is assigned to at least two of the plural sets of the setting information, when the names are cognominal.
US08472035B2	Image processing apparatus, image processing system, and computer readable medium An image processing apparatus includes the following elements. An image information generator generates, in response to an instruction, print image information to print plural pieces of image information in parallel in plural columns. A division manager divides the print image information into regions, each region having a length equal to the greatest common divisor of lengths of the image information. A manager manages, every time a printing operation is performed, the regions subjected to the printing operation such that the regions are divided into print guaranteed regions and print non-guaranteed regions. A print restart region determining unit determines, upon detection of an occurrence of an abnormality during the printing operation, a print restart region after recovery from the abnormality is completed on the basis of the print guaranteed regions and the regions of the print image information.
US08472034B2	Job control device, job control file, job control method, and job control program When batch jobs are submitted, the names of the jobs can be arbitrarily designated, so that a user can prepare a configuration file in an easy manner, and the time and effort of the management thereof can be alleviated. Upon submitting batch jobs, a configuration file reading part (1) reads in a control file (F) in which job names arbitrarily designated by the user are described, and a processing execution part, which is constituted by a job state handling part 6, an execution-content executing part (4) and a job submitting part (5), determines the sequence of the respective jobs according to the job names by making reference to a job state database (2), submits necessary jobs at appropriate timing, and thereafter monitor the states of the jobs thus submitting.
US08472033B2	Method of detecting amount of axis displacement in power transmission device using automatic self-aligning engagement clutch A method of detecting an amount of an axis displacement in a power transmission device includes, for each of the rotary shafts of the first and second drive sources, measuring an amount of an axis position variation by using non-contact sensors respectively provided to face the rotary shafts, and detecting an amount of a relative axis displacement of the rotary shaft of the second drive source relative to the rotary shaft of the first drive source on the basis of the amount of the axis position variation between before and after engagement.
US08472032B2	Single-lens 3-D imaging device using polarization coded aperture masks combined with polarization sensitive sensor A device and method for three-dimensional (3-D) imaging using a defocusing technique is disclosed. The device comprises a lens, at least one polarization-coded aperture obstructing the lens, a polarization-sensitive sensor operable for capturing electromagnetic radiation transmitted from an object through the lens and the at least one polarization-coded aperture, and a processor communicatively connected with the sensor for processing the sensor information and producing a 3-D image of the object.
US08472028B2	Optical coherence tomographic apparatus An optical coherence tomographic apparatus wherein a reference light path includes at least a first reference light path and a second reference light path having an optical path length shorter than that of the first reference light path, wherein first tomographic information of the object at a first inspection position based on the optical interference using the first reference light path and second tomographic information of the object at a second inspection position based on the optical interference using the second reference light path, are acquired, the second inspection position being shallower than the first inspection position with respect to a depth direction of the object, and wherein a positional deviation a tomographic image at the first inspection position obtained based on the first tomographic information is corrected using the second tomographic information.
US08472025B2	Device and method for detecting reflected and/or emitted light of an object A device and a method for detecting reflected and/or emitted light of an object (1) are proposed having at least one illumination device (2) illuminating the object (1) with pulsed light, and having at least one sensor (4, 6) capturing the light reflected and/or emitted by the object (1), and having a transport device transporting the object relative to the illumination device (2) and past the sensor 4, 6) in the direction of transport, and having a power supply (16, 17, 18, 19, 20, 21, 22) for the illumination device (2) providing the illumination device (2) with a current that is a periodic function over time, wherein a period comprises at least two current pulses (23, 24) of different magnitudes.
US08472021B2	Particle detector A particle detector for evaporation flux is disclosed. The particle detector includes a light source and at least one reflective surface.
US08472020B2	Process for enhancing dye polymer recording yields by pre-scanning coated substrate for defects A method for enhancing recording yields by monitoring dye polymer formation on a glass substrate is provided. After the glass substrate is coated with a dye polymer layer and before pits are formed on the dye-polymer coated glass, the dye polymer coated glass substrate is scanned to detect defects. The dye-polymer coated glass is discarded on the one hand if the defects detected through the scanning are at or above an unacceptable threshold level, and on the other hand data is written on the dye-polymer coated glass if the defects detected through the scanning are below the unacceptable threshold level.
US08472019B2	Spectroscopic characteristics acquisition unit, image evaluation unit, and image forming apparatus A spectroscopic characteristics acquisition unit includes a light emitting unit to illuminate a measurement target; a lens array including lenses to receive reflected light reflected from the measurement target; a light blocking member having a pinhole array including openings; a focusing unit to focus light coming from the pinhole array; a diffraction unit to diffract the light to different directions depending on wavelength of light received by the focusing unit; and a light receiving unit to receive the reflected light diffracted by the diffraction unit. The light receiving unit includes a spectroscopic sensor array having spectroscopy sensors including pixels. Each of the lenses constituting the lens array corresponds to one of the openings of the pinhole array. The numerical aperture NA of the lens in the arrangement direction in the lens array satisfies the formula NA>sin(θmax) with respect to the maximum angle of view θmax of the focusing unit.
US08472011B2	Motion rate sensor A motion rate sensor for detecting the rate of movement of an article, comprising: a housing relative to which, in use, the article moves, a detection unit disposed within the housing, the detection unit including a conversion device adapted for generating detector signals caused by the motion of the article, and processing circuitry adapted for receiving said detector signals and outputting motion signals indicative of the rate of movement of the article. In embodiments, the detector signals are caused by variations in optical or light energy, in magnetic fields or radiation intensity. The variations may be caused by variations on the surface in the article, for example a random or repetitive pattern. An apparatus and method for calibrating the sensor are also disclosed, as are a system and method for determining the speed of motion of an article using the sensor.
US08472007B2	Substrate holding device, lithography apparatus using same, and device manufacturing method The substrate holding device of the present invention includes a holding unit that adsorbs and holds the substrate, a measuring section that measures a physical quantity relating to a adsorption force of the holding unit with the substrate mounted on the holding unit; and a control section that carries out a first determination based on a first condition and a measurement result obtained by the measuring section and a second determination based on a second condition that is different from the first condition and a measurement result obtained by the measuring section to select one of at least three preset operations based on the result of first and second determinations to thereby execute processing depending on the selected operation.
US08472002B2	Lithographic apparatus and device manufacturing method A lithographic projection apparatus is disclosed in which a space between the projection system and the substrate is filled with a liquid. An edge seal member at least partly surrounds the substrate or other object on a substrate table to prevent liquid loss when edge portions of the substrate or other object are, for example, imaged or illuminated.
US08472001B2	Exposure method, exposure apparatus, and method for producing device A liquid immersion exposure apparatus in which a substrate is exposed with an exposure beam, includes a projection optical system by which the substrate is exposed to the exposure beam, a first inlet disposed at a first position, which is capable of supplying a first liquid to a space adjacent to a bottom surface of the projection optical system, and a second inlet disposed at a second position which is different from the first position, the second inlet being capable of supplying a second liquid that is different from the first liquid to the space.
US08471999B2	Low voltage liquid crystal lens with variable focal length Disclosed herein is a liquid crystal lens with a variable focal length. The gradient profile of the liquid crystals molecules that causes the gradient profile of the refractive index is achieved by inducing non-uniformly distributed anchoring energy and an external electric or magnetic field applied to the liquid crystal layer. Unlike existing electrically controlled liquid crystal lens, the external electric or magnetic field has a uniform spatial distribution within the liquid crystal layer. The focal length of the liquid crystal lens is controlled via the non-uniformly distributed anchoring energy and by varying the uniformly distributed electric or magnetic field.
US08471998B2	Liquid crystal display element, display device, and method for driving the same A liquid crystal display element includes a liquid crystal composition sandwiched between substrates, wherein at least two types of liquid crystal compositions which exhibit liquid crystal phase in different temperature ranges are contained within each one pixel, and each of the at least two types of liquid crystal compositions is sealed and isolated within each pixel.
US08471996B2	Liquid crystal panel, liquid crystal display unit, liquid crystal display device, and television receiver A liquid crystal panel includes: an active matrix substrate (3) including a transparent substrate (31) formed with a transistor, a pixel electrode, and a signal wire; a color filter substrate (30) including a transparent substrate (32) formed with a common electrode; a liquid crystal material (40) disposed between the substrates (3, 30); and a spherical main spacer (2m) contacting the active matrix substrate (3) and the color filter substrate (30). The active matrix substrate (3) has a surface including a sub spacer region (SA) away from the transparent substrate (31) at a distance shorter than a distance between the transparent substrate and a portion where the surface of the active matrix substrate (3) contacts the main spacer (2m). A spherical sub spacer (2s) is disposed to overlap the sub spacer region (SA). This provides a liquid crystal panel where liquid crystal bubbles hardly occur even when the liquid crystal material contracts due to low temperature, etc.
US08471989B2	Pixel unit of FFS type TFT-LCD array substrate A pixel unit of an FFS type TFT-LCD array substrate comprises a slit electrode. The slit electrode comprises at least one slit unit, a direction from one side of the slit unit to the opposite side of the slit unit is defined as a first direction, the slit unit comprises a plurality of slits, extending in a same direction and arranged along the first direction, and electrode parts between two adjacent slits. The sum of the width of each electrode part and the width of a slit adjacent to the electrode part at a side in the first direction increases gradually along the first direction.
US08471988B2	Electrode contact structure, liquid crystal display apparatus including same, and method for manufacturing electrode contact structure A water-repellent pattern (26) made from a water-repellent material is provided around a contact hole (20), and causes a polarizing layer (24) made from a water-soluble material to be separated from the contact hole (20). It is therefore possible to provide (i) an electrode contact structure which can prevent a reduction in mass productivity, (ii) a liquid crystal display apparatus in which the electrode contact structure is provided, and (iii) a method for manufacturing the electrode contact structure.
US08471985B2	Liquid crystal display panel A liquid crystal display (LCD) panel includes an active device array substrate, an opposite substrate, a liquid crystal layer, a polarizer, an analyzer, and a cover. The liquid crystal layer is configured between the active device array substrate and the opposite substrate. The polarizer is configured on the opposite substrate, and the polarizer and the liquid crystal layer are respectively located at two opposite sides of the opposite substrate. The analyzer is configured on the active device array substrate, and the analyzer and the liquid crystal layer are respectively located at two opposite sides of the active device array substrate. In addition, the cover is joined to the analyzer.
US08471980B2	Backlight unit and liquid crystal display device having the same A backlight unit with uniform brightness (luminance) is disclosed.The backlight unit includes: a plurality of light sources arranged at a fixed interval; a diffusion plate disposed on the light sources to primarily diffuse light emitted from the light sources; and a diffusion sheet configured to secondarily diffuse the primarily diffused light from the diffusion plate, wherein the surface of the diffusion sheet is divided into first regions not opposite to the light and second regions opposite to the light sources, and the diffusion sheet includes lens pattern portions formed on the second regions.
US08471978B2	Driving device and a liquid crystal display including the same A driving device including a board on which a timing controller for signal processing and a memory are mounted, the board having a conductive field, in which the conductive field has a non-contact region which is coated with an insulating material, and an exposed contact region which is not covered with the insulating material, the exposed contact region formed adjacent to the timing controller or the memory, a conductive member disposed in the exposed contact region, and a shield covering the board and electrically connected to the conductive field via the conductive member.
US08471977B2	Liquid crystal display device A flexible printed circuit board is pulled out to the outside from an end portion of the bottom surface portion. A notch is formed on a tip end of the end portion of the bottom surface portion such that an inner edge of the notch and an outer edge which projects from the notch are contiguously formed. A side of the flexible printed circuit board is arranged so as to overlap the notch. The outer edge of the bottom surface portion which projects overlaps the flexible printed circuit board. An angle made by a straight line which connects an intersecting point between the side of the flexible printed circuit board and the inner edge and a point of inflection between the inner edge and the outer edge and the side of the flexible printed circuit board is set to 45° or less.
US08471976B2	Liquid crystal display assembly A liquid crystal display (LCD) assembly includes a liquid crystal display device for displaying images, a first frame receiving the LCD device, a second frame receiving the first frame, at least a clamping component, and at least an ejecting component. The at least a clamping component is mounted between the first frame and the second frame and configured for clamping the first frame in the second frame. The at least an ejecting component is mounted between the first frame and the second frame and configured for providing a driving force for ejecting the first frame out of the second frame.
US08471967B2	Eyepiece for near-to-eye display with multi-reflectors An eyepiece for a head mounted display includes an illumination module, an end reflector, a viewing region, and a polarization rotator. The illumination module includes an image source for launching computer generated image (“CGI”) light along a forward propagating path. The end reflector is disposed at an opposite end of the eyepiece from the illumination module to reflect the CGI back along a reverse propagation path. The viewing region is disposed between the illumination module and the end reflector. The viewing region includes a polarizing beam splitter (“PBS) and non-polarizing beam splitter (“non-PBS”) disposed between the PBS and the end reflector. The viewing region redirects the CGI light from the reverse propagation path out of an eye-ward side of the eyepiece. The polarization rotator is disposed in the forward and reverse propagation paths of the CGI light between the viewing region and the end reflector.
US08471964B2	Device, method and medium for conversion of control signal output by incompatible remote control An electronic device (1) which is remote controllable has a conversion table storing unit (31) for holding a conversion table for converting an incompatible control signal that does not support the electronic device (1) into a compatible control signal that supports the electronic device (1), an input receiving unit (32) for receiving the input of the incompatible control signal based on the output of an incompatible remote control (4) that does not output the compatible control signal, a conversion unit (33) for converting the incompatible control signal the input of which has been received by the input receiving unit (32) into the compatible control signal according to the conversion table, and a control unit (34) for controlling the electronic device (1) according to the compatible control signal converted by the conversion unit (33).
US08471960B2	Method capable of avoiding data error from incorrect sampling points Data decoding devices avoiding data error from incorrect sampling points caused by serious interference are disclosed. The data decoding devices receive an analog signal carrying a reference clock and at least one digital data. In the data decoding device, a slicer slices the analog signal at different sampling points by first and second sampling clocks to obtain first and second bitstreams, and the first and second sampling clocks have the same frequency and a predetermined phase difference. A data check unit evaluates whether the first bitstream is erroneous according to an error checking code thereof, outputs the first bitstream if it is error-free, and evaluates whether the second bitstream is erroneous according to the error checking code if the first bitstream is erroneous.
US08471958B2	Method for controlling display device A method for controlling a display device is disclosed. The method includes receiving an input video image having a plurality of active scan lines, controlling the display device to display a plurality of background scan lines on a first display area with a first scan line frequency, and controlling the display device to display an output image on a second display area with a second scan line frequency. A second aspect ratio of the output image is substantially equal to a first aspect ratio of the input video image. The second scan line frequency is substantially lower than the first scan line frequency.
US08471957B2	Lens barrel with supporting flames and imaging device The lens barrel includes a flexible wire, a first supporting frame, and a second supporting frame. The flexible wire has a first end, a second end, and a flexible mounting portion. The first end includes at least one terminal. The second end includes at least one terminal. The mounting portion is disposed between the first end and the second end. The first supporting frame is configured to support the first end. The second supporting frame includes a storage component configured to support the mounting portion and is movably disposed in a first direction.
US08471955B2	Method and device for controlling the contrast range of an image capturing light falling on an image capturing medium A method for controlling the contrast range of the image recording light falling on an image recording medium by means of control light coupled into the optical path of the image recording light, which is composed of several base colors whose brightness is adjusted independent of each other, is provided. The brightness at least of those base colors of the control light is varied, whose dynamics in the recorded image go beyond the admissible dynamic range.
US08471953B2	Electronic camera that adjusts the distance from an optical lens to an imaging surface An electronic camera includes an image sensor. The image sensor has an imaging surface irradiated with an optical image of an object scene through a focus lens and repeatedly generates an object scene image. A CPU executes an AF process for adjusting a distance from the focus lens to the imaging surface to a distance corresponding to a focal point, based on the object scene image generated by the image sensor. However, the CPU has a high-luminance excluding function for excluding from a target to be noticed of the AF process a partial image having a luminance exceeding “TH1” out of the object scene image generated by the image sensor. The CPU determines whether or not a partial image having a luminance exceeding “TH2” larger than “TH1” exists on the object scene image generated by the image sensor, and turns on the high-luminance excluding function when a determination result is affirmative and turns off the high-luminance excluding function when the determination result is negative.
US08471952B2	Image pickup apparatus An image pickup apparatus includes: an imaging lens; an image pickup element including pixels of a first and second group, the pixels of the second group including pixels for phase difference detection, the image pickup element configured to be capable of independently reading out first and second image signals from the pixels of the first and second group, respectively; a defocus amount calculation device configured to calculate an amount of defocus of the imaging lens based on image signals read out from the pixels for phase difference detection; a focus control device configured to perform a focus adjustment to make the amount of defocus “0”; an image processing device configured to read out the first and second image signals after the focus adjustment and generate an image for recording based on the first and second image signals; and a recording device configured to record the generated image.
US08471949B2	Focus-adjustment signal generating apparatus and method, and imaging apparatus and method, with manual focus adjustments A focus-adjustment signal generating apparatus includes a filter to extract a high-frequency component at a specific frequency or higher from a luminance signal of an input video signal, a comparator to compare an absolute value of the high-frequency component with a specific reference value, to output a first detection signal when the absolute value is equal to or larger than the reference value whereas a second detection signal when the absolute value is smaller than the reference value, an extender to extend an output period of the first detection signal according to a period indicated by a period-length setting signal, to output an extended first detection signal, and a selector to select a first chrominance difference signal indicating a specific color in response to the extended first detection signal whereas a second chrominance difference signal indicating an achromatic color in response to the second detection signal, the first or the second chrominance difference signal being output as a focus-adjustment signal.
US08471945B2	Image display device and imaging device There are provided an image display device and an imaging device with which efficiency can be improved in the comparison of a plurality of images. A digital camera includes a liquid crystal monitor, a body microcomputer, and an image display controller. The body microcomputer has a display manager and a selector. The liquid crystal monitor has a first display region and a second display region and is configured to display images recorded to a recording medium. The display manager is configured to manage as display objects one or more images that have yet to be displayed on the liquid crystal monitor in a specific mode. The selector is configured to select an image from among the display objects as a selected image for display on the liquid crystal monitor. The image display controller is configured to display the selected image in the first display region or the second display region.
US08471943B2	Stacked organic light-emitting device, and image display apparatus and digital camera including the same Provided is a stacked organic light-emitting device in which organic compound layers for respective emission colors are capable of separately emitting light. The stacked organic light-emitting device includes a first organic compound layer, a second organic compound layer, and a third organic compound layer, which have emission colors different from each other. The first organic compound layer is provided on one side of a common transparent electrode, and the second organic compound layer and the third organic compound layer are provided on another side thereof. The first organic compound layer has a polarity direction opposite to polarity directions of the second organic compound layer and the third organic compound layer.
US08471941B2	Missing pixel array An active pixel sensor (APS) comprises a regular repeating pattern of geometrically similar pixel regions, active pixels of which have photodiodes formed therein. A remainder of the geometrically similar regions has electrical components shared amongst neighboring photodiodes, such as for collecting and amplifying signals from the photodiodes. A 4-way sharing arrangement is shown, with four active pixel regions aligned in a column and the shared electrical components in a pixel region, the pixel region being shaped and sized similarly to the active pixel regions, in an adjacent column.
US08471936B2	Imaging device and signal processing method The present invention provides an imaging device that generates, for each of a red color, a green color, and a blue color, an image signal having pixels arranged adjacent to each other in a two-dimensional array, including a red color imaging element that senses incident light to output a red color signal (20R) having pixels arranged in a check pattern, a green color imaging element that senses the incident light to output a green color signal (20G) having pixels arranged in a check pattern, a blue color imaging element that senses the incident light to output a blue color signal (20B) having pixels arranged in a check pattern, interpolation means for interpolating a blank pixel using neighboring pixels, and correlation means for determining a correlation of the neighboring pixels of the blank pixel, wherein the correlation means determines a correlation for each of the red color signal, the green color signal, and the blue color signal on the basis of at least one color signal of the red color signal, the green color signal, and the blue color signal, and wherein the interpolation means interpolates the blank pixel for each of the red color signal, the green color signal, and the blue color signal on the basis of the correlation to generate an imaging signal.
US08471927B2	Image processing device, image generating system, method, and program An image generation device includes an image acquisition section for acquiring the first and second moving images having different resolutions and different frame rates or different exposure times; a light amount determination section for determining whether each pixel is saturated or blocked-up-shadowed; and an image processing section for generating, from the moving images, a new moving image having a frame rate which is equal to or higher than the frame rate of the moving images and having a resolution of each frame image which is equal to or higher than the resolution of the moving images. For a pixel not determined as being saturated or being blocked-up-shadowed, the image processing section generates a new moving image fulfilling a first condition; and for a pixel determined as being saturated or being blocked-up-shadowed, the image processing section generates a new moving image which does not fulfill the first condition.
US08471926B2	Imaging apparatus, information processing apparatus and information processing method An imaging apparatus includes an information acquiring unit operable to acquire information representing a state of a recoding medium from the recording medium, a determining unit operable to determine the state of the recording medium based on the information acquired by the information acquiring unit, and an informing unit operable to inform result of the determination by the determining unit to an outside of the imaging apparatus.
US08471920B2	Focused plenoptic camera employing different apertures or filtering at different microlenses Methods and apparatus for capturing and rendering images with focused plenoptic cameras employing different filtering at different microlenses. In a focused plenoptic camera, the main lens creates an image at the focal plane. That image is re-imaged on the sensor multiple times by an array of microlenses. Different filters that provide different levels and/or types of filtering may be combined with different ones of the microlenses. A flat captured with the camera includes multiple microimages captured according to the different filters. Multiple images may be assembled from the microimages, with each image assembled from microimages captured using a different filter. A final image may be generated by appropriately combining the images assembled from the microimages. Alternatively, a final image, or multiple images, may be assembled from the microimages by first combining the microimages and then assembling the combined microimages to produce one or more output images.
US08471917B2	Night vision camera mount quick disconnect The night vision camera system includes a light, a night vision camera, and a linkage. The night vision camera is attached to the light such that the light and camera maintain a fixed orientation with respect to each other. The light is attached to the linkage and is configured to manipulate the light and night vision camera concurrently. The linkage is attached to the vehicle and extends into the vehicle interior where a handle is provided allowing the user to aim the light and night vision camera from the interior of the vehicle.
US08471916B2	Image pickup apparatus including image shake correction An image pickup apparatus includes a first detection unit for detecting a rotation shake, a first computation unit for processing a detection signal of the rotation shake into a rotation shake correction target value, a second detection unit for detecting a parallel shake in a plane surface perpendicular to an optical axis, a second computation unit for process a detection signal of the parallel shake into a parallel shake correction target value, a shake correction unit for correcting an image shake in the plane surface of the image pickup apparatus based on the rotation and parallel shake correction target values, an initialization unit for initializing the parallel shake correction target value, and a control unit for moving the shake correction unit based on an image pickup start instruction prior to an image pickup operation while initializing the parallel shake correction target value.
US08471915B2	Self-correcting adaptive long-stare electro-optical system An imaging platform minimizes image distortion when there is relative motion of the imaging platform with respect to the scene being imaged where the imaging platform may be particularly susceptible to distortion when it is configured with a wide field of view or high angular rate of movement, or when performing long-stares at a given scene (e.g., for nighttime and low-light imaging.) Distortion correction may be performed by predicting distortion due to the relative motion of the imaging platform, determining optical transformations to prevent the distortion, dynamically adjusting the optics of the imaging platform during exposure, and performing digital image correction.
US08471914B2	Image processing system with ease of operation When a shot is taken by a portable terminal, the position and orientation at the time of shooting is transmitted to an information processing apparatus. The information processing apparatus, which stores information including the position of equipment, detects the equipment included in the shot image by the portable terminal, based on the position and orientation of the portable terminal and the position of the equipment, and transmits information about the equipment to the portable terminal. The portable terminal obtains an operation history on an image processing apparatus in the equipment based on the received information, and displays an operation screen presenting the operation history in a selectable manner on a display unit. Then, when a selection of operation history is accepted, a control signal for allowing the image processing apparatus to execute image processing indicated by the operation history is transmitted to the image processing apparatus.
US08471913B2	Information processing apparatus, system and control method thereof In an information processing apparatus for transmitting and receiving information via a communication medium established relative to an external apparatus, it is determined whether the information to be transmitted and subject to specific processing in the external apparatus is selected or not. If it is determined that the information to be transmitted is selected, the selected information is transmitted via the communication medium. If it is determined that the information is not selected, designation information indicating the information selectable subject to transmission is transmitted via the communication medium. Then, the information designated by the designation information received in response to the transmission of the selection information is transmitted to the external apparatus via the communication medium.
US08471906B2	Miniature celestial direction detection system A celestial direction finding system. The system includes an inclinometer, at least one camera for imaging both the daytime sky and the nighttime sky and a computer programmed with a sun, moon and star catalog and algorithms for automatically determining directions based on positions of celestial bodies imaged by at least one camera and incline positions measured by the inclinometer. In a preferred embodiment all of the above features are combined in a single battery operated miniature celestial direction finding module. Geographical positions of nearby objects can be determined with the addition of a rangefinder and knowledge of the geographical position of the camera. The geographical position of the system in preferred embodiments can be determined with the addition of a GPS unit.
US08471905B2	Methods and apparatus for imaging Methods and apparatus for imaging according to various aspects of the present invention may generate an enhanced image of a target in an environment using image data from a sensor. The methods and apparatus may scale the image data to a higher resolution and register the image represented by the image data with other images of the same target. The enhanced image of the target is generated according to the registered images.
US08471900B1	Gooseneck hose with retrieval claws adapted for a camera A gooseneck hose device comprising a semi-flexible tube; a housing disposed on a first end of the tube, wherein a camera device is disposed in the housing which functions to allow a user to inspect a location, and a retractable claw is disposed in the housing which functions to grab an item in the location; a wire disposed in an inner cavity of the tube, a first end of the wire is attached to the retractable claw and a second end of the wire extends past a second end of the tube; and a gripping means disposed on the second end of the wire for allowing a user to grip and push or pull the wire inside the tube; wherein the camera device is operatively connected to an electrical viewing device via a cord (or Bluetooth®) comprising an adaptor component, the cord being wrapped in a retractable wheel.
US08471898B2	Medial axis decomposition of 2D objects to synthesize binocular depth A computer-based method for generating a stereoscopic image from a two dimensional (2D) image such as a 2D cell animation. An object is selected in the 2D image, such as an animated character, and is stored in memory as the base image. With an erosion engine, the selected object is eroded to generate a set of eroded versions of the base image corresponding to a number of erosion levels. Each erosion level image may be formed by eroding or removing a set of outer or edge pixels from the image on the prior level. The method continues with calculating a parallax shift value for each of the eroded versions of the base image. An alternate eye image is then generated by compositing the set of eroded versions along with the base image. The eroded versions are horizontally offset from the base image by the level-specific parallax shift values.
US08471896B2	Signal processing apparatus, signal processing method, display apparatus, and program product A signal processing apparatus includes: a phase matching unit which matches phases of a left image signal and a right image signal input from two cameras which are disposed so as to be matched with an interval between both eyes of a human to image the same object; and a phase adjusting unit which moves in a horizontal direction by a predetermined distance both or any one of a left image and a right image displayed on a display unit by the left image signal and the right image signal by changing the phases of the left image signal and/or the right image signal in the horizontal direction based on displacement amounts of phases designated by an operating unit, and outputs the left image signal and the right image signal obtained by changing disparity between the left image and the right image.
US08471895B2	Systems and methods of high resolution three-dimensional imaging Embodiments of the invention provide systems and methods for three-dimensional imaging with wide field of view and precision timing. In accordance with one aspect, a three-dimensional imaging system includes an illumination subsystem configured to emit a light pulse with a divergence sufficient to irradiate a scene having a wide field of view. A sensor subsystem is configured to receive over a wide field of view portions of the light pulse reflected or scattered by the scene and including: a modulator configured to modulate as a function of time an intensity of the received light pulse portion to form modulated received light pulse portions; and means for generating a first image corresponding to the received light pulse portions and a second image corresponding to the modulated received light pulse portions. A processor subsystem is configured to obtain a three-dimensional image based on the first and second images.
US08471893B2	Method and apparatus for generating stereoscopic image bitstream using block interleaved method Provided are a method and apparatus for generating a stereoscopic image bitstream. The method includes dividing a base view image and an additional view image into blocks having a predetermined size, generating a combined image by combining the blocks of the base view image and the blocks of the additional view image, recording the combined image in a payload area of the stereoscopic image bitstream, and recording block combination pattern information about a pattern of arranging the blocks of the base view image and the additional view image in the combined image, in a header area of the stereoscopic image bitstream.
US08471892B2	Wide field-of-view reflector and method of designing and making same A system and method for designing and using freeform reflectors to collect images of a wide angle field-of-view scene is provided. A freeform reflector may enable a wide angle field-of-view to be collected in an unwarpped and unwrapped manner such that computer processing may be eliminated. Furthermore, the use of a freeform reflector allows for larger areas of an image sensor chip to be used, thereby providing higher resolution images. Because freeform reflectors may be configured to map a scene onto the image sensor chip in a scalar and mathematically correct manner, output images may be directly displayed from the image sensor chip. Wide angle field-of-view imaging systems, such as surveillance, alarm, and projector system, may utilize freeform reflectors as provided herein.
US08471890B1	Adaptive video communication channel A videoconference system includes a camera at each several user locations, a computer at each user location linked to the camera at each location, and one or more bridges linking the computers to one another. A video encoding program stored on each computer causes each computer to encode video data received from the camera at the user location. A decode information set request monitoring program stored on at least one of the computers causes the computer to monitor the bridges for reception of a decode information set request message; and respond to the decode information set request message by querying the request message for an ID. If the ID of the request message matches an ID assigned to the computer, the computer generates a decode information set based on video data received from the camera, and communicates the decode information set to all of the other computers.
US08471887B2	Video-telephony terminal and method for controlling video-telephony terminal A video telephony terminal includes a session verification unit to verify whether stuffing data is received from a motion picture ring back tone (RBT) server and a terminating terminal with respect to a request for a video telephony connection, and a communication unit to perform the video telephony connection with the terminating terminal if reception of terminal side stuffing data is verified before reception of server side stuffing data associated with the motion picture RBT server is verified. A method for controlling a video telephony terminal includes performing a video telephony connection with the terminating terminal if terminal side stuffing data is received from the terminating terminal with respect to the request for a video telephony connection before a reception of the server side stuffing data associated with the motion picture RBT server is verified.
US08471885B2	Image processing method and image processing apparatus An image processing method including calculating a density of a character to be recorded based on information of a type, size and line width of the character; adjusting an irradiation energy of a laser beam for recording the character based on the density of the character; and irradiating a recording medium with the laser beam whose irradiation energy is adjusted so as to record the character thereon.
US08471882B2	Image forming apparatus An image forming apparatus, which forms an image by forming an electrostatic latent image on a photosensitive member with a laser beam, developing the electrostatic latent image with a developer to obtain a developer image, and transferring the developer image to a sheet, includes a light source which outputs the laser beam for exposing the photosensitive member; a PLL circuit which generates a multiplied clock that is obtained by multiplying a reference clock; a pulse-width modulating circuit which outputs a pulse-width-modulated signal based on image data and the multiplied clock in order to drive the light source; and a CPU which obtains image data to be input to the pulse-width modulating circuit and, when it is unnecessary to output the pulse-width-modulated signal based on the obtained image data, controls the PLL circuit so as not to generate the multiplied clock.
US08471881B2	Image forming apparatus and image forming method using the apparatus An apparatus to form plural images on an image conveyor includes plural photoconductor bodies, a light exposure device, a development device, a transfer device, and a pattern detection device, wherein the light exposure device includes an optical scanning part, a first light detection part having a first light receiving face, a second light detection part having a second light receiving face being non-parallel to the first light receiving face, a third light detection part having a third light receiving face being non-parallel to the first light receiving face, the optical scanning part, the first light detection part, and the second light detection part being provided inside a housing of the light exposure device, the third light detection part being provided outside the housing, and a light exposure timing control device.
US08471879B2	Image forming apparatus and image forming method Disclosed is an image forming method including forming a concave-convex pattern on a surface of a plate by pressing the plate and a mold having the convex-concave pattern on a surface thereof against each other, the plate having the surface made of a material in which a hardness changes reversibly at a transition point temperature, forming a plate image constituted of a concave-convex region having the concave-convex pattern and a smooth region in which the concave-convex pattern is erased on the plate by erasing the concave-convex pattern by selectively heating the surface of the plate to the transfer point temperature or above corresponding to an image signal, and forming an image on a recording medium by forming an ink image on the plate by applying an ink on the plate image and by transferring the ink image on to the recording medium.
US08471877B2	Image forming apparatus for and method of correcting color registration error Disclosed is an image forming apparatus capable of, and a method of, correcting a color registration error. The image forming apparatus corrects a color registration error by adjusting a scan start time of, and/or the distance in a sub-scanning direction between, multiple light beams that are scanned by a light scanning unit onto several photosensitive media.
US08471875B2	Method and system for driving light emitting display A display system includes a driver for operating a panel having a plurality of pixels arranged by a plurality of first lines and at least one second line The driver includes a driver output unit for providing to the panel a single driver output for activating the plurality of first lines, the single driver output being demultiplexed on the panel to activate each first line.
US08471871B1	Authoritative text size measuring Methods and systems for uniform rendering of text across a plurality of client computing devices using a server are disclosed. In one aspect, a method includes sending the document from the server to the plurality of client computing devices and receiving initial text formatting information at the server from a first client computing device in the plurality of client computing devices. The method further includes generating revised text formatting information on the server for the first client computing device in the plurality of client computing devices and sending the revised text formatting information from the server to the first client computing device in the plurality of client computing devices for re-rendering of the document so that the document text appears substantially the same on each client computing device.
US08471869B1	Optimizing display orientation An accelerometer of a mobile computing device is operable to provide a first input to an orientation module of the device. The orientation module is configured to use multiple signals to determine a spatial orientation of the device. A magnetometer of the device is operable to provide a second input to the orientation module. The orientation module is operable to receive the first input from the accelerometer and the second input from the magnetometer, and to determine an orientation of the device based on a combination of the first input and the second input.
US08471860B2	Optimization of memory bandwidth in a multi-display system Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.
US08471857B1	Changing animation displayed to user A computing system may perform a method comprising displaying, on a graphical user interface (GUI) on a display of the computing system, a plurality of initial animations to a user, each of the plurality of animations being displayed in response to an identical function call, having an identical visual appearance, and being displayed to prompt an input from the user. The method may also comprise monitoring, by a processor of the computing system, the user's input to each of the plurality of animations. The method may also comprise displaying, by the GUI, a subsequent animation to the user, the subsequent animation being displayed in response to the identical function call but having a different visual appearance than the plurality of initial animations, the different visual appearance of the subsequent animation being based on the monitored inputs.
US08471856B2	Rendering stroke pairs for graphical objects The principles of the present invention relate to rendering stroke pairs. A graphical object includes at least a first stroke and a second similarly oriented second stroke collectively representing a stroke pair. A calculated distance between the first stroke and the second stroke is constrained (e.g., to a center line between the strokes) to mitigate the possibility of rounding errors causing the represented stroke pair to be inappropriately rendered. After the stroke pair is constrained, controls points of the individual strokes can be adjusted so that the individual strokes are appropriately rendered at their respective constrained locations. The adjusted stroke pair is constrained between external reference points for appropriate rendering relative to other graphical objects. The graphical object, including the adjusted constrained stroke pair, is rendered at an output device.
US08471853B2	Reconstructable geometry shadow mapping method A reconstructable geometry mapping method is provided. The reconstructable geometry mapping method includes: extracting geometry information of a plurality of occluding geometry shapes of an object's front-face with respect to a light source's point of view; performing a consistency test on a testing pixel so as to determine an occluding geometry shape corresponding to the testing pixel from the object's front-face among the plurality of occluding geometry shapes, in which the occluding geometry shape includes an occluding point, and the testing pixel overlaps with the occluding point when viewing from the light's point of view; reconstructing a depth value of an occluding point corresponding to the testing pixel; and performing a shadow determination of the testing pixel.
US08471848B2	System and method for tracking three dimensional objects Embodiments of the invention are directed to improved systems and methods for three dimensional (3D) image reconstruction. The systems and methods are directed to extracting, digitally reconstructing and optionally tracking 3D objects from multiple two dimensional (2D) video camera sources. The systems and methods are directed to reconstructing a 3D scene via 2D cameras and then re-projecting this data back onto 2D surfaces. This system and method can greatly simplify the image processing required to analyze the 3D model by moving the analysis techniques back into the 2D domain.
US08471847B1	Use of constructed three-dimensional geometries to efficiently represent time varying Cartesian data A computing device configured to render time-varying geographic data or other Cartesian data, for example on a map. The computing device includes a memory device, and processing hardware configured to access, from the memory device, data defining a three-dimensional object representing time-varying geographic data, the three-dimensional object defined in a three-dimensional coordinate space; to determine a two-dimensional plane in the three-dimensional coordinate space, the two-dimensional plane corresponding to a time value of interest; and to render, on a map, a shape defined by an intersection of the two-dimensional plane with the three-dimensional object.
US08471846B2	Method and apparatus for determining medical image position A method and a corresponding apparatus for determining a position in an image, in particular a medical image enables a reliable determination of positions of interest in images of a variety of structures by displaying a volume rendering of image data acquired from an object, in particular a patient, pointing at a structure of interest displayed in the volume rendering of the image data, generating a viewing ray profile comprising information characterizing a ray running through said structure of interest, selecting a contextual profile from various contextual profiles, each of said contextual profiles comprising a representative ray profile representing a viewing ray profile of a structure, in particular an anatomical structure, and comprising profile information, and determining a position within said structure of interest based on said profile information of said selected contextual profile in the case that the representative ray profile of said selected contextual profile is matching with at least a part of said viewing ray profile.
US08471845B1	System and method for constructing a bounding volume hierarchical structure A system and method for constructing a bounding volume hierarchical structure are disclosed. The method includes defining a parent node for the bounding volume hierarchical structure, the parent node including a parent node bounding volume enclosing a plurality of objects. A first cost is computed for performing an object partition of the parent node bounding volume to produce a first plurality of child node bounding volumes, and a second cost is also computed for performing a spatial partitioning of the parent node bounding volume to produce a second plurality of child node bounding volumes. The bounding volume hierarchical structure is constructed employing the second plurality of child node bounding volumes produced from the spatial partitioning of the parent node bounding volume if the second cost is lower than the first cost.
US08471843B2	Geometric and texture modifications of objects in a virtual universe based on real world user characteristics A computer implemented method, apparatus, and computer usable program product for modifying objects in a virtual universe. A user priority controller determines a real world identity of a set of users controlling a set of avatars within a viewable field of an object in a virtual universe. The user priority controller receives user information describing characteristics of the set of users based on the real world identity of each user in the set of users. The user priority controller generates a temporary and dynamic rule to control modification of the object based on the user information. The user priority controller modifies the object in accordance with the temporary and dynamic rule to increase visibility of the object to an avatar in the set of avatars. The temporary and dynamic rule initiates implementation of geometric and texture modifications to modify the object in accordance with the temporary and dynamic rule.
US08471839B2	Signal control circuit and method thereof, liquid crystal display and timing controller thereof A signal control circuit and a method thereof, and a liquid crystal display (LCD) and a timing controller thereof are provided. The signal control circuit of the present invention maintains a voltage level of a driving signal output from the timing controller for driving data drivers to the supply voltage, such that the data drivers may cease outputting display data to the liquid crystal display panel when the LCD is turned off. Therefore, the image sticking, ghost image and fan-out phenomenon occurred when the LCD is turned off may be avoided.
US08471838B2	Pixel circuit having a light detection element, display apparatus, and driving method for correcting threshold and mobility for light detection element of pixel circuit A pixel circuit includes: a light emitting element; a driving transistor for applying current to the light emitting element in response to a signal value applied between a gate and a source thereof when a driving voltage is applied between a drain and the source thereof; first and second capacitors connected in series between the gate and the source of the driving transistor; a sampling transistor connected between the gate of the driving transistor and a predetermined signal line; a switching transistor connected to supply a potential of the signal line to a node between the first and second capacitors; and a light detection element connected between the gate of the driving transistor and the node between the first and second capacitors for supplying current of a current amount in accordance with an emitted light amount of the light emitting element.
US08471837B2	Channel scan logic A device that can autonomously scan a sensor panel is disclosed. Autonomous scanning can be performed by implementing channel scan logic. In one embodiment, channel scan logic carries out many of the functions that a processor would normally undertake, including generating timing sequences and obtaining result data; comparing scan result data against a threshold value (e.g., in an auto-scan mode); generating row count; selecting one or more scanning frequency bands; power management control; and performing an auto-scan routine in a low power mode.
US08471835B2	Receiver and signal transmission system A receiver includes: an adjustment circuit that adjusts an electric potential of a midpoint provided on a side of the receiver such that the electric potential of the midpoint provided between a pair of signal lines and on the side of the receiver is identical with an electric potential of a midpoint provided between the pair of signal lines and on a side of the transmitter, the transmitter transmitting a plurality of image signals, a vertical synchronizing signal, and a horizontal synchronizing signal, and transmitting and receiving differential signals on the pair of signal lines; a control circuit that controls the velocity of rise and decay of the differential signals which flow on the pair of signal lines; and a cancel circuit that cancels crosstalk by the vertical synchronizing signal generated on the horizontal synchronizing signal by inputting the vertical synchronizing signal.
US08471834B2	Display device, method of laying out wiring in display device, and electronic device A display device includes: a pixel array section having pixels arranged in a form of a matrix on a display panel; a first terminal group disposed on the display panel so as to correspond to each control line of a first control line group arranged in each pixel row of the pixel array section; a first wiring group for electrically connecting each terminal of the first terminal group to each control line of the first control line group; a second terminal group disposed on the display panel for a second control line group arranged in each pixel row of the pixel array section with a plurality of control lines as a unit; and a second wiring group for electrically connecting each terminal of the second terminal group to each control line of the second control line group through parts between the terminals of the first terminal group.
US08471833B2	Handheld electronic device, executing application method, and digital data storage media An application executing method is provided. The application executing method is applied to a handheld electronic device having a body and a touch element. The touch element is disposed at the body. The application executing method comprises the following steps. Firstly, a communication mode is entered. Next, whether the touch element is moved is detected. If the touch element is moved, then an application is activated.
US08471832B2	Keypad assembly having light leakage prevention structure A keypad assembly having a light leakage prevention structure includes a switch board having at least one switch; a light guide panel mounted on the switch board, light propagating inside the light guide panel; and a first light blocking member stacked on a lateral surface of the light guide panel, the first light blocking member extending to the switch board and reflecting or absorbing incident light.
US08471831B2	Touch panel with carbon nanotube film An exemplary touch panel, includes a flexible first substrate, a second substrate opposite to the first substrate, a first electrically conductive layer formed on the first substrate and facing the second substrate, a second electrically conductive layer formed on the second substrate and facing the first substrate, a carbon nanotube film formed on the second electrically conductive layer, a plurality of insulated dot spacers arranged between the first electrically conductive layer and the carbon nanotube film, an infrared sensor array arranged on the second substrate and including a number of infrared sensors corresponding to pixels of the touch panel; and a signal processor receiving signals from the infrared sensors.
US08471825B2	Information processing apparatus, information processing method and computer program An information processing apparatus according to the present invention comprises a display unit for displaying thereon a plurality of input regions operated by an operating body, a detection unit for detecting an approach distance between the operating body and a surface of the display unit, and a region control unit for, when the operating body approaches one of the input regions within a predetermined distance, enlarging the input region which the operating body approaches, and moving at least one of the input regions such that the adjacent input regions do not overlap each other. The input region is enlarged and an overlap between the input regions is avoided so that a user can easily select a desired input region, thereby preventing erroneous selection of other input region.
US08471823B2	Systems and methods for providing a user interface A device may include a touch sensitive display and logic configured to control the touch sensitive display to display information to a user, provide a window of enlarged information via the touch sensitive display based on a determined position of input on the touch sensitive display, and receive a selection from the enlarged information based on a determined position of input within the provided window.
US08471821B2	System and method for analyzing movements of an electronic device using rotational movement data The disclosure relates to a system and method for analyzing movements of a handheld electronic device. The method comprises: calculating a matching score for a rotational string representation of rotational movement data for the device to a gesture string representing a gesture related to a command for the device by recursively traversing a matrix containing the rotational string representation, the gesture string representation and earlier movement data of the device using a distance edit algorithm to generate matching scores for values of the rotational string representation against the gesture string; and if a threshold for the matching score is met, executing a command associated with the gesture on the device.
US08471820B2	Pivotable display guide mechanism for an electronic mobile device An electronic mobile device includes a base and a pivotable assembly that is pivotable relative to the base. A linkage connects to the pivotable assembly so as to be pivotable about a first axis and connects to the base so as to be pivotable about a second axis. As such, the pivotable assembly is pivotable relative to the base about the first axis and the second axis. The electronic mobile device further includes a guide mechanism that includes a guide path defined by one of the base and the pivotable assembly. The guide mechanism further includes a guide member supported by the other of the base and the pivotable assembly. The guide member moves along the guide path as the pivotable assembly pivots relative to the base to inhibit the pivotable assembly from simultaneously pivoting about both the first axis and the second axis.
US08471819B2	Mobile communications terminal having key input error prevention function and method thereof A mobile communications terminal and a method for preventing an input error of a key input unit are provided. The mobile communications terminal includes a touch sensor unit for sensing a key that is input by touching a keypad region in order to output a key input signal corresponding to the key and a controller adapted to determine a key input according to either a priority between multiple keys from which key signals are received or whether a received key signal was generated inadvertently.
US08471818B2	Flexible data entry device A data entry device includes a flexible base, a receiving module, a rolling mechanism, and a stop mechanism. The receiving module includes a sleeve and a subsidiary cover detachably attached to the sleeve. The base is received in the sleeve. The rolling mechanism rotates the base. One end of the base is secured to the rolling mechanism, and the other end of the base is secured to the subsidiary cover. The stop mechanism is for controlling the movement of the rolling mechanism. A selected length of the base exposed out of the sleeve can be controlled by the stop mechanism.
US08471817B2	Pocket data input board The invention is a transparent keyboard with translucent markings to show the functions of each key. It can rest over the screen of a computer, hand held device, smart phone or the like, without obstructing the screen or using it for marking the keys or reducing the size of the screen area that is used as a screen or monitor as against a keyboard. It can be made by translucent markings on existing touchscreen keyboards or a transparent layer over the touchscreen with translucent markings. It can be a transparent screen with programmable markings. It can be touch sensitive, yet use key layouts and sizes to prevent unintended key activation and ease multi finger typing.
US08471816B2	Variable gain mouse A motion capture device for communicating with a host device in order to input captured motion. The device includes an amplifier module structured to weight displacement measurements by a gain, and an adjustment module structured to adjust the gain as a function of a speed of the capture device.
US08471814B2	User interface control using a keyboard User interface control using a keyboard is described. In an embodiment, a user interface displayed on a display device is controlled using a computer connected to a keyboard. The keyboard has a plurality of alphanumeric keys that can be used for text entry. The computer receives data comprising a sequence of key-presses from the keyboard, and generates for each key-press a physical location on the keyboard. The relative physical locations of the key-presses are compared to calculate a movement path over the keyboard. The movement path describes the path of a user's digit over the keyboard. The movement path is mapped to a sequence of coordinates in the user interface, and the movement of an object displayed in the user interface is controlled in accordance with the sequence of coordinates.
US08471811B2	Puck-based pointing device that provides multiple buttons A pointing device having a puck that is confined to move in a field of motion on a surface and that provides pointing and clicking functions analogous to those of a conventional mouse is disclosed. The puck has first and second members that are spaced apart from one another by a resilient spacer when no force is applied between the members. The puck includes a tilt mechanism for allowing the first and second members to assume a tilted configuration with respect to one another in response to a force being applied between the first and second members. A position detector determines the position of the puck in the puck field of motion and a tilt position of the first member with respect to the second member. The determined tilt position is used to emulate two or more switches that are actuated by varying the tilt position.
US08471809B2	Operation body, information-input device, and information terminal device An operation body having a pointing function with respect to information includes a chassis having a reflection face, a circuit charging an inner second battery when receiving an electrical power from outside through a terminal exposed from the chassis, and a circuit transmitting switch information to outside cordlessly. On the other hand, an information-input device includes a chassis supporting a keyboard, and an optical system that transmits a light to an operation body operated on the chassis and receives a reflected light of the light. The chassis supporting the keyboard has a recess housing the operation body. The operation portion may be housed in the recess. The second battery is charged when the operation body is housed. And a light emitting of the optical system is stopped when the operation body is housed.
US08471808B2	Method and device for reducing power consumption in a display A method and system for reducing power consumption in a display includes driving a display comprising a plurality of display elements characterized by a display state. In a first mode of operation, the display state of substantially all the display elements is periodically re-set so as to display a first series of image frames. Upon changing to a second mode of operation, a second mode of operations comprises re-setting the display state of only a portion of the display elements so as to display a second series of image frames at a display element resolution which is less than said display element resolution used to display said first series of image frames.
US08471805B2	Imaging device, driving method of the same, display device and electronic apparatus In an imaging device including imaging elements, a driver configuration which does not require much layout space and ensures a reduced number of wirings is provided. The imaging device includes imaging elements 1 arranged in a matrix or in lines and a single driver circuit 6 disposed along the vertical direction of the matrix or along the direction in which the lines extend to control the driving of the imaging elements 1. Then, the driver circuit 6 serves the double function of a reset driver adapted to reset the imaging elements and a read driver adapted to read out the signals from the imaging elements.
US08471803B2	Level shifters including circuitry for reducing short circuits and display devices using the same Provided are a level shifter and a display device including the level shifter. The level shifter includes: a first circuit that blocks a supply of a source voltage to a first node while a signal input to an input terminal is maintained at a logic high level, and that supplies the source voltage to the first node while the signal input to the input terminal is transitioned from a logic high level to a logic low level; a second circuit that supplies the source voltage to the first node only when a voltage of an output terminal is maintained at a logic low level; a first inverter that reverses a logical level of the signal input to the input terminal by using the voltage supplied from the first node and outputs the signal to a second node; and a second inverter that reverses the logical level of the signal input to the second node by using the source voltage and outputs the signal to the output terminal.
US08471799B2	Liquid crystal display having pixel data self-retaining functionality and operation method thereof A liquid crystal display having pixel data self-retaining functionality includes a gate line for delivering a gate signal, a data line for delivering a data signal, a control unit for providing a first control signal and a second control signal, a data switch, a voltage-control inverter, a liquid crystal capacitor, and a pass transistor. The data switch is utilized for inputting the data signal to become a first data signal according to the gate signal. The voltage-control inverter is utilized for inverting the first data signal to generate a second data signal furnished to the liquid crystal capacitor according to the enable operation of the first control signal. The pass transistor is used for passing the second data signal to become the first data signal or for passing the first data signal to become the second data signal according to the second control signal.
US08471790B2	Display device, picture signal processing method, and program There is provided a display device including a display unit having pixels, each of which includes a luminescence element that individually becomes luminous depending on a current amount and a pixel circuit for controlling a current applied to the luminescence element according to a voltage signal, where the pixels are arranged in a matrix pattern. The display device includes an average luminance calculator (200) for calculating average luminance for a predetermined period of the input picture signal, and also includes a luminous time setter (202) for setting an effective duty depending on the calculated average luminance by the average luminance calculator (200), the effective duty regulating for each one frame a luminous time for which the luminescence element is luminous. The luminous time setter (202) sets the effective duty such that a luminescence amount regulated by a preset reference duty and possible maximum luminance of a picture signal.
US08471789B2	Organic electroluminescence display device and method for driving the same In an organic electroluminescence display device (30) comprising an organic EL element (26) having a structure wherein an organic luminescent medium (24) is sandwiched between a top electrode (20) and a bottom electrode (22), and a driving circuit (14) for driving the organic EL element (26), the organic luminescent medium (24) comprises a host compound and a triplet-related luminous compound and the driving circuit (14) applies a electric pulse voltage or pulse current having a frequency of 30 Hz or more and a duty ratio of 1/5 or less. In this way, it is possible to provide an organic EL display device which consumes a low electric power and has a long luminous life span, and a method for driving the same.
US08471788B2	Organic light emitting diode driver There is provided an organic light emitting diode driver capable of compensating for pixel deterioration in real time during the driving of pixels by selectively compensating pixels, requiring compensation, for the deterioration thereof, and precisely setting calibration data by removing an IR drop across a transistor, employed as a switch in the pixels, by calculating a difference between at least two representative values of different gray scale ranges among predetermined gray scale ranges.
US08471787B2	Display method of emission display apparatus A display method of an emission display apparatus including a display panel in which a plurality of pixels each having at least one subpixel are disposed, includes a first display method of performing the display of an image input data with only a subpixel using emission luminance, and a second display method of performing the display of the image input data with a nearby subpixel group. A display according to the second display method is performed with the emission luminance distributed to the subpixels of the nearby subpixel group, wherein a display is performed using an intermediate mode in which the first display method and the second display method are combined with a variable combination ratio. In the intermediate mode the emission luminance of the subpixel corresponding to the image input data is reduced in accordance with the combination ratio, and the display of the image input data is performed with the subpixel using the reduced emission luminance and with the nearby subpixel group with the emission luminance corresponding to the reduction distributed to the subpixels of the nearby subpixel group.
US08471783B2	Systems and methods for adaptive transmission of data The present disclosure describes systems and methods for transmitting, receiving, and displaying data. The systems and methods may be directed to providing a constant or substantially constant data transmission rate (e.g., frame rate per second) to a device and controlling bandwidth by presenting information directed to an area of interest to a user. Bandwidth can be lowered, for example by presenting high resolution data directed to the area of interest to the user (e.g., an area to which the user is looking or “gazing” using a heads-up display), and lower resolution data directed to other areas. Data can be transmitted and received at a constant frame rate or substantially constant frame rate, and gaze direction and progressive compression/decompression techniques can be used to transmit data focused on areas directed to an area of interest to the user.
US08471782B2	Systems and methods for multiple display support in remote access software A method of supporting multiple display configurations in a remote access environment, the remote access environment having a host computing device in communication with a viewer computing device comprises: receiving from a host computing device, by a viewer computing device having one or more viewer displays, a list of rectangles, each rectangle representing the boundaries of one of a plurality of host displays; presenting, by the viewer computing device to an end-user of the viewer computing device, a graphical user interface including means for selecting a configuration for displaying a window representing screen data of the plurality of host displays in the viewable area of the one or more displays of the viewer computing device; and displaying in the selected configuration, by the viewer computing device, the window representing the screen data of the one or more host displays. Corresponding systems are also described.
US08471778B2	Solid dual-band antenna device A solid dual-band antenna device is provided. The solid dual-band antenna device includes a Z-shape antenna structure comprising a first turn having a first turning angle, and connected to a ground portion and a first radiating portion; and a second turn having a second turning angle, and connected to the first radiating portion and a second radiating portion; a feeding portion disposed at the second turn for feeding a signal; an extending ground portion non-coplanarly extended from an outer side of the ground portion; and an extending radiating portion non-coplanarly extended from an outer side of the second radiating portion, wherein a first slot is disposed at an arbitrary position of the second radiating portion, and a length of the first radiating portion is different from a length of the second radiating portion.
US08471775B2	Array antenna and radar apparatus The array antenna includes a feed line, and a plurality of radiating element sections arranged at a predetermined arranging interval in a first direction, each of the radiating element sections including at least one radiating element fed a traveling wave through the feed line. The inter-element line length as a length of the feed line between each succeeding two of the radiating element sections is longer than the arranging interval in the first direction.
US08471774B2	Apparatus and method for measuring antenna radiation patterns An antenna radiation pattern measurement device that measures a radiation pattern of an AUT by using a source antenna includes a control unit, an analysis unit, and a measurement unit. The control unit controls driving of the source antenna and the AUT. The analysis unit measures an electric field value from a radio frequency (RF) signal that is transmitted from one of the source antenna and the AUT and received by the other antenna. In addition, the measurement unit controls the control unit and the analysis unit and measures a radiation pattern of the AUT by using the electric field value.
US08471768B2	Method and apparatus for an antenna In accordance with one example embodiment of the present invention an apparatus is disclosed. The apparatus includes a cover, a ground plane, a first inductor, and a second inductor. The cover includes a first end and an opposite second end. The cover is configured to operate as a first loop radiator portion. The ground plane is proximate the cover. The ground plane is configured to operate as a second loop radiator portion. The first inductor is proximate the first end of the cover. The second inductor is between the second end of the cover and the ground plane. The cover, the ground plane, the first inductor, and the second inductor are configured to provide a loop radiator.
US08471763B2	Processing of satellite navigation system signals and related receive-signal verification A system implements a location based service, and comprises a satellite navigation receiver implementing a position tracking function for providing the location of a user of the service. An analogue RF receiver receives satellite signals and performs at least a frequency downconversion. Correlation and decoding functions are applied to the downconverted signals for deriving location information from detected specific satellite signals. The system further comprises a server for receiving samples of the downconverted signals, and for verifying the samples are consistent with the expected satellite signals at that time and location. The invention provides a counter measure for detecting the counterfeiting of, or tampering with, the satellite signals at the receiver. A check can be made that the received satellite signals correspond to those which are expected at that location and time.
US08471761B1	Wideband radar nulling system This disclosure describes a radar system that in certain embodiments can, among other features, take into account the phase noise and/or drift of a transmit signal when generating a nulling signal. A receiver of the radar system can produce an IF signal by mixing a received signal with a local oscillator. The receiver can also mix the local oscillator with a transmit signal provided directly by the transmitter to the receiver to produce a control signal. Using the control signal to generate a nulling signal, the receiver can maintain or substantially maintain phase coherence between the nulling signal and the transmit signal. As a result, in certain embodiments, more precise nulling can occur, resulting in greater receiver sensitivity. Improved receiver sensitivity can provide a greater maximum detectable range and/or improved target detection.
US08471754B2	Time measurement circuit A time measurement circuit measures the time difference between edges of a first signal and a second signal. A sampling circuit acquires the logical level of the first signal at a timing of the edge of the second signal. When a sampling circuit enters a metastable state, an output signal thereof transits with a long time scale. A transition time measurement circuit measures a transition time (settling time) of the output signal of the sampling circuit in the metastable state.
US08471751B2	Two-stage analog-to-digital converter using SAR and TDC Various embodiments of this disclosure may describe a two-stage ADC circuit, and a time-interleaved system based on the two-stage ADC circuit. The two-stage ADC circuit may include a SAR converter for the first stage and a charge based TDC for the second stage. The two-stage ADC circuit may be used in high performance serial I/O applications. Other embodiments may be disclosed and claimed.
US08471749B2	Comparator A comparator is provided. In one embodiment, a method of operating a comparator comprises providing a bias current (920); comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal (930); latching the difference signal and the inverted difference signal to generate a first and second latched signals (950); generating a control signal using at least the first and second latched signals (970); and controlling the bias current in response to the control signal (980), wherein the comparing the input signal and the reference signal (930) is activated and deactivated in response to the controlling the bias current (980). In another embodiment, a comparator comprises a bias circuit (420) configured to provide a bias current; a comparator circuit (430) configured to determine a difference signal and an inverted difference signal by comparing an input signal and a reference signal, wherein the bias current is used to place the comparator circuit (430) in an active mode; a latch circuit (450) configured to latch the difference signal and the inverted difference signal to generate a first and second latched signals; a control circuit (470) configured to generate a control signal using at least the first and second latched signals; and a switch circuit (480) configured to use the control signal to control the bias current to place the comparator circuit (430) in an active mode and an inactive mode.
US08471748B2	Analog-to-digital converter with a resolution booster An analog-to-digital converter with a resolution booster is provided. The analog-to-digital converter may include a successive approximation analog-to-digital converter, a resolution booster, and an output combiner. The successive approximation analog-to-digital converter may be configured to convert an analog signal into digital data. The resolution booster may be selectively activated to enhance the resolution of the successive approximation analog-to-digital converter, and the output combiner may be configured to combine the respective outputs of the successive approximation analog-to-digital converter and the resolution booster.
US08471747B1	Phase averaged pulse width modulator A method is provided. A noise shaped signal having a plurality of instants is generated with each instant being associated with at least one of a plurality of output levels. A next phase is selected for each instant, where each next phase is a circularly shifted phase based at least in part on a previous phase for the associated output level for its instant. A plurality of PWM signals is then generated using the phase for each instant, and an amplified signal is generated from the plurality of PWM signals.
US08471743B2	Quantization circuit having VCO-based quantizer compensated in phase domain and related quantization method and continuous-time delta-sigma analog-to-digital converter A quantization circuit includes a quantizer and a compensation circuit. The quantizer includes a voltage-to-phase converter and a phase difference digitization block. The voltage-to-phase converter is arranged for generating a phase signal according to an input voltage. The phase difference digitization block is arranged for generating a quantization output according to a phase difference between a phase of the phase signal and a reference phase input. The compensation circuit is arranged for applying compensation to the phase difference digitization block according to the quantization output.
US08471739B2	Digital analog converter and method for calibrating sources thereof Provided is a digital analog converter that output currents having different magnitudes for a digital input value according to a mapping table. The digital analog converter includes: a plurality of current sources; and a calibration unit configured to sort index values for identifying the plurality of current sources according to current magnitudes of the current sources, couple each two current sources which are symmetrical left and right about the center of the sorted index values, and map the current source pairs into a mapping table.
US08471737B2	System and method for providing high resolution digital-to-analog conversion using low resolution digital-to-analog converters DA conversion is performed while improving resolution and reducing the influence of errors. A predetermined weight is applied to an output of at least one of a plurality of DA converters to each of which calibration data is given; the resultant outputs are added by an adder. An output of the adder is converted to a digital value by an AD converter. If the predetermined weight has an error outside an allowable range on the basis of the obtained digital value, a calibrating process of obtaining a correction factor for correcting the digital signal to be converted so as to reduce influence of the error is controlled. When a digital signal is to be converted to an analog signal with high precision, the digital signal is corrected with the correction factor, the resultant value is supplied to the DA converters, and DA converted outputs are added by the adder.
US08471732B2	Method for re-using photorealistic 3D landmarks for nonphotorealistic 3D maps A method of displaying a navigation map includes preprocessing photorealistic three-dimensional data offline. A location of a vehicle is automatically determined online. A portion of the preprocessed photorealistic three-dimensional data is identified that is associated with objects that are disposed within a geographic area. The geographic area includes the location of the vehicle. A nonphotorealistic image is rendered based on the identified portion of the preprocessed data. The nonphotorealistic image is electronically displayed to a user within the vehicle.
US08471725B2	Methods and supporting telemetry to determine, monitor and control the metagenomic and physical states of grease interceptors, FOGs, vaults and other waste collecting enclosures A system capable of ascertaining, determining, monitoring and controlling the biological state of and metagenomic state of microbial colonies as well as the physical state of waste liquids in grease interceptors, vaults and other waste collecting enclosures. The system consists of an array of cameras (14) a multi-phased sonar array (18), pH in (42)/pH out (24) and delta temperature arrays (36, 44), redundant liquid level sensors (10, 12), a nutrient measurement array (30, 32) and dissolved oxygen sensor (22). These sensors are mounted inside a grease interceptor (2) or waste collecting enclosure and enable accurate monitoring and control of all physical and biological processes to enable, optimize and control bioremediation processes. Continuous optimized control algorithms are either generated locally or updated remotely via internet or modem connection. All data is collected, logged in a Control/Telemetry Unit (20) and can be retrieved either locally or remotely via internet or modem connection.
US08471711B2	Method and systems of tagging objects and reading tags coupled to objects Methods and systems of tagging objects and reading tags coupled to objects. At least some of the illustrative embodiments are systems comprising a reading antenna, a tag reader coupled to the reading antenna, and a radio frequency identification (RFID) tag comprising a tag antenna electromagnetically coupled to the reading antenna. The RFID tag couples to an object such as the body of a living organism or a metallic article. Moreover, the tag antenna has a far-field radiation pattern in a direction away from the object that is substantially unaffected by proximity of the RFID tag to the object, and substantially unaffected by which surface of the RFID tag faces the object.
US08471710B2	Wireless tag and method of producing wireless tag According to an aspect of the invention, a wireless tag includes a base member that is flexible and on a surface of which a wiring pattern is formed, a wireless circuit chip that is mounted on the base member and connected to the wiring pattern; protective members that cover the base member and the wireless circuit chip and are lower in hardness than the base member, and a plurality of spherical projections that are arranged on the surfaces of the protective members, higher in hardness than the base member, and so arranged as to interfere with other adjacent spherical projections when at least the protective members are bent beyond a predetermined angle.
US08471706B2	Using a mesh of radio frequency identification tags for tracking entities at a site A system for tracking entities at a site comprises a mesh of radio frequency identification (RFID) tags. Each of the tracked entities, which may move about the site, is associated with and attached to a portable RFID tag. Each RFID tag is at least periodically caused to transmit a signal that includes an identification of the RFID tag. The signal is received by other RFID tags that are within range, which determine a location indicative parameter. Some of the RFID tags receiving the signal are fixed at predefined locations. Specific fixed RFID tags are designated as controller nodes. Data comprising an identification of the RFID tag receiving a signal, the location indicative parameter, and the identification of the portable RFID tag transmitting the signal are communicated to a location engine server, which processes the data to determine at least a relative position of the portable RFID tags on the site.
US08471705B2	Method and apparatus for detecting presence of a target object via continuous laser and range of the target object via laser pulse A multifunction detector for detecting energy reflected from the surface, the detector comprising: a focal plane array in communication with the optical receiving path; and an optical receiving path; a read-only integrated circuit in communication with the optical receiving path, integrated with a focal plane array; and a processor programmed to operate the focal plane array and read-out integrated circuit in a first mode to process signals in a first frequency band, and in a second mode to process signals in a second, wider frequency band.
US08471703B2	Network status indication system and method thereof A network status indication system utilizes indicators on a keyboard to indicate the network status of a computer. When a simultaneous activation of two predetermined keys is detected and when the number of simultaneous activations is odd, the network status is determined, thereby indicating the network status of the computer.
US08471702B2	Method and system for compressor health monitoring A method for monitoring the health of a compressor of a gas turbine is disclosed. The method includes receiving a plurality of turbine data points, wherein the plurality of turbine data points may include one or more operating parameters, at least one of a computer discharge temperature (CTD), and one or more performance parameters. The plurality of turbine data points may be categorized based on the one or more operating parameters. A statistical variability measure of at least one of the CTD and the one or more performance parameters may be computed for each of the plurality of bands. An alarm indicator may be computed based on the at least one statistical variability measure. The method may also include combining two or more of the operating parameters, the CTD and the performance parameters using sensor fusion techniques. The alarm indicator may be computed based on the combined parameters.
US08471698B2	Pluggable radio navigation satellite system street light controller An RNSS based street light controller pluggable into a standard electrical interface of a street light for drawing power and controlling a lamp of the street light eliminates the need for photosensors, wiring terminals and related components and yields a street light controller with modest installation and configuration requirements and robust performance and failure recovery characteristics. In some embodiments, the RNSS based street light controller comprises an RNSS receiver, a first electrical interface and a lamp controller, wherein the first electrical interface is adapted to couple with a second electrical interface of a street light and the lamp controller is adapted to regulate a supply of power to a lamp of the street light via the first electrical interface based at least in part on information received by the RNSS receiver.
US08471692B2	Driving support system, driving support apparatus, method, and computer-readable medium A driving support system includes an image pickup apparatus captures an image of a periphery of a vehicle in which the image pickup apparatus is provided, a measurement apparatus measures a distance from the vehicle to an obstacle around the vehicle, a driving support apparatus, which includes a determination unit determines a driving danger level of a driver of the vehicle based on the distance, an image enlargement unit changes a size of a simulated image of the vehicle stored in advance based on a result of determination, and an image generation unit combines the image of the periphery of the vehicle and the simulated image of the vehicle changed by the image enlargement unit, and a display apparatus displays the image combined by the image generation unit.
US08471687B2	Method and apparatus for communicating message signals in a load control system A system for independent control of electric motors and electric lights includes a plurality of two-wire wallstations coupled in series via power wires between an alternating-current (AC) source and a light/motor control unit. The light/motor control unit is preferably located in the same enclosure as an electric motor and an electric light and has two outputs for independent control of the motor and the light. The light/motor control unit and the wallstations each include a controller and a communication circuit that is coupled to the power wiring via a communication transformer and communicate with each other using a loop current carrier technique. The light/motor control unit and the wallstations utilize pseudo random orthogonal codes and a median filter in the communication process.
US08471685B2	Non-contact IC card system A non-contact IC card system includes a non-contact IC card having a display element and an IC card reader/writer communicating with the non-contact IC card. The IC card reader/writer disables detection of a load modulated signal from the non-contact IC card when the non-contact IC card displays data on the display element.
US08471682B1	Method and system for determining asset disposition using RFID A system and method of determining a disposition of an electronic device as installed, in-need-of-repair, or in-storage are provided, using Radio Frequency Identification (RFID) devices on the electronic devices and a sensor which detects disposition. Diagnostic test results and locations of installed devices may also be communicated to the RFID associated with the device and provided in a response to an interrogation. Shared memory on the device is integrated with the RFID device to store utilization and health history on the device for later retrieval. The disposition data is provided in a response to an interrogation of each device. Optionally, a communications device (e.g., RFID, or wireless interconnection) on a chassis housing electronic devices provides the disposition and location of all installed devices in response to an interrogation. The device disposition and location information is communicated to the communications device upon installation via a processing unit integral to the chassis.
US08471680B2	Turntable for display unit and control method therefor The invention provides an automatically rotatable turntable for a display unit and includes: a mounting section mounted with the display unit; an electric rotating mechanism that rotates the mounting section; a reception section in the display unit which receives a wireless signal from a remote control unit; and a control section that controls the electric rotating mechanism based upon the received wireless signal. Upon receipt of the wireless signal, the control section detects a reception strength of the reception section while cyclically rotating the mounting section around a predetermined rotational position, to initially detect a rotational position at which the reception strength is maximum. Thereafter, as a main operation, the control section detects the reception strength while rotating the mounting section in a direction extending from the predetermined rotational position to the initially-detected rotational position, to detect a rotational position at which the reception strength is maximum.
US08471675B2	Method for managing lockers remotely A method capable of remotely managing the implementation, the installation control and use of cabinets or storage lockers at any location over the Internet, through communication between databases that interconnect the end user needs with the capacities and needs of the location that makes the lockers available.
US08471666B2	Coil bobbin, coil component and switching power source apparatus To improve insulating properties of a coil winding having three turns. In a coil bobbin, insulation between mutually adjacent winding members of a first coil winding are achieved by a projecting section. Furthermore, the first coil winding and the second coil winding are insulated from each other by the flange section. Moreover, the projecting sections and the projecting sections are respectively provided in positions at either end when the first coil winding and the second coil winding are viewed in a direction perpendicular to the direction of the axis line. Consequently, even with coil windings having three turns, insulation between the windings is achieved by means of this coil bobbin, and furthermore, insulation is also achieved in the region outside the coil windings as viewed in a direction perpendicular to the axis line direction, thereby making it possible to improve the insulating properties without increasing the number of parts.
US08471664B1	Transformer without coil racks A transformer without coil racks includes a winding set, multiple conductive plates and an insulation mounting sheet. The winding set includes a coil portion and a magnetic core set running through the coil portion. The magnetic core set includes at least one inner magnetic core portion and at least two outer magnetic core portions that are spaced from each other by a gap. Each conductive plate includes a connecting section and two extended arms connected to two ends of the connecting section and running through the gap. The insulation mounting sheet includes multiple retaining slots corresponding to the gap to allow the extended arms to pass through and multiple retaining portions each being formed between two neighboring retaining slots to prevent the extended arms from contacting each other. The conductive plates run through the retaining slots and are confined by the retaining portions from moving.
US08471659B1	Automatic transfer switch having an interlock arrangement An automatic transfer switch to automatically electrically connect an electrical panel to a second power source, e.g., an electric generator, during interruption or failure of a first power source, e.g., a utility power supply, includes a powered interlock arrangement that is operative to prevent the electrical panel from being electrically connected to both power sources simultaneously.
US08471657B1	Trip mechanism and electrical switching apparatus including a trip member pushed by pressure arising from an arc in an arc chamber An electrical switching apparatus includes separable contacts, an operating mechanism structured to open and close the separable contacts, and a trip mechanism cooperating with the operating mechanism to trip open the separable contacts. The trip mechanism includes a trip latch, and an arc chamber operatively associated with the separable contacts. The arc chamber includes a plurality of arc plates and a barrier disposed between the arc plates and the trip latch. The barrier has an opening therein. A trip member is disposed in or about the opening of the barrier of the arc chamber. During interruption of current flowing through the separable contacts, pressure arising from an arc in the arc chamber pushes the trip member away from the barrier of the arc chamber to engage the trip latch and cause the trip mechanism to trip open the separable contacts.
US08471653B2	Elastic wave resonator and ladder filter To enhance a heat dissipation property and achieve stabilization of a resonance characteristic in an elastic wave resonator including an IDT electrode weighted so as to have a plurality of apodization local maximum value portions, the elastic wave resonator includes an IDT electrode located on a piezoelectric substrate, the IDT electrode is apodization-weighted so that a plurality of local maximum values occur in apodization in an elastic wave propagation direction, heat dissipation electrodes are provided in at least one apodization local minimum value portion occurring in the elastic wave propagation direction in the IDT electrode, and when it is assumed that direction dimension widths of the heat dissipation electrodes in the elastic wave propagation direction are A and the dimension of about ½ of a wave length of a propagating elastic wave is B, B
US08471650B2	Diplexer, and wireless communication module and wireless communication apparatus using the same A diplexer that can demultiplex and multiplex two signals having wide frequency bands, and a wireless communication module and a wireless communication apparatus using the same, are provided. A diplexer has a multilayer body including a first interlayer, a second interlayer and a third interlayer. On the first interlayer, first resonant electrodes are disposed in an interdigital form. On the second interlayer, a plurality of second resonant electrodes are disposed in an interdigital form. On the third interlayer, there are disposed an input coupling electrode that faces the input-stage first resonant electrode and the input-stage second resonant electrode in an interdigital form, a first output coupling electrode that faces the output-stage first resonant electrode in an interdigital form, and a second output coupling electrode that faces the output-stage second resonant electrode.
US08471641B2	Switchable electrode for power handling A MEMS oscillator includes a resonator body and primary and secondary drive electrodes to electrostatically drive the resonator body. Primary and secondary sense electrodes sense motion of the resonator body. The primary and secondary drive and sense electrodes are configured to be used together during start-up of the MEMS oscillator. The secondary drive electrode and secondary sense electrode are disabled after start-up, while the primary drive and sense electrodes remain enabled to maintain oscillation.
US08471639B2	Method and system for a feedback transimpedance amplifier with sub-40khz low-frequency cutoff A system for a feedback transimpedance amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing a transimpedance amplifier (TIA) having feedback paths comprising source followers and feedback resistors. The feedback paths may be coupled prior to the coupling capacitors at inputs of the TIA. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the TIA. The TIA may be integrated in a CMOS chip and the source followers may comprise CMOS transistors. The TIA may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode and may be differentially coupled to the TIA. The chip may comprise a CMOS photonics chip where optical signals for the photodetector in the CMOS photonics chip may be received via one or more optical fibers.
US08471633B2	Differential amplifier and data driver A differential amplifier has an interpolating function and has: first and second differential pairs including transistors of a first conductivity type; third and fourth differential pairs including transistors of a second conductivity type; first and second current sources providing operating currents to the first and second differential pairs; third and fourth current sources providing operating currents to the third and fourth differential pairs; a first control circuit which controls, in a first operating range where the amounts of currents flowing through the first and second differential pairs become smaller, respectively, a changing point at which the operating current of the first differential pair changes; and a second control circuit which controls, in a second operating range where the amounts of currents flowing through the third and fourth differential pairs become smaller, respectively, a changing point at which the operating current of the fourth differential pair changes.
US08471627B2	Cross current minimization A method of optimizing cross current in class D amplifiers and simultaneously minimizing the harmonic distortion is provided. The method overcomes the problem of using the limited speed voltage comparators often used in cross current preventing circuits. Method embodiments are based on introducing a replica amplifier with a current sensor matched to a main amplifier. The duration of a sensed cross current within the replica amplifier is compared by a current comparator with a small enough reference current. The comparator output generates a pulse with a duration equal to the duration of the cross current event in the replica amplifier. The duration of that pulse is measured and used to generate a dead time pulse for blanking amplifier pre-driver inputs.
US08471625B1	Beta enhanced voltage reference circuit A beta enhancement circuit includes a current source connected in series with a transistor between two voltage supply lines. In an embodiment, the voltage supply lines are configured for connection to a power source and ground potential. A resistor device is connected between a control terminal of the transistor device and one of voltage supply lines. A value for the resistor device is selected based on one or more process dependent parameters of the transistor.
US08471622B2	Drive circuit of semiconductor device The invention provides a switching circuit of a power semiconductor device having connected in parallel SiC diodes with a small recovery current, capable of significantly reducing turn-on loss and recovery loss without increasing the noise in the MHz band, and contributing to reducing the loss and noise of inverters. The present invention provides a switching circuit and an inverter circuit of a power semiconductor device comprising a module combining Si-IGBT and SiC diodes, wherein an on-gate resistance is set smaller than an off-gate resistance.
US08471621B2	Circuit and method for performing arithmetic operations on current signals A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode.
US08471620B2	Semiconductor device and electronic appliance The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.
US08471619B2	Circuit and method for generating a clock signal A circuit comprises a frequency divider coupled to receive an oscillating signal generated by an oscillator and a division ratio and configured to divide the oscillating signal by the division ratio into a clock signal; a temperature compensation circuit configured to measure a temperature of the oscillator and generate a division ratio to be provided to the frequency divider and a first value on the basis of the measured temperature; and a control system configured to control connection between a calibration element and the oscillator based on the first value and the oscillating signal of the oscillator.
US08471618B2	Flip-flop for low swing clock signal The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.
US08471617B2	Duty cycle correction in a delay-locked loop Circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals. One example provides a duty-cycle correction that can be used to improve the duty cycle of a clock signal that is received by, or generated by, a delay-locked loop. This example receives an input clock signal and uses a variable delay element to construct an improved duty-cycle output clock signal. The duty cycle of the output clock is examined to determine if the delay element is providing excess or insufficient delay. The delay of the delay element is then adjusted. To improve response times, a successive approximation technique is used to determine the most significant bits of a count that adjusts the delay through the delay element. To improve accuracy, a linear technique is used to adjust the least significant bits of the count.
US08471615B2	Timing adjustment circuit, solid-state image pickup element, and camera system A timing adjustment circuit includes at least one data line; a phase synchronization circuit that includes a plurality of oscillation delay elements which oscillate an oscillation signal, and that is configured to oscillate the oscillation signal by synchronizing a phase of a feedback clock with a phase of a reference clock; at least one delay circuit that includes a delay element which is disposed on the data line and which is equivalent to one of the plurality of oscillation delay elements, and that is configured to delay data which is to be transmitted on the data line; and a delay adjustment unit configured to adjust an amount of delay of the delay element of the delay circuit in accordance with a signal associated with oscillation of the phase synchronization circuit.
US08471613B2	Internal clock signal generator and operating method thereof An internal clock signal generation circuit is capable of controlling a unit delay time depending on a frequency of an external clock signal. The internal clock signal generation circuit includes an internal clock signal generation unit configured to generate an internal clock signal corresponding to a plurality of unit delay cells enabled in response to a control signal, and a unit delay time control unit configured to detect a frequency of an external clock signal and control a unit delay time of each of the plurality of unit delay cells.
US08471610B2	Application of phase-locked loop (PLL) in oscillation monitoring for interconnected power systems The present invention relates to a method for accurately detecting oscillations and improving stability of power systems. The method includes the steps of providing a phase-locked loop having a phase detector, a loop filter, and a number-controlled oscillator. The method further includes the steps of extracting an input signal from the power system, using the phase-locked loop to track the frequency and phase of a targeted mode in the input signal, and creating a locally generated reference signal to fit the input signal and to allow the input signal's modal information to be obtained. The method further includes the step of performing mode shape analysis utilizing the reference phase signals constructed from the tracked frequencies.
US08471609B1	Intelligent power supervisor A system can include at least one power supervisor coupled to a power supply voltage and including a processing element configured by instructions stored in a memory to assert at least one output signal in response to at least one comparator output, at least one comparator having a first input coupled to the power supply voltage and a second input coupled to a reference voltage, and configured to provide one comparator output, and at least one programmable voltage divider coupled to one input of the comparator and configured to vary a voltage divided output in response to the processing element.
US08471607B1	High-speed frequency divider architecture A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-back circuit is clocked on a rising clock edge of an input clock signal, while the second shift register loop-back signal is clocked on a negative edge of the input clock signal. The outputs of the first and second loop-back shift registers are ORed to provide a 50% duty cycle output clock signal.
US08471605B2	Driving circuit having current balancing functionality A driving circuit having current balancing functionality includes a control unit, a bias resistor, a current switch unit and plural current driving modules. The control unit is utilized for generating a control signal having at least one bit according to a control current. The bias resistor is put in use for providing a bias voltage according to a bias current. The current switch unit employs the control signal and plural bias setting currents to generate the bias current, for keeping the bias voltage within a preset voltage range. The current driving modules are used to provide plural driving currents according to the bias voltage and the control signal. Each current driving module includes a current-limit control unit which is utilized for controlling a corresponding driving current according to the control signal.
US08471600B2	Detection of the zero crossing of the load current in a semiconductor device A circuit arrangement includes a reverse conducting transistor having a gate electrode and a load current path between an emitter and collector electrode. The transistor is configured to allow for conducting a load current in a forward direction and in a reverse direction through the load current path and activated or deactivated by a respective signal at the gate electrode. The circuit arrangement further includes a gate control unit and a monitoring unit. The gate control unit is connected to the gate electrode and configured to deactivate the transistor or prevent an activation of the transistor via the gate electrode when the transistor is in a reverse conducting state. The monitoring unit is configured to detect a sudden rise of a collector-emitter voltage of the reverse conducting transistor which occurs, when the load current crosses zero, while the transistor is deactivated or activation is prevented by the gate control unit.
US08471599B2	Adjustable voltage comparing circuit and adjustable voltage examining device In an adjustable voltage examining module, while a logic tester issues an input signal to an audio module under test, upper/low-threshold reference signals are simultaneously issued to an adjustable voltage comparing circuit. While the adjustable voltage comparing circuit receives a signal under test returned by the to-be-examined audio module after a while, the adjustable voltage comparing circuit loads both an high-threshold reference voltage and a low-threshold reference voltage respectively indicated by the reference upper/low-threshold signal so as to compare both the upper and low-threshold reference voltages with the signal under test. Therefore, while the signal under test is examined to acquire a voltage level between voltage levels of the upper and low-threshold reference signals, precise operations of the audio module under test are assured, and time wasted by continuously-issued interrupt is saved.
US08471595B1	Selectable dynamic/static latch with embedded logic A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.
US08471593B2	Logic cell array and bus system A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
US08471592B1	Recursive code logic A logic device includes a transmission gate block configured to receive a binary input and a control input, the transmission gate block configured to provide a multi-bit output that is correlated from the binary input and in response to the control input having a first value. A state driver block is activated to drive one of a low state bit pattern or a high state bit pattern to the multi-bit output in response to the control input having a second value, which is different from the first value.
US08471591B2	Termination circuit for on-die termination In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.
US08471585B2	Method for evaluating semiconductor device A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.
US08471578B2	Probe and method of manufacturing probe A probe is made to contact an electrode terminal in an electric circuit or an electronic part for an electric measurement of the electric circuit or the electronic part. The probe includes a terminal portion which is brought in contact with the electrode terminal at one end of the probe, a spring portion in which U-shaped unit portions are arrayed in a zigzag formation, and a housing portion which surrounds the spring portion. The probe is formed of a sheet of a sheet-metal plate which is bent multiple times, the sheet-metal plate having a predetermined configuration in which a portion corresponding to the terminal portion, a portion corresponding to the spring portion, and a portion corresponding to the housing portion are continuously linked together.
US08471575B2	Methodologies and test configurations for testing thermal interface materials Methodologies and test configurations are provided for testing thermal interface materials and, in particular, methodologies and test configurations are provided for testing thermal interface materials used for testing integrated circuits. A test methodology includes applying a thermal interface material on a device under test. The test methodology further includes monitoring the device under test with a plurality of temperature sensors. The test methodology further includes determining whether any of the plurality of temperature sensors increases above a steady state.
US08471573B2	Dynamic quantity sensor and manufacturing method thereof A dynamic quantity sensor includes a first substrate, a fixed part arranged in the first substrate, a spiral shaped movable electrode arranged separated from the first substrate, one end of the spiral shaped movable electrode being supported by the fixed part, a fixed electrode positioned on the periphery of the movable electrode and arranged in a detection direction of a dynamic quantity, and a first terminal electrically connected to the fixed part and a second terminal electrically connected to the fixed electrode.
US08471570B2	Device for quantifying an electric unbalance and touch detection system incorporating it A device for detecting and quantifying an unbalance between first and second electric paths (R, S; S, VPS), particularly for a touch detection system, comprises: (a) comparison means (CC; CD) receiving at respective inputs the first and second paths; (b) variable transfer capacitance means (CPB; CPC) connected to at least one of the paths; and (c) a control unit (UC) connected between the comparison means and the variable transfer capacitance means and adapted to vary the variable transfer capacitance of said variable transfer capacitance means as a function of the result (Q) produced by the comparison means up to compensation of the unbalance.
US08471568B2	Evaluation of a charge impedance at the output of a directional coupler A method and circuit for evaluating a charge impedance at the output of a directional coupling having a first line adapted to convey a desired signal between a first terminal and a second terminal adapted to be connected to an antenna, and having a second line coupled to the first one including a third terminal on the side of the first terminal and a fourth terminal on the side of the second terminal, wherein the signal present on the fourth terminal is submitted to a homodyne detector having its local oscillator signal sampled from the third terminal.
US08471567B2	Circuit for detection of failed solder-joints on array packages A circuit for detecting changes in resistance at a solder joint connecting a constant voltage source supplying a first voltage and a pin of an array package during operation of the array package includes: a test circuit for applying a second voltage different from the first voltage at a side of the solder joint opposite the constant voltage source; and a monitoring circuit for monitoring an output of the test circuit, wherein the test circuit is configured to output the first voltage when the resistance at the solder joint is below a threshold value, and to output a voltage other than the first voltage when the resistance at the solder joint is above the threshold value, and wherein the monitoring circuit is configured to indicate a failure of the solder joint connection when the voltage other than the first voltage is output by the test circuit.
US08471559B2	Downhole micro magnetic resonance analyzer A downhole micro MR analyzer for use in a wellbore, having a micro sample tube, a micro RF coil in close proximity to the micro sample tube, and one or more magnets disposed about the micro sample tube is disclosed. The micro MR analyzer can be used for nuclear magnetic resonance or electron spin resonance experiments to ascertain formation properties and chemical compositions.
US08471556B2	Magnetic probe and processes of analysis An apparatus comprising a probe having an elongated probe casing includes a magnetometer and a permanent magnet having a north-south magnetic axis disposed in an orientation relative to a longitudinal axis of a drill string or pipe casing when the probe is inserted into the drill string or the pipe casing. The permanent magnet is disposed in a non-vertical plane that does not contain the longitudinal axis to induce a magnetic field in the plane from the north of the magnetic axis to the south of the magnetic axis along a portion of a circumference of the drill string or the pipe casing. The magnetometer is to detect magnetization of the drill string or the pipe casing independently of movement of the permanent magnet. Additional apparatus and methods of analysis using the apparatus are disclosed.
US08471552B2	Rotational angle-measurement apparatus and rotational speed-measurement apparatus A rotational angle-measurement apparatus with high accuracy is provided through electric correction of the rotational angle-measurement apparatus by rotating the rotation shaft at a constant speed. The rotational angle-measurement apparatus includes an electric motor having a rotation shaft, a magnet mounted on one end of the rotation shaft, and a magnetic sensor with an output signal that changes in accordance with an orientation of a magnetic field surrounding the magnetic sensor. The magnetic sensor outputs an angle signal representing the rotational angle of the rotation shaft, and the correction procedure utilizes rotation of the electric motor shaft through more than one revolution at a rotational speed with a known rate of change.
US08471544B2	Power controller for supplying power voltage to functional block A power controller including a processor which outputs a first output signal based on a first voltage in response to a clock signal, a selector which receives the first output signal via a first input terminal, and outputs a second output signal, a holding circuit which outputs a third output signal and holding data, based on the second output signal, a determination circuit which outputs a selector signal based on the holding data, and a control circuit which controls an output of the clock signal based on the selector signal. The selector receives the third output signal via a second input terminal, and outputs the first output signal or the third output signal as the second output signal.
US08471538B2	Controlled load regulation and improved response time of LDO with adaptive current distribution mechanism A low drop-out (LDO) voltage regulation circuit includes first and second internal current paths. The first internal current path is between the input supply voltage and ground and includes the regulator's buffer circuit. The second internal current path is between the input supply voltage and ground and includes the regulator's power transistor. The amount of current flowing through the first internal current path relative to the amount of current flowing through the second internal current path is an increasing function of a current supplied to a load connected to the output supply node. The load regulation of the LDO is improved as the DC gain will not go down at lower load currents. Further, the no load to full load response time is improved as the load pole and power MOS gate pole are actively controlled with respect to output load current. In this mechanism, as the amount of current being supplied to the load decreases, the internal current flow shifts from the first internal current path to the second internal current path and vice versa. This arrangement maintains the desired pole structure and keeps the quiescent current largely the same for all load current levels.
US08471537B2	Low power high voltage regulator for non-volatile memory device A high-voltage regulator includes a charge pump for generating a high voltage, a voltage regulator for generating a regulated voltage, and an oscillator having an oscillation frequency. The voltage regulator includes an operational amplifier having the high voltage as power supply, a first input, a second input coupled to a voltage reference, and an output. The voltage regulator further includes a first transistor having gate coupled to the output of the operational amplifier, a first terminal coupled to the high voltage and a second terminal coupled to a first voltage divider. The first voltage divider generates a first divided voltage that is coupled to the first input of the operational amplifier. The voltage regulator also includes a second voltage divider for providing a second divided voltage, wherein the second divided voltage controls the oscillator frequency.
US08471535B2	Large current handling capable semiconductor switching device with suppression of short circuit damage and recovery current switching loss A semiconductor switching device includes a power control part, which includes a voltage dropping chopper circuit having a first switching element and a first diode, a voltage boosting chopper circuit having a second switching element and a second diode, and an inductance. And the inductance is connected such that an unusual current caused by the arm short circuit is forced to pass through the inductance.
US08471533B2	System and method of charging a battery using a switching regulator In one embodiment the present invention includes a system and method of charging a battery using a switching regulator. In one embodiment, a switching regulator receives an input voltage and input current. The output of the switching regulator is coupled to a battery to be charged. The switching regulator provides a current into the battery that is larger than the current into the switching regulator. As the voltage on the battery increases, the current provided by the switching regulator is reduced. The present invention may be implemented using either analog or digital techniques for reducing the current into the battery as the battery voltage increases.
US08471532B2	Battery pack A system and method for battery protection. In some aspects, a battery pack includes a housing, a cell supported by the housing, a circuit supported by a flexible circuit board. The circuit is operable to control a function of the battery pack.
US08471526B2	Protection device for secondary batteries, and battery pack and electronic equipment employing same A protection device includes a voltage detector having N or more sub-circuits each for monitoring a specific battery cell to output a detection signal when at least one of the battery cells outputs an abnormal voltage. Each sub-circuit includes voltage dividing resistors, a reference voltage generator, and a comparator. The voltage dividing resistors generate a voltage division signal by dividing an output voltage of the battery cell. The reference voltage generator generates a reference voltage. The comparator compares the voltage division signal against the reference voltage. Each comparator is powered with voltage across the battery cell associated with the sub-circuit.
US08471525B2	Apparatus and method for charging internal battery in wireless sensor network Provided are an apparatus and method for charging an internal battery in a wireless sensor network. A method for a slave sensor node to charge an internal battery in a sensor network includes estimating an hourly chargeable electric energy rate in a scan phase with a master sensor node, transmitting the estimated hourly chargeable electric energy rate using an association request message requesting association with the master sensor node after recognizing the master sensor node, requesting charging from the master sensor node and performing wireless charging when a power level of an internal battery requires charging, reporting the power level of the internal battery varied by the wireless charging to the master sensor node by predetermined time periods during the wireless charging, and stopping the wireless charging when the power level reported to the master sensor node reaches a predetermined power level.
US08471516B2	Adjustable speed drive lifetime improvement method The present techniques include methods and systems for operating an inverter to maintain a lifespan of the inverter. In some embodiments, the switching frequency and/or the output current of the inverter may be changed such that stress may be reduced on the inverter bond wires of the inverter. More specifically, embodiments involve calculating the aging parameters for certain operating conditions of the inverter and determining whether the operating conditions result in aging the inverter to a point which reduces the inverter lifespan below a desired lifespan. If the operating conditions reduce the inverter lifespan below the desired lifespan, the switching frequency may be reduced to a lower or minimum switching frequency of the inverter and/or the output current of the inverter may be reduced to a maximum output current at the minimum switching frequency.
US08471514B2	Adaptive harmonic reduction apparatus and methods Power conversion systems with active front end converters for example motor drives and power generation systems for distributed energy sources are presented with adaptive harmonic minimization for grid-tie converters for minimized or reduced total harmonic distortion in the line current spectrum including the source harmonic current and the grid-tie converter injected current spectrum referred to the line side.
US08471512B2	Robotic drive control A robotic device includes an electric motor in which a drive control circuit includes a driver circuit for intermittently supplying the magnetic coils with a supply voltage VSUP; a switching signal generating circuit that generates a switching signal supplied to the driver circuit; and a voltage setter that supplies a supply voltage control value Ya to the switching signal generating circuit. By adjusting pulse width of the switching signals DRVA1, DRVA2 with reference to the supply voltage control value Ya, the switching signal generating circuit adjusts the effective voltage which is applied to the magnetic coils.
US08471511B2	Brushless motor control device and brushless motor A voltage application unit causes switching elements to apply voltage to flow an electric current into corresponding windings to generate a revolving magnetic field. A period derivation unit derives an energization period of the windings. A signal generation unit generates a PWM signal for causing the voltage application unit to activate and deactivate the switching elements, such that a duty ratio decreases gradually in a predetermined time period subsequent to the derived energization period. A period specifying unit specifies a detection period of an electric current, which is supplied from the switching elements presently switched and deactivated, by a predetermined time period between an edge, which is caused when the PWM signal changes in level to deactivate the switching elements, and a time point in advance of the edge in the energization period.
US08471510B2	Control of electrical machines An electrical machine for converting electrical energy into mechanical energy and/or mechanical energy into electrical energy, including at least one rotor position sensor device configured to undertake the steps of measuring an electrical signal during a switching cycle in an end region, and comparing the measurement with at least one similar measurement in at least one previous switching cycle to determine if a known rotor position has been reached.
US08471504B2	Motor controller and electric power steering system In a motor controller, a current detection unit detects an electric current flowing through a brushless motor. An open loop control unit determines a command value indicating a level of a command voltage in accordance with a motor circuit equation, based on a command current value indicating an amount of electric current to be supplied to the brushless motor and an angular velocity of a rotor in the brushless motor. A correction unit calculates a correction value based on a difference between the command current value and a current value detected by the current detection unit when the electric current is detected by the current detection unit and corrects the command value according to the correction value, and corrects the command value according to the correction value even when an electric current is not detected by the current detection unit.
US08471500B2	Electronic device and method of illumination A method and system are set forth for automatically adjusting keypad luminance based on display content. In one embodiment, the method comprises calculating a lighting level based on ambient light; calculating a luminance level of an image on the display; setting a maximum lighting level to the luminance level of the image on the display; and in the event the calculated lighting level exceeds the maximum lighting level then selecting the maximum lighting level, and in the event the calculated lighting level does not exceed the maximum lighting level then selecting the calculated lighting level.
US08471499B2	Light source driver A light emitting diode (LED) driver is provided that includes a light emitting diode, a converter connected to the light emitting diode, wherein the converter receives an input voltage and converts the input voltage to a basic voltage for driving the light emitting diode, a current regulator connected to the light emitting diode, a first operational amplifier connected to the current regulator, an analog dimming voltage generating unit including a second operational amplifier, a first resistor, a second resistor, and a third resistor, wherein a first terminal of the first resistor, a first terminal of the second resistor, and a first terminal of the third resistor are connected to a non-inversion terminal of the second operational amplifier, and connected to the first operational amplifier, and a pulse-width-modulation dimming pulse generating unit connected to a second terminal of the third resistor.
US08471497B2	Control circuit and method for LED drivers A control circuit and method for a LED driver accurately control the output current of the LED driver by adjusting a reference voltage or a feedback voltage according to the input voltage of the LED driver such that the output current decreases with the decrease of the input voltage. Therefore, it enhances the efficiency of the LED driver and maximizes the battery use time of a battery powered system.
US08471495B2	Light-emitting diode driving apparatus and light-emitting diode lighting controlling method A LED driving apparatus includes a rectifying circuit, first, second and third blocks, and first and second switching portions. The rectifying circuit is connected to AC power supply, and rectifies AC voltage of the AC power supply to provide pulsating current voltage. Each block includes a plurality of LEDs. The first, second and third blocks are serially connected to the output side of the rectifying circuit. The first switching portion switches ON/OFF of a first bypass path based on flowing current amount in the first block. The first bypass path bypasses the second block. The second switching portion switches ON/OFF of a second bypass path based on flowing current amount in the first and second blocks. The second bypass path bypasses the third block.
US08471493B2	Combination LED driver A driver circuit for a Light Emitting Diode (LED) is disclosed. The driver circuit is capable of supporting a constant LED current circuit configuration as well as an external resistor-controlled LED current circuit configuration. By integrating both configurations into a single driver circuit, the either circuit configuration can be selected without requiring a different driver circuit.
US08471486B2	Energy-saving mechanisms in multi-color display devices Some embodiments regard a method comprising: using an input voltage to generate an output voltage having a first voltage level; in a first period, when the output voltage changes from the first voltage level to a second voltage level, storing electrical charges resulted from the output voltage changing from the first voltage level to the second voltage level; and in a second period subsequent to the first period when the output voltage demands energy, using a voltage generated from the stored electrical charges in place of the input voltage to generate the output voltage.
US08471485B2	Dimmer switch assembly Disclosed herein is a dimmer switch having a broad range of control with a relatively simple circuit having a number of safety features. The circuit employs a triac and diac to selectively conduct an AC power wave. A variable phase shift network having an improved range of control governs the firing angle of the diac. The variable phase shift network includes a first and second series R-C circuits coupled by a bridge resistor.
US08471484B2	Reversed-polarity pulse generating circuit for direct current plasma and direct current plasma power supply unit A capacitor is connected between direct current voltage terminals, and inductance means is connected between one end of the capacitor and one of load terminals. In a case in which the direct current voltage exceeds a set value, voltage at both ends of the capacitor is shared by the first and second switching elements that are not electrically conductive; in a case in which the direct current voltage is below the set value, the first and second switching elements are electrically conductive on a periodic basis or as needed to output reversed-polarity voltage between load terminals; and in a case in which the first and second switching elements are turned off, voltage at both ends of the capacitor restricts voltage applied to both ends of the first and second switching elements, during a period in which the first and second feedback rectifier elements are electrically conductive.
US08471478B2	Light control signal generating circuit A light control signal generating circuit includes a photosensitive element, two transistors, and four resistances. A first resistance and the photosensitive element are connected in series between a power voltage terminal and a ground terminal. A base electrode of a first transistor is connected to a node between the first resistance and the photosensitive element, a collecting electrode is connected to the power voltage terminal through a second resistance, and an emitting electrode is connected to the ground terminal through a third resistance. A base electrode of a second transistor is connected to a node between the second resistance and the first transistor, a collecting electrode is connected to the power voltage terminal through a fourth resistance, and an emitting electrode is connected to the ground terminal through the third resistance. An output terminal is formed from a node between the fourth resistance and the second transistor.
US08471477B2	Substrate processing apparatus and method of manufacturing semiconductor device A processing speed may be easily controlled over the wide range within the impedance variation range. A substrate processing apparatus includes: a processing chamber configured to process a substrate; a substrate support unit configured to support the substrate in the processing chamber; a processing gas supply unit configured to supply a processing gas into the processing chamber; a plasma generation electrode configured to convert the processing gas supplied into the processing chamber to be in a plasma state; a radio frequency power source configured to apply a radio frequency power to the plasma generation electrode; a variable impedance electrode installed at the substrate support unit and configured to control an electric potential of the substrate; a variable impedance mechanism connected to the variable impedance electrode and configured to vary an impedance according to a reciprocal of a peak-to-peak voltage of the plasma generation electrode; an exhaust unit configured to exhaust an atmosphere in the processing chamber; and a controller configured to control at least the variable impedance mechanism.
US08471473B2	Arc tube for discharge lamp device In a mercury free arc tube provided with a sealed glass chamber in which at least metallic halide for main light emission is sealed as well as rare gas by pinch-sealing both end openings of a glass tube and electrode bars are opposite to each other, the tip of a region projecting into the sealed glass chamber of each the electrode bars is formed of a single crystal. Owing to repetition of ON/OFF of the arc tube, the crystal at the tip of the electrode bar grows but the shape of the electrode end face formed of the single crystal remains unchanged. Further, even if the tip of the electrode bar is gradually consumed by thermal load acting on the tip of the electrode bar, the entire shape of the electrode end face is consumed nearly uniformly so that decline of the luminescent spot does not occur during discharging.
US08471467B2	Encapsulated electroluminescent device This invention relates to an electroluminescent device (10) comprising an organic light emitting layer (50) and an encapsulation means (70) with a closed contour encapsulating the side of the electroluminescent layer stack (59) and for electrically contacting the counter electrode (40) to an electrical source. Furthermore, the invention relates to a method for providing such a device, the use of the contiguous contour as an encapsulation means and a covered substrate to be used in such a device.
US08471458B2	Light emitting device There is provided a light emitting device which includes a light emitting element having a main emission peak in the wavelength region of greater than 420 nm and equal to or less than 500 nm, and a phosphor layer formed on the light emitting element. The light emitting element of this light emitting device has a junction temperature of from 100° C. to 200° C. at the time of continuous driving. Furthermore, the phosphor layer contains a phosphor represented by the following general formula (A), which absorbs the light emitted from the light emitting element and thereby emits light having a main emission peak in the wavelength region of equal to or greater than 650 nm and equal to or less than 665 nm: (Mg1-x,AEx)a(Ge1-y,Sny)bOcHAd:zMn (A) wherein AE represents at least one or more elements selected from the group consisting of Ca or Sr; HA represents at least one or more elements selected from the group consisting of F or Cl; 2.54≦a≦4.40, 0.80≦b≦1.10, 3.85≦c≦7.00, 0≦d≦2.00, 0≦x≦0.05, 0≦y≦0.10, and 0
US08471456B2	Electroluminescent light source with improved color rendering An electroluminescent light source includes a layer structure comprising a first sublayer structure comprising at least one electrode as anode, one electrode as cathode and an electroluminescent layer located therebetween for emitting light, a second sublayer structure which adjoins the electrode provided for transmission, said second sublayer structure consisting of at least one semitransparent layer for partially reflecting the light, and a third sublayer structure which, as seen in the emission direction of the light, is arranged behind the second sublayer structure, said third sublayer structure comprising at least one layer having particles for absorbing some of the light at wavelengths below a threshold wavelength, for emitting light at wavelengths above the threshold wavelength, and for scattering the non-absorbed light.
US08471451B2	Ruthenium-based electrode material for a spark plug A ruthenium-based electrode material for use with a spark plug. The electrode material comprises ruthenium (Ru) and a precious metal. The ruthenium (Ru) is the single largest constituent of the electrode material on a wt % basis. The electrode material may have a density that is less than or equal to about 15.5 g/cm3 and may include at least one other precious metal. The electrode material may be used in a spark plug that includes a metallic shell having an axial bore, an insulator having an axial bore and at least partially disposed within the axial bore of the metallic shell, a center electrode at least partially disposed within the axial bore of the insulator, and a ground electrode attached to a free end of the metallic shell. The center electrode, the ground electrode or both may be formed at least in part from the electrode alloy.
US08471450B2	Ceramic electrode, ignition device therewith and methods of construction thereof A spark plug, a center electrode therefore and method of construction is provided. The spark plug has a generally annular ceramic insulator extending between a terminal end and a nose end. A conductive shell surrounds at least a portion of the ceramic insulator and a ground electrode having a ground electrode sparking surface is operatively attached to the shell. An elongate center electrode has a body extending between opposite ends, wherein the body is compacted and sintered of a conductive or semi-conductive ceramic material. One of the electrode ends provides a center electrode sparking surface to provide a spark gap between the center electrode sparking surface and the ground electrode sparking surface.
US08471448B2	High-frequency plasma spark plug High-frequency plasma spark plug includes an insulator which has an axial hole extending in the axis direction, a center electrode inserted into a distal end side of the axial hole, a terminal electrode inserted into a rear end side of the axial hole, and being electrically connected to the center electrode, and a cylindrical main fitting mounted on an outer periphery of the insulator. With respect to a coaxial cable, the inner conductor is connected to the terminal electrode and the outer conductor is connected to the main fitting. High frequency power generated by a predetermined high-frequency power source is supplied via the coaxial cable thus generating high frequency plasma. The main fitting includes a large diameter portion which bulges radially outward and a connection portion which is brought into contact with the outer conductor.
US08471445B2	Anti-reflective coatings for light bulbs A light bulb having anti-reflective coatings on an inner surface and/or an outer surface of the shell of the light bulb. The anti-reflective coatings reduce light loss due to reflections at the interfaces between the interior of the bulb and the shell and between the shell and the exterior of the bulb. The light source may be either incandescent, fluorescent or LED.
US08471441B2	Piezoelectric component and manufacturing method thereof A piezoelectric component including a piezoelectric device having wiring electrodes disposed adjacent to a comb electrode and an insulation layer formed on an upper surface of a piezoelectric section. A rewiring layer is formed on an upper surface of the insulation layer and a protective film layer covers the entire upper surface of the rewiring layer excluding the comb electrode. An outer periphery wall section is formed by laminating a photosensitive resin film onto the protective film layer and a ceiling section is formed by laminating the photosensitive resin film onto top openings of the outer periphery wall section. Electrode posts are formed so as to pass through the outer periphery wall section and the ceiling section.
US08471440B2	Magnetic head driving piezoelectric ceramic actuator A magnetic head driving piezoelectric ceramic actuator having an actuator body and a coating layer. The actuator body has a piezoelectric ceramic substrate and first and second electrodes. The piezoelectric ceramic substrate has first and second principal surfaces, first and second side surfaces, and first and second edge surfaces. The first electrode has a first external electrode portion formed on a part of the first principal surface, and a second external electrode portion formed on the first edge surface. The second electrode has a third external electrode portion formed on the second edge surface, and a fourth external electrode portion formed on the first principal surface. Each of: at least a part of each of the first and second external electrode portions; and at least a part of each of the third and fourth external electrode portions, constitutes a joined portion mounted on the substrate by an electrically-conductive agent. The coating film covers at least a part of a surface of a portion of the actuator body other than the joined portions.
US08471435B2	Boundary acoustic wave device and method of manufacturing same In the boundary acoustic wave device, an IDT electrode, a first dielectric layer, and a second dielectric layer are provided on a piezoelectric substrate. The first dielectric layer is made of a deposited film. A thickness of the IDT electrode is about 10% or more of λ. A difference between a height of the first dielectric layer, measured from an upper surface of the piezoelectric substrate, above a center of an electrode finger of the IDT electrode and a height of the first dielectric layer, measured from the upper surface of the piezoelectric substrate, above a center of a gap between adjacent electrode fingers, i.e., a magnitude of unevenness in an upper surface of the first dielectric layer, is about 5% or less of λ.
US08471434B2	Surface acoustic wave device, surface acoustic wave oscillator, and electronic apparatus A surface acoustic wave device includes: a quartz substrate with Euler angles of (φ, θ, ψ); and an IDT which excites a surface acoustic wave in an upper mode of a stop band; wherein, the Euler angle φ is −60°≦φ≦60°, and the Euler angle φ determines the ranges of the Euler angles θ and ψ.
US08471433B2	Elastic wave device and electronic device using the same An elastic wave device has the following elements: a piezoelectric substrate; an inter-digital transducer (IDT) electrode disposed on the piezoelectric substrate; internal electrodes disposed above the piezoelectric substrate and electrically connected to the IDT electrode; side walls disposed above the internal electrodes surrounding the IDT electrode; a cover disposed above the side walls so as to cover a space above the IDT electrode; an electrode base layer disposed on the internal electrodes outside the side walls; and connection electrodes disposed on the electrode base layer. Each connection electrode has a first connection electrode disposed on the electrode base layer, and a second connection electrode disposed on the first connection electrode. The horizontal sectional shape of the second connection electrode is non-circular.
US08471430B2	Electric motor An electric motor includes a stator and a rotor rotatably installed in the stator. The stator has a stator core and windings. The stator core has a yoke and a plurality of teeth extending inwardly from the yoke. The stator includes two end caps disposed at opposite axial ends thereof and a plurality of locking members securing the end caps to the stator core. The windings are wound on the respective teeth, and the locking members extend between the end caps through gaps formed between adjacent teeth.
US08471428B2	Rotating electrical machine A rotating electrical machine includes a rotor, in which a plurality of magnetic poles are provided in circumferential direction, and a stator, within which the rotor is disposed. In the stator, two stator magnetic poles are formed by winding coils of one phase and by a stator core of the stator within 360° of electrical angle defined by the magnetic poles of the rotor. The coils that form respective stator magnetic poles have angular widths in circumferential direction of less than 180° of electrical angle, the coils that form the respective two stator magnetic poles are provided so as not to mutually overlap and are wound so that adjacent ones of the stator magnetic poles have mutually opposite polarities, and, in the stator, each winding of each coil consists of an external bridge wire, a turn portion, an internal bridge wire, and a turn portion, in that order.
US08471424B2	Permanent-magnet (PM) rotors and systems Permanent-magnet (PM) rotors, rotor components, and machines using PM rotors.
US08471423B2	Transverse flux rotary machine and switching device equipped with such a machine A rotary machine including two coaxial parts, the first part including an intermediate part, an energizing coil, and fingers distributed around the circumference of the intermediate part with a constant finger pitch and directed alternately in opposite directions. The fingers are positioned so as to interlace over part of the coil. The second part includes a permanent magnet and two lateral parts mounted substantially coaxially, the lateral parts being secured to the permanent magnetic part so as to have opposite polarities, the lateral parts including protrusions distributed around the circumference of the lateral parts and arranged in alternation on one and the other of the lateral parts with a protrusion pitch substantially equal to the finger pitch. A control device can be equipped with such a rotary machine.
US08471415B1	Identifying a device with a universal power supply by reading a communication tag Disclosed is a system and method for supplying power to devices from a receptacle with a universal pin configuration. In an example configuration, a plug reader and a controller are provided. The plug reader reads a communication tag of an electrical device plug, and receives data read from the plug reader from which it can identify an electrical capability of the electrical device, such voltage and/or frequency compatibility of the device. Based on the compatibility data, the controller determines whether a universal power supply is included in the device and causes power to be provided to the device.
US08471413B2	Control device of power supply circuit An ECU executes a program including a step of turning on an SMRP and an A-SMRP if an ignition switch is turned on; a step of detecting voltage values VB(1) and VB(2) of running batteries when VH is detected and if VH is higher than 180 V; a step of detecting that SMRP connected to the running battery is welded, if VB(1) is higher than 150 V; and a step of detecting that A-SMRB connected to the running battery is welded, if VB(2) is higher than 150 V.
US08471412B2	Switch assembly, electric consumer as well as machine tool The invention relates to a switch assembly (1) for switching an electric consumer (2) on and off, in particular for the use in a hand machine tool, comprising a power switch (3) and a power electronic (5) for supplying the consumer (2) with electric energy. According to the invention it is provided that a help switch (6) is provided, which works together with the power electronic (5) in such a way that it supplies the electric consumer (2) with electric energy only after switching on the help switch (6). The invention furthermore relates to an electric consumer (2) as well as a machine tool.
US08471402B2	Power supply system and container data center including same A power supply system includes a number of aerogenerators, a number of rectifiers, and a direct current to direct current (DC/DC) converter. A first terminal of each rectifier is connected to a corresponding one of the aerogenerators. A first terminal of the DC/DC converter is connected to second terminals of the rectifiers. A second terminal of the DC/DC converter is connected to a power unit of a container data center. Each rectifier converts the alternating current (AC) generated by the corresponding aerogenerator to a pulsating direct current (DC). The DC/DC converter converts the pulsating DC to a constant voltage DC and supplies power to the power unit.
US08471400B2	Vehicle generator control system and method for saving fuel A vehicle generating system for saving fuel includes a battery supplying power to electric loads in a vehicle, an electric generator supplying power to the battery and the electric loads, a speed calculation module that calculates operation speed of a wiper in the electric loads, and an ECU including an electric generation control prevention module controlling the electric generator to perform electric generation control prevention when the operation speed calculated by the speed calculation module is compared with a predetermined reference speed and the calculated operation speed is equal to or more than the reference speed, and controlling the electric generator to remove the electric generation control prevention when the operation speed is less than the reference speed.
US08471399B2	Floating wind power apparatus The present invention concerns a floating wind power apparatus with a floating unit and at least three rotors supported in rotor housings, placed on separate towers with a longitudinal central axis. The towers are attached in the floating unit and the rotor housing, and the floating unit may yaw to direct the rotors in relation to the wind. At least one rotor is a downwind rotor, and at least one rotor is an upwind rotor. The towers are placed at an inclined angle in relation to the rotors.
US08471395B2	Vehicle speed detection means for power generation system A vehicle energy harvester including a subunit having an upper surface forming a roadway surface; a vehicle activated treadle on the subunit, the vehicle activated treadle moveable between a first position in which an upper surface of the treadle is at an angle with respect to the upper surface of the roadway surface and a second position in which the upper surface of the treadle is flush with the upper surface of the roadway surface; a generator that generates power in response to movement of the vehicle activated treadle; and a vehicle speed detection device that detects a speed of a vehicle travelling over the roadway surface based on a speed of movement of the vehicle activated treadle.
US08471393B2	Semiconductor component including a semiconductor chip and a passive component A semiconductor component includes a semiconductor chip, and a passive component, with the semiconductor component including a coil as the passive component. The semiconductor chip and the passive component are embedded in a plastic encapsulation compound with connection elements to external contacts.
US08471391B2	Methods for multi-wire routing and apparatus implementing same A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.
US08471390B2	Power MOSFET contact metallization A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.
US08471388B2	Integrated circuit and method for fabricating the same A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5 μm and 27 μm over a semiconductor substrate, and forming a passivation layer on the metal trace, wherein the passivation layer includes a layer of silicon nitride on the metal trace and a layer of silicon oxide on the layer of silicon nitride, or includes a layer of silicon oxynitride on the metal trace and a layer of silicon oxide on the layer of silicon oxynitride.
US08471385B2	Method for the connection of two wafers, and a wafer arrangement A method for the connection of two wafers in which a contact area is formed between the two wafers by placing the two wafers one on top of the other. The contact area is heated locally and for a limited time. A wafer arrangement comprises two wafers which have been placed one on top of the other and between whose opposite surfaces a contact area is located. The wafers are connected to one another at selected areas of the contact area.
US08471383B2	Semiconductor package and fabrication method thereof A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved.
US08471382B2	Package and high frequency terminal structure for the same A package includes: a metal wall disposed on a conductive base plate; a through-hole disposed in input/output portions of the metal wall; a lower layer feed through disposed on the conductive base plate; a wiring pattern disposed on the lower layer feed through; an upper layer feed through disposed on a part of the lower layer feed through and a part of the wiring pattern; and a terminal disposed on the wiring pattern, wherein a width of a part of the lower layer feed through and a width of the upper layer feed through are wider than a width of the through-hole, the lower layer feed through is adhered to a side surface of the metal wall, the upper layer feed through is adhered to the side surface of metal wall, and an air layer is formed between the wiring pattern and an internal wall of the through-hole.
US08471381B2	Complete power management system implemented in a single surface mount package A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.
US08471379B2	Semiconductor device A semiconductor device includes a semiconductor chip with first and second low noise amplifier for amplifying an inputted signal. The chip is mounted over a wiring substrate which includes first and second electrodes and first, second and third GND electrodes. The wiring substrate includes first and second conductor patterns, wherein the first conductor pattern electrically connects the first and second GND electrodes and surrounds the first and second electrodes in a plan view. The second conductor pattern electrically connects the first conductor pattern and the third GND electrode to each other and is arranged between the first and second electrodes in the plan view. The first conductor pattern extends toward an inside of the semiconductor chip from the first and second GND electrodes in the plan view.
US08471378B2	Power semiconductor device and method therefor A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.
US08471373B2	Resin-sealed semiconductor device and method for fabricating the same A resin-sealed semiconductor device includes a power element (1), a control element (4), a first lead frame (3) having a first die pad (3A) which holds the power element (1), a second lead frame (5) having a second die pad (5A) which holds the control element (4), and a housing (6) made of a resin material and sealing the power element, the first die pad, the control element, and the second die pad. A lower surface of the second die pad is higher than an upper surface of the first element, and at least part of the first die pad and at least part of the second die pad overlap each other when viewed from the top. One of the first leads and one of the second leads are directly joined together by a joint portion (23) and electrically coupled together in the housing.
US08471369B1	Method and apparatus for reducing plasma process induced damage in integrated circuits An insulating material interposed between two conductive materials can experience plasma process induced damage (PPID) when a plasma process is used to deposit a dielectric onto one of the conductive materials. This PPID can be reduced by reducing electric charge accumulation on the one conductive material during the plasma process dielectric deposition.
US08471368B2	Polysilicon control etch back indicator This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
US08471366B2	Nitride semiconductor substrate A nitride semiconductor device includes a main surface and an indicator portion. The main surface is a plane inclined by at least 71° and at most 79° in a [1-100] direction from a (0001) plane or a plane inclined by at least 71° and at most 79° in a [−1100] direction from a (000-1) plane. The indicator portion indicates a (−1017) plane, a (10-1-7) plane, or a plane inclined by at least −4° and at most 4° in the [1-100] direction from these planes and inclined by at least −0.5° and at most 0.5° in a direction orthogonal to the [1-100] direction.
US08471365B2	Nitride semiconductor substrate, semiconductor device, and methods for manufacturing nitride semiconductor substrate and semiconductor device A nitride semiconductor substrate having a main surface serving as a semipolar plane and provided with a chamfered portion capable of effectively preventing cracking and chipping, a semiconductor device fabricated using the nitride semiconductor substrate, and a method for manufacturing the nitride semiconductor substrate and the semiconductor device are provided. The nitride semiconductor substrate includes a main surface inclined at an angle of 71° or more and 79° or less with respect to the (0001) plane toward the [1-100] direction or inclined at an angle of 71° or more and 79° or less with respect to the (000-1) plane toward the [−1100] direction; and a chamfered portion located at an edge of an outer periphery of the main surface. The chamfered portion is inclined at an angle θ1 or θ2 of 5° or more and 45° or less with respect to adjacent one of the main surface and a backside surface on a side opposite to the main surface. Accordingly, cracking and chipping occurring from the edge of the outer periphery of the nitride semiconductor substrate can be effectively suppressed.
US08471363B2	Semiconductor device and method of manufacturing the same A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.
US08471362B2	Three-dimensional stacked structure semiconductor device having through-silicon via and signaling method for the semiconductor device A three-dimensional (3D) semiconductor device including a plurality of stacked layers and a through-silicon via (TSV) electrically connecting the plurality of layers, in which in signal transmission among the plurality of layers, the TSV transmits a signal that swings in a range from an offset voltage that is higher than a ground voltage to a power voltage, thereby minimizing an influence of a metal-oxide-semiconductor (MOS) capacitance of TSV.
US08471361B2	Integrated chip package structure using organic substrate and method of manufacturing the same An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
US08471360B2	Memory cell with carbon switching material having a reduced cross-sectional area and methods for forming the same In a first aspect, a method of forming a metal-insulator-metal (“MIM”) stack is provided, the method including: (1) forming a dielectric material having an opening and a first conductive carbon layer within the opening; (2) forming a spacer in the opening; (3) forming a carbon-based switching material on a sidewall of the spacer; and (4) forming a second conductive carbon layer above the carbon-based switching material. A ratio of a cross sectional area of the opening in the dielectric material to a cross sectional area of the carbon-based switching material on the sidewall of the spacer is at least 5. Numerous other aspects are provided.
US08471357B2	Integrated inductor structure This invention provides an integrated inductor structure including a substrate, a metal coil layer on the substrate and a dielectric layer between the substrate and the metal coil layer. A well shielding structure for reducing eddy current is disposed in the substrate under the metal coil layer. The well shielding structure is chequered with a plurality of N wells and a plurality of P wells. The N wells and P wells are arranged in a chessboard-like manner. A P+ pickup ring is provided in the substrate to encompass the well shielding structure. A guard ring is formed directly on the P+ pickup ring.
US08471356B2	Programmable anti-fuse structures with conductive material islands Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.
US08471354B2	E-fuse structure of semiconductor device An e-fuse structure includes an anode, a cathode, a fuse part connecting the anode and the cathode to each other, and a dielectric contacting the fuse part. The dielectric is configured to apply a stress to the fuse part, where the stress constructively acting on a migration effect of atoms constituting the fuse part. The migration effect is generated by electromigration and thermomirgration.
US08471347B2	Solid-state imaging device capable of suppressing generation of dark current and imaging apparatus A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on the light receiving surface of the light sensing section.
US08471346B2	Semiconductor device including a cavity A semiconductor device includes a substrate including a cavity and a first material layer over at least a portion of sidewalls of the cavity. The semiconductor device includes an oxide layer over the substrate and at least a portion of the sidewalls of the cavity such that the oxide layer lifts off a top portion of the first material layer toward a center of the cavity.
US08471343B2	Parasitic capacitance reduction in MOSFET by airgap ild The instant disclosure relates to MOSFET semiconductor structures exhibiting a reduced parasitic capacitance, as well as methods of making the MOSFET semiconductor structures. The MOSFET semiconductor structures of the instant disclosure comprise an air-gap interlayer dielectric material between the contacts to the source/drain and gate structures and gate stack structures. The air-gap interlayer dielectric material causes the MOSFET semiconductor structures of the instant disclosure to have a reduced parasitic capacitance.
US08471336B2	Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.
US08471335B2	Semiconductor structure with alignment control mask A semiconductor structure includes a semiconductor substrate, formed on which are a first layer and a second layer, and an alignment-control mask. The alignment-control mask includes a first direction reference element, formed in a first region of the first layer and extending in a first alignment direction, and first position reference elements, formed in a first region of the second layer that corresponds to the first region of the first layer accommodating the first direction reference element. The first position reference elements are arranged in succession in the first alignment direction and in respective staggered positions with respect to a second alignment direction perpendicular to the first alignment direction.
US08471333B2	Semiconductor device and manufacturing method of the same A trench is formed so as to reach a p−-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.
US08471332B2	Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
US08471329B2	Tunnel FET and methods for forming the same A tunnel field-effect transistor (TFET) includes a gate electrode, a source region, and a drain region. The source and drain regions are of opposite conductivity types. A channel region is disposed between the source region and the drain region. A source diffusion barrier is disposed between the channel region and the source region. The source diffusion barrier and the source region are under and overlapping the gate electrode. The source diffusion barrier has a first bandgap greater than second bandgaps of the source region, the drain region, and the channel region.
US08471328B2	Non-volatile memory and manufacturing method thereof A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening.
US08471323B2	3-D electrically programmable and erasable single-transistor non-volatile semiconductor memory device A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate.
US08471322B2	Semiconductor device and manufacturing method thereof A semiconductor device includes a wiring configured to be formed in a surface portion of a first interlayer insulating layer in a first region, a common upper electrode configured to be formed in a surface portion of the first interlayer insulating layer in a second region, a plurality of capacitance portions configured to have the common upper electrode as an upper electrode and be extended below, wherein an upper surface of the first interlayer insulating layer and an upper surface of the common upper electrode approximately lie in the same plane.
US08471313B2	Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic apparatus A solid-state imaging device includes a substrate, a plurality of photodiodes arranged in the substrate in a depth direction of the substrate, a vertical readout gate electrode for reading signal charges in the photodiodes, the vertical readout gate electrode being embedded in the substrate such that the readout gate electrode extends in the depth direction of the substrate, a dark-current suppressing area which covers a bottom portion and a side surface of the readout gate electrode, the dark-current suppressing area including a first-conductivity-type semiconductor area having a uniform thickness on the side surface of the readout gate electrode, and a reading channel area disposed between the first-conductivity-type semiconductor area and the photodiodes, the reading channel area including a second-conductivity-type semiconductor area.
US08471310B2	Image sensor pixels with back-gate-modulated vertical transistor Image sensor arrays may include image sensor pixels each having at least one back-gate-modulated vertical transistor. The back-gate-modulated vertical transistor may be used as a source follower amplifier. An image sensor pixel need not include an address transistor. The image sensor pixel with the back-gate-modulated vertical source follower transistor may exhibit high fill factor, large charge storage capacity, and has as few as two row control lines and two column control lines per pixel. This can be accomplished without pixel circuit sharing. The pixel may also provide direct photo-current sensing capabilities. The ability to directly sense photo-current may facilitate fast adjustment of sensor integration time. Fast adjustment of sensor integration time may be advantageous in automotive and endoscopic applications in which the time available for the correction of integration time is limited.
US08471308B2	Process-variation tolerant series-connected NMOS and PMOS diodes, and standard cells, tags, and sensors containing the same Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.
US08471298B2	Nanoscopic wire-based devices and arrays Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used to form nanotubes in arrays in the presence of directing electric fields, optionally in combination with self-assembled monolayer patterns. Bistable devices are described.
US08471297B2	Semiconductor memory device and method of manufacturing the same A semiconductor memory device according to an embodiment includes a cell array block having a plurality of cell arrays stacked therein, each of the cell arrays including a plurality of memory cells and a plurality of selective wirings selecting the plurality of memory cells are stacked, a pillar-shaped first via extending in a stack direction from a first height to a second height and having side surfaces connected to a first wiring, and a pillar-shaped second via extending in the stack direction from the first height to the second height and having side surfaces connected to a second wiring upper than the first wiring, the second wiring being thicker in the stack direction than the first wiring and having a higher resistivity than the first wiring.
US08471296B2	FinFET fuse with enhanced current crowding A method forms an eFuse structure that has a pair of adjacent semiconducting fins projecting from the planar surface of a substrate (in a direction perpendicular to the planar surface). The fins have planar sidewalls (perpendicular to the planar surface of the substrate) and planar tops (parallel to the planar surface of the substrate). The tops are positioned at distal ends of the fins relative to the substrate. An insulating layer covers the tops and the sidewalls of the fins and covers an intervening substrate portion of the planar surface of the substrate located between the fins. A metal layer covers the insulating layer. A pair of conductive contacts are connected to the metal layer at locations where the metal layer is adjacent the top of the fins.
US08471294B2	GaN-based nitric oxide sensors and methods of making and using the same GaN-based heterojunction field effect transistor (HFET) sensors are provided with engineered, functional surfaces that act as pseudo-gates, modifying the drain current upon analyte capture. In some embodiments, devices for sensing nitric oxide (NO) species in a NO-containing fluid are provided which comprise a semiconductor structure that includes a pair of separated GaN layers and an AlGaN layer interposed between and in contact with the GaN layers. Source and drain contact regions are formed on one of the GaN layers, and an exposed GaN gate region is formed between the source and drain contact regions for contact with the NO-containing fluid. The semiconductor structure most preferably is formed on a suitable substrate (e.g., SiC). An insulating layer may be provided so as to cover the semiconductor structure. The insulating layer will have a window formed therein so as to maintain exposure of the GaN gate region and thereby allow the gate region to contact the NO-containing fluid. Electrical contact pads are preferably provided in some embodiments so as to be in electrical contact with the source and drain contact regions, respectively. Electrical leads may thus be connected to the contact pads. According to other embodiments, the NO detection device will include a metalloporphyrin adsorbed on the GaN gate region.
US08471293B2	Array of mutually insulated Geiger-mode avalanche photodiodes, and corresponding manufacturing process An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
US08471292B2	Semiconductor ESD device and method of making same A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
US08471280B2	Silicone based reflective underfill and thermal coupler In one embodiment, a flip chip LED is formed with a high density of gold posts extending from a bottom surface of its n-layer and p-layer. The gold posts are bonded to submount electrodes. An underfill material is then molded to fill the voids between the bottom of the LED and the submount. The underfill comprises a silicone molding compound base and about 70-80%, by weight, alumina (or other suitable material). Alumina has a thermal conductance that is about 25 times better than that of the typical silicone underfill, which is mostly silica. The alumina is a white powder. The underfill may also contain about 5-10%, by weight, TiO2 to increase the reflectivity. LED light is reflected upward by the reflective underfill, and the underfill efficiently conducts heat to the submount. The underfill also randomizes the light scattering, improving light extraction. The distributed gold posts and underfill support the LED layers during a growth substrate lift-off process.
US08471277B2	Light emitting device A light emitting device according to one embodiment includes a light emitting element that emits light having a wavelength of 380 nm to 470 nm; a CASN first red phosphor that is disposed on the light emitting element; a sialon second red phosphor that is disposed on the light emitting element; and a sialon green phosphor that is disposed on the light emitting element.
US08471273B2	Light emitting device and manufacturing method thereof A light emitting device which includes a first TFT, a second TFT, a first pixel electrode, a second pixel electrode, an organic compound layer, a first opposing electrode and a second opposing electrode. The organic compound layer is formed on the first pixel electrode and the second pixel electrode. The first opposing electrode and a second opposing electrode are formed on the organic compound layer. When the first pixel electrode and the second opposing electrode are anodes, the second pixel electrode and the first opposing electrode are cathodes. When the first pixel electrode and the second opposing electrode are cathodes, the second pixel electrode and the first opposing electrode are anodes.
US08471270B2	Indirect-bandgap-semiconductor, light-emitting diode An indirect-bandgap-semiconductor, light-emitting diode. The indirect-bandgap-semiconductor, light-emitting diode includes a plurality of portions including a p-doped portion of an indirect-bandgap semiconductor, an intrinsic portion of the indirect-bandgap semiconductor, and a n-doped portion of the indirect-bandgap semiconductor. The intrinsic portion is disposed between the p-doped portion and the n-doped portion and forms a p-i junction with the p-doped portion, and an i-n junction with the n-doped portion. The p-i junction and the i-n junction are configured to facilitate formation of at least one hot electron-hole plasma in the intrinsic portion when the indirect-bandgap-semiconductor, light-emitting diode is reverse biased and to facilitate luminescence produced by recombination of a hot electron with a hole.
US08471269B2	Light emitting devices having roughened/reflective contacts and methods of fabricating same Light emitting devices include an active region of semiconductor material and a first contact on the active region. The first contact is configured such that photons emitted by the active region pass through the first contact. A photon absorbing wire bond pad is provided on the first contact. The wire bond pad has an area less than the area of the first contact. A reflective structure is disposed between the first contact and the wire bond pad such that the reflective structure has substantially the same area as the wire bond pad. A second contact is provided opposite the active region from the first contact. The reflective structure may be disposed only between the first contact and the wire bond pad. Methods of fabricating such devices are also provided.
US08471265B2	Epitaxial substrate with intermediate layers for reinforcing compressive strain in laminated composition layers and manufacturing method thereof Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes a (111) single crystal Si substrate, a buffer layer, and a crystal layer. The buffer layer is formed of a first lamination unit and a second lamination unit being alternately laminated. The first lamination unit includes a composition modulation layer and a first intermediate layer. The composition modulation layer is formed of a first unit layer and a second unit layer having different compositions being alternately and repeatedly laminated so that a compressive strain exists therein. The first intermediate layer enhances the compressive strain existing in the composition modulation layer. The second lamination unit is a second intermediate layer that is substantially strain-free.
US08471264B2	Method of manufacturing GaN substrate, method of manufacturing epitaxialwafer, method of manufacturing semiconductor device and epitaxialwafer Assuming that r (m) represents the radius of a GaN substrate, t1 (m) represents the thickness of the GaN substrate, h1 (m) represents a warp of the GaN substrate before formation of an epitaxialwafer, t2 (m) represents the thickness of an AlxGa(1-X)N layer, h2 (m) represents a warp of the epitaxialwafer, a1 represents the lattice constant of GaN and a2 represents the lattice constant of AlN, the value t1 found by the following expression is decided as the minimum thickness (t1) of the GaN substrate: (1.5×1011×t13+1.2×1011×t23)×{1/(1.5×1011×t1)+1/(1.2×1011×t2)}/{15.96×x×(1−a2/a1)}×(t1+t2)+(t1×t2)/{5.32×x×(1−a2/a1)}−(r2+h2)/2h=0 A GaN substrate having a thickness of at least this minimum thickness (t1) and less than 400 μm is formed.
US08471261B2	Solid-state image pickup device A solid-state image pickup device 1 is back surface incident type and includes a semiconductor substrate 10, a semiconductor layer 20 and a light receiving unit 30. The solid-state image pickup device 1 photoelectrically converts light incident on the back surface S2 of the semiconductor substrate 10 into signal electrical charges to image an object. The semiconductor substrate 10 has a resistivity ρ1. A semiconductor layer 20 is provided on the surface S1 of the semiconductor substrate 10. The semiconductor layer 20 has a resistivity ρ2. Where, ρ2>ρ1. A light receiving unit 30 is formed in the semiconductor layer 20. The light receiving unit 30 receives signal charges produced by the photoelectric conversion.
US08471260B2	Pixel structure A pixel structure disposed on a substrate having an array of pixel areas is provided. A common electrode is disposed on the substrate to surround each of the pixel areas. A capacitance storage electrode is disposed on the common electrode. A first passivation layer covers the capacitance storage electrode and the common electrode. A gate insulation layer covers the scan line and the gate electrode. A semiconductor layer is disposed on the gate insulation layer. A data line, a source and a drain are disposed in each of the pixel areas and the source and the drain are disposed on two sides of the semiconductor layer. A second passivation layer has a contact window and covers the data line, the source, and the drain. A pixel electrode is disposed in each of the pixel areas and is electrically connected with the drain through the contact window.
US08471254B2	Liquid crystal cells with uniform cell gap and methods of manufacture A laminate structure and method of manufacture, such as a processed silicon wafer with an overlying layer or cover, includes a first layer or substrate which has a generally-planar region and a peripheral contoured region with falloff from a planar region of the first layer, and a second layer which overlies the first layer and is spaced from the planar region of the first layer a uniform distance by a plurality of uniform spacers, and peripheral spacers located in the peripheral contoured region which extend from the first layer to the second layer to maintain the second layer in the same plane as it extends over the falloff of the peripheral contoured region of the first layer to increase the useable area of the laminate structure. Spherical, deformable and fixed dimension spacers are used.
US08471250B2	Display apparatus A display apparatus includes an organic electroluminescence (OEL) device and a color filter. At different correlated color temperatures (CCTs), a light emitting spectrum of the OEL device is adjusted to meet specific display requirements and improve the display quality of the display apparatus. In addition, a light filtering spectrum of the color filter is adjusted simultaneously to match the light emitting spectrum of the OEL device, so that the display apparatus has an excellent display effect.
US08471247B2	Organic light-emitting diode luminaires There is provided an organic light-emitting diode luminaire. The luminaire includes a patterned first electrode, a second electrode, and a light-emitting layer therebetween. The light-emitting layer includes a first plurality of pixels having an emission color that is blue; a second plurality of pixels having an emission color that is green, the second plurality of pixels being laterally spaced from the first plurality of pixels; and a third plurality of pixels having an emission color that is red, the third plurality of pixels being laterally spaced from the first and second pluralities of pixels.The additive mixing of all the emitted colors results in an overall emission of white light.
US08471246B2	Photoelectric conversion device and imaging device A photoelectric conversion device is provided, the photoelectric conversion device including: a pair of electrodes; a photoelectric conversion layer arranged between the pair of electrodes and containing an n-type organic semiconductor; and a charge blocking layer arranged between one of the pair of electrodes and the photoelectric conversion layer, the charge blocking layer being formed of a single layer or two or more layers, wherein a difference Δ1 between ionization potential Ip of a layer of the charge blocking layer adjacent to the photoelectric conversion layer and electron affinity Ea of the n-type organic semiconductor is at least 1 eV; and the charge blocking layer has a gross thickness of at least 20 nm.
US08471245B2	Use of sack geometry to implement a single qubit phase gate An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the υ=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two σ-quasiparticles, which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the υ=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a π/8 gate may be effected.
US08471241B2	Light emitting device, light emitting device package, and lighting system Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a light emitting structure layer, a conductive layer, a bonding layer, a support member, first and second pads, and first and second electrodes. The light emitting structure layer includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The conductive layer is disposed under the light emitting structure layer. The bonding layer is disposed under the conductive layer. The support member is disposed under the bonding layer. The first pad is disposed under the support member. The second pad is disposed under the support member at a distance from the first pad. The first electrode is connected between the first conductive type semiconductor layer and the first pad. The second electrode is connected between the bonding layer and the second pad.
US08471239B2	Light-emitting element and a production method therefor Disclosed is a light emitting device. The light emitting device includes a support substrate; a planar layer over the support substrate; a wafer bonding layer over the planar layer; a current spreading layer over the wafer bonding layer; a second conductive semiconductor layer over the current spreading layer; an active layer over the second conductive semiconductor layer; a first conductive semiconductor layer over the active layer; a first electrode layer over the first conductive semiconductor layer; and a second electrode layer over the current spreading layer.
US08471238B2	Light emitters using nanotubes and methods of making same Light emitters using nanotubes and methods of making same. A light emitter includes a nanotube article in electrical communication with a first and a second contact, a substrate having a predefined region with a relatively low thermal conductivity said region in predefined physical relation to said nanotube article; and a stimulus circuit in electrical communication with the first and second contacts. The stimulus circuit provides electrical stimulation sufficient to induce light emission from the nanotube article in the proximity of the predefined region. The predefined region is a channel formed in the substrate or a region of material with relatively low thermal conductivity. The light emitter can be integrated with semiconductor circuits including CMOS circuits. The light emitter can be integrated into optical driver circuits (on- and off-chip drivers) and opto-isolators.
US08471237B2	Circuit board including a graphene film having contact region covering a recessed region and a patterned metal film covering the contact region and in direct electrical contact therewith, and device including same A circuit board having a graphene circuit according to the present invention includes: a base substrate; a patterned aluminum oxide film formed on the base substrate, the patterned aluminum oxide film having an average composition of Al2−xO3+x (where x is 0 or more), the patterned aluminum oxide film having a recessed region whose surface has one or more cone-shaped recesses therein; a graphene film preferentially grown only on the patterned aluminum oxide film, the graphene film having one or more graphene atomic layers, the graphene film having a contact region that covers the recessed region, the graphene film growing parallel to a flat surface of the recessed region and parallel to an inner wall surface of each cone-shaped recess of the recessed region; and a patterned metal film, a part of the patterned metal film covering and having electrical contact with the contact region, the patterned metal film filling each recess covered by the graphene film.
US08471234B2	Multilayer memristive devices A multilayer memristive device includes a first electrode; a second electrode; a first memristive region and a second memristive region which created by directional ion implantation of dopant ions and are interposed between the first electrode and the second electrode; and mobile dopants which move within the first memristive region and the second memristive region in response to an applied electrical field.
US08471233B2	Semiconductor memory and method of manufacturing the same Disclosed herein is a semiconductor memory including: a first MOS transistor having two diffusion layers formed in a semiconductor substrate; a second MOS transistor which is formed in the semiconductor substrate and has one of the two diffusion layers of the first MOS transistor as a common diffusion layer for the first and second MOS transistors; and a variable resistance element which is formed between side wall insulating films formed at respective side walls of a first gate electrode of the first MOS transistor and a second gate electrode of the second MOS transistor and is connected to the common diffusion layer.
US08471232B2	Resistive memory devices including vertical transistor arrays and related fabrication methods A resistive memory device includes a vertical transistor and a variable resistance layer. The vertical transistor includes a gate electrode on a surface of a substrate, a gate insulation layer extending along a sidewall of the gate electrode, and a single crystalline silicon layer on the surface of the substrate adjacent to the gate insulation layer. At least a portion of the single crystalline silicon layer defines a channel region that extends in a direction substantially perpendicular to the surface of the substrate. The variable resistance layer is provided on the single crystalline silicon layer. The variable resistance layer is electrically insulated from the gate electrode. Related devices and fabrication methods are also discussed.
US08471221B2	Device for measuring fluorescent radiation on biological substances with a semi-conductor sensor arrangement The invention relates to a device for measuring fluorescent radiation emitted by biological substances, comprising a light source, a capturing unit, an evaluation unit, at least one emission fiber, and at least one detection fiber. Said emission fiber guides excitation radiation to the biological substrate and the detection fiber receives fluorescent radiation and guides it to the evaluation unit. The capturing unit comprises a semiconductor sensor arrangement that detects fluorescent radiation emitted by the biological substance in wave length areas that are separate from each other, are arranged. Data sets of at least two different reference measurements on at least two different biological substances are stored and compared to the measured measurement values to the stored data sets and issues a result relating to the pathological attacks of the examined biological substances and/or relating to the type of examined, biological substances.
US08471220B2	Optical analysis device, optical analysis method and computer program for optical analysis The inventive optical analysis technique uses an optical system capable of detecting light from a micro region in a solution, such as an optical system of a confocal microscope or a multiphoton microscope, to detect the light from the light-emitting particle to be observed while moving the position of the micro region in the sample solution (while scanning the inside of the sample solution with the micro region); generates time series light intensity data, and after smoothing the time series light intensity data; and detects in the smoothed time series light intensity data the light-emitting particle crossing the inside of the micro region individually, thereby enabling the counting of the light-emitting particle(s) or the acquisition of the information on the concentration or number density of the light-emitting particle.
US08471218B2	Detecting device and optical apparatus including the detecting device A detecting device includes a wavelength dispersion element for dispersing light into wavelengths and for emitting dispersed light, a photodetector for detecting the dispersed light, and a wavelength restriction element, which is arranged between the wavelength dispersion element and the photodetector and has an optical characteristic dependent on a wavelength, for restricting an incidence of light having a particular wavelength to the photodetector. Light that is part of the dispersed light and includes the light having has the particular wavelength is incident to the wavelength restriction element.
US08471217B2	Fluorescent non-metallic particles encapsulated in a metallic coating The present invention relates to a particle comprising a non-metallic core having a fluorescent material and a metallic shell encapsulating the non-metallic core wherein the metallic shell has transparency for an electromagnetic radiation having a first wavelength to excite the said fluorescent material and reflectance for an electromagnetic radiation having a second wavelength emitted by the said fluorescent material to confine the electromagnetic radiation having the second wavelength in the metallic shell. This system allows for the excitation of optical cavity modes inside the particle even at sub-micron particle size. The cavity modes are extremely sensitive to any change of the dielectric environment of the particle. This sensitivity can be used for the construction of optical nano-biosensors. Another application of the system is that of a microscopic source for spherical light waves, which may find applications in digital inline holography and display technology.
US08471216B2	Electrostatic atomizing device An electrostatic atomizing device comprises an electrostatic atomizing part (2) applying high-voltage to water supplied to an atomization electrode (1), thereby generating negatively-charged minute water particles, a positive ion generator (3) being configured to generate positive ions, and a controller (16) being configured to control operation of said electrostatic atomizing part (2) and said positive ion generator (3). Said controller (16) controls so as to cause said electrostatic atomizing part (2) to generate the negatively-charged minute water particles, after the positive ions are generated by said positive ion generator (3).
US08471208B1	Non-dispersive infrared (NDIR) gas sensor A non-dispersive infrared gas sensor provides the same light path for light used in a reference mode and a test mode for testing for the presence or concentration of one or more gases. A vacuum is formed in the light pipe in the reference mode. Gas flows into the light pipe before the test mode. The same emitter and detector maybe used for both the test and reference modes. The emitter transmits an electromagnetic wave through the light pipe in both the reference and test modes. The detected signals in both modes are compared to determine the concentration or presence of gas in the light pipe.
US08471203B2	Particle-beam microscope A particle beam microscope includes an illumination system generating a particle beam having a ring-shaped conical configuration. A selective detection system is configured to selectively detect one of two groups of particles having traversed the object region. The first group of particles includes the particles that traversed the object region un-scattered or scattered by a small scattering amount. The second group of particles includes particles scattered in the object region by a greater scattering amount.
US08471201B2	Methods and apparatus for ion sources, ion control and ion measurement for macromolecules Disclosed are methods, apparatus, systems, processes and other inventions relating to: ion sources with controlled electro-pneumatic superposition, ion source synchronized to RF multipole, ion source with charge injection, optimized control in active feedback system, radiation supported charge-injection liquid spray, ion source with controlled liquid injection as well as various embodiments and combinations of each of the foregoing.
US08471200B2	Mass spectrometer A mass spectrometer is disclosed comprising a sampling cone and a cone-gas cone wherein, in use, sulphur hexa fluoride (‘SF6’) is supplied as a cone gas to the annulus between the cone-gas cone and the sampling cone in order to improve the transmission of high molecular mass ions passing through the sampling cone into and through subsequent stages of the mass spectrometer.
US08471192B2	Safety scanner tracking dangerous objects and dynamically switching protected field configuration A safety scanner (10) is set forth for securing a monitored zone (18), wherein the safety scanner (10) has a light transmitter (12) for transmitting a light beam (14), a deflection unit (16) for the periodic deflection of the light beam (14) into the monitored zone (18), a light receiver (24) for generating received signals from the light beam (20) remitted by objects in the monitored zone (18) as well as an evaluation unit (30) which is made to recognize intrusions into a protected field within the monitored zone (18) with reference to the received signals and thereupon to provide a securing signal, except for the case that the intrusion can be associated with an expected dangerous object (40). In this respect, the evaluation unit (30) is made to track the dangerous object (40) in the protected field and to carry out the association of intrusions with the expected dangerous object (40) with reference to the contour and to the then current position, orientation and/or speed of the dangerous object (40).
US08471190B2	Vertical waveguides with various functionality on integrated circuits An embodiment relates to a device comprising an optical pipe comprising a core and a cladding, the optical pipe being configured to separate wavelengths of an electromagnetic radiation beam incident on the optical pipe at a selective wavelength through the core and the cladding, wherein the core is configured to be both a channel to transmit the wavelengths up to the selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the core. Other embodiments relate to a compound light detector.
US08471188B2	Sensor device with tilting or orientation-correcting photo sensor for atmosphere creation The present invention relates to a method and a device for controlling a physical property of light emitted from a light source. In particular, the invention can be applied to a lighting system for atmosphere creation. The measurements needed for feedback control are made at a portable user device comprising a planar photodetector. More or less all industrially available photodetectors are of the planar type, but planarity is in fact a necessary feature to achieve faithful relative measurements. Since the user device is portable, variations in the orientation of the photodetector can introduce large and unpredictable measurement errors, making effective control of the light source impossible. According to one embodiment of the invention, the orientation-dependent errors are eliminated by measuring the actual orientation of the photodetector and processing the detection signal appropriately. According to a second embodiment, the photodetector is movably mounted in the user device in order to retain its preferred orientation irrespective of the orientation of the user device. In a third embodiment, the emitted light is monitored by a plurality of photodetectors; knowing the actual orientation of the user device, the control device can give priority to the measurements coming from the best oriented photodetector at every instant.
US08471186B2	Missile guidance system In a CLOS missile guidance system, target and missile tracking data e.g. video image data are acquired on a UAV and transmitted to the missile where they are processed to provide guidance control data to the missile. Alternatively the video image data may be transmitted to a command station where the guidance control data is generated and transmitted to the missile, preferably via the UAV.
US08471185B2	Microwave oven A microwave oven is provided. Components can be easily replaced through a service opening. Therefore, rapid and easy maintenance of the microwave oven can be possible.
US08471184B2	Elevated microwave heating tray Various blanks and constructs formed therefrom are provided. The various constructs include features for supporting a food item at an elevated position to enhance the heating, browning, and/or crisping of the food item in a microwave oven.
US08471179B2	Ceramic heater Provided is a ceramic heater having enhanced joining strength between a heater section and a cylindrical metal member and having enhanced durability. A ceramic heater includes a heater section including a ceramic body and a heat-generating resistor configured to be buried in the ceramic body, a metal layer which is on part of a surface of the ceramic body and is configured to apply electric current to the heater section, and a cylindrical metal member, and inner surface of one end thereof being joined to the metal layer with a brazing material interposed therebetween, wherein the cylindrical metal member includes a brazing material restraining portion in an end face of the one end thereof, the brazing material restraining portion having lower wettability to the brazing material than that of other portions of the end face of the one end.
US08471178B2	Image heating apparatus and heater used for the image heating apparatus The image heating apparatus includes a heater having first and second and heat-generation segments each having a plurality of spaced-apart heat generating parts therein in the longitudinal direction respectively. The heat generating parts each have first and second electro-conductive patterns provided along the longitudinal direction on a substrate and overlapping in the longitudinal direction, and a heat generating resistor which electrically connects the respective overlapping regions of the first electro-conductive pattern and the second electro-conductive pattern with each other and generates heat by supplied electric power. It simultaneously prevents the temperature in a non-sheet feeding portion from rising and secures fixing properties in the gap between the adjacent heat generating parts.
US08471177B2	Heated laminated glass pane having an improved vision comfort A laminated heated glazing including at least two superposed transparent and mechanically strong substrate panes with interposition of an interlayer made of a transparent plastic between two adjacent panes. The glazing further includes, in its thickness or on the surface, at least one thin transparent conductive film that extends over at least part of the glazing, the film or films being heated for deicing and/or demisting by Joule effect, at least one film having flow separation lines formed by etching to guide current from one band to the other. The width of the flow separation lines is small enough for them to be invisible to the naked eye in the laminated heated glazing.
US08471175B2	Laser blanking from coil strip profile conveyor system A laser blanking system for cutting material stock includes a first series of conveyor lanes that include a plurality of support conveyors which are situated in parallel, generally spaced apart relationships. A second series of conveyor lanes is situated downstream from the first series. The second series includes a plurality of support conveyors situated in parallel, generally spaced apart relationships with respect to each other. The laser blanking system further includes a multiple-axis gantry system. The multiple-axis gantry includes a moveable transverse-axis component is supported by and moveable along a longitudinal-axis component that is situated adjacent to a longitudinal edge of the first and second series. A moveable laser head is supported by the transverse-axis component. A controller operatively controls movements of each one conveyor of the first and second lanes, the transverse-axis component, and the laser head as stock material is indexed downstream and supported by the system.
US08471174B2	Method for welding tip of electrode in spark plug A method of welding a noble metal tip of a spark plug to an electrode is provided. In the method of welding, in a waveform of a power of a laser beam according to a time of the laser welding, a power of a central portion thereof is smaller than those of both end portions thereof. In addition, the waveform of the power of the laser beam according to a time of the laser welding is a trapezoidal waveform which includes: a rising portion in which the power of the laser beam is gradually increased; a power maintaining portion in which the power of the laser beam after the rising portion is maintained uniform; and a falling portion in which the power of the laser beam after the power maintaining portion is gradually decreased. In addition, the waveform of the power of the laser beam according to a time of the laser welding is a triangular waveform which includes: a rising portion in which the power of the laser beam is gradually increased; and a falling portion in which the power of the laser beam after the rising portion is gradually decreased. Accordingly, it is possible to securely attach the electrode tip to a central electrode or a ground electrode.
US08471170B2	Methods and apparatus for the production of group IV nanoparticles in a flow-through plasma reactor A plasma processing apparatus for producing a set of Group IV semiconductor nanoparticles from a precursor gas is disclosed. The apparatus includes an outer dielectric tube, the outer tube including an outer tube inner surface and an outer tube outer surface, wherein the outer tube inner surface has an outer tube inner surface etching rate. The apparatus also includes an inner dielectric tube, the inner dielectric tube including an inner tube outer surface, wherein the outer tube inner surface and the inner tube outer surface define an annular channel, and further wherein the inner tube outer surface has an inner tube outer surface etching rate. The apparatus further includes a first outer electrode, the first outer electrode having a first outer electrode inner surface disposed on the outer tube outer surface. The apparatus also includes a first central electrode, the first central electrode being disposed inside the inner dielectric tube, the first central electrode further configured to be coupled to the first outer electrode when a first RF energy source is applied to one of the first outer electrode and the first central electrode; and a first reaction zone defined between the first outer electrode and the central electrode.
US08471167B2	Rough machining electroerosion method for machining a channel in a workpiece A rough machining method for machining a channel in a workpiece includes the steps of: provide a power supply to energize one of a workpiece and an electrode as an anode and the other as a cathode; advance the electrode into the workpiece from a first start point to travel a first toolpath, so as to generate a first annular groove with a first core connecting with the workpiece; advance the electrode into the workpiece from a second start point to travel a second toolpath, so as to generate a second annular groove with a second core connecting with the workpiece, wherein the second annular groove intersects with the first annular groove and the first and the second cores are at least partially broken and disconnected with the workpiece upon intersecting of the first and the second annular grooves; and circulating a cutting fluid cross a working gap between a working face of the electrode and the workpiece.
US08471164B2	Capacitive switch A capacitive switch (1) comprising a housing frame (2), a thin-walled cover plate (3) held thereon, a printed circuit board (4) with a copper layer (6) that generates a capacitive field (7) applied to a surface (5) of the circuit board (4) that faces the cover plate (3), the copper layer (6) being connected to an inside surface (8) of the cover plate (3), the capacitive switch (1) being adapted to ensure that electrical devices can be operated safely, in that changes in the capacitive field (7) are picked up by the switch (1) in a redundant manner. At least two sensor surfaces (17, 17′, 18, 18′) are disposed in the circuit board (4), and are each electrically connected via an integrated circuit (11, 12) to a microcontroller control and evaluation unit, and the circuit board (4) functions as an insulation between the copper layer (6) and the sensor surfaces (17, 17′, 18, 18′), and both integrated circuits (11, 12, 11′, 12′) are controlled alternately by the microcontroller (13) for measuring the capacitive field (7) of the copper layer (6).
US08471162B2	Switching device for low voltage systems The present invention relates to a switching device for low voltage systems comprising one or more accessory devices. The switching device according to the invention comprises a case containing at least one pair of contacts that can be reciprocally coupled/decoupled. The device furthermore comprises a containment structure to contain at least one accessory device of the switching device. Said structure is provided with means for interfacing with the accessory device which comprises a body that can be inserted in the containment structure. The accessory device also comprises coupling means to couple it to the containment structure and operating means which interact with the switching device via the interface means of the containment structure. The accessory device is also provided with disengagement means operatively connected to the coupling means. Said disengagement means, once activated, free the coupling means to permit extraction of the accessory device from the containment structure.
US08471161B2	Rolling-ball switch A rolling-ball switch includes a surrounding wall defining an axial hole and including two opposite open ends, and two metallic terminals plugged in the axial hole respectively from the open ends. The surrounding wall has an inner surface formed with two spaced-apart first annular recesses proximate to the open ends, respectively, and two spaced-apart second annular recesses respectively adjacent to the first annular recesses but distal from the respective open ends. Each terminal has an insert portion inserted into the axial hole, and axially spaced-apart first and second barbed surfaces formed annularly around the insert portion. The first barbed surface is engaged to a respective first annular recess. The second barbed surfaces of the metallic terminals are engageable respectively with the second annular recesses when the terminals expand due to heat. A ball member is disposed rollably in the axial hole to contact the terminals.
US08471159B2	Undercarriage and keylock assembly for use with a circuit breaker An undercarriage for use with a circuit breaker includes a bottom plate, a front beam removably coupled to the bottom plate via a lead screw, wherein the lead screw is configured to engage with a threaded support that is coupled to the bottom plate to facilitate racking the circuit breaker in a switchgear. The undercarriage also includes a keylock assembly configured to enable racking the circuit breaker in the switchgear. The keylock assembly includes a lock and an interlock configured to couple to the lock such that the interlock is movable between a locked position and an unlocked position, wherein engagement of a racking handle with the lead screw is enabled when the interlock is in the unlocked position.
US08471158B2	Power seat switch assembly A switch assembly is provided that includes a series of bridge actuators that include oppositely spaced protrusions separated by a bridge. The protrusions extend through apertures in a support that provides a sliding surface for overlying actuator plates. The actuator plates include ramps to act on the protrusions and in turn activate underlying dome switches. The bridge actuators utilize an angled underside to provide better alignment with the top surface of the dome to reduce shearing. The switch assembly also includes a sub-assembly that uses a micro switch cell in a knob instead of a PCB to reduce the number of connections. The sub-assembly uses an elastomeric keypad to preload a button on the knob and provide tactile feel. The switch assembly also includes a four-way knob that provides distinct feel to the directions of movement using a contoured male-female connection that uses tabs and slots, a contoured female connection and a protrusion on the tip of the male connector.
US08471157B2	EMI shielding device and container data center using the same A container data center includes a container defining a wire hole therein, a cable extending through the wire hole of the container, and an EMI shielding device preventing electromagnetic radiation from entering into the container from the outside environment or leaking from the container to the outside environment through the wire hole of the container. The EMI shielding device includes a metal cylinder through which the cable extends and an effective amount of metal powder packed between the metal cylinder and the cable for shielding EMI. The metal cylinder has an end thereof inserted into the wire hole of the container and engaged with a circumferential edge of the wire hole. The disclosure further relates to an EMI shielding device.
US08471156B2	Method for forming a via in a substrate and substrate with a via The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method includes the following steps: (a) providing a substrate; (b) forming a groove on a first surface of the substrate; (c) forming a conductive metal on the groove so as to form a central groove; (d) forming an annular groove that surrounds the conductive metal; (e) forming an insulating material in the central groove and the annular; groove; and (f) removing part of the substrate to expose the conductive metal and the insulating material.
US08471153B2	Multilayer printed wiring board including a capacitor section A multilayer printed wiring board includes a core substrate, a resin insulation layer laminated on the core substrate and a capacitor section coupled to the resin insulating layer. The capacitor section includes a first electrode including a first metal and configured to be charged by a negative charge, and a second electrode including a second metal and opposing the first electrode, the second electrode configured to be charged by a positive charge. A dielectric layer is interposed between the first electrode and second electrode, and an ionization tendency of the first metal is larger than and ionization tendency of the second metal.

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