| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 实现削峰和数字预失真相互补偿的系统及方法 | CN200810085784.7 | 2008-03-20 | CN101247154B | 2012-07-11 | 戴征坚; 邓英; 茹洪涛 |
| 本发明公开了一种实现削峰和数字预失真相互补偿的系统，该系统包括削峰(CFR)设备和数字预失真(DPD)设备，该系统还包括CFR和DPD综合处理设备，用于对所述CFR设备和所述DPD设备所处理的信号进行控制和优化处理，实现CFR设备和DPD设备所处理的信号之间的相互补偿。本发明还公开了一种实现削峰和数字预失真相互补偿的方法。采用本发明的系统及方法，使采用CFR设备和DPD设备所处理的信号之间实现相互补偿，利用CFR设备和DPD设备的处理存在逆关系的原理，降低CFR设备对信号的不可恢复性损伤，从而有效地实现信号峰均比的降低，提高功放效率的同时也提高了功放的线性。 | ||||||
| 2 | 固体发酵及其产品回收设备 | CN86108383 | 1986-12-12 | CN86108383A | 1988-07-06 | 莫锡荣 |
| 本发明提供了一种按生产过程设计、竖直安装的整体式、密闭型固体发酵及其产品回收设备。它适用于酒、酱油、醋、曲、柠檬酸及类似发酵酿造产品的生产。它不仅将现有的加料、发酵、回收、排渣四个单独的生产装置按生产过程设计安装在一整体设备中，而且将现有的四个离散的加工过程变为一连续的生产过程。从而改善了劳动条件和降低了劳动强度，节省了设备投资，提高了产品的质量。 | ||||||
| 3 | 实现削峰和数字预失真相互补偿的系统及方法 | CN200810085784.7 | 2008-03-20 | CN101247154A | 2008-08-20 | 戴征坚; 邓英; 茹洪涛 |
| 本发明公开了一种实现削峰和数字预失真相互补偿的系统，该系统包括削峰(CFR)设备和数字预失真(DPD)设备，该系统还包括CFR和DPD综合处理设备，用于对所述CFR设备和所述DPD设备所处理的信号进行控制和优化处理，实现CFR设备和DPD设备所处理的信号之间的相互补偿。本发明还公开了一种实现削峰和数字预失真相互补偿的方法。采用本发明的系统及方法，使采用CFR设备和DPD设备所处理的信号之间实现相互补偿，利用CFR设备和DPD设备的处理存在逆关系的原理，降低CFR设备对信号的不可恢复性损伤，从而有效地实现信号峰均比的降低，提高功放效率的同时也提高了功放的线性。 | ||||||
| 4 | 低相移限幅器 | CN86108386 | 1986-12-13 | CN86108386A | 1988-07-06 | 张九愚; 陈玉英 |
| 本发明涉及一种宽频带低相移的限幅器。该限幅器的特征是在差分放大器的发射极之间分别接入晶体二极管，以便抑制工作于非饱和开关状态下晶体管的容性馈通信号，减小输入、输出信号间的相位差，改善调幅——调频转换效应，提高输出信噪比。该限幅器可广泛应用于调频制雷达接收机、微波通信接收机、卫星广播电视接收机、无线电定位和电子测量仪器的中频放大器中。 | ||||||
| 5 | LIMIT CIRCUIT | PCT/JP2001/011185 | 2001-12-20 | WO02052737A1 | 2002-07-04 | |
| A limit circuit capable of providing high gain. The limit circuit included in an FM receiver comprises, for example, seven amplifiers (11 to 17), and a BPF (18) inserted substantially in the middle thereof. Each of the amplifiers (11 to 17) operates as a differential amplifier, and has a gain of about 13 dB. The BPF (18) serving as a limit circuit passes components in a bandwidth wider than the bandwidth of the signal to be amplified. The level of 1/f noise and heat noise can be reduced by eliminating low-frequency components and high- frequency components of the signal amplified by the four amplifiers (11 to 14), respectively. Therefore, each of the amplifiers (15 to 17) connected to the rear end of the BPF (18) is not saturated by the noise component. | ||||||
| 6 | An FM intermediate-frequency circuit | EP89109186.0 | 1989-05-22 | EP0343569B1 | 1994-03-23 | Nyqvist, Jouni |
| 7 | METER DRIVE CIRCUIT. | EP83901981 | 1983-04-25 | EP0109430A4 | 1984-09-06 | MAIN WILLIAM ERIC |
| 8 | FM TVRO RECEIVER WITH IMPROVED OSCILLATING LIMITER | PCT/US1986000622 | 1986-03-26 | WO1986005937A1 | 1986-10-09 | CINCINNATI MICROWAVE, INC.; WASHBURN, Clyde, Jr. |
| An improved FM receiver (10) incorporating improved oscillating limiter circuitry having an electrically tunable bandpass filter (54) which is phase modulated by the baseband signal the phase of which has been advanced in accordance with formula (I), wherein td1? equals the time delay through the limiter (46), td2? equals the time delay through the feedback filter (54), td3? equals the time delay through the demodulator (52) and fn? equals the frequency of the respective baseband components. | ||||||
| 9 | A METHOD AND APPARATUS FOR LIMITING THE AMPLITUDE OF A FREQUENCY MODULATED SIGNAL | PCT/GB1985000437 | 1985-09-20 | WO1986001952A1 | 1986-03-27 | INDEPENDENT BROADCASTING AUTHORITY |
| Amplitude limiting of a frequency modulated signal, in particular a sampled signal such as a multiplexed analogue component television signal, in order to reduce the bandwidth taken up by the signal. A number of problems arise when applying limiting to a signal, in particular limiting especially a sampled signal can produce aliasing effects due to harmonics. Also if any filtering is applied to the signal after limiting much of the effect of the limiting is removed. The present invention overcomes these problems by applying differing degrees of limiting to the signal depending upon the frequency being limited at a particular time. In one embodiment the signal is filtered prior to the application of limitation, so that more of some frequencies are allowed to pass through to the limiter than others. A post-filter is applied to the signal after limitation to correct for the effects of the pre-filter. | ||||||
| 10 | An FM intermediate-frequency circuit | EP89109186.0 | 1989-05-22 | EP0343569A3 | 1990-08-22 | Nyqvist, Jouni |
An FM intermediate-frequency circuit into which there is integrated at least a limiter-amplifier (1A), a level detector included in the amplifier, and a phase-locked loop (2, 3, 4) which contains a VCO (4). A large dynamic range of the level detector is obtained without having to use excessive limiter-amplifier amplification, which would cause oscillation problems. In parallel with the said limiter-amplifier (1A) is at least a second limiter-amplifier (1B), in connection with which there is also a level detector. By means of a dividing circuit (R1, R2) the level of the input signal of the second limiter-amplifier (1B) is dropped. The signals (1A, 1B) obtained from the level detectors are combined to form one level detection signal (ITOT). If the signals are in the form of current, the combining can be carried out directly by summating the signals. |
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| 11 | FM TVRO RECEIVER WITH IMPROVED OSCILLATING LIMITER. | EP86904995 | 1986-03-26 | EP0224585A4 | 1989-05-16 | WASHBURN CLYDE JR |
| 12 | Level detector for use with a differential amplifier circuit | EP84105569.2 | 1984-05-16 | EP0126427B1 | 1988-03-30 | Hashimoto, Masaru |
| 13 | Level detector for use with a differential amplifier circuit | EP84105569.2 | 1984-05-16 | EP0126427A2 | 1984-11-28 | Hashimoto, Masaru |
@ Disclosed is a level detector in a differential amplifier circuit (21) in an amplitude-limiting amplifying system for angle-modulation signal amplification. The differential amplifier circuit (21) is made up of differentially paired transistors (Q1, Q2). The level detector (24) contains first and second transistors (Q7, Q8) which form a differential pair. In the first transistor (Q7), the base is connected to an interjunction of the emitters of the differentially paired transistors (Q1, Q2). A second transistor (Q8) is connected at the emitter to the emitter of the first transistor (07). A current source (13) is connected to the emitter interjunction of the first and second transistors (Q7, Q8). A bias circuit (25) applies a predetermined bias potential to the base of the second transistor (Q8). An output signal containing the detected level information of the input signal is derived from the collector of the first or second transistor (Q7, Q8). |
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| 14 | An FM intermediate-frequency circuit | EP89109186.0 | 1989-05-22 | EP0343569A2 | 1989-11-29 | Nyqvist, Jouni |
An FM intermediate-frequency circuit into which there is integrated at least a limiter-amplifier (1A), a level detector included in the amplifier, and a phase-locked loop (2, 3, 4) which contains a VCO (4). A large dynamic range of the level detector is obtained without having to use excessive limiter-amplifier amplification, which would cause oscillation problems. In parallel with the said limiter-amplifier (1A) is at least a second limiter-amplifier (1B), in connection with which there is also a level detector. By means of a dividing circuit (R1, R2) the level of the input signal of the second limiter-amplifier (1B) is dropped. The signals (1A, 1B) obtained from the level detectors are combined to form one level detection signal (ITOT). If the signals are in the form of current, the combining can be carried out directly by summating the signals. |
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| 15 | Dispostif amplificateur-limiteur à large bande | EP84402366.3 | 1984-11-20 | EP0145568B1 | 1989-05-31 | Corlieu, Patrick; Bursztejn, Jacques |
| 16 | FM RECEIVER. | EP86903723 | 1986-03-26 | EP0217952A4 | 1989-03-22 | WASHBURN CLYDE JR |
| 17 | Level detector for use with a differential amplifier circuit | EP84105569 | 1984-05-16 | EP0126427A3 | 1985-08-28 | Hashimoto, Masaru |
@ Disclosed is a level detector in a differential amplifier circuit (21) in an amplitude-limiting amplifying system for angle-modulation signal amplification. The differential amplifier circuit (21) is made up of differentially paired transistors (Q1, Q2). The level detector (24) contains first and second transistors (Q7, Q8) which form a differential pair. In the first transistor (Q7), the base is connected to an interjunction of the emitters of the differentially paired transistors (Q1, Q2). A second transistor (Q8) is connected at the emitter to the emitter of the first transistor (07). A current source (13) is connected to the emitter interjunction of the first and second transistors (Q7, Q8). A bias circuit (25) applies a predetermined bias potential to the base of the second transistor (Q8). An output signal containing the detected level information of the input signal is derived from the collector of the first or second transistor (Q7, Q8). |
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| 18 | Broad-band amplifiying and limiting device | EP84402366 | 1984-11-20 | EP0145568A3 | 1985-07-10 | Corlieu, Patrick; Bursztejn, Jacques |
| 19 | Dispostif amplificateur-limiteur à large bande | EP84402366.3 | 1984-11-20 | EP0145568A2 | 1985-06-19 | Corlieu, Patrick; Bursztejn, Jacques |
Le dispositif amplificateur-limiteur est destiné à amplifier, jusqu'à une valeur prédéterminée, un signal reçu. Il comporte 2n circuits intégrés, montés en série, du type récepteurs de ligne de la famille à couplage par les émetteurs (appelés dans la littérature anglo-saxonne, emitter coupled logic ou E.C.L.); ces circuits intégrés forment n paires successives (1-2, 3-4) et à chaque paire est associé un circuit de compensation (L1 - L2 - C1- C2 - L1' - L2' - C1' - C2') pour compenser la distorsion linéaire amenée par les circuits intégrés de la paire. Application, en particulier, dans les récepteurs à large bande des faisceaux hertziens. |
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| 20 | 바이플레나 테이퍼된 라인 주파수 선택 리미터 | KR1020207026755 | 2019-05-10 | KR1020200118884A | 2020-10-16 | |
