Scanning apparatus for a matrix display panel
阅读：36发布：2022-03-14
专利汇可以提供Scanning apparatus for a matrix display panel专利检索，专利查询，专利分析的服务。并且A scanning apparatus for a matrix display panel having a plurality of picture elements at the intersections of X- and Yline conductors. The scanning apparatus has an X-line driving circuit, Y-line driving circuit, a video signal generator, a timing signal generator, a width control signal generator, a second switching circuit and an analog-to-digital converter. The Y-line driving circuit has a plurality of sets of first memory circuits, a set of second memory circuits, a set of first switching circuits, and a set of brightness control circuits. The scanning apparatus is capable of reproducing moving images having many steps of gray scale from coded video signals having relatively few bits by digital circuits and is also capable of finely controlling the brightness by the efficient use of a horizontal sweep retrace period of the video signals with simplified circuits.，下面是Scanning apparatus for a matrix display panel专利的具体信息内容。
1. A scanning apparatus for a matrix display panel having a plurality of picture elements at the intersections of X- and Yline conductors, said scanning apparatus comprising: an X-line driving circuit coupled to said X-line conductors for supplying X-line selecting pulses to the X-line conductors to be scanned in predetermined sequence; a Y-line driving circuit coupled to said Y-line conductors; a video signal generator for generating video signals; a timing signal generator coupled to said video signal generator, said X-line driving circuit and said Y-line driving circuit; a width control signal generator coupled to said timing signal generator for generating a plurality of sets of width control signals; a second switching circuit coupled between said width control signal generator and said Y-line driving circuit for selectinG one of said plurality of sets of width control signals and supplying the width control signals thereof to said Y-line driving circuit; and an analog-to-digital converter coupled between said video signal generator and said Y-line driving circuit for converting said video signals into parallelcoded video signals which are supplied to said Y-line driving circuit, and wherein said Y-line driving circuit comprises: a plurality of sets of first memory circuits for sequentially writing said parallel-coded video signals for one horizontal line period; a set of second memory circuits for holding parallelcoded video signals which are supplied from one of said sets of first memory circuits; a set of first switching circuits coupled between said plurality of sets of first memory circuits and said set of second memory circuits for connecting one of said plurality of sets of first memory circuits at a time to said set of second memory circuits; and a set of brightness control circuits coupled between said second memory circuits and said Yline conductors for supplying Y-line driving pulses to said Yline conductors, whereby both of said set of first switching circuits and said second switching circuit are switched a plurality of times during one horizontal line period in synchronization with switching signals from said timing signal generator so that said Y-line driving pulses are changed a plurality of times during one horizontal line period in response to both said sets of width control signals and said parallelcoded video signals held in said set of second memory circuits.
2. A scanning apparatus as claimed in claim 1, wherein said timing signal generator is coupled to both said set of first switching circuits and said second switching circuit and comprises means for generating a switching signal for switching said switching circuits a plurality of times during the time from the end of writing of said parallel-coded video signals into said plurality of sets of first memory circuits to the end of the horizontal sweep retrace period of said video signals.
3. A scanning apparatus as claimed in claim 2, wherein said parallel-coded video signals are composed of least significant signals and most significant signals, said least significant signals being held in said set of second memory circuits during the time from the end of writing of said parallel-coded video signals into said plurality sets of first memory circuits to the end of horizontal sweep retrace period of said video signals, and said most significant signals of said parallel-coded video signals being held in said set of second memory circuits during the remaining time interval of one horizontal line period.
4. A scanning apparatus as claimed in claim 1, wherein said scanning apparatus further comprises a plurality of delay circuits coupled between said analog-to-digital converter and said plurality of sets of first memory circuits which have different delay times from each other which are an integral multiple of one horizontal line period within one field period, some sets of said plurality of sets of first memory circuits being directly coupled to said analog-to-digital converter, the remaining sets of said plurality of sets of first memory circuits are coupled to said analog-to-digital converter through said plurality of delay circuits, whereby said X-line driving circuit supplies a plurality of X-line selecting pulses to a plurality of X-line conductors to be scanned during one horizontal line period in response to the delay time of corresponding delay circuits in synchronization with said switching signals from said timing signal generator.
5. A scanning apparatus as claimed in claim 4 in which said parallel-coded video signals are composed of least significant signals and most significant signals, said some sets of said plurality of sets of first memory circuits into which said least significant signals are written being directly connected to said analog-to-digital converter, and the remaindEr of said sets of said plurality of sets of first memory circuits being connected to said analog-to-digital converter through said delay circuits, whereby the most significant signals of said parallel-coded video signals are written into the sets of said plurality of sets of first memory circuits through said delay circuits.
| 标题 | 发布/更新时间 | 阅读量 |
|---|---|---|
| 实现离散节点间工频信号相位同步检测系统及监测方法 | 2020-05-11 | 649 |
| 一种纵轴磁悬浮导向控制无差别风力发电系统 | 2020-05-11 | 981 |
| 一种超声波高压发生系统及方法 | 2020-05-12 | 188 |
| 一种人机协同模拟演练系统及其方法 | 2020-05-13 | 563 |
| 一种基于探测信号的3D成像与人体识别方法 | 2020-05-12 | 323 |
| 一种储罐底部油品泄漏的监测装置及监测方法 | 2020-05-14 | 1003 |
| 在分解的密集波分复用系统的一致性检查的方法和装置 | 2020-05-14 | 73 |
| 非易失性存储装置及非易失性存储装置的操作方法 | 2020-05-13 | 158 |
| 一种基于OCC系统的二维星座辅助CSK传输系统 | 2020-05-12 | 119 |
| 一种基于多芯光纤传感的多参量同步传感采集仪 | 2020-05-08 | 232 |
高效检索全球专利专利汇是专利免费检索,专利查询,专利分析-国家发明专利查询检索分析平台，是提供专利分析，专利查询，专利检索等数据服务功能的知识产权数据服务商。
我们的产品包含105个国家的1.26亿组数据，免费查、免费专利分析。
分析报告
专利汇分析报告产品可以对行业情报数据进行梳理分析，涉及维度包括行业专利基本状况分析、地域分析、技术分析、发明人分析、申请人分析、专利权人分析、失效分析、核心专利分析、法律分析、研发重点分析、企业专利处境分析、技术处境分析、专利寿命分析、企业定位分析、引证分析等超过60个分析角度，系统通过AI智能系统对图表进行解读，只需1分钟，一键生成行业专利分析报告。
QQ群二维码
意见反馈
意见反馈