The invention relates to a sigma-delta modulator for converting an input signal into a 1-bit digital output signal, comprising:

• - a low-pass filter constituted by a series connection of first, second and third sections having at least first order filter functions, each section having an input and having an output for producing respective first, second and third section signals,
• - quantisation means for converting the third section signal into the 1-bit digital output signal and for producing first and second feedback signals in response to the digital output signal,
• - a first subtractor stage for producing a first differential signal from the second section signal and the first feedback signal and for applying the first differential signal to the input of the third filter section,
• - a second subtractor stage for producing a second differential signal from the input signal and the second feedback signal and for applying the second differential signal to the input of the first filter section,
• - coupling means for coupling the first section signal to the input of the second filter section.

Such a sigma-delta modulator (SDM) is known from "A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping", IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 6, December 1987, pp. 921-928. Sigma-delta modulation is a technique in which an analog signal is made into a digital signal having high resolution and low quantisation noise with the aid of oversampling by quantisation means having low resolution and high quantisation noise. The digital signal is reconverted to an analog feedback signal by means of a digital-to-analog converter having the same low resolution and is subtracted in a subtracting stage from the analog input signal. The difference between the two signals is filtered in an analog loop filter and applied to the quantisation means. The use of a sufficiently high loop gain for baseband frequencies of the analog signal achieves that in the digital signal the quantisation noise within the baseband is low at the expense of a higher quantisation noise above this baseband. By means of digital filter techniques, however, noise above the baseband can be suppressed effectively, for example, by means of a decimating filter that converts the oversampled 1-bit digital signal into a multi-bit digital signal at the desired lower sampling rate.

Sigma-delta modulation to a 1-bit digital signal is advantageous in the simplicity of the quantisation means. A simple decision circuit having an inherently good linearity will then be sufficient, while the associated digital-to-analog converter may be omitted. The attainable signal-to-noise ratio in the 1-bit digital signal is determined, for example, by the extent of oversampling and the order of the loop filter. A higher order loop filter is advantageous because it admits a lower oversampling rate while a specific signal-to-noise ratio in the baseband is maintained. The order of the loop filter is limited in practice by stability problems. In the prior art SDM from aforementioned article, third-order loop filters are used comprising a cascade connection of three first-order high-gain active integrators. With these third-order filters satisfactory results can be achieved when digitizing audio signals in which the signal-to-noise ratio is so high that a 16-bit resolution in the ultimate digital audio signal is attainable. This requires oversampling rates of several MHz.

For digitizing the video signals in above manner, the prior art 1-bit modulators fail due to the much higher oversampling rate needed. For a digital video signal having 10-bit resolution a 32-fold oversampling rate of 432 MHz will be necessary if a third order loop filter is utilised. At such high sampling rates, however, the customary implementations of third order loop filters comprising the so- called switched capacitor filters and also RC-active filters will fail, because such filters can no longer proces these rates as a result of parasitic influences. The loop gain at the high oversampling rate (clock signal frequency) becomes unpredictable so that nothing will come of the intended third order filter characteristic.

It is an object of the invention to provide a 1-bit SDM which can also be used at very high oversampling rates.

According to the invention a sigma-delta modulator of the type mentioned in the preamble is therefore characterized in that the first and third filter sections as regards the signal frequencies are arranged as passive networks and in that the second filter section is arranged as an active filter stage.

This SDM has two negative feedback loops. The first loop feeds back the digital signal to the quantisation means via the first subtractor stage and the passive third filter section. The second loop feeds back the digital signal to the quantisation means via the second subtractor stage, the passive first filter section, the active second filter section, the first subtractor stage and the passive third filter section. The loop gain in the second loop is high for frequencies in the baseband of the input signal and determines the accuracy of digital approximation of the input signal. With the applied very high sampling rate the spectrum of the feedback signal is very wide and extends to several times the sampling rate. These very high rates are suppressed in the passive first filter section and the remaining lower signal frequencies can further be amplified and conveyed to the third filter section by the active filter section without causing any problems.

The first loop only comprising the passive third filter section determines the behaviour of the SDM at high frequencies. For these high frequencies no high loop gain but still a small phase shift is necessary to maintain system stabilisation, which is only possible by implementing a passive filter section.

A further embodiment of a SDM according to the invention is characterized in that the quantisation means comprise

• - a first latch for measuring the third section signal during a first phase of a clock signal and for producing a first latched signal during a second phase of the clock signal,
• - a second latch for measuring the first latched signal during the first phase of the clock signal and for producing a second latched signal during the second phase of the clock signal, the first and second latched signals functioning as the first and second feedback signals respectively.

The 1-bit quantisation means decide whether the filtered signal is larger or smaller than a certain reference. An accurate digital signal needs a very sensitive decision switch having little signal crosstalk and a very large bandwidth in view of the very high oversampling rate at which the decision switch is clocked. By arranging the decision switch as two cascaded latches a high sensitivity and low signal crosstalk is achieved which, however, at very high clock rates is attended with additional undesired phase shift. Therefore, according to the invention the latched signal of the second cascaded latch is only used as the second feedback signal for the second loop in which the undesired additional phase shift at very high frequencies does not play any role but in which, nevertheless, a high sensitivity and reliability at the low baseband frequencies is necessary. The latched signal of the first cascaded latch is only used as the first feedback signal for the first loop in which the still relatively low sensitivity of the first latch is of minor importance, because in this first loop a much smaller loop gain is necessary. This first feedback signal, however, has less phase shift at high frequencies so that the phase margin of the system is wider and the stability of the system is enhanced.

If so desired, the loop filter can be made steeper so that the signal-to-noise ratio increases and an even higher bit resolution is attainable.

Yet another embodiment of a SDM according to the invention is characterized in that the modulator further includes at least one mixer stage for replacing during the first phase of the clock signal the instantaneous value of one of the first and second latched signals with a fixed signal value that is independent of this instantaneous value.

By exchanging the first and/or second feedback signal during the first phase of the clock signal, preceding the latching phase, for a fixed signal value it is achieved that the signal shape of the feedback signals is independent of the output signals of the latches during the first phase of the clock signal. During the first phase these output signals are determined by the amplitude of the input signal applied to the latch. Due to the finite gain and bandwidth of the latches the output signals show a constantly changing variation of the signal shape that depends on the instantaneous value of the input signal applied to the latch. This causes undesired non-linear crosstalk of this input signal to the feedback loops and causes an undesired error in the digital output signal. This very error is reduced by the mixer stages.

The invention will now be further explained with reference to the appended drawing, in which:

• Fig. 1 shows a first block diagram of a sigma-delta modulator according to the invention;
• Fig. 2 shows a graph of the frequency characteristic of a third-order loop filter of a sigma-delta modulator;
• Fig. 3 shows a second block diagram of a sigma-delta modulator according to the invention;
• Fig. 4 shows the signal shapes in a mixer stage of the block diagram shown in Fig. 3;
• Fig. 5 shows a circuit diagram of a mixer stage in a sigma-delta modulator according to the invention;
• Fig. 6 shows a circuit diagram of a latch that can suitably be used in a sigma-delta modulator according to the invention; and
• Fig. 7 shows a circuit diagram of an embodiment of a sigma-delta modulator according to the invention.

Fig. 1 shows the block diagram of a 1-bit sigma-delta modulator (SDM) according to the invention. An input voltage Vi to be digitized is applied to input terminal 1 and common terminal 2 and converted by means of a voltage-to-current converter 3 into an input current li to be applied to a current summation point 4 which is connected to the common terminal 2 across a passive first-order impedance 5. The voltage-to-current converter 3 can be omitted if the input signal to be digitized is already available as a current. The passive first-order impedance 5 has a complex impedance Z1-(p). The signal voltage across impedance 5 is connected to the input of an active first-order filter section 6 having complex admittance Y₂(p). This section has a high gain and an inbuilt voltage-to-current converter so that the output signal of filter section 6 is again available as a signal current. The output current of filter section 6 flows to a second current summation point 7 connected to the common terminal 2 across a passive first-order filter impedance 8 having complex impedance Z3(p). The voltage across impedance 8 is connected to the input of a decision switch 10 in which a decision is made under the control of a clock signal CL on control input 11 as to whether this voltage is larger or smaller than a specific reference. The result of this decision is available as a digital output signal at the outputs 12, 13 and 14 of the decision switch 10. Two of these digital output signals, that is to say, those at the outputs 13 and 14, function as first and second feedback signals and are available as a current lo and are fed back to the current summation points 7 and 4 respectively. The third digital output signal at output 12 of decision switch 10 is available as a voltage Vo on an output terminal 15, but may as well be realised as considered a current source.

The circuit acts as a SDM comprising a third-order loop filter around the decision switch 10. Fig. 2 shows in a diagrammatic manner the frequency characteristic of the loop filter. The loop gain for low frequencies situated in the baseband B of the input signal is large. The loop gain decreases with increasing frequency according to a slope determined by the order of the loop filter and subsequently becomes constant again around the clock rate fcl. The phenomenon of negative feedback achieves that the quantisation noise in the digital output signal is small in the baseband B and increases for higher frequencies (noise shaping). Suppression of the quantisation noise in the digital output signal is proportional to the loop gain in the baseband B. In order to achieve the optimum result a high loop gain in the baseband B and a steep transfer to a lower gain for frequencies exceeding B are desired. In order to avoid stability problems in the feedback system, in practice the order of the loop filter determining the slope of the transfer are chosen not to be greater than three. Very high oversampling rates (clock rates) are necessary in a 1-bit SDM for video signals. A digital video signal having 10-bit resolution requires a clock rate fcl of, for example, 432 MHz when a third-order loop filter and 32-bit oversampling is used. At such high frequencies the third-order SDM's customary thus far will no longer function. A published in, for example, "A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping" IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 6, December 1987, pp. 921-928, the prior art third-order loop filters are constituted by a cascade connection of three active high-gain first-order integrators. Such active filters cannot cope with the very high rates involved in oversampling the video signals. This problem is solved by means of the SDM as shown in Fig. 1. The overall third-order transfer function H(P) of the loop filter is determined here by a cascade connection of a passive first-order filter section 5, an active first-order filter section 6 and a passive first order filter section 8 with a feedback of the digital output signal lo to the summing points 4 and 7. The general shape of the third order loop gain H(P) is:

where K is a constant value, z_; is the zeroes and p_; the poles of H(p).

This formula can be reduced to:

The digital output signal passes through two loops in accordance with formula (2). The first loop comprises output 13 of the decision switch 10, summation point 7 and the passive first order impedance 8 which has a zero z₃ and a pole _P3. The second loop comprises output 14 of the decision switch 10, summation point 4, the passive first order impedance 5 with a pole pi, the active first order admittance Y₂ (p) of section 6 with a pole p₂ and a suitably selected zero. This third order loop filter does function at very high clock rates because the active section 6 need not amplify the very high frequencies as they have been filtered out by the passive impedance 5 operating smoothly with these frequencies. The active filter section 6 now in essence needs to amplify the frequencies of the baseband B of the input signal. This is attainable with advanced video amplifier stages. The second loop thus contributes to the overall loop gain only for the low frequency range and determines by means of a high gain in the baseband the accuracy with which the digital output signal approaches the input signal. For a 10-bit resolution in the 1-bit oversampled signal the necessary baseband gain is approximately 60 to 70 dB more than at high frequencies. The first loop contributes to the overall loop gain for the entire frequency range of which, however, the area above the baseband is most important. For this matter, due to the relatively low loop gain for the baseband B in the first loop with respect to the second loop, only the higher frequencies above the baseband play a role in the first loop. The first loop comprises the decision switch 10 and the passive impedance 8 and is suitable for very high frequencies due to the simplicity of the loop components so that parasitic phase shift can be avoided. Therefore the feedback system remains stable even with very high frequencies.

Fig. 3 shows a block diagram of a second embodiment of a 1-bit SDM according to the invention. Components having like reference numerals in Fig. 3 correspond to those shown in Fig. 1. The decision switch 10 is now arranged as a cascade connection of a first latch L1 whose input is connected to summation point 7, and a second latch L2 whose input is connected to the output of the first latch L1. The two latches are clocked with the same clock signal at the control input 11 of the decision switch 10. During a first phase of the clock signal CL, for example, when the clock signal is high, the latches amplify the difference between the signal at their inputs and a reference. During a second phase of the clock signal CL, for example, when the clock signal is low, the amplified signal is regeneratively amplified and latched. Due to the finite gain of the latches at very high frequencies the latched signal of the first latch L1 is still rather inaccurate, but that of the second latch L2 is sufficiently accurate due to the increased gain and the longer decision time. However, the main point of the latched signal of the second latch L2 has an overall delay of 3/4 clock period relative to the decision instant occurring in the first latch L1 a half clock period earlier. This delay is undesired for high frequencies because this is at the cost of the high-frequency phase margin which is very narrow as it is. According to the invention the output signal of the first latch L1 is used as a first feedback signal for output 13 and the output signal of the second latch L2 is used as a second feedback signal for output 14 of the decision switch 10. The first feedback signal at output 13 is relatively inaccurate it is true, but this is of minor importance in the first feedback loop. It is certainly important for the delay in the first loop to be minimal with high frequencies so that the phase margin is maintained. The additional delay in the output signal of the second latch L2 is of minor importance in the second loop, because in this loop the phase shift of the active loop filter is dominant. The much larger gain and reliability of the output signal of the second latch L2 does add to the overall loop gain in the second loop and enhances the accuracy with which the baseband B of the input signal is approached in the digital output signal.

With high clock rates the output signals at outputs 13 and 14 are sub-ideal. During the first phase of the clock signal CL, referenced 1 in Fig. 4, the output signals of the latches, referenced Ls in Fig. 4, do not change abruptly from one extreme value L to the other extreme value H, but according to a certain curve determined by the latch rate. The signal shape of signal Ls changes with the input signal and causes an undesired component in the first and second feedback loops which reduces the accuracy of the SDM. In order to render the signal shape of the output signals at outputs 13 and 14 of the latches L1 and L2 independent of what occurs during the first phase of the clock pulse CL, these signals are applied to inputs 20 and 25 of mixer stages M1 and M2 respectively. The mixer stages further have an output 23, 26 respectively, and a control input 21, 24 respectively, to which the clock signal CL is applied. The mixer stage produces an output signal referenced M in Fig. 4 in which during the first phase of the clock signal CL the instantaneous value of the input signal is replaced with a fixed value and which follows the input signal during the second phase of the clock signal CL. Either of the two mixer stages M1 and M2 can be omitted as desired or as required.

Fig. 5 shows a circuit diagram of a mixer stage suitable for use at very high clock frequencies. The mixer stage has balanced inputs 31, 32 for connecting the latched signal originating from the latch L1 of L2. If the latches produce unbalanced signals, either of the inputs 31 and 32 is to be connected to a suitable reference voltage. The mixer stage further has balanced outputs 33, 34 either of which can remain unused if so desired by connecting it to a fixed supply voltage. The clock signal CL is connected to a clock input terminal 35. To input 31 are connected the bases of transistors T1 and T2 whose two collectors are connected to output 33 and whose two emitters are connected to a first current source 36 and a second current source 37 respectively. To the other input 32 are connected the bases of transistors T3 and T4 whose two collectors are connected to output 34 and whose two emitters are connected to the second current source 37 and the first current source 36 respectively. Both current sources produce a current J. The collector-emitter paths of transistors T5 and T6 respectively, whose bases are connected to clock input terminal 35, are connected in parallel to the collector-emitter path of the transistors T1 and T3.

During the second phase of the clock signal CL the voltage at terminal 35 is low and the transistors T5 and T6 are blocking. If during that phase the voltage at terminal 31 is high and at terminal 32 low, the transistors T1 and T2 will be conductive and transistors T3 and T4 will be blocking. The current of current source 36 flows through transistor T1 and the current of current source 37 flows through transistor T2 to output terminal 35 in which a current 21 flows. There is no current flowing through output terminal 34 and, consequently, the value is 0. If, on the other hand, the voltage at terminal 31 is low and at terminal 32 high, the current through terminal 33 will be 0 (zero) and through terminal 34 21.

During the first phase of the clock signal CL the voltage at terminal 35 is high and the transistors T5 and T6 are conductive so that there is a continuous connection between terminal 33 and current source 36 on the one hand and terminal 34 and current source 37 on the other. A current I now flows through both terminal 33 and terminal 34 irrespective of the voltages at the terminals 31 and 32.

So, the mixer stage produces at the outputs 33, 34 currents having a fixed value I during the first phase of the clock signal and a value 01 or 21, depending on the sign of the voltage difference across the terminals 31, 32, during the second phase of the clock signal.

The circuit shown in Fig. 5 is structured in bipolar NPN-transistors. Bipolar PNP-transistors or unipolar N-channel and P-channel transistors can also be used. This similarly applies to the circuit shown in Fig. 6 to be discussed hereinafter.

Fig. 6 shows a suitable latch to be used as latch L1 and L2 in the SDM as shown in Fig. 3. As in the mixer stage shown in Fig. 5 the latch has balanced inputs, one input of which may be connected to a suitable fixed voltage as desired.

The signal to be latched is connected to terminals 1 and 2 which are connected to the bases of the respective transistors T1, T2 arranged as differential amplifiers, whose emitters are connected to a negative supply terminal 5 by means of a bias current source 4. The collectors of the transistors T1 and T2 are connected to the respective load resistors 6 and 7 in terminals 8 and 9 by means of the collector emitter paths of the respective transistors T5 and T6. The other ends of the resistors 6 and 7 are connected to a positive supply terminal 10. The bases of the transistors T5 and T6 are connected to a clock signal input 12 to which the clock signal CL is applied. By means of the base emitter junction of a transistor T9 arranged as a buffer, terminal 8 is connected to the bases of transistors T4 and T8 whose collectors are connected to terminal 9 and whose emitters are connected to the collectors of the respective transistors T2 and T1 at respective junctions 11 and 14. By means of the base emitter junction of a buffered transistor T10 terminal 9 is connected to the bases of the transistors T3 and T7 whose collectors are connected to terminal 8 and whose emitters are connected to the respective junctions 11 and 14. The emitters of the buffer transistors T9 and T10 are furthermore connected to supply terminal 5 by means of two transistors T11, T12 and T13, T14 respectively, arranged as diodes and a bias current source 15, 16 respectively. The terminals 17 and 18 of the respective current sources 15 and 16 and the diodes T11, T12 and T13, T14 are connected to output terminals 17 and 18 respectively, at which complementary buffered output signals are available that may be fed to the inputs 1, 2 of the same latch or to the inputs 31, 32 of a mixer stage as shown in Fig. 5.

If the clock signal CL at terminal 12 is "high" the transistors T5 and T6 will conduct so that the resistors 6 and 7 will be connected to the collectors of transistors T1 and T2. The voltage difference across the terminals 1, 2 appears in amplified form across the terminals 8 and 9. If the clock signal CL is "low", the transistors T5 and T6 will lock and the voltage difference at the terminals 8 and 9 will be regeneratively amplified and latched by means of the transistors T3, T4, T7 and T8 arranged as flip- flops. The flip-flop will then receive a bias current from the current source 4 through the transistors T1 and T2.

Fig. 7 shows a possible embodiment of a SDM according to the invention which operates with balanced signals. The SDM is arranged in accordance with the block diagram shown in Fig. 3. The input signal is fed to the input terminals 1A and 1B of a voltage-to-current converter 3 which delivers balanced output currents to current summation points 4A and 4B. A passive impedance 5 consisting of a series connection of a resistor and a capacitor is arranged across the points 4A and 4B. Alternatively, it is possible to connect each of the points 4A and 4B to a common signal mass point across a similar impedance 5. Furthermore, the inputs of an active first order filter section 6 that comprises a balanced active integrator 40 followed by a balanced voltage-to-current converter 50 delivering currents to current summation points 7A and 7B are connected to points 4A and 4B. A passive impedance 8 consisting of a parallel connection of a resistor and a series connection of a resistor and a capacitor is connected over these points 7A and 7B. Also in this case it is possible to connect each of the points 7A and 7B to a common signal mass point by means of a similar impedance 8. To the points 7A and 7B are furthermore connected the inputs 1, 2 of a first latch L1 of the type represented in Fig. 6. The outputs 17, 18 of latch L1 are connected to the inputs 31, 32 of a mixer stage M1 of the type represented in Fig. 5 and also to the inputs 1, 2 of a second latch L2 which is identical with latch L1. The outputs of latch L2 are connected to the inputs 31, 32 of a mixer stage M2 identical with a mixer stage M1 and, furthermore, to the output terminals 15A and 15B of the SDM. The outputs 33, 34 of the mixer stage M1 are connected in a negative feedback arrangement to the summation points 7A and 7B and the outputs 33 and 34 of mixer stage M2 in like manner to the summation points 4A, 4B. A clock signal CL is fed to the appropriate inputs 12 of the latches L1 and L2 and 35 of the mixer stages M1 and M2.

The relatively small phase shift in the first loop provides the possibility of optimising the second passive impedance for high frequencies, for example, by connecting a capacitor in parallel to the resistor which is connected in series to the capacitor. This results in a fourth order loop filter. The stability of the system permitting, a similar thing may also be effected in the passive first and/or active second filter section.