Circuit arrangement for surpressing the chrominance subcarrier in pal signal
阅读：755发布：2022-03-18
专利汇可以提供Circuit arrangement for surpressing the chrominance subcarrier in pal signal专利检索，专利查询，专利分析的服务。并且A circuit for eliminating the color component of a composite television signal has two comb filters. Both filters have internal feedback and one uses subtraction, while the other uses addition. This prevents a loss of vertical definition in the picture.，下面是Circuit arrangement for surpressing the chrominance subcarrier in pal signal专利的具体信息内容。
1. A circuit for suppressing the color signal component of a composite color television signal comprising a pair of comb filters; means for applying at least said color signal component to said filters; each of said filters comprising a delay line having a delay substantially equal to one line period of said television signal and having an input coupled to receive said color signal component and an output, means coupled to said delay line output for combining the delayed and undelayed color signal component, a first of said combining means adding said signals, the remaining second combining means subtracting said delayed from said undelayed color signal components, means for feeding back a portion of said combining means output to the input of said respective delay lines; first and second means for amplifying the output signals from said combining means by selected values; and means for subtracting said amplified signals from said composite television signal; whereby a luminance signal is produced.
2. A circuit as claimed in claim 1 wherein said second combining means comprises a phase inverter coupled to the second filter delay line, and an adder coupled to said phase inverter and to receive the undelayed signal.
3. A circuit as claimed in claim 1 wherein said applying means comprises a bandpass filter for passing only the color signal component, said filter having a given time delay; and further comprising a delay line having a delay substantially equal to said bandpass filter delay and having an input coupled to receive said composite signal and an output coupled to said subtracting means.
4. A circuit as claimed in claim 1 wherein said amplifying means amplify by the same amount, and both of said feedback means satisfy the equation v (1 - k)/2 + 2k wherein v is the value of said amplification, and k is the value of said feedback, k being greater than zero.
5. A circuit as claimed in claim 1 wherein both of said delay lines having a delay time that satisfies the equation 1/T fz (1 - e/n) wherein T is said delay time, fz is thE line frequency, e is equal to 0.25, and n equals 284.
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