The present invention generally relates to MIS voltage variable capacitors and particularly relates to a pair of MIS voltage variable capacitors connected in a back-to-back configuration in a body of semiconductor material and having a relatively high quality factor.

It is known in the semiconductor art to use an MIS voltage variable capacitor for the purpose of switching between two values of capacitance. However, it has been difficult to employ the transition state between capacitance values for tuning because the transition state is very sensitive to overdrive from interferring signals, which may cause intermodulation distortion and cross modulation distortion. These interfering signals also tend to cause a shift in the bias point of the device and thus detune the circuit.

In the drawing:

The single FIGURE is a partial cross-sectional view of the present device, not drawn to scale.

The present device, having a planar type structure, indicated at 10 in the FIGURE comprises a body 12 of semiconductor material having a surface 14 and having one type conductivity, for example P type. The body 12 contains at least a first region 16 and a second region 18. Preferably the first region 16 is adjacent the surface 14 and has a carrier concentration on the order of about 10⁴ atoms/cm³ lower than that of the second region 18. The second region 18 preferably has a carrier concentration between from about 10¹⁸ atoms/cm³ to about 10²⁰ atoms/cm³. The first region than has a carrier concentration between from about 10¹⁴ atoms/cm³ to about 10¹⁶ atoms/cm³.

A third region 20 of semiconductor material having the one type conductivity is within the first region 16. The third region 20 is adjacent the surface 14 and extends through the first region 16 to the second region 18. Preferably the carrier concentration of the third region 20 is at least about the same as that of the second region 18.

In the preferred device a layer 22 of insulating material overlies at least substantially all of the third region 20. The layer 22 may be, for example, silicon dioxide. A layer 24 of dielectric material is adjacent the surface 14 and overlies the first region 16 of semiconductor material. The layer 24 may be, for example, silicon dioxide, silicon nitride, or the like. The layer 22 should be on the order of from between about 10 to about 5 times as thick as the layer 24 of dielectric material.

A first electrode 26 overlies a first portion 28 of the layer 24 of dielectric material which overlies the first region 16. A second electrode 30 overlies a second portion 32 of the layer 24 of dielectric material. The second electrode 30 is insulatingly separated from the first electrode 26, and the third region 20 is in the electrical path between the first electrode 26 and the second electrode 30.

First and second terminal means, 34 and 36 respectively, are in electrical contact with the first and second electrodes, 26 and 30 respectively.

One method of fabricating the present device 10 is to begin with a body of semiconductor 12, preferably silicon, which has been cleaned and polished in a conventional manner. The first region 16 and the second region 18 may be formed by methods known in the semiconductor art. For example, the first region 16 may be an epitaxially grown layer of semiconductor material. As another example, the first region 16 may be diffused or ion implanted into the body 12. In such a case, the body 12 would then be attached to a handle, not shown in the drawings, and lapped and polished to yield the desired thickness of the first region 16. The preferred method of forming the first region 16 is by an epitaxial growth. In the preferred example the body 12 constitutes the second region 18.

The third region 20 may be formed in the first region 16 by methods known in the art, such as doped oxide diffusion, ion implantation, or the like. In the preferred example, that is, formation by a doped oxide diffusion, the oxide remaining after the dopant has been driven into the first region 16 is not removed. This then is designated as the layer 22 of insulating material. Allowing the layer 22 to remain is a matter of convenience since processing steps are saved. The layer 24 of dielectric material, for example silicon dioxide, may be formed adjacent the surface 14 by methods known in the art, for example it may be thermally grown.

The first and second electrodes 26 and 30 respectively, are then formed by methods known in the semiconductor art, for example, by RF sputtering, chemical vapor deposition, or the like. The material of the first and second electrodes 26 and 30 respectively may be any conductive material which is compatible to the method of formation.

It will be understood that the device 10 is comprised of a pair of voltage variable capacitors having a first capacitor member 38 and a second capacitor member 40. THe first capacitor member 38 is comprised of the first electrode 26, which may be designated as one plate thereof, the first portion 28, and the first region 16 of semiconductor material thereunder. The second capacitor member 40 is comprised of the second electrode 30, which may be designated as one plate thereof, the second portion 32, and the first region 16 of semiconductor material thereunder. The first and second capacitor members 38 and 40 respectively share, as a common node, the second region 18. THe third region 20 provides a current path between them. The layer 22 of insulating material reduces the overlap capacitance between the first capacitor member 38 and the second capacitor member 40.

The present device 10 may be utilized as one component in a hybrid circuit or it may be fabricated as one element of an integrated circuit. The device 10 may be used in conjunction with an inductive component, either lumped or integrated, to provide a tuning circuit.

Since the actual maximum and minimum values of the device 10 depend on the dielectric properties of the layer 24 of dielectric material and the thickness of layer 24 covered by the first and second electrodes 26 and 30 respectively, it will be understood that a relatively wide range of capacitance values are available across the first and second terminal means 34 and 36 respectively.

Capacitors connected in the general manner of device 10 are said to be in a back-to-back configuration. That is, a back-to-back configuration is where a plate of one capacitor is connected through resistive means to a plate of another capacitor. In the device 10 the third region 20 may be designated as the resistive means. In this configuration the overall capacitance of the device 10 is related to the square root of the applied voltage, as is known in the art. Thus the present device 10 is less susceptible to any voltage intermodulation distortion. That is, any voltage distortion has a reduced effect on the device 10 because of the square root voltage dependance.

The present device 10 also has a relatively high quality factor. In order to understand this it should be noted that the third region 20 has a higher, on the order of about 10⁴ atoms/cm³, carrier concentration than the first region 16. Thus the third region 20 has a relatively lower resistivity than the first region 16. In this case, the resistivity may be viewed as a series transverse resistance between the first capacitor member 38 and the second capacitor member 40 and may be designated as R_s. The relationship of the quality factor, Q, to the series transverse resistance, R_s, is given by the known equation: Q = 1/(2πfCR_s) where f is the frequency of operation and C is the value of capacitance. It follows from the above equation that Q is inversely proportional to R_s, and is relatively high since R_s is low.