BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic block diagram of the apparatus of the class of transforms which is implemented by the present invention;

FIG. 2a shows the apparatus of a schematic block diagram of a clock generator for the class of transforms of FIG. 1;

FIG. 2b shows a timing diagram for the apparatus of FIG. 2a;

FIG. 3 is a schematic block diagram of the apparatus for realizing the inverse class of transforms which is implemented by the present invention;

FIG. 4 is the Haar transform matrix;

FIG. 5 is the schematic block diagram of apparatus for obtaining the rationalized Haar transforms of FIG. 4 with provisions for outputting ordered serial transform coefficients;

FIG. 6 is a detailed timing diagram for the Haar transform unit of FIG. 5;

FIG. 7 is the timing apparatus for the Haar transform unit of FIG. 5; and

FIG. 8 is the schematic block diagram of the apparatus for realizing inverse Haar transform.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The Forward Transform

FIG. 1 is a schematic block diagram of a system to convert input data signals into transform coefficients in real time. The process of converting the input data signals into transform coefficients is called transformation. The system provides a plurality of adder/subtractor modules cascaded in stages with each stage having twice the number of modules as the preceding stage.

Each module includes a pair of multipliers denominated by the letter X which are operative to multiply each applied data sample by an appropriate scale factor. Each module further includes a pair of data latches denominated in FIG. 1 by the letter L. Each latch is coupled to the output of one of the associated multipliers and is formed of any suitable register for storing digital information. The data latches L are activated to receive and store data by pulse outputs denominated by φ and φ from a binary counter shown in FIG. 2a. The sequential counting of the binary counter is controlled by clock pulses which are synchronized with the serial application of input data to thereby synchronize the entire operation of the system, as shown in FIG. 2b.

Each module further includes an adder/subtractor denominated in FIG. 1 by AS. The adder/subtractor may be any suitable asynchronous adder. It is operative upon the suitable application of two inputs each from one of the associated latches of the module to produce two outputs; one is the sum of the contents of the two latches; the second, the difference between the contents of the two latches.

The modules are shown in FIG. 1 cascaded in stages with the first stage including the adder/subtractor AS11, the multipliers, the latches L₁₁ through L₁₄, and taps T₁₁ through T₁₄. The data extracted from the taps are transform coefficients. The modules are cascaded in FIG. 1 as shown so that each succeeding stage has twice as many modules as the preceding stage.

In the operation of FIG. 1, temporally sampled data is caused to serially enter the input part of the apparatus. The first input data sample is multiplied by the scale factor, W₀₁, and stored in data latch, L₀₁ when φ₀ is a binary one. The second input data sample is multiplied by scale factor, W₀₂, and stored in data latch L₀₂ on the positive transition of φ₀. Adder/subtractor, AS11, now has two valid input time samples and a meaninfgul addition and subtraction of the input signals stored in L₀₁ and L₀₂ can be performed. Adder/Subtractor, AS11, must be mechanized in such a manner as to insure the completion of the addition and subtraction process before the third input sample arrives for processing.

The data latches are activated by positive transitions of φ as shown in FIG. 2b from the binary counter shown in FIG. 2a. The output pulses from the binary counter activate the latches to receive and store data in synchronism with the sampled data. The binary counter is operative to generate φ₀ pulses at twice the clock rate of φ₁ pulses; at twice the clock rate of φ₂, etc.

On the second positive transition of φ₀ the first φ₁ binary one pulse is generated as shown in FIG. 2b. The sum of the contents of L₀₁ and L₀₂, which was added by AS11 is multiplied by scale factor W₁₁ and stored in data latch L₁₁ on the positive transition of φ₁. At the same time, the third input data sample is multiplied by scale factor W₀₁ and stored in data latch L₀₁. The fourth input data sample is multiplied by scale factor W₀₂ and stored in input data latch L₀₂ on the next positive transition of φ₀. As before, AS11 once again has valid input data applied thereto from L₀₁ to L₀₂ to allow AS11 to perform its addition/subtraction function to generate the sum output L₀₁ plus L₀₂ on the add output of AS11 and the difference L₀₁ minus L₀₂ on the subtract output of AS11. The sum of L₀₁ and L₀₂ is multiplied by scale factor W₁₂ and stored in data latch L₁₂ on the positive transition of φ₁. Simultaneously, the difference L₀₁ minus L₀₂ is multiplied by scale factor W₁₄ and stored in data latch L₁₄ as the positive transition of φ₁. Adder/subtractor units AS21 and AS22 now have valid data stored in their respective input data latches and the indicated addition and subtraction can be performed.

The entire sequence of events as detailed above is repeated and extended for as many stages as desired.

The selection of a particular transform is accomplished by extracting transform coefficients generated at the various stages at the taps indicated by T_ij where T_ij is the j^th tap of the i^th stage of processing. The taps are selected in such a manner as to once and only once account for all of the input data.

The operation of the taps of FIG. 1 may be roughly analogized to a water pipeline distributing system. In this rough analogy, the taps T_ij are analogized to water valves. As a valve is selected, it prevents the flow of water past that selected point, which precludes the use of additional valves (taps) downstream. The object is to select those combinations of valves which stop all flow. Each combination of properly selected taps represents a different member of the class of transforms.

The binary counter shown in FIG. 2a includes 6 Type D digital delay elements, each of which changes the logic level of the Q and Q outputs in response to the logic level of the D input on the positive edge of the input clock. Delay elements F₁, F₂ and F₃ are connected to form a suitable binary ripple counter to provide the φ and φ pulses for the latches of FIG. 1. Delay elements F₄, F₅ and F₆ are connected to form a pulse synchronizer, which compensates for the data skewing due to the propagation delay of the ripple counter. The use of the delay elements is optional in low speed applications. The timing diagram in FIG. 2a shows the waveforms generated at the Q output of F₄, F₅ and F₆.

FIG. 2b shows the timing of the clock generator of FIG. 2a to control the apparatus of FIG. 1 to produce an eight point transform. The asterisks show when valid transform coefficients can be extracted from the various taps of the class of transform apparatus of FIG. 1. Those asterisks associated with φ1 are for transform coefficients obtained from taps selected in stage 1, i.e., T_ij. The asterisks associated with φ2 are for transform coefficients obtained from taps selected in stage 2, i.e. T_2j. The double asterisk associated with φ2 represents the point when transform coefficients first become available in stage 3, i.e., T_3j. Thus it is seen that the transform coefficients are produced in real time after a predetermined delay as shown in FIG. 2b.

A quick inspection of the apparatus of FIG. 1 and the timing diagrams of FIG. 2b shows that the last stage of processing (i.e., stage 3 in FIG. 1) is not clocked by a φ3, as would be required if there were four or more stages of processing, but rather it is clocked by φ2. This was done to simplify mechanization of the clock generating apparatus of FIG. 2a. By clocking the stage 3 storage latches, L_3j, with φ2 instead of φ3, one complete ripple counter stage and pulse synchronizer stage may be eliminated.

THE INVERSE TRANSFORM

The process of converting transform coefficients back into (input) data samples is called inverse transformation. FIG. 3 shows how the inverse transformations are realized. Its operation is similar to that of the forward transformation apparatus of FIG. 1 with the signal flows being reversed. In the forward transform, the transform coefficients are obtained by adding and subtracting the input data signals. Therefore, the inverse transform must be normalized by a factor of two. To achieve this, the scale factors are replaced by one-half of their corresponding reciprocals.

Data is applied to the inverse transform in parallel order at a relatively slow rate (at the end of each transformation), and is transmitted continuously at the output of the inverse transform in serial order at a relatively high rate. Each transform requires a predetermined number of clock pulses.

Switches SWφ are ganged as shown and are clocked to select the appropriate data from each stage at the appropriate time to be processed by the next stage. Since each stage has a number of adder/ subtractor units operating in parallel, the outputs of each stage are transmitted in parallel. The switches SWφ thereby integrate or reduce the data from the one stage to the next succeeding stage.

The switches SW_ij are input selector switches and are positioned according to the taps and correspondingly to the particular transform selected during the forward transformation process. By way of example, if the selector switches are set as shown in FIG. 3, the inverse transform would proceed as follows. The clock generating apparatus for the class of transforms and the timing diagram as shown in FIG. 2b are applicable to the Inverse Class of Transforms. The first six clock pulses of the clock generating apparatus cause no meaningful operation of the Inverse Class of Transforms as shown in FIG. 3. These six pulses merely initialize the clock generating apparatus. On the first positive transition of φ2 those transform coefficients which were derived from the T_3j taps in the forward Class of Transforms, FIG. 1, are multiplied by the appropriate weight, W_3j, and stored in the appropriate data latch, L_3j. The clock generation continues to cycle until the next positive transition of φ2 wherein the weighted sums of the L_3j data latches are multiplied by the appropriate weights of the second stage, W_2j, and stored in the odd numbered stage 2 data latches, L_2j.

The data switches SWφ are shown ganged together. As shown in the forward transform in FIG. 1, data is shown latched to either even latches or odd latches in any one module. Therefore in the inverse transform, the switches SWφ are ganged to transmit data from either odd or even latches of any module.

Data switch SWφ1 is shown connected to the odd numbered data latches, L_2j, which allows the second stage Adder/Subtractor Units AS21 and AS22 to perform valid additions and subtractions. The clock generator continues to cycle until the negative transistion of φ, (positive transition of φ₁) wherein the weighted sums of the odd numbered L_2j data latches are multiplied by the appropriate weights W_ij and are stored in the odd numbered data latches L_1j.

Data Switch SWφ₀ is shown connected to the odd numbered data latches, L_ij, which allows the first state Adder/Subtractor Unit to perform a valid addition and subtraction. The clock generator continues to cycle until the next negative transition of φ₀ (positive transition of φ₀), wherein the weighted sum of the odd L_ij latches are multiplied by the appropriate weights W₀₂ and stored in the odd numbered data latch L₀₁. Switch SWCK is now connected to data latch L₀₁, which now contains the first recovered inversed transformed data point. The next positive transition of φ₀ is also the next positive transition of φ1 and φ2.

The data switches SWCK, SWφ0, and SWφ1 may be switched to contact the even positions. The even data latches of the respective stages L_0j, L_1j and L_2j store weighted difference data from its corresponding preceding stage and the L_3j data latches store a new set of transform coefficients. The data is further processed according to FIG. 3 and timing diagram 2b in analagous fashion as previously described.

SPECIAL CASES OF IMPORTANCE

1. A special case of importance of the embodiment of FIG. 1 is that case wherein all the multiplication scale factors, W_ij, are limited to powers of two, i.e., W = 2^k, k = 1,2 . . . . This case leads to an especially economical hardware implementation, since the multiplication blocks can be replaced by a hard wired shifting of the binary point.

2. If the ultimate in operating speed is not required, then some economy of hardware can be gained by eliminating all of the even numbered data latches, except for those output stages being tapped.

3. The Haar Transform: The simplest transform to mechanize is the rationalized Haar transform, which in matrix form is shown in FIG. 4. The Class of Transforms of FIG. 1, reduces to the rationalized Haar Transform as shown in FIG. 5. A four stage 16 point Haar transform unit based upon FIG. 5 has been constructed and operated at input data sample rates in excess of 8 MHZ 4 or 8 bits/sample which equals 64 in BPS throughput rate. By comparing FIG. 5 with FIG. 1, it is possible to summarize the functioning of the Haar transformer apparatus as outputting the differences from the adder/subtractor unit as transform coefficients and propagating the sum terms for additional processing. The apparatus of FIG. 5 has provisions through registers R11, R12, R21, R22, R31, R32, R41 and R42 for outputting transform coefficients in an ordered serial fashion as shown in the matrix of FIG. 4. This feature was included to illustrate the simplicity of generating a serial stream which is useful in most forms of processing.

DETAILED OPERATION OF THE HAAR TRANSFORM UNIT

The clocking of the apparatus of FIG. 5 is somewhat complicated by the additional circuitry which provides for outputting the Haar transform coefficients in serial ordered form. The required timing and control can be implemented with hard-wired logic, but the current state-of-the art in digital read only memories (ROM) makes it more economical to use an ROM to generate most of the required clocking signals. When such as ROM is used, a timing apparatus such as that shown in FIG. 7 is required.

In the operation of the apparatus of FIG. 7, a 4-bit synchronous counter 101 is caused to increment its count on the positive transitions of the input clock pulses. The input pulses are usually provided by a crystal oscillator. The frequency of the input clock pulses is selected to be numerically equal to the desired input data sample rate. The ROM 102 is programmed according to the timing diagram in FIG. 6, wherein an X in FIG. 6 means: store a true logic level (+1) at the indicated address and bit position; in the absence of an X, store a false logic level (0) at the indicated address and bit position. In response to the binary address provided by the 4-bit counter, the ROM 102 produces the required bit pattern which in turn is stored in a holding register 103 on the next positive transition of the clock signal. Signals Dφ₂ and Dφ₃ are one pulse time delayed replica of φ₂ and φ₃ respectively, as required by the apparatus of FIG. 5. Signal CK is a propagation delay compensated replica of CLOCK pulse as required by the apparatus of FIG. 5.

The Haar transform unit of FIG. 5 operates as follows: Temporally sampled input data is caused to serially enter the input of the apparatus of FIG. 5.

Clock 1: L11 stores 1st data sample.

Clock 2: L12 stores 2nd data sample. AS11 adds and subtracts L11 and L12.

Clock 3: (L11) - (L12) is shifted into Register R11, (L11) + (L12) is stored in L21, L11 stores 3rd data sample.

Clock 4: L12 stores 4th data sample, AS11 adds and subtracts L11, L12,

Clock 5: (L11) - (L12) is shifted into Register R11, (L11) + (L12) is stored into L22, AS21 adds and subtracts L21, L22. L11 stores 5th data sample.

Clock 6: (L21) + (L22) is stored in L31, (L21) - (L22) is shifted into Register R21, (L12 stores 6th data sample, AS11 adds and subtracts L11, L12.

Clock 7: (L11) - (L12) is shifted into R11, (L11) + (L12) is stored in L21, L11 stores 7th data sample.

Clock 8: L12 stores 8th data sample, AS11 adds and subtracts L11, L12.

Clock 9: (L11 - L12) is shifted into Register R11, (L11 + L12) is stored into L22, A21, adds and subtracts L21, L22. L11 stores 9th data sample.

Clock 10: L21) - (L22) is shifted into R21, (L21) + (L22) is stored into L32, L12 stores data sample 10.

Clock 11: (L11) - (L12) is shifted into R11, (L11) + (L12) is stored into L21. (L31) + (L32) is stored into L41, (L31) - (L32) is shifted into R31, L11 stores the 11th data sample.

Clock 12: L12 stores 12th data sample.

Clock 13: (L11) + (L12) is stored into L22, (L11 - (L12) is shifted into R11, L11 stores 13th data sample.

Clock 14: (L21) + (L22) is stored in L31, (L21) - (L22) is shifted into R21, L12 stores 14th data sample.

Clock 15: (L11) + (L12) is stored in L21, (L11) - (L12) is shifted into R11, L11 stores 15th data sample.

Clock 16: L12 stores 16th data sample.

Note: at this point, the last input data sample has just entered the transform unit for a 16 point transform. Subsequent data marks the beginning of a new transform period. Due to the pipeline approach, the transform of the first 16 data samples is not yet complete. Clock 17: (L11) + (L12) is stored in L22, (L11) - (L12) is shifted into R11, L11 stores 1st data sample of 2nd transform time.

Clock 18: L12 stores 2nd data sample of 2nd transform time. Strobe 1 causes the contents of R11 to be copied in parallel into Registor R12. (Register R12 now contains the last 8 Haar transform coefficients). (L21) + (L22) is stored into L32, (L21) - (L22) is shifted into R21.

Clock 19: (L11) + (L12) is stored into L21, (L12) is shifted into R11. (L11 stores 3rd data sample of 2nd transform time. R12 shifts (down) 1 place. Strobe 2 causes R21 to be copied into R22, (L31) + (L32) is stored into L42, (L31) - (L32) is shifted into R31,

Clock 20: R12 and R22 shift (down) 1 place. Strobe 3 causes R31 to be copied into R32. Strobe 3 also stores (L41) + (L42) into R41. Strobe 3 also stores (L41) - (L42) into R42. L12 stores 4th data sample of 2nd transforms time.

Note: the first 16 data samples are now completely transformed and converted into an ordered serial stream of transform coefficients. The R12, R22, R32, R42, R41 registors continue to shift the transform coefficients one place for every additional clock pulse. The entire sequence continues as outlined above.

INVERSE HAAR TRANSFORM UNIT

An inverse Haar Transform Unit is shown in FIG. 8. Clocking signals are generated by the apparatus of FIG. 2a. Transform coefficients serially enter the serial-to-parallel shift registers 105 through 108 of FIG. 8. After all 16 transform coefficients are contained within the serial-to-parallel registors, the load control for the parallel-to-serial shift registors 115 through 118 is pulsed, which causes the data in the serial-to-parallel registors to be copied into the parallel-to-serial registors on the leading (positive) edge of φ2. This copying process is referred to as "double buffering" in the state of the art, and its use here allows transform data to be continually shifted into the serial-to-parallel register for continuous real-time processing. The timing diagram as shown in FIG. 2b starts yielding proper clock pulse signals for the Inverse Haar Apparatus of FIG. 8 at the first positive transition of φ₂. The first "DON'T CARE" interval corresponds to the 16 clock pulses needed to clock input transform coefficients into the serial-to-parallel registors of FIG. 8. Adder/Subtractor units AS11 through AS41 are assumed to have neglible propagation delay with respect to the maximum clocking frequency, CK.

The detailed operation of the inverse Haar Transform Unit is similar to the inverse class of transforms. During the first true time of CK, the output data is seen to be ((((T₁ + T₂) /2 + T₃) /2 + T₅) /2 + T₉)/2 = No. 1 recovered time sample. During the first false time of CK, the output is seen to be: ((((T₁ + T₂) /2 + T₃) /2 + T₅) /2 - T₉)/2 = No. 2 recovered time sample. By shifting the data and selecting the appropriate switch settings as shown in FIG 2a, all of the time samples are recovered. Those skilled in the art will recognize immediately that for those applications where the propagation delays of the adder/subtractor units cannot be ignored, it is a simple matter to insert clocked latches between processing stages and to adjust the clocking to achieve the required signal processing.