Zero-crossing jitter detection method and circuit
阅读：268发布：2023-05-04
专利汇可以提供Zero-crossing jitter detection method and circuit专利检索，专利查询，专利分析的服务。并且An electronic circuit and method for providing a d.c. voltage proportional to the randomness of the zero-crossings of an input sine wave signal includes a hard limiter for converting the sine wave to a square wave of the same frequency, a narrow band filter tuned to twice the frequency of the input sine wave signal for removing all the spectral energy except that centered at the second harmonic and a circuit for converting any energy at the output of the filter to a d.c. component which represents the randomness of the zero-crossings (zero-crossing jitter).，下面是Zero-crossing jitter detection method and circuit专利的具体信息内容。
1. A zero-crossing jitter detector circuit comprising means for converting an input waveform of electrical energy s(t) A sin omega ot + n(t) to a square waveform of repetition rate equal to the fundamental frequency omega o to thereby have no energy in the square waves of fixed repetition rate at the second harmonic 2 omega o of the repetition rate, any randomness of the zero crossings of the square waves being due primarily to zerocrossing jitter in the input waveform s(t), filter means in communication with an output of said square wave converting means for removing substantially all of the spectral energy except that centered at the second harmonic frequency 2 omega o wherein any energy present at frequency 2 omega o is due primarily to the zero-crossing jitter, and means in communication with an output of said filter means for converting any energy at the output of said filter means to a d.c. component which is thereby directly proportional to the magnitude of zero-crossing jitter in the input waveform s(t).
2. The zero-crossing jitter detector circuit set forth in claim 1 wherein said square wave converting means is a hard limiter circuit.
3. The zero-crossing jitter detector circuit set forth in claim 2 wherein said hard limiter circuit includes means for providing symmetrical clipping of the input waveform s(t) whereby the square wave output thereof is symmetrical relative to ground potential.
4. The zero-crossing jitter detector circuit set forth in claim 1 wherein said filter means is a narrow bandpass filter having a center frequency of 2 omega o.
5. The zero-crossing jitter detector circuit set forth in claim 1 wherein said filter means is a single-tuned inductor-capacitor filter tuned to frequency 2 omega o.
6. The zero-crossing jitter detector circuit set forth in claim 1 wherein said filter means is a cascade of two single-tuned filters each tuned to frequency 2 omega o to thereby improve rejection of the fundamental frequency omega o.
7. The zero-crossing jitter detector circuit set forth in claim 1 wherein said d.c. component converting means is an envelope detector.
8. The zero-crossing jitter detector circuit set forth in claim 7 wherein said envelope detector comprises a rectifier having an input connected to an output of said filter means and a first low pass filter having an input connected to an output of said rectifier.
9. The zero-crossing jitter detector circuit set forth in claim 1 and further comprising means in communication with an output of said d.c. component converting means for detecting the magnitude of the d.c. component to thereby determine the magnitude of the zero-crossing jitter.
10. The zero-crossing jitter detector circuit set forth in claim 1 and further comprising means having a first input in communication with an output of said d.c. component converting means and a second input in communication with a bias source representing a predetermined jitter level to thereby provide a threshold mode of operation wherein the latter means is triggered to indicate the presence of an input waveform s(t) having a zero-crossing jitter in excess of the predetermined level established by the bias input.
11. The zero-crossing jitter detector circuit set forth in claim 3 wherein said hard limiter circuit comprises a first operational amplifier provided with a positive polarity input adapted to be supplied with the input waveform s(t), and a diode clipper circuit connected between an output of said first operational amplifier and ground, said diode circuit including at least two diodes of the same type connected in opposite polarity sense.
12. The zero-crossing jitter detector circuit set forth in claim 11 wherein said symmetrical clipping means includes a variable input resistor network connected to a source of bias voltage, output of said resistOr network connected to the positive polarity input of said first operational amplifier to provide thereto a compensating bias voltage for improving symmetry of the input waveform s(t) about a zero voltage reference and thereby aid in nulling out any even order harmonica of the square wave at the output of said diode clipper circuit in the absence of any zero-crossing jitter in input waveform s(t).
13. The zero-crossing jitter detector circuit set forth in claim 12 wherein said symmetrical clipping means further includes a second low pass filter connected from an output of said first amplifier to a negative polarity input thereof to provide a negative d.c. feedback of the average output voltage of said first amplifier for compensating for amplifier output offset voltage.
14. The zero-crossing jitter detector circuit set forth in claim 6 wherein said filter means further comprises a second operational amplifier provided with a positive polarity input in communication with an output of said square wave converting means, a first of said two filters connected from the positive polarity input of said second amplifier to ground, a second of said two filters connected from an output of said second amplifier to a negative polarity input thereof, said two filters each being of the parallel inductor-capacitOr type.
15. The zero-crossing jitter detector circuit set forth in claim 8 wherein said envelope detector further comprises a third operational amplifier for providing a high impedance buffer at the output of said jitter detector circuit, said third amplifier provided with a positive polarity input connected to the cathode of said rectifier, the anode of said rectifier in communication with an output of said filter means, said first low pass filter connected from the positive polarity input of said third amplifier to ground.
16. A circuit for measuring the randomness of the zero-crossings of electrical sine wave signals comprising a hard limiter having an input adapted to be provided with a sine wave signal, a narrow band filter tuned to twice the frequency of the input sine wave signal, said filter connected to an output of said hard limiter, and an envelope detector connected to an output of said narrow band filter for translating the spectral energy of the hard limited second harmonic of the input sine wave signal to baseband and obtaining a d.c. voltage component which is directly proportional to the randomness of the zero-crossings of the input sine wave signal.
17. A method for detecting the randomness of the zero-crossings of an input sinusoidal waveform of electrical energy comprising the steps of converting the input sinusoidal waveform to a square waveform of repetition rate equal to the fundamental frequency of the input sinusoidal waveform to thereby have no energy in the square waves of fixed repetition rate at the second harmonic of the repetition rate, filtering out substantially all of the spectral energy of the square waveform except that centered at the second harmonic of the fundamental frequency of the input sinusoidal waveform, and converting any energy of the square waveform centered at the second harmonic frequency into a d.c. voltage which is directly proportional to the magnitude of randomness of the zero-crossings of the input sinusoidal waveform.
18. The method set forth in claim 17 and further comprising the step of continuously recording the d.c. voltage to thereby obtain continuous monitoring of the randomness of zero-crossings of the input sinusoidal waveform.
19. The method set forth in claim 17 and further comprising the step of comparing the d.c. voltage with a bias voltage representing a predetermined random zero-crossing level to thereby provide a threshold mode of operation indicative of the presence of an input sinusoidal waveform having a randomness of zero-crossings in excess of the predetermined level.
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