Log spectrum decoding utilizing symmetry
阅读：282发布：2022-10-20
专利汇可以提供Log spectrum decoding utilizing symmetry专利检索，专利查询，专利分析的服务。并且A log spectrum decoder for performing the Discrete Fourier Transform (DFT) of a set of samples of an input signal employs first and second counter devices, the output value of the first counter device being related to the number of samples of the input signal and the output value of the second counter device determining the number of samples in an output signal. A multiplier circuit multiplies each of the input samples by a plurality of voltage signals collectively representing a cosine function. The number of voltage signals are related to the number of output signals of the second counting device. The resultant product signals are directed simultaneously to a first predetermined storage location in a memory device and through a function generator to a second predetermined storage location in the memory device. The product of each odd-numbered input sample and the sampled cosine function signals is inverted in the function generator and stored in the second predetermined storage location so as to form a series of signals having odd symmetry about the last output signal of the second counting device. Similarly, the product of each even-numbered input sample and the sampled cosine function is directed through the function generator without inversion to form a series of signals having even function symmetry about the last output signal of the second counting means. The series of signals stored in the memory device are directed to an accumulator circuit which adds, on a corresponding storage location basis, the most recent calculated series of signals to the accumulated sum of the previous signals. When the last input sample has been processed, the accumulated series of signals represents the logarithm of spectrum magnitudes of the input signal.，下面是Log spectrum decoding utilizing symmetry专利的具体信息内容。
1. A signal processor apparatus for computing the logarithm of the spectrum magnitudes of a predetermined signal from an input signal including a predetermined number of coefficient signals representing the Fourier transform of the logarithm of the spectrum magnitudes of the predetermined signal, said processor apparatus comprising: function storage means operative to store in addressable locations a predetermined number of signals representing a predetermined function; means coupled to said function storage means for selecting certain ones of said predetermined number of signals representing a predetermined function; multiplying means coupled to said function storage means for multiplying each of the predetermined number of the coefficient signals by the selected ones of said predetermined number of signals stored in said function storage means to generate a predetermined number of product signals; storage means having a first input port coupled to said multiplying means and a second input port and having a predetermined number of storage locations, said storage means being operative to store in certain ones of said predetermined number of storage locations said predetermined product signals in a first predetermined arrangement; function generator means coupled between the common juncture of said first input port of said storage means and said multiplying means and the second input port of said storage means and being operative in response to each of certain ones of said coefficient signals to store the associated product signals of each of said certain ones in a second predetermined arrangement in the storage locations of said storage means and being operative in response to each of the remaining ones of said coefficient signals to negate and to store the product signals for each of said remaining ones in the second predetermined arrangement in storage locations of said predetermined number of storage locations of said storage means; and accumulating means coupled to said storage means and being operative to add and accumulate on a storage location basis the sum of the product signals stored in each storage location of said storage means to generate an output signal including a plurality of signals, each of said signals being the sum of the product signals stored in a particular location of said storage means.
2. A signal processor apparatus according to claim 1 wherein said means for selecting includes: first counter means operative to generate a series of output signals representing a first predetermined numerical count over a first predetermined time interval; second counter means operative to generate a series of output signals representing a second predetermined numerical count over a second predetermined time interval, said series of output signals of said second counter means occurring for each numerical count of said first counter means; and multiplier means having an input connection coupled to said first and second counter means and an output connection coupled to said function storage means and being operative to generate an output signal, the value of which is proportional to the product of the output signals of said first and second counter means, each of said output signals corresponding to a specific addressable location in said function storage means.
3. A signal processor apparatus according to claim 2 wherein said function generator means comprises: a flip-flop circuit having an input connection coupled to said first counter means and first and second output connections and being operative in response to certain ones of the output signals of said first counter means to generate an output signal of a first polarity at said first output connection and an output signal of a second polarity at said second output connection and being operative in response to the remaining ones of the output signals of said first counter means to generate an output signal of said second polarity at said first output connections and an output signal of said first polarity at said second output connection; first gating means having a first input connection coupled to said common juncture of said first input port of said storage means and said multiplying means, a second input signal coupled to the first output connection of said flip-flop circuit, and an output connection and being operative in response to the first polarity signal of said flip-flop circuit to transfer the product signals from said multiplying means to its output connection and being operative in response to said second polarity signal to inhibit the transfer; negating circuit means having an input connection coupled to the first input connection of said first gating means and being operative to change the sign of the product signal from said multiplying means; second gating means haviNg a first input connection coupled to said negating circuit means, a second input connection coupled to the second output connection of said flip-flop circuit, and an output connection and being operative in response to said first polarity signal of said flip-flop circuit to transfer the sign-changed product signals from said negating circuit to its output connection and being operative in response to said second polarity signal of said flip-flop circuit to inhibit the transfer; and storage address means having a first input connection coupled to the output connections of said first and second gating means, a second input connection coupled to said second counter means and an output connection coupled to the second input port of said storage means and being operative in response to an input signal from said second counter means to store alternately the output signals of said first and second signals from said first and second gating means in said second predetermined arrangement in the storage locations of said storage means.
4. A signal processor apparatus according to claim 3 wherein said accumulating means comprises: an addressable accumulating storage device having an input/output port and a predetermined number of storage locations corresponding to the storage locations in said storage means and being operative to transfer data to and from said predetermined storage locations; third counter means operative to generate over a third predetermined interval a predetermined number of output signals corresponding to the number of storage locations in said addressable accumulating storage device; adder circuit having first and second input connections and an output connection and being operative to provide an output signal at said output connection equal to the sum of the signals at said first and second input connections; first address means having a first input connection coupled to said storage means, a second input connection coupled to said third counter means and an output connection coupled to the first input connection of said adder circuit and being operative in response to a signal from said third counter means to transfer the product signals stored in a particular location in said storage means to the first input connection of said adder circuit; and second address means coupled between the second input connection and the output connection of said adder circuit and said addressable accumulating storage device and having an input connection coupled to said third counter means, said second address means being operative in response to each signal from the third counter means to transfer to the adder circuit the data stored in the particular storage location of said addressable accumulating storage device corresponding to the storage location in said storage means of the data at said first connection of said adder circuit, and being operative to transfer the resulting sum signal at the adder circuit output connection to the particular storage location in said addressable accumulating storage device vacated by the data at the second input connection of the adder circuit.
5. A log spectrum decoder apparatus for spectrum decoding an input signal comprising a predetermined number of signal samples representing the Fourier transform of the logarithm of spectrum magnitudes of a predetermined signal, said spectrum decoder including the combination of; first counter means operative to generate a first predetermined number of output signals having a first predetermined time interval between successive output signals: second counter means operative to generate a second predetermined number of output signals over a second predetermined time interval, said second predetermined number of output signals being generated once during each first predetermined time interval; first multiplier means coupled to said first and second counter means and being operative to generate an output signal proportional to the product of the output siGnals of said first and second counter means whereby the number of product signals generated for each of the output signals of said first counter means corresponds to the second predetermined number of the output signals of said second counter means; function storage means having an input connection coupled to said first multiplier means and an output connection and being operative to store in specific locations a third predetermined number of signals, representing a predetermined mathematical function, said function storage means being operative in response to the magnitude of the product signal of said first multiplier means to transfer one of said third predetermined number of signals to its output terminal from a specific location corresponding to the magnitude of the product signal of said first multiplier means; input signal storage means coupled to said first counter means and having an output connection and being operative in response to each of said first predetermined number of output signals to transfer to its output connection one of said signal samples of said input electrical signal; second multiplier means having input connections coupled to said input signal storage means and to said function storage means and being operative to multiply each of the predetermined number of signal samples of the input electrical signal by each one of said third predetermined number of signals from said function storage means to generate product signals the number of which are related to the second predetermined number of output signals of said second counter means; product storage means having a plurality of storage locations the number of which is equal to at least twice the second predetermined number of output signals of said second counting means; first memory address means having a first input connection coupled to said second multiplier means, a second input connection coupled to said second counter means and an output connection coupled to said product storage means and being operative to store each product signal in said product storage means in a predetermined location determined by the signal from said second counter means; function generator means coupled between said second multiplier means and said product storage means and having input connections from said first and second counter means and being operative in response to certain ones of said predetermined number of the output signals of said first counting means to transfer directly to a second predetermined location in said product storage means the output signals of said second multiplier means to thereby produce a first function having a predetermined symmetry and being operative in response to the other ones of said predetermined number of output signals of said first counter means to inert the output signals of said second multiplier means and to transfer the inverted output signals to the second predetermined locations in said product storage means to thereby produce a second function having a second predetermined symmetry, said second predetermined location being determined by said second counting means; and accumulator means coupled to said product storage means and being operative to add the product signals stored in each of said first and second predetermined locations of said product storage means to the product signals stored in the same locations for each count of said first counter means and to store the sum of the product signals for each of the first and second predetermined locations, said sum of the product signals representing the logarithm of spectrum magnitudes of the input electrical signal.
6. In a data-processing system a machine-implemented method of generating a set of output signals representing the logarithm of the spectrum magnitudes of a predetermined signal from a set of input signals representing the Fourier transform of the logarithm of spectrum magnitudes of said predetermined signal, said method comprising the machine steps of: multiplying each one of the set of input signals by a first predetermined number of electrical signals representing a mathematical function to generate a first predetermined number of electrical product signals including a sign bit; arranging, for each one of the set of electrical input signals, said first predetermined number of product signals in a first predetermined arrangement, each of said product signals having a certain position within the first predetermined arrangement; arranging, for each one of the set of electrical input signals, said first predetermined number of product signals in a second predetermined arrangement so as to form with said first predetermined arrangement a series of product signals having symmetry about the last product signal; and combining each series of product signals produced from each set of electrical input signals on a position basis such that all the product signals arranged in a particular position within the first and second arrangement are combined whereby the series of product signals represents the logarithm of the spectrum magnitudes of the predetermined signal.
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