Data transferring system utilizing frame and bit timing recovery technique
阅读：949发布：2022-03-24
专利汇可以提供Data transferring system utilizing frame and bit timing recovery technique专利检索，专利查询，专利分析的服务。并且The transmitter-encoder of the data transferring system includes a combiner which develops an information signal by sequentially sampling the output states of a plurality of data sources. A timing signal generator develops bit and frame timing control signals for the combiner and a carrier and two pilot signals which are synchronized with the control signals to facilitate timing recovery at a receiver-decoder of the data transferring system. A composite signal comprised of an encoded information signal, carrier and pilots is transferred to the receiver through a medium which might produce abnormal information, such as an undesired frequency shift or phase perturbations, in the signal at the receiver-decoder input. The receiver includes circuitry which derives the carrier signal to facilitate demodulation. A demodulation circuit establishes the difference of each of the pilot signals and the encoded information signal from the carrier to produce two difference mixing signals and a difference information signal which have any frequency shift caused by the medium eliminated therefrom. One of the two difference mixing signals is utilized to reconstruct the bit timing signal and the other mixing signal along with a control signal derived from the bit timing signal is utilized to provide a frame timing signal which does not have any frequency or phase ambiguity. The bit and frame timing signals operate a bit separator included in the receiver which selectively channels the decoded data from the information signal to each of a plurality of data utilization devices corresponding to each of the data sources. A monitor signal which is synchronized with the data signal and which has a known pulse code may form part of the information signal to facilitate secure data transmission.，下面是Data transferring system utilizing frame and bit timing recovery technique专利的具体信息内容。
1. A timing system for use with a data transferring system having, a data source developing a serial bit stream which has a frame frequency and time intervals between successive frames each including a predetermined number of bits occurring at a bit frequency, communication means transferring signals applied to the input thereof from the data source to its output which is coupled to a bit processing circuit which requires control signals at the frame and bit frequencies at other inputs thereof, the communication means being subject to producing a frequency shift in signals transferred thereby, the timing system including in combination: timing generator means included in the data source and providing first, second and third signals having first, second and third respective frequencies at an output terminal thereof and all of which are synchronized with the frequency of the serial bit stream; first circuit means connecting said output terminal of said timing generator means to the input of the communication means so that the communication means can transfer said first, second and third signals to the output thereof; first frequency selective means having an input connected to the output of the communication means and providing said first signal at its output; mixing means having a first input connected to said output of said first frequency selective means and receiving said first signal therefrom and a second input connected to the output of the communication means and receiving said second and third signals therefrom, said mixing means providing at tHe output thereof first and second mixing signals having frequencies respectively equal to the difference between said first frequency and said second frequency and to the difference between said first frequency and said third frequency, said first, second and third signals having frequencies selected so that said first and second mixing signals have frequencies which are multiples of the frame frequency; second frequency selective means connected to said output of said mixing means being responsive to said first mixing signal to provide a bit timing signal at its output at a frequency equal to the bit frequency; third frequency selective means connected to said output of said mixing means being responsive to said second mixing signal to provide a frame timing signal at its output at a frequency equal to the frame frequency; and coupling means connected between said outputs of said second and third frequency selective means and the bit processing circuit for applying the bit and frame timing signals to the bit processing circuit.
2. The timing system of claim 1 wherein said second frequency selective means includes a first phase lock loop coupled to said output of said mixing means, said first phase lock loop being synchronized by said first mixing signal to provide a first phase locked signal at its output of a frequency which is a multiple of the bit timing frequency, said second frequency selective means also including a first frequency divider means having an input connected to said output of said first phase lock loop and which divides the frequency of said first phase locked signal to provide a first control signal having the form of a first square wave at the output thereof; and first circuit means including pulse delay and shape means connected to said output of said first frequency divider means, said first circuit means providing the bit timing signal at an output thereof.
3. The timing system of claim 2 wherein said third frequency selective means includes: a second phase lock loop coupled to said output of said mixing means, said second phase lock loop being synchronized by said mixing signal to provide a second phase locked signal at its output having a frequency which is a given multiple of the frequency of the frame timing pulses; and monostable means responsive to one polarity of said excursions of said second phase locked signal to generate a second control signal at the output thereof which facilitates the generation of the frame timing signal.
4. The timing system of claim 3 wherein said third frequency selective means further includes: gate means having first and second inputs and an output, said second input of said gate means being connected to said output of said monostable means to receive said second control signals; second circuit means connecting said first input of said gate means to said output of said first frequency divider means so that said first control signals are applied thereto; said gate means developing third control signals in response to the simultaneous occurrence of said first and second control signals, said third control signals having an interval of time therebetween equal to the frame time interval; and trigger circuit means responding to said third control signal to develop the frame timing signal at its output.
5. The timing system of claim 4 wherein said second circuit means includes: second frequency divider means whose input is connected to said output of said first frequency divider means, and which provides at the output thereof a fourth control signal having a frequency which is the next lower order multiple of the frequency of the frame timing signal than said given multiple of said second phase locked signal; differentiator means having its input coupled to said output of said second frequency divider means and its output connected to said first input of said gate means, said first differentiator means differentiating said fourth control signal to provide a first differentiated signal; and said gate responding to the simultaneous occurrence of said first differentiated signals and said second control signals to provide said third control signals at its output which are synchronized with the bit timing and which have an interval of time therebetween equal to the frame interval.
6. A timing recovery system for use with a data transferring system having an encoder and a decoder, the encoder including a data source developing a serial bit stream having frame time intervals each including a predetermined number of bits, communication means transferring signals from the encoder to the decoder, the communication means being subject to producing a frequency shift in the signals, the decoder having a bit processing means receiving the serial bit stream and which requires frame and bit timing pulses to facilitate the operation thereof, the bit timing pulses having a first time interval therebetween equal to the time interval between bits, the frame timing pulses being synchronized with the bit timing pulses and having a second time interval therebetween equal to the frame time interval, the timing recovery system including in combination: timing generator means included in said encoder and providing control signals to the data source, a carrier signal and first and second pilot signals which are all synchronized with each other; said carrier signal and said first and second pilot signals being transferred through the communication means to an output terminal thereof; first frequency selective means included in the decoder and having an input terminal connected to the output terminal of the communication means, said first frequency selective means providing said carrier signal at its output; mixing means included in the decoder and having a first input connected to said output of said first frequency selective means and receiving said carrier signal therefrom, said mixing means having a second input connected to the output of the communication means and receiving said first and second pilot signals therefrom, said mixing means providing at the output thereof first and second mixing signals having frequencies respectively equal to the difference between said carrier frequency and said first pilot frequency and between said carrier frequency and said second pilot frequency, said carrier and said first and second pilot signals having frequencies selected so that said first and second mixing signals have frequencies which are multiples of the frequency of the frame timing pulses; second frequency selective means having an input connected to said output of said mixing means being responsive to said first mixing signal to provide a first control signal at the output thereof having a frequency equal to said bit timing frequency; first circuit means coupled to the output of said second frequency selective means and producing the bit timing pulses at its output in response to said first control signal; third frequency selective means having an input connected to said output of said mixing means and being responsive to said second mixing signal to provide a second control signal at the output thereof; gate means having a first input coupled to said output of said second frequency selective means and a second input coupled to said output of said third frequency selective means and developing third control signals in response to the simultaneous occurrence of said first and second control signals which have an interval of time therebetween equal to the frame time interval; first trigger circuit means responding to said third control signal to develop the frame timing pulses at its output; and coupling means applying the bit and frame pulses to the bit processing means.
7. The timing recovery system of claim 6 wherein said second frequency selective means includes a first phase lock loop coupled to said output of said mixing means, said first phase lock loop being synchronized by said first mixing signal tO provide a first phase locked signal at its output of a frequency which is a multiple of the bit timing frequency, said second frequency selective means also including a first frequency divider means having an input connected to said output of said first phase lock loop and which divides the frequency of said first phase locked signal to provide said first control signal at the output thereof, said first control signal having the form of a first square wave; and said first circuit means including pulse delay and shape means connected to said output of said first frequency divider means, said first circuit means providing the bit timing pulses at the output thereof.
8. The timing recovery system of claim 6 wherein said third frequency selective means includes: a second phase lock loop having an input and an output, said input being coupled to said output of said mixing means, said second phase lock loop being synchronized by said second mixing signal to provide a second phase locked signal at said output thereof which is a given multiple of the frequency of the frame timing pulses; and first monostable means having an input connected to said output of said second phase lock loop and an output, said second monostable means being responsive to said second phase locked signal to generate said second control signal at said output thereof.
9. The timing recovery system of claim 8 further including second circuit means coupling said output of said second frequency selective means to said first input of said gate means, said second circuit means having: second frequency divider means having an input coupled to said output of said second frequency selective means, said second frequency divider means providing at the output thereof a fourth control signal having a frequency which is the next lower order multiple of the frequency of the frame timing pulses than said given multiple of said second phase locked signal; first differentiator means having an input coupled to said output of said second frequency divider means and its output connected to said first input of said gate means, said first differentiator means differentiating said fourth control signal to provide a first differentiated signal; said gate responding to the simultaneous occurrence of said first differentiated signal and said second control signal to provide said third control signals at its output which are synchronized with the bit timing and which have an interval of time therebetween equal to the frame interval; and said first trigger circuit means including a second monostable multivibrator means which responds to said third control signal to provide the frame timing pulses at its output.
10. The timing recovery system of claim 9 wherein said fourth control signal has a frequency which is the next higher order multiple than said given multiple of said frame timing signal.
11. A data transferring system comprised of an encoder and a decoder, including in combination: a plurality of data sources each providing at its output a digital signal to be transferred; timing generator means included in the encoder and providing combiner control signals at a first output thereof, a carrier signal and a first and second pilot signals respectively developed at second, third and fourth outputs thereof, said combiner control, carrier, first and second signals all being synchronized with each other; combiner means included in the encoder having a set of sampling inputs and a timing input, said sampling inputs being connected to said outputs of said plurality of data sources and said timing input being connected to said first output of said timing generator means, said combiner means sequentially sampling each of said digital signals in response to said combiner control signals for a bit time interval and all of said plurality of data sources during a frame time interval to form a serial, binary bit stream therefrom at its output; encoding means included in the Encoder and having an input connected to said output of said combiner and transforming said serial bit stream into an information waveform at its output; communication means having an input connected to said output of said encoding means and transferring said information waveform and said carrier and said first and second pilot signals to an output thereof, said communication means capable of causing undesirable frequency shift in said carrier, and first and second pilot signals and said information waveform; first frequency selective means included in the decoder and having an input connected to said output of said communication means, said first frequency selective means deriving said carrier signal at its output; mixing means included in the decoder and having a first input thereof connected to said output of said first frequency selective means and receiving said carrier signal therefrom and a second input connected to said output of said communication means for receiving said first and second pilot signals, said mixing means providing first and second mixing signals at its output having frequencies respectively equal to the difference between said carrier and said first pilot frequency and said carrier and said second pilot frequency, so that any frequency shift caused by said communication means in said carrier and said first and second pilot frequencies is not created in said first and second mixing signals; second frequency selective means connected to said output of said mixing means being responsive to said first mixing signal to provide a first control signal at the bit timing frequency at the output thereof; third frequency selective means connected to said output of said mixing means being responsive to said second mixing signal to provide a second control signal at the output thereof; gate means having a first input coupled to said output of said second frequency selective means and a second input coupled to said output of said third frequency selective means and developing a frame timing signal in response to the simultaneous occurrence of said first and second control signals; decoding means also included in the decoder and deriving said serial bit stream at its output from said information waveform; and bit separator means having a first input coupled to said output of said decoding means to receive said serial bit stream and a second input coupled to said output of said gate means to receive said frame timing signal and a third input coupled to said output of said second frequency selective means to receive said bit timing signals, said bit separator means providing the binary bits from each of said plurality of data sources at each of a plurality of corresponding outputs thereof in response to said bit and frame timing pulses and said serial bit stream.
12. The data transferring system of claim 11 wherein: each of said plurality of data sources includes measuring means for monitoring electrical quantities in a power transmission system, and each of said measuring means developing one of said digital signals in response to said quantities, and, each of a plurality of protective means is coupled to each of said outputs of said bit separator means, said protective means selectively removing electrical power from said power transmission system in response to a digital signal having a predetermined code.
13. The data transferring system of claim 11 wherein said encoding means has a polybinary correlative encoding means including: first signal means having an input connected to said output of said combiner means and an output, said first signal means forming a first encoded signal at said output thereof comprised of the modulo-two addition of said serial, binary bit stream and said first encoded signal which is delayed by two bits; second signal means having an input connected to said output of said first signal means and an output, said second signal means forming a ternary signal at its output by addinG the inverse of said first encoded signal delayed by two bits to said first encoded signal, said ternary signal thereby having a sine function frequency spectrum; and low pass filter means having an input connected to said output of said second signal means and selecting said frequency components of said ternary waveform within a first recurring portion of said sine function frequency spectrum to provide a filtered ternary waveform at its output.
14. The data transferring system of claim 13 wherein said encoding means further includes: modulator means having a first input connected to said second output of said timing generator means and receiving said carrier signal therefrom, and a second input connected to said output of said low pass filter and receiving said filtered ternary signal therefrom, said modulator means amplitude modulating said carrier signal with said filtered ternary signal to produce a sideband at its output having a selected frequency spectrum; and bandpass filter means having an input connected to said output of said modulator means and providing said sideband at its output thereby forming said information waveform.
15. The data transferring system of claim 14 wherein said sideband has a frequency spectrum equal to the sum of the frequency components of said filtered ternary signal and said carrier signal.
16. The data transferring system of claim 15 wherein said mixing means included in said decoder, mixes said sideband with said carrier signal to provide a band of third mixing signals at its output having frequencies equal to the difference between the frequencies of said sideband and said carrier so that any frequency shift caused by said communication means in said sideband and in said carrier signal is not created in said third mixing signal.
17. The data transferring system of claim 16 wherein said decoding means includes slicing means connected between said output of said mixing means and said first input of said bit separator means, said slicing means converting said band of third mixing signals back into said serial bit stream applied to said first input of said bit separator means.
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