Decode circuitry for bipolar random access memory专利检索-肖特基晶体管双极结型晶体管电气元件和设备专利检索查询-专利查询网

Decode circuitry for bipolar random access memory

阅读：906发布：2022-06-10

专利汇可以提供Decode circuitry for bipolar random access memory专利检索，专利查询，专利分析的服务。并且An N-bit binary address decoder suitable for use in an emittercoupled logic bipolar random access memory (RAM) is provided. Each of the N address input signals is applied to an input terminal and is level shifted and applied to the input node of an emitter-coupled logic inverter. The outputs of the emittercoupled logic inverter are the collectors of the emitter-coupled transistors on which complementary output signals representative of the corresponding binary address input signal are produced. The complementary output signals generated by the N inverters are connected to 2N AND gates to form the possible 2N minterm combinations. Each of the AND gates includes a load resistor coupled to a power supply and N Schottky diodes having their anodes coupled to the load resistor and their cathodes coupled to the corresponding address inverter output terminals. The anodes of the input diodes of each AND gate are also connected to the base of a transistor, the emitter of which produces the signal representing the corresponding minterm function generated by that AND gate.，下面是Decode circuitry for bipolar random access memory专利的具体信息内容。

权利要求

1. A high speed logic gate comprising: a plurality of emitter-coupled inverters, each including first and second transistors having their emitters coupled together, said first transistor having its base coupled to a node adapted to have applied thereto a signal representative of an input logic signal, said second transistor having its base coupled to a reference voltage conductor, a current source connected to said emitters; a plurality of diodes having anodes thereof coupled together to resistive load means coupled between said anodes and a first voltage conductor; a collector electrode of one of said first and second transistors of each of said emitter coupled inverters being coupled respectively, to the cathode of one of said diodes; and output circuit means coupled to the anodes of said plurality of diodes.

2. The high speed emitter coupled logic gate as recited in claim 1 wherein said output circuit means including an output transistor having its base coupled to said anodes of said diodes, its collector coupled to said first voltage conductor, and its emitter coupled to an output node of said high speed logic gate.

3. The high speed logic gate as recited in claim 2 further including a plurality of emitter follower circuits, each having an output coupled, respectively, to the base node of each of said first transistors, each of said emitter followers having an input node coupled to a conductor adapted to receive an input logic signal.

4. The high speed logic gate as recited in claim 1 wherein said diodes are Schottky diodes.

5. An N-input high speed emitter-coupled logic decoder for selecting one out of 2N combinations of N-input variables comprising: N emitter-coupled logic inverters each comprising first and second emitter-coupled transistors and a current source coupled to said emitters for producing complementary output signals, respectively, at the collectors of said first and second transistors; 2N N-input diode AND gates each including resistive load means coupled between a first voltage conductor and the anodes of the N diodes of each of said N-input diode AND gates; a plurality of output circuit means each coupled to the anodes of the N diodes of a respective one of said AND gates; said collectors of said first and second emitter-coupled transistors of said N emitter-coupled logic inverters being coupled, respectively, to the cathodes of said diodes in order to form the 2N minterm combinations oF said N-input variables at the respective output circuit means of each of the respective AND gates.

6. The N-input high speed ECL decode circuit as recited in claim 5 wherein each of said plurality of output circuit means of said N-input diode AND gates includes an output transistor having its collector coupled to said first voltage conductor, its base coupled to the anodes of said input diodes, and its emitter coupled to an output of said gate; each of said emitter-coupled logic inverters having an input node coupled to an output of an emitter follower circuit adapted to receive an input signal representative of one of said N-input variables.

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Decode circuitry for bipolar random access memory

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