High isolation r. f. signal selection switches专利检索-肖特基晶体管双极结型晶体管电气元件和设备专利检索查询-专利查询网

High isolation r. f. signal selection switches

阅读：380发布：2022-06-22

专利汇可以提供High isolation r. f. signal selection switches专利检索，专利查询，专利分析的服务。并且A selection switch with high isolation between R.F. signal input terminals is achieved with a gated Schmitt trigger circuit feeding into a control NAND gate in each signal switching channel. The control NAND gates of the separate signal channels are coupled to an output terminal by a single NAND gate. The schmitt trigger circuits and all gates are implemented with Schottky transistor-transistor logic (TTL) circuits having input clamping diodes. Each Schmitt trigger circuit includes two cascaded NAND gates and a feedback isolation Schottky diode between one input terminal connected to receive an R.F. input and another input terminal connected to receive a feedback signal from the second of the two cascaded NAND gates. Both NAND gates of the Schmitt trigger circuits are enabled by the same switch control signal which enables the control gates.，下面是High isolation r. f. signal selection switches专利的具体信息内容。

权利要求

1. A system for R.F. signal selection under control of low level binary signals with high isolation between input terminals of a plurality of selection channels, and between the input terminal of an unselected channel and an output terminal to which a selected signal is coupled by one of said selection channels, each of said channels being coupled to an output terminal by means comprising a NAND gate having an output terminal and a plurality of input terminals, one input terminal for each channel, and each of said channels comprising a gated Schmitt trigger circuit in cascade with a control NAND gate, said Schmitt triGger circuit comprising two NAND gates in cascade and a feedback resistor connected between the output of the second of said two NAND gates to an input terminal of the first of said two NAND gates, each of said two NAND gates and said control NAND gate being enabled by a low level binary control signal at distinct input terminals thereof to function as digital logic gates, the first of said two NAND gates of said Schmitt trigger circuit having voltage reducing means connected between a distinct input terminal thereof connected to receive an input R.F. signal and said input terminal connected to said feedback resistor, each of said NAND gates being a transistor-transistorlogic circuit comprised of a plurality of transistors of the same conductivity type including an input transistor having a plurality of emitters, each connected to receive an input signal, a base connected to a voltage source by a resistor, and a collector; a control transistor having a base connected directly to said collector of said input transistor, a collector connected to said source of voltage, and an emitter; and a pair of output transistors, one having its emitter and the other having its collector connected directly to an output terminal, said one transistor having its collector connected to said source of voltage and a base connected to said collector of said control transistor by direct current means, and said other transistor having an emitter connected to circuit ground and a base connected to said emitter of said control transistor by direct current means.

2. A system as defined in claim 1 wherein said voltage reducing means connected between distinct input terminals of said Schmitt trigger circuit is diode poled to be forward biased when said input R.F. signal increases in amplitude with a given polarity necessary to turn off the input transistor of said first of said two NAND gates of said Schmitt trigger circuit.

3. A system as defined in claim 2 wherein said diode is a Schottky barrier type of diode.

4. A system as defined in claim 3 wherein each of said emitters of said input transistor of each NAND gate is clamped to circuit ground by a distinct clamping diode poled to be forward biased by an input signal of a polarity opposite said given polarity.

5. A system as defined in claim 4 wherein each of said clamping diodes is a Schottky-barrier type of diode.

6. A system as defined in claim 5 wherein each of said input transistor and said control transistor of each NAND gate has its collector clamped to its base by a Schottky-barrier diode junction therebetween.

7. A system as defined in claim 6 wherein said output transistor of each NAND gate having its emitter connected to circuit ground has its collector clamped to its base by a Schottky-barrier diode junction.

8. A system as defined in claim 7 including a distinct impedance matching section coupling each input signal to a distinct input terminal of said plurality of selection channels.

9. A system as defined in claim 8 including an output impedance matching section connected to said output terminal to which a selected signal is coupled by one of said selection channels, said output impedance matching section being adapted to said output terminal to a load.

10. A system as defined by claim 9 wherein each of said distinct impedance matching sections coupling input signals to input terminals includes a filter characteristic selected for the input signal coupled to an input terminal.

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