Schottky clamped ttl circuit
阅读：680发布：2022-06-26
专利汇可以提供Schottky clamped ttl circuit专利检索，专利查询，专利分析的服务。并且A low power TTL gating circuit wherein PNP transistors have been used in place of the usual current source resistors and Schottkyclamped NPN have been used in place of the usual gold doped NPN gating elements to obtain a faster operating circuit which requires less chip area than similar prior art circuits.，下面是Schottky clamped ttl circuit专利的具体信息内容。
1. A TTL circuit comprising: a plurality of Schottky-clamped transistor elements of a first conductivity forming a gating circuit having a circuit output terminal and responsive to an input signal and operative to couple the circuit output terminal to a first source of potential when said input signal is of a first signal state and to couple the circuit output terminal to a second source of potential when said input signal is of a second switching state; and current source means for suppLying drive current to said gating circuit, said current source means including at least one transistor of a second conductivity type.
2. A logic gating circuit comprising: a first transistor of a first conductivity type having a first emitter for receiving input gating signals, a first base, and a first collector; a first Schottky diode coupled between said first base and said first collector; a second transistor of said first conductivity type having a second base coupled to said first collector, a second collector for developing a first switching signal and a second emitter for developing a second switching signal; a second Schottky diode coupling said second base to said second collector; current source means including a third transistor of a second conductivity type for supplying base drive current to said first transistor and collector current to said second transistor; a first switching means responsive to said first switching signal and operative to develop an output signal of a first logic state; and a second switching means responsive to said second switching signal and operative to develop an output signal of a second logic state.
3. A logic gating circuit as recited in claim 2 wherein said third transistor is a lateral transistor having a third base, a third emitter, and a pair of collectors, one being coupled to said second collector, and the other being coupled to said first base
4. A logic gating circuit as recited in claim 3 wherein said current source means further includes a fourth transistor of said second conductivity type having a fourth base coupled to said third base, a fourth collector coupled to said third base, and a fourth emitter.
5. A logic gating circuit as recited in claim 2 and further comprising: a first source of potential; a second source of potential; an output terminal; and wherein said first switching means includes, a fourth transistor having a fourth base for receiving current in response to said first switching signal, a fourth collector coupled to said first source of potential and a fourth emitter coupled to said output terminal, and a Schottky diode coupling said fourth base to said fourth collector.
6. A logic gating circuit as recited in claim 5 wherein said second switching means includes, a fifth transistor having a fifth base for receiving said second switching signal, a fifth collector coupled to said output terminal, and a fifth emitter coupled to said second source of potential, and a fourth Schottky diode coupling said fifth base to said fifth collector.
7. A logic gating circuit, comprising: a first source of potential; a second source of potential; an input terminal; an output terminal; a first transistor of a first conductivity type having a first base, a first emitter coupled to said first source of potential, and a first collector coupled to said first base; a second transistor of said first conductivity type having a second base coupled to said first collector, a second emitter coupled to said first source of potential, and a pair of collectors; a third Schottky-clamped transistor of a second conductivity type having a third base coupled to one of said pair of collectors, a third emitter coupled to said input terminal, and a third collector; a fourth Schottky-clamped transistor of said second conductivity type having a fourth base coupled to said third collector, a fourth emitter, and a fourth collector coupled to the other of said pair of said collectors; a fifth transistor having a fifth base coupled to said fourth collector, a fifth collector coupled to said first source of potential, and a fifth emitter; a sixth Schottky-clamped transistor of said second conductivity type having a sixth base coupled to said fifth emitter, a sixth collector coupled to said first source of potential, and a sixth emitter coupled to said output terminal; and a seventh Schottky-clamped transistOr of said second conductivity type having a seventh base coupled to said fourth emitter, a seventh collector coupled to said output terminal; and a seventh emitter coupled to said second source of potential.
8. A logic gating circuit as recited in claim 7 and further comprising a resistor coupling said first collector to said second source of potential.
9. A logic gating circuit as recited in claim 7 and further comprising a diode coupling said sixth collector to said first source of potential.
10. A logic gating circuit as recited in claim 7 wherein said Schottky-clamped transistors each include a Schottky diode coupling the base of the transistor to the collector of the transistor.
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