BACKGROUND OF THE INVENTION

(a) Field of the invention:

The present invention pertains to a transistor amplifier employing a plurality of transistors serving at its amplifying elements, and more particularly it pertains to a multi-stage transistor amplifier of a full stage direct-coupled configuration.

(B) Description of the prior art:

Currently known transistor amplifiers almost invariably adopt the full stage direct-coupled configuration. With such a configuration, it is most important to stabilize the quiescent operating point for each amplifying transistor in the respective stage circuits, particularly in the input stage circuit in order to obtain a good over-all operation stability of the amplifier.

To meet the above requirement, most of the conventional transistor amplifiers according to the prior art are so arranged that their input circuit and/or the subsequent stage circuits are comprised of a differential amplifiers, respectively, of which operation is, as well known, hardly affected by fluctuations in the ambient temperature and in the voltages of the operating power supplies, and/or that there are provided circuit means such as for making compensation for those variations of the quiescent operating point for each amplifying transistor in the respective stage circuits which might be caused by the changes in the ambient temperature and in the voltages of the operating power supplies. As such, the prior art transistor amplifiers have tended to be complicated in their structure.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a transistor amplifier which is simple in arrangement, and the operation of which is hardly affected by variations in the ambient temperature and in the voltages of the operating power supplies.

Another object of the present invention is to provide a transistor amplifier of the type described, in which the quiescent operating point for each amplifying transistor employed in the amplifier is stabilized against variations in the ambient temperature and in the voltages of the operating power supplies.

Still another object of the present invention is to provide a transistor amplifier which is suitable for use as the input stage circuit of a multi-stage transistor amplifier of full stage direct-coupled configuration.

According to one aspect of the present invention, there is provided a transistor amplifier comprising: an input stage circuit including a first and a second transistor which are complementary to each other and are connected together at their bases to an input terminal of the transistor amplifier, the emitters of the first and second transistors being connected to constant current sources and grounded through capacitors, respectively, the collectors of the first and second transistors being connected to constant potential lines, respectively; and an output stage circuit which is direct-coupled to the input stage circuit and is comprised of a single-ended push-pull amplifier circuit including as amplifying elements a third transistor and a fourth transistor which are complementary to each other, the bases of the third and fourth transistors being direct-coupled to the corresponding ones of the collectors of the first and second transistors, respectively.

These and other objects as well as the features and the advantages of the present invention will become apparent by reading the following detailed description of the preferred embodiments of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electric circuit diagram, showing an example of the transistor amplifier embodying the present invention.

FIG. 2 is an electric circuit diagram, showing an example of the constant current circuit employed in the amplifier shown in FIG. 1.

FIG. 3 is an electric circuit diagram, showing a modification of an output stage in the transistor amplifier of FIG. 1.

Like parts are indicated by like reference symbols throughout the drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In FIG. 1 is shown diagrammatically an example of two-stage transistor amplifier according to the present invention, which is composed of an input stage circuit and an output stage circuit.

The input stage circuit includes a pnp transistor Q₁ and an npn transistor Q₂. The two transistors Q₁ and Q₂ are coupled to each other in common at their bases which, in turn, are connected to an input terminal IN of the transistor amplifier. The emitters of the transistors Q₁ and Q₂ are connected to constant current sources, respectively, containing constant current circuits CC₁ and CC₂ and through said constant current sources the emitters are connected to operating power supply lines +B and -B, respectively, to which are applied the voltages of the positive and negative operating power supplies, respectively. The emitters of those transistors Q₁ and Q₂ are also grounded through capacitors C₁ and C₂, respectively. The collectors of the transistors Q₁ and Q₂ are connected to constant potential lines which in this example are the negative and the positive operating power supply lines -B and +B and which contain load resistors RL₁ and RL₂, respectively.

The output stage circuit is comprised of a single-ended push-pull amplifier circuit including a pnp transistor Q₃ and an npn transistor Q₄. The transistors Q₃ and Q₄ have their collectors connected to the operating power supply lines -B and +B, respectively, and have their emitters connected in common through resistors RE₁ and RE₂ and further connected to an output terminal OUT of the transistor amplifier. The bases of the transistors Q₃ and Q₄ are direct-coupled to the collectors of the transistors Q₁ and Q₂, respectively, of the input stage circuit. The output terminal OUT is connected back to the input terminal IN through a voltage divider network composed of resistors RO₁ and RO₂. The AC operation of the transistor amplifier described above is as follows: signals applied at the input terminal IN are first amplified as well as phase-inverted by the input circuit to be delivered out at the collectors of the respective transistors Q₁ and Q₂. It should be noted that the capacitors C₁ and C₂ are so selected as will offer no or negligible impedance against the input signal frequencies evaluated for amplification. Therefore, the input stage circuit will provide a large voltage gain for the input signals. The transistors Q₃ and Q₄ of the output state circuit are driven by the amplified input signals on the corresponding ones of the collectors of the transistors Q₁ and Q₂, respectively. Thus, at the output terminal OUT are delivered out the input signals which have been amplified by both of the input and output stage circuits. The output signals at the output terminal OUT are partially fed back to the input stage circuit through the voltage divider network.

Description will hereunder be made in detail on the DC operation of the above-mentioned transistor amplifier shown in FIG. 1.

The emitter DC currents ie₁ and ie₂ supplied to the emitters of the transistors Q₁ and Q₂ are stabilized at constant values by the constant current circuits CC₁ and CC₂. Accordingly, voltage drops VC₁ and VC₂ developed across the load resistors RL₁ and RL₂ will remain constant, so that the potentials at both bases of the transistors Q₃ and Q₄ as well as the voltages between the collectors and emitters of the transistors Q₁ and Q₂ will be kept constant, provided that the operating power supply lines +B and -B are held at constant potentials, respectively. The changes in the voltage of the operating power supplies applied to these lines +B and -B might cause some variations in the biasing conditions for the transistors Q₃ and Q₄, but such changes will hardly affect the biasing conditions for the transistors Q₁ and Q₂. Thus, the quiescent operating points for the respective transistors Q₁, Q₂, Q₃ and Q₄ are stabilized against variations in the ambient temperature and in the voltages of the operating power supplies. Furthermore, the transistor amplifier shown in FIG. 1 is arranged so that the output terminal OUT is connected back to the input terminal IN in order to further enhance the stability of the biasing conditions. In case there occur fluctuations in the biasing conditions for the transistors Q₁ and Q₂, such fluctuations are detected by the output stage circuit and they are fed back to the input stage circuit, whereby suppressing those fluctuations.

The DC operating conditions of the present invention transistor amplifier are stable irrespective of the variations in the ambient temperature as well as in the voltages of the operating power supplies as described above, so that the AC operation characteristics such as the gain and frequency response are also stabilized.

An input offset current of the transistor amplifier shown in FIG. 1 corresponds to the difference between the base currents iB₁ and iB₂ of the transistors Q₁ and Q₂ when the input terminal IN is at zero volt, and will cause an input offset voltage. If the base currents iB₁ and iB₂ are same, then the input offset current as well as the input offset voltage will become nil. such conditions can be attained by properly determining the values of the emitter currents iE₁ and iE₂. FIG. 2 diagrammatically shows an example of arrangement of the constant current circuit CC₁ (or CC₂ ) shown in FIG. 1, which is comprised of an n-channel field effect transistor Q₅ having a drain D, a source S and a gate G which is connected to the source S via a variable resistor RV. When this constant current circuit is employed as the circuit CC₁ (or CC₂) shown in FIG. 1, the drain D and the junction of the gate G with the resistor RV are connected to the line +B (or the emitter of the transistor Q₂) and the emitter of the transistor Q₁ (or the line -B), respectively. The zero setting for both the input offset current and voltage can be easily accomplished by adjusting the resistance values of variable resistors RV in the constant current circuits CC₁ and CC₂ to meet the above-mentioned requirement.

The output offset voltage at the terminal OUT can be adjusted to be zero volt by appropriately determining the resistance ratio between both resistors RE₁ and RE₂. To easily accomplish the zero setting for the output offset voltage, the arrangement of the output stage circuit may preferably be modified as shown in FIG. 3. In this Figure, the emitters of the transistors Q₃ and Q₄ are connected in common through an intervening potentiometer VO in place of the resistors RE₁ and RE₂ in FIG. 1, the output terminal OUT being led out from the slider tap of the potentiometer VO. The above zero setting can be accomplished by a mere adjustment of the position of the slider tap.