Fabrication of MOS devices and complementary bipolar transistor devices in a monolithic substrate专利检索-沟道式电容器存储电容器电气元件和设备专利检索查询-专利查询网

Fabrication of MOS devices and complementary bipolar transistor devices in a monolithic substrate

阅读：491发布：2021-04-09

专利汇可以提供Fabrication of MOS devices and complementary bipolar transistor devices in a monolithic substrate专利检索，专利查询，专利分析的服务。并且P and N channel MOS''s, MOS capacitors, and PNP and NPN transistor devices are fabricated in isolated single crystal P and N type regions by a series of four deposition-diffusions common to both types of devices. The bases of PNP''s and the sources and drains of N channel MOS''s are formed simultaneously while the bases of NPN''s, and the sources and drains of P channel MOS''s, are also formed simultaneously. Thirdly, the emitters and collector contacts and guard rings of PNP''s, the base contacts for NPN''s, and the body contacts and guard rings for N channel MOS''s are simultaneously formed. Finally, an N+ type diffusion is performed to form the emitters and collector contacts of NPN''s, the source and drain contacts for N channel MOS''s, the base contacts for PNP''s, the body contacts for P channel MOS''s and one plate of MOS capacitors. An additional step may be performed to obtain thin gate oxide MOS''s and thin dielectric MOS capacitors. By surrounding the N channel MOS''s drain with a combination of the P+ guard ring and the gate metal, this device will function in the depletion mode.，下面是Fabrication of MOS devices and complementary bipolar transistor devices in a monolithic substrate专利的具体信息内容。

权利要求

1. A PROCESS FOR THE SIMULTANEOUS FABRICATION OF NPN, PNP, AND MOS DEVICES IN ISOLATED P AND N TYPE REGIONS COMPRISING IN SEQUENCE: DIFFUSING TO FORM IN P TYPE ISOLATED REGIONS BASES OF PNP''S AND SOURCES AND DRAINS OF N CHANNEL MOS''S, DIFFUSING TO FORM IN N TYPE ISOLATED REGIONS BASES OF NPN''S; DIFFUSING TO FORM IN P TYPE ISOLATED REGIONS COLLECTOR

2. A process as in claim 1 wherein the source and draIn regions of P channel MOS''s are formed in N type regions by said second diffusion steps; source and drain contacts of P channel MOS''s are formed by said third diffusion step; and body contacts of P channel MOS''s are formed in N type isolated regions by said fourth diffusion step.

3. A process as in claim 1 wherein a P type diffused resistor is formed in an N type isolated region by said second diffusion step and an N type diffused resistor is formed in a P type isolated region by said first diffusion step.

4. A process as in claim 1 wherein a first plate of a P type MOS capacitor is formed in a P type isolated region by said third diffusion step and a first plate of an N type MOS capacitor is formed in a N type isolated region by said fourth diffusion step.

5. A process as in claim 4 wherein oxide is accumulated over said first plates of said MOS capacitors and the channel region of said N channel MOS transistors during the process.

6. a process as in claim 4 including: partially etching oxide formed over said first plates of said MOS capacitors and the channel regions of said channel MOS transistors to form thin oxide dielectric MOS capacitors and thin gate oxide MOS transistors respectively.

7. A process as in claim 6 including doping said etched regions with an N type dopant.

8. A process as in claim 1 wherein oxide is accumulated over the channel region of said MOS transistors during said four diffusion steps.

9. A process as in claim 1 including partially etching oxide formed over the channel region of said MOS transistors to form thin gate oxide MOS transistors.

10. A process as in claim 9 including doping said etched regions with an N type dopant.

11. A process as in claim 1 wherein said second and third diffusion steps are performed by a single P type diffusion.

12. A process as in claim 11 including: partially etching oxide formed over the channel region of said MOS transistors to form thin gate oxide MOS transistors; and doping said etched regions with an N type dopant.

13. A process as in claim 1 wherein guard rings are formed in said P type isolated region on three sides of said drain regions by said third diffusion step.

14. A process as in claim 13 including applying metal to form gates across the channels of said N channel MOS''s such that said drain regions are surrounded by said guard rings and said metal gates.

15. A process for fabricating PNP''s and N channel MOS''s in isolated P type surface regions comprising: diffusing to form bases of PNP''s and sources and drains of N channel MOS''s; diffusing to form collector contacts and emitters of PNP''s and body contact of N channel MOS''s; and diffusing to form source and drain contacts of N channel MOS''s and base contact of PNP''s.

16. A process as in claim 15 wherein guard rings are formed in said P type isolated regions on three sides of said drain regions by said third diffusion step.

17. A process as in claim 16 including applying metal to form gates across the channels of said N channel MOS''s such that said drain regions are surrounded by said guard rings and said metal gates.

18. A process as in claim 15 including: partially etching oxide formed over the channel region of said MOS transistors to form thin gate oxide MOS transistors; and doping said etched regions with an N type dopant.

19. A process for the simultaneous fabrication of MOS capacitors and MOS transistors including the steps of forming a heavily doped N or P type semiconductor region for one plate of said MOS capacitor and forming the sources and drains, and body contacts for said N and P channel MOS transistors wherein the last steps before metallization comprises: partially etching oxide formed over said semiconductor plate of said capacitors and the channel regions of said transistoRs to form thin dielectric MOS capacitors and thin gate oxide MOS transistors, respectively; and doping said etched regions with an N type dopant.

20. A process as in claim 1 wherein said first and second diffusions may be performed in reverse order.

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