BACKGROUND OF THE INVENTION

The invention relates generally to digital frequency synthesis, and in particular, to digital frequency synthesis wherein frequencies may be changed rapidly with high resolution and minimal phase modulation.

Synthesis is the making up of a whole by combining separate parts or elements, and frequency synthesizers produce a range of output frequencies using this principle. Early frequency synthesizers used multiple crystals and contained as many crystal oscillators as frequency decades. Due to advances in various technologies, these multi-crystal synthesizers have now been superseded by single crystal synthesizers.

Direct synthesizers add and subtract multiples and submultiples of a single crystal oscillator frequency to provide a wide range of output frequencies. One such synthesizer is a multi-loop synthesizer which works on a “divide-and-add” principle. For example, if a 1 KHz output frequency is divided by 10 using a digital counter, the result is 100 Hz frequency resolution at one tenth the 1 KHz output frequency. Using a conventional heterodyne frequency converter or “mixer”, the resulting 100 Hz frequency may be added to the 1 KHz output frequency to generate successive 100 Hz steps. The 100 Hz frequency may also be divided by 10 to yield 10 Hz steps. These 10 Hz steps may then be added and/or subtracted to any of the preceding frequencies. Unfortunately, direct synthesizers suffer some serious drawbacks including generation of unwanted frequencies by the mixers requiring extensive filtering, a high sensitivity to wideband phase noise, complex circuitry, and a relatively high manufacturing cost.

The required frequency range in most current synthesizers is obtained using a variable voltage-controlled oscillator (VCO) whose output frequency is corrected by comparison with a reference frequency. This type of synthesizer is oftentimes referred to as an indirect synthesizer.

A block diagram of a known phase-locked loop (PLL) digital frequency synthesizer

10

is shown in FIG.

1

. The frequency synthesizer

10

includes a reference frequency source/oscillator

12

, a reference divider (divide-by-M)

14

, a phase error detector

16

, a loop filter

18

, a voltage-controlled oscillator (VCO)

20

, and a variable VCO divider (divide-by-N)

22

. The VCO divider

22

may comprise a digital counter that generates a series of count pulses. A VCO output signal at an output frequency F

vco

is generated by the VCO

20

and is detected by the VCO divider

22

. As those skilled in the art will readily comprehend, the output frequency F

vco

is used herein to designate a frequency which is typically changing in a predetermined manner. Thus, the output frequency F

vco

may represent one or more distinct, desired frequencies or may represent a range of desired frequencies. The VCO divider

22

counts the number of cycles of the VCO output signal and produces an output pulse after every N cycles, where N is a programmable divisor that can be varied between different count cycles. The VCO divider

22

therefore produces output pulses at a frequency of the output frequency F

vco

divided by the divisor N.

In order to synthesize multiple different frequencies from the VCO

20

, the VCO divider

22

is programmed to divide by different output divisors N whose value is variably set by a control mechanism

23

based on a desired value for the output frequency F

vco

. In a typical application, the desired value of the output frequency F

vco

may be one of many possible radio frequency (RF) channels for RF transmission or RF reception. Of course, if the variable output divisor N is equal to 1, the VCO divider

22

would output count pulses forming an output pulse train having a frequency substantially identical to the current value of the output frequency F

vco

.

The output pulse train generated by the VCO divider

22

is fed back to the phase error detector

16

for comparison with a reference frequency F

ref

. The reference frequency F

ref

is usually a fixed, accurate frequency generated by a crystal oscillator; but in some cases, it is a variable frequency derived from some other source that may include another frequency synthesizer. Since the reference frequency source

12

generates a reference frequency F

ref

that is usually higher than the desired step size between frequencies generated by the VCO

20

, the reference frequency F

ref

is transformed by the reference divider

14

into a reference pulse train having a frequency corresponding to the desired step size. The reference divider

14

divides the reference frequency F

ref

by a reference integer M. The reference integer M is selected so that the phase detector

16

is able to compare the reference pulse train and the output pulse train generated by the VCO divider

22

.

The difference/error in phase or frequency between the compared pulse trains is output as a phase error signal (typically a voltage) by the phase detector

16

. The phase error signal is filtered by the loop filter

18

to produce an output error, or control, signal. The loop filter

18

is typically a low-pass filter. The characteristics of the loop filter

18

govern how the PLL responds to changes in the phase error signal. The VCO

20

is a sinusoidal oscillator whose frequency is controlled by the output error signal. A negative value for the output error signal causes the VCO

20

to decrease the output frequency F

vco

and a positive value for the output error signal causes the VCO

20

to increase the output frequency F

vco

.

In this way, the VCO

20

may be tuned through a wide range of desired values for the output frequency F

vco

simply by varying the output error signal. By continuously comparing the output frequency F

vco

of the VCO

20

with a reference frequency F

ref

having a desired accuracy and, in response thereto, continuously correcting the output error signal, the frequency synthesizer

10

can achieve a very high accuracy. Indeed, the accuracy of the frequency synthesizer

10

can be on the order of one part per million or better, which is typically the accuracy of the reference frequency source

12

.

As mentioned above, the reference frequency F

ref

generated by the reference frequency source

12

is usually not equal to the output frequency F

vco

to which the VCO

20

is currently tuned; otherwise, the reference frequency source

12

could be used directly to generate the output frequency F

vco

. Because the reference frequency F

ref

and the desired value of the output frequency F

vco

typically differ, they must first be reduced by division to some common submultiple frequency before they can be compared. For example, suppose a desired range of the output frequency F

vco

includes a series of frequencies spaced apart by frequency steps of 25 KHz, for example, 1000.000 MHz, 1000.025 MHz, 1000.050 MHz . . . , and the reference frequency F

ref

is 12.8 MHz. The reference frequency F

ref

would need to be divided by 512 (the reference integer M equal to 512) by the reference divider

14

to generate a reference pulse train having a frequency of 25 KHz which is the spacing between the desired series of output frequencies F

vco

. For this example, the reference divider

14

may be comprised of a 9-stage binary counter (2

9

=512) to produce such a reference pulse train.

The output frequency F

vco

of the VCO

20

is divided by the variable output divisor N in the VCO divider

22

. The variable output divisor N is set to one of the numbers in the series 40000, 40001, 40002 . . . corresponding to the desired output frequency F

vco

expressed in multiples of 25 KHz, i.e., 1000.000 MHz/40000=25 KHz, 1000.025 MHz/40001=25 KHz, 1000.050 MHz/40002=25 KHz . . . If the output frequency F

vco

is at the desired value, the VCO divider

22

will generate pulses at the same 25 KHz rate as the reference divider

14

. Any difference between the frequencies of the reference pulse train and the output pulse train is detected by the phase detector

16

which generates an appropriate phase error signal, or voltage, to correct the output frequency F

vco

.

In many frequency synthesizer applications, relatively small frequency steps, or fine resolution, in the output frequency F

vco

is desired. The minimum frequency steps, or resolution, between different values of the output frequency F

vco

is a function of the value of the reference integer M and the reference frequency F

ref

. Consequently, the reference frequency F

ref

should be minimized and the reference integer M should be large. Unfortunately, as those skilled in the art will readily comprehend, lowering the reference frequency F

ref

tends to cause the loop to become unstable unless the loop bandwidth is correspondingly narrowed. In particular, loop bandwidth should preferably be an order of magnitude lower than the reference frequency F

ref

to assure that the loop filter

18

adequately smoothes the phase error signal generated by the phase detector

16

. At frequencies within the loop bandwidth, phase jitter, or phase noise, caused by a sudden phase change tends to be corrected by negative feedback in the PLL. Unfortunately, at frequencies outside the loop bandwidth, phase jitter is not corrected and the PLL may become noisy or unstable. A further disadvantage of a PLL with a narrow loop bandwidth is relatively lengthy settling times before the output frequency F

vco

reaches its desired value. Therefore, in designing a frequency synthesizer the need for fine resolution which requires a narrow loop bandwidth must be balanced with the need for low phase jitter, and the corresponding PLL stability, which requires a wide loop bandwidth. This incompatibility between fine resolution of the output frequency F

vco

and PLL stability is a significant disadvantage of simple single loop synthesizers.

Returning to the frequency synthesizer

10

of

FIG. 1

, the frequency of the pulses (in the reference pulse train and the output pulse train) received by the phase error detector

16

is dependent upon the spacing between frequencies in the desired series of output frequencies. This spacing between frequencies is known as “channel spacing” or “frequency resolution”. When narrower channel spacing or finer frequency resolution is desired, the pulses received by the phase error detector

16

become proportionally less frequent.

For a channel spacing of 100 Hz, pulses from the VCO divider

22

and the reference divider

14

are received at a rate of one pulse per 10 milliseconds ({fraction (1/100)} Hz=10 msec). If a smaller channel spacing is desired, for example 1 Hz, the phase detector

16

only receives one pulse per second ({fraction (1/1)} Hz=1 s). Consequently, the phase detector

16

has only one opportunity per second to measure the phase error between the output pulse train (derived from the current value of the output frequency F

vco

) and the reference pulse train. Because of this relatively long time between phase error measurements, narrow channel spacing may result in an undesirable delay before the frequency synthesizer

10

selects and settles down to a new output frequency with the desired precision. Therefore, there is yet another frequency synthesizer design tradeoff—resolution and speed. Finer frequency resolution also reduces the synthesizer's ability to correct for undesired short-term fluctuations in the output frequency F

vco

which can arise, for example, from mechanical vibrations.

Frequency changing speed may be decoupled from frequency resolution by varying an output divisor N used to reduce a particular output frequency for comparison to a reference frequency. Such a synthesizer using a variable output divisor is referred to hereafter as a “fractional-N” synthesizer since it synthesizes frequencies by apparently dividing by values of the output divisor N which are not whole numbers. As will be apparent, the output divisor N is variable around some base value, for example, the output divisor N can be varied between N and N+1 or N and N−1.

In operation, a fractional synthesizer varies the output divisor N between two or more integers, such as N and N+1, in a predetermined divisor sequence to approximate division with a non-integral output divisor. The fractional synthesizer may also compensate for any resulting post-division, fractional remainders. For example, suppose that in a certain fractional-N synthesizer design the output divisor N should optimally be equal to N+(⅓). As was stated, conventional non-fractional-N synthesizers only divide the output frequency F

vco

by integers. However, dividing by the output divisor N equal to N+(⅓) may be approximated by dividing by the integer sequence:

N=N, N, N+

1,

N, N, N+

1,

N, N, N+

1

Accordingly, if the output frequency F

vco

is divided by the output integer N two times out of three and by the output integer N plus 1 one time out of three, the output frequency F

vco

will be divided, on average, by the output digital divisor N having a value of N+⅓. This type of fractional-N synthesizer, as described below, results in a periodic approximation error which is large and must be accurately compensated.

The approximation of a fractional part by varying the output divider N between N and N+1 according to some pattern gives rise to a periodic error in the oscillator control voltage which is termed “fractional ripple”. In prior art fractional-N synthesizers, the periodic error is of such magnitude that steps must be taken to reduce it. A block diagram of a known technique described in U.S. Pat. No. 4,179,670 issued to Kingsbury for reducing the error is shown in FIG.

1

B. Typically, this prior art technique equates the instantaneous digital value in the fractional-N accumulator

38

with the approximation error, and converts the digital value to an analog compensation signal using the D/A converter

40

. The compensation signal must further be scaled down in proportion to the N value of the divider

22

before being subtracted from the phase comparator output at the ripple compensator

32

. The Kingsbury patent discloses that the variable divider

22

has an output pulse mark space ratio proportional to 1/N and thus the desired scaling down by the factor N can be achieved by chopping the compensation signal from the D/A convertor

40

using a chopper switch

41

driven by the output pulses from the variable divider

22

.

Despite these ingenuities of the prior art, fractional-N ripple compensation remains prone to analog circuit component tolerances, and thus a need exists to reduce the amount of ripple to be compensated or to otherwise devise simpler methods of compensation, which improvements may be obtained by practicing the present invention as described herein.

SUMMARY OF THE INVENTION

Using a novel fractional synthesis approach and arrangement, the present invention achieves fine frequency resolution with low phase noise while retaining a high phase comparison frequency/fast frequency changing speed using a single phase-lock synthesizer loop. Benefits of the invention also include low complexity and low cost.

In a first example embodiment of the present invention, a frequency synthesizer accurately generates an output signal of a desired frequency related to a reference phase comparison frequency signal by a non-integral factor. A reference frequency generator supplies a reference frequency signal. A first variable divider divides the reference frequency signal by a first predetermined divisor M and produces an output pulse for the reference phase comparison frequency signal after every M cycles of the reference frequency signal. A fractional controller varies the first predetermined divisor M between successive output pulses of the variable reference divider to produce a mean output pulse frequency having a non-integral relationship to the reference signal frequency. A voltage controlled oscillator produces the output signal frequency and is controlled by a control voltage signal. A second variable divider divides the output signal frequency by a second predetermined divisor N to produce an output pulse of a second phase comparison frequency signal after every N cycles of the output signal. A phase detector compares the reference phase comparison frequency signal with the second phase comparison frequency signal to produce an error signal. A signal processor processes the error signal to produce the control signal such that the output signal from the oscillator is controlled to the desired frequency.

The signal processor includes a low pass loop filter and a ripple compensator, the latter being used to compensate for variations of the first divisor M from a non-integral mean value. In a relatively simple implementation, the fractional-M controller varies the reference divisor M between preselected integer values in a predetermined pattern, e.g., M and M+1. An overflow accumulator is incremented when the reference divider produces an output pulse, and the predetermined pattern is determined by overflow of the accumulator.

In a second example embodiment of the present invention, a fractional controller varies the first and the second predetermined integers between a first pair of values (N1, M1) and a second pair of values (N2, M2). The pairs of values are selected so that a ratio of the first pair of values is a close fractional approximation less than a ratio of the desired frequency to the reference frequency, and the ratio of the second pair of values is a close fractional approximation greater than the ratio of the desired frequency to the reference frequency. Thus, the fractional controller varies the integers M and N between different pairs of preselected integer values in a predetermined pattern.

In a third example embodiment of the present invention, the fractional controller generates a loop gain compensation signal for controlling a gain of the error signal generated by the phase detector. This loop gain compensation signal minimizes the effect of varying N and/or M. The phase detector error signal is scaled based on a current value of M or N. For example, a larger value of M results in a larger scaling of the error signal.

In a fourth example embodiment, the phase detector is a charge pump type of phase detector that includes a pull-up current mirror and a pull-down current mirror for reflecting a current generated based on the compensation signal received from the fractional controller. A negative or positive pulse of current is generated depending upon a sign of the detected phase error. The width of the current pulse is based on the magnitude of the phase error while the magnitude of the current pulse is varied in proportion to a variation of M or N.

The present invention also provides various methods for synthesizing a range of frequencies generated by an electrically tuned oscillator. For a desired output frequency to be generated by the oscillator, a sequence of rational fractions is determined that equals a non-integral value in the mean. The reference oscillator frequency is divided by the sequence of denominator values of the rational fractions while the electrically tuned oscillator frequency is divided by the sequence of numerators of the rational fractions. The divided frequencies are compared to a phase error signal. From the error signal, a control signal is produced applied to the oscillator to generate the desired output frequency.

In accordance with the second example embodiment, a first and second pair of integer divisors are determined. The reference frequency and oscillator output frequency are divided by a sequence of the first and second pairs. Various procedures are set forth for determining the values of the first and second pairs of integer values for each desired output frequency and the sequence in which those integer pairs are used to reduce an accumulated/integrated phase error.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the present invention will be described in further detail below in conjunction with the drawings in which like reference numbers refer to similar elements throughout the drawings:

FIG. 1A

is a functional block diagram of a known PLL digital frequency synthesizer;

FIG. 1B

is a block diagram of a prior art fractional-N synthesizer;

FIG. 2A

is a function block diagram of a fractional-M digital frequency synthesizer in accordance with the present invention;

FIG. 2B

is a block diagram of a fractional-M controller which may be used in the fractional-M frequency synthesizer shown in

FIG. 2A

;

FIG. 3

is a functional block diagram of a sequential fraction approximation synthesizer according to the present invention in which both N and M are varied during production of a single output frequency;

FIG. 4

is a flowchart showing example procedures for selecting optimal values for a reference divisor M and an output divisor N which may be implemented in the synthesizer shown in

FIG. 3

in accordance with the present invention;

FIG. 5

is an illustration of a highest common period concept used in a cycle selection embodiment in accordance with the invention;

FIGS. 6-8

are flowcharts showing various example procedures for selecting values for integer pairs (M, N) in accordance with another exemplary embodiment of the invention; and

FIG. 9

is a diagram showing an exemplary implementation of a phase detector that may be used in a fractional digital frequency synthesizer in accordance with the present invention.

DETAILED DESCRIPTION OF INVENTION

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular circuits, components, techniques, etc. in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well known methods, devices, and circuits are omitted so as not to obscure the description of the present invention with unnecessary detail.

Fractional-M Frequency Synthesis

In one exemplary embodiment of the present invention shown in

FIG. 2

, the frequency changing speed and the synthesizer settling time are decoupled from the fineness of frequency resolution by varying a reference divisor M. The reference divisor M is a variable integer divisor which is used to reduce the reference frequency F

ref

for comparison to an output frequency F

vco

during the time a single output frequency is being generated. A frequency synthesizer in accordance with the present invention that accomplishes this decoupling is referred to hereafter as a “fractional-M” synthesizer which synthesizes frequencies by varying the reference divider between integer values as opposed to varying the output divider. As described below, the fractional-M frequency synthesizer in accordance with this exemplary embodiment of the invention may employ a variable reference divisor M together with value of an output integer N that is fixed during production of a given frequency in order to approximate a fractional frequency ratio while compensating for approximation errors.

More specifically, the reference divisor M is varied between two or more integers with a “mark-space ratio” selected to approximate the desired fractional part. The various values of the reference divisor M include typically a base (reference) integer M and integers around the base integer M, such as M+1, M+2 or M−1. The value of the reference integer M may vary for different desired output frequencies F

vco

, as may the output divisor N. To approximate division by a reference divisor M which has a fractional value, the reference divisor M is varied in accordance with a predetermined divisor sequence. To approximate the reference divisor M having a value equal to a selected base reference integer M plus a fraction of ⅓, for example, the reference divisor M is varied in accordance with the following reference divisor sequence:

M=M, M, M+

1,

M, M, M+

1,

M, M, M+

1  (1)

In this reference divisor sequence (1), every third value of the reference divisor M is M+1 instead of M. A more complicated reference divisor sequence involving M, M+1, and M−1 may be used in order to reduce any resulting approximation errors, i.e., dividing periodically by M−1 to offset the error in approximating division by (M+⅓) using M and M+1.

The reference divisor sequence (1) may be produced by using one or more registers, designated herein as an accumulator, to accumulate fractional remainders from each division until an accumulated sum equals or exceeds one. At that point, a variable reference divider

30

divides by M+1 for the next frequency cycle to correct for the accumulated remainders, or error. Any residual fractional remainder is carried forward in the accumulator, and the accumulator continues to accumulate unused fractional remainders for subsequent divisions until the accumulated sum again equals or exceeds one. In this way, overflow from the accumulator generates the required reference divisor sequence of values for the reference divisor M.

In known implementations, such as that shown in

FIGS. 1A and 1B

, the reference divisor M is fixed during a period in which the output frequency F

vco

is required to be constant. The present invention advantageously varies the value of the reference divisor M during this period. In a second example embodiment described below, both the reference divisor M used to reduce the reference frequency F

ref

and the output divisor N used to reduce the output frequency F

vco

may be varied during this period.

FIG. 2A

illustrates a fractional-M frequency synthesizer in accordance with the present invention. Since many of the elements described previously with respect to

FIG. 1A

are duplicated in

FIG. 2A

, the following description focuses on the newly-added features or elements. The fractional-M synthesizer comprises the variable reference divider

30

and a programmable VCO divider

34

. While not shown, the reference frequency F

ref

from the reference source

12

and/or the output frequency F

vco

from the VCO

20

may be prescaled (by a suitable prescaler) to reduce the required operating speed of the digital logic used to build either, or both, of the variable dividers

30

and

34

. A suitable dual-modulus prescaler and further variable divider design techniques are disclosed in U.S. Pat. No. 5,066,927, entitled “Dual Modulus Counter For Use In A Phase Locked Loop” and issued to Dent, the disclosure of which is hereby incorporated by reference. Alternatively, the reference frequency F

ref

and/or the output frequency F

vco

may be converted using a heterodyne frequency converter or mixer to a different frequency (usually lower), if more suitable for the realization of the desired divider ratios.

The variable reference divider

30

closely approximates division by a non-integral value of the reference divisor M by using a reference divisor sequence of integers M and M+1. Of course, other more complicated divisor sequences of M-based integers may be used. Using the exemplary reference divisor sequence (1) set forth above, the variable reference divider

30

divides the reference frequency F

ref

by reference integers M or M+1 as controllably selected based on a control signal generated by a fractional-M controller

36

. The variable reference divider

30

produces an output pulse in a reference pulse train after every M cycles of the reference frequency F

ref

. The output pulse train generated by the variable reference divider

30

is compared by the phase detector

16

to an output pulse train from the VCO divider

22

.

The fractional-M controller

36

accumulates, in an accumulator

38

, fractional remainders dM from each division until the accumulated sum equals or exceeds some maximum value, or maximum count, M

max

. The maximum value M

max

is called the “modulus” of the accumulator

38

. When the accumulated sum equals or exceeds the modulus M

max

, the accumulator sum is reset and a “carry” pulse is generated. In this example, the fractional remainder dM determines the number of times (on average) that the reference frequency F

ref

should be divided by the reference integer M before being divided by M+1. The reference divider

30

, the controller

36

and the accumulator

38

comprise a reference divider circuit for dividing the reference frequency by the reference integer M, or reference divisor M. The values of the reference integer M and the fractional remainder dM are shown as inputs to the fractional-M controller

36

and are set taking account of such factors as the output frequency F

vco

of the VCO

20

, the value of the output divisor N, and other possible factors described in later example embodiments.

When the accumulated sum equals or exceeds the modulus M

max

, the accumulator

38

is reduced by a value equal to modulus M

max

and the variable reference divider

30

is instructed by the fractional-M controller

36

to divide by M+1 for the next divide cycle of the reference divider

30

to correct for accumulated error. Thereafter, the fractional-M controller

36

changes the value of the reference divisor M back to the reference integer M until instructed otherwise via the control signal. Any residual fractional remainder in the accumulator

38

after reduction modulo M

max

is carried forward in the accumulator

38

and the accumulator

38

continues to accumulate fractional remainders dM from subsequent division cycles until the accumulated value again equals or exceeds the modulus M

max

. In this way, overflow from the accumulator

38

generates the required reference divisor sequence, such as the sequence (1), for the reference divisor M.

For example, a modulo-Q accumulator, where Q is an integer, may be used to generate the desired reference divisor sequence. The modulo-Q accumulator stores the fractional remainder dM. Based on whether the modulo-Q accumulator overflows, or underflows, on a last accumulation cycle, a value for the reference divisor M (which could vary between the reference integer M and the reference integer plus one M+1) is selected. The modulo-Q accumulator may be incremented, or decremented, on each count cycle by a selected integer X amount. The value of “Q” may be determined in accordance with the following equation:

Q=F

vco

/C

where C is a common factor, or preferably the highest common factor, of the output frequency F

vco

and the reference frequency F

ref

.

The approximation of fractional values for the reference divisor M by varying the integer divider between different values, e.g., M and M+1, according to a particular divisor sequence, or pattern, results in a periodic error in the output error signal to the VCO

20

, referred to hereafter as “fractional ripple”. The cumulative fractional remainder stored at any one time in the accumulator

38

represents the instantaneous fractional ripple error.

The fractional ripple error may be visualized as a sawtooth waveform that ramps up to a peak value as the accumulator

38

counts up to the modulus M

max

. When the accumulator

38

reaches the modulus M

max

, the value in the accumulator

38

is reduced by the modulus M

max

. To subtract out the instantaneous fractional ripple error of the loop, a ripple circuit

37

generates a digital ripple compensation signal which is representative of the current accumulated value stored in the accumulator

38

. A digital-to-analog (D/A) converter

40

converts the digital ripple compensation signal into an analog ripple compensation signal. The analog ripple compensation signal representing the fractional ripple error is then subtracted from, or added to (as necessary), the phase error signal generated by the phase detector

16

in a ripple compensator

32

. The loop filter

18

, the ripple compensator

32

, the D/A converter

40

and the controller

36

or

42

comprise a signal processor. The phase detector

16

and the signal processor in combination comprise an output processing circuit.

In a general embodiment of the fractional-M synthesizer according to the invention, a sequence of division ratios M

1

, M

2

. . . M

i

together with the number of times A

i

each division ratio is used in a repeating cycle is determined to satisfy the equation:

A

1

*

M

1

+

A

2

*

M

2

⁢

⁢

…

+

A

i

*

M

i

N

*

(

A

1

+

A

2

+

…

+

A

i

)

=

F

ref

F

vco

where M

1

, M

2

. . . M

i

represent i different values for the reference divisor M used by the reference divider during production of the output frequency F

vco

and A

1

, A

2

. . . A

i

represent a corresponding number of times that each value of the reference divisor M is used in one cycle of the predetermined pattern. Since many solutions exist, the invention comprises selecting that solution which minimizes fractional ripple error.

To illustrate the operation of this exemplary embodiment, the ratio of the output frequency F

vco

and the reference frequency F

ref

may be expressed in a prior art manner as:

F

vco

/F

ref

=(

N+dN

)/

M

o

  (2)

where the reference integer M

o

is a fixed integer to be divided into the reference frequency F

ref

, the output integer N is the integral portion of the variable output divisor N and dN is the fractional portion of the variable output divisor N to be realized by prior fractional-N techniques. According to the present invention, the reciprocal ratio F

ref

/F

vco

may be expressed as:

F

ref

/F

vco

=(

M+dM

)/

N

o

  (3)

where the output integer N

o

is an integer, the reference integer M is the integer portion of the reference divisor M and the fractional remainder dM is the fractional portion of the reference divisor M realized using fractional-M techniques.

Equating equations (2) and (3) results in the following equation:

M+dM=N

o

*M

o

/(

N+dN

)

Now suppose that the fractional-N synthesizer was to have synthesized a fraction dN given by n/d, where n is the numerator of the fraction and d is the denominator of the fraction. For example, if the denominator d equals 10, then the fractional-N synthesizer would have synthesized VCO output frequencies of {N, N+{fraction (1/10)}, N+{fraction (2/10)}, N+{fraction (3/10)} . . . } times the phase comparison frequency F

ref

/M

o

. Substituting dN=n/d in the above equation and rearranging so that the resulting denominator is an integer results in the equation:

M+dM=No*Mo*d

/(

N*d+n)

Thus, the reference integer M is the whole part and dM is the remainder of (N

o

*M

o

*d) divided by (N*d+n). The remainder dM has the form r/(N*d+n) showing that it is a rational fraction with a denominator equal to (N*d+n). Thus the required fractional-M value dM that is to be produced by fractional-M controller

36

has a denominator of (N*d+n), which is the required modulus of the accumulator

38

.

Further details of the fractional-M controller are shown in

FIG. 2B. A

calculator

39

receives an indication of the desired frequency, which may be in terms of the parameters N, dN=n/d and M

o

that would be used in a prior art fractional-N synthesizer. The calculator

39

computes the required accumulator modulus (N*d+n) and the remainder r upon division of N

o

*M

o

*d by this modulus, where N

o

is the value of the output divider to be used for the fractional-M synthesizer One method for selecting a value of N

o

that the calculator

39

may be programmed to implement is to select a value of N

o

so that the computed value of M is always the same. An alternative criterion may be to select a value of N

o

nearest to the value of N

o

which results in a constant computed value of M which is an easily obtained division ration, such as a multiple of 64 or other prescaler value. The fractional-M synthesizer can thus be used to simplify the high-speed output divider

34

such as by eliminating the need for a multi-modulus prescaler, or by using a higher prescaler division ratio that cannot provide certain values of N

o

.

The calculator

39

can thus be programmed to computer fractional-M parameters while avoiding the values of N

o

that cannot be reached. The calculator

39

computers the fractional-m modulus for the accumulator

38

from the parameters N, d, and n that would normally be used to program a prior art fractional-N synthesizer, while the increment to the accumulator

38

is computed as the remained upon dividing N

o

*M

o

*d by this modulus. The base value M for the reference divider

30

is computed as the whole part obtained when N

o

*M

o

*d is divided by the accumulator modulus.

In cases where the reference integer M is greater than the output integer N, such as when the output frequency F

vco

is mixed down to a lower frequency before being input to the VCO divider

22

, or where the reference frequency F

ref

is higher than the output frequency F

vco

, the fractional ripple is advantageously reduced since the ratio of N/M is less than 1. There is also an advantage in making the fractional ripple a function of the reference source

12

rather than the VCO

20

. If the magnitude of the fractional ripple is dependent upon the value of the output divisor N, the ripple compensation signal provided to the ripple compensator

41

must be accurately scaled for each different selected output frequency F

vco

. Such scaling requires extra multiplication and determination of many different scaling factors. However, in this example embodiment of the present invention, the magnitude of the fractional ripple is based on the reference divisor M. Because the reference frequency F

ref

is fixed, the fractional ripple is independent of the output divisor N and the output frequency F

vco

. Therefore, scaling of the ripple compensation signal to correct the fractional ripple is not needed.

The modulus N*d+n of the accumulator

38

is the lowest integer value of the output divisor N that produces a desired output frequency F

vco

using conventional non-fractional synthesis as in FIG.

1

A. Assume as an example that the desired output frequency F

vco

is 1000.1 MHz and the reference frequency F

ref

is 10 MHz. The reference integer M is selected on the order of 10 to give a phase comparison rate (as well as channel spacing/frequency resolution) in the 1 MHz range, i.e., 10 MHz/10=1 MHz. A value for the output integer N and a reference divisor sequence containing “m1” divide-by-10's, (i.e., divide by M=10), and “m2” divide-by-11's, (i.e., divide by M+1=11) are determined which result in a mean output frequency corresponding to the desired output frequency F

vco

of 1000.1 MHz. The equation therefore to be satisfied and solved is:

F

ref

(

10

*

m1

)

+

(

11

+

m2

)

=

F

vco

(

m1

+

m2

)

*

N

(

4

)

Thus, the sum (m1+m2) equals the total number of integer divisions required to approximate one cycle of the fractional-M division. Since the desired output frequency F

vco

is just over 1000 times the 1 MHz phase comparison rate/frequency resolution, a suitable choice for the output integer N is the next highest integer, or N=1001. With M=10 and N=1001, the solution of the equation (4) is m1=9911, m2=90, and (m1+m2)=10001. Accordingly, the reference frequency F

ref

is divided 90 times by 11 for every 9911 times the reference frequency F

ref

is divided by 10. The 90 instances of divide-by-11 are preferably distributed among the 9911 instances of divide-by-10 as evenly as possible throughout the total 10001 division cycles. Such a pattern may be produced by the overflow events of a modulo-10001 accumulator repeatedly incremented by 90. Thus, in the novel fractional-M synthesizer in accordance with the present invention, the value of the output integer N that would be needed in a non-fractional synthesizer is determined and used to program the modulus M

max

of the fractional-M accumulator

38

. In the above example, the output integer N equals 10001 with a corresponding 0.1 MHz phase comparison frequency.

It may be practically inconvenient to use an accumulator whose modulus varies according to the desired output frequency F

vco

. A constant modulus equal to a power of two (binary) is typically easier to implement because it facilitates generation of a ripple compensation signal of constant magnitude using a digital-to-analog converter driven directly by the most significant fractional accumulator bits. Use of a binary-modulus accumulator results in an approximation to the desired output frequency, the accuracy of which can be as high as necessary by using sufficiently long word length.

For example, if in the above example a 16-bit binary accumulator were used (modulo-65536 instead of modulo-10001), the increment to the accumulator which most nearly yields the desired frequency is 649, and the resulting frequency error is −305 Hz. Irrespective of which particular accumulator modulus is used, accumulator increments may be computed in real time by the fractional-M controller

36

for each new desired output frequency, or computed in advance for each possible output frequency, stored in a look-up table and later retrieved by the fractional-M controller

36

.

In the above example, the choice of the output integer N=1001 was somewhat arbitrary. If the reference divisor M has the values M=10 and M+1=11, the output integer N may be chosen anywhere in the range of 1000<N≦1100 with different resulting error patterns, some of which may be more desirable than others. For each desired output frequency F

vco

, a value of the output integer N is chosen within this range based on desired characteristics of the fractional ripple pattern, e.g. minimum low frequency spectral energy. Some inventive methods for selecting values, or sequences of values, for both the reference integer M and the output integer N will now be described.

Fractional N and M Frequency Synthesis

Another exemplary embodiment of the present invention is shown in FIG.

3

. Under the control of a controller

42

, the variable reference divider

30

divides the reference frequency F

ref

by a reference divisor sequence of values for the reference divisor M. The controller

42

sends the values of the reference divisor M to reference divider

30

from the controller

42

. For example, a reference divisor sequence of values for the reference divisor M comprised of M and M+1 may be generated to produce a “mean”, non-integer divisor between M and M+1 as described in the above embodiment.

Moreover, the controller

42

also generates an output divisor sequence of values for the variable output divisor N which is provided to the VCO divider

34

to produce a mean, non-integer divisor. The controller

42

may be implemented using any suitable electronic circuitry including for example, a programmed microprocessor, a digital signal processor, an application specific integrated circuit (ASIC), and the like. The values of the reference integer M and the output integer N are selected by the controller

42

based on the selected desired output frequency F

vco

, such as the frequency of a recently assigned RF working channel, which is an input to the controller

42

.

The principle of the second exemplary embodiment is described herein for the example case where only two pairs of divisor values are used. These pairs of divisor values are first output and reference integers N1, M1 and second output and reference integers N2, M2. Values for the output and reference integers N1, M1, N2, M2 may be determined within certain bounds to satisfy the following:

F

vco

(below)=(

N

1/

M

1)*

F

ref

  (5)

and

F

vco

(above)=(

N

2

/M

2)*

F

ref

  (6)

The values of the first and second integer pairs (N1, M1) and (N2, M2) are preferably determined so that a below frequency F

vco

(below) and an above frequency F

vco

(above) are equal to the desired output frequency F

vco

. However, if this cannot be accomplished, the integer pairs should be determined so that the below and above frequencies F

vco

(below) and F

vco

(above) are respectively as close as possible below (using N1, M1) and above (using N2, M2) the desired output frequency F

vco

. In this way, when the selected values of the first output and reference integers N1, M1 are used, the phase error at the phase detector

16

develops a progressive lag as slowly as possible. Similarly, when the selected values of the second output and reference integers N2, M2 are used, the phase error develops a progressive advance as slowly as possible.

By alternating between the first integer pair N1, M1 and the second integer pair N2, M2, the accumulation of phase error may be substantially minimized. Various algorithms may therefore be devised to minimize the cumulative phase error (or sometimes even more advantageously the integral of the cumulative phase error) thereby resulting in a fractional ripple considerably smaller than in a purely fractional-N frequency synthesizer. As mentioned above, the goal of such an algorithm is to determine values for the reference and output integers M and N that best approximate a frequency just below (for the first integer pair N1, M1) and just above (for the second integer pair N2, M2) the desired output frequency F

vco

.

Table 1 gives an example of values for the first and second integer pairs (N1, M1) and (N2, M2) calculated in accordance with an algorithm described below for synthesizing a series of 25 KHz spaced channels (i.e., the frequency resolution) starting at an output frequency of 1000 MHz using a reference frequency of 13 MHz with a design constraint that phase comparisons should be performed at least every 200 KHz so that the reference integer M should be no greater than 65 (13 MHz/200 KHz=65).

TABLE 1

CHANNEL

ERROR

ERROR

Entry

(MHz)

N1

M1

(KHz)

N2

M2

(KHz)

1

1000.000

1000

13

0

1000

13

0

2

1000.025

3077

40

0

3077

40

0

3

1000.050

3154

41

−1.2

4231

55

+4.6

4

1000.075

1077

14

−3.6

6385

57

+12

5

1000.100

3308

43

−7.0

2231

29

+3.5

6

1000.125

4539

59

−6.3

1154

15

+8.4

7

1000.150

4963

61

−2.5

3539

46

+2.1

Consider Entry 3 wherein the desired output frequency F

vco

, or channel, is 1000.050 MHz with the reference frequency F

ref

at 13 MHz. Using equation (5), when the first output integer N1 is 3154 and the first reference integer M1 is 41, we obtain:

F

vco

(below)=(3154*13 MHz)/41=1000.0488 MHz

which is just below the desired output frequency F

vco

of 1000.050 MHz, or an error of −1.2 KHz. When the second output integer N2 equals 4231 and the second reference integer M2 is 55, we obtain a value for the above frequency F

vco

(above) of 1000.0545 MHz, or an error of+4.5 KHz, using equation (6):

F

vco

(above)=(4231*13 MHz)/55=1000.0545 MHz

The solution then is to choose a sequence of the first and second integer pairs N1, M1 and N2, M2 that generates a mean between the two determined “close” above and below frequencies to approximate the desired output frequency F

vco

of 1000.050 MHz. One solution is a sequence consisting of dividing by the first integer pair N1, M1 three times and the second integer pair N2, M2 one time, then repeating the four pair sequence.

In Table 1, the values for both the output integer N and the reference integer M in the integer pairs (N1, M1) and (N2, M2) may be multiplied by a factor if the determined value of the output integer N is too low to be practical, as long as the determined value of the reference integer M remains below a desired maximum. This may be necessary when the variable output divider

22

incorporates a variable-ratio, high-speed prescaler that sets limits on the lower values of the output integer N that can be programmed.

The approximate magnitudes of the errors listed in Table 1 (all less than 13 KHz) are significantly smaller than the 175 KHz peak error of a fractional-N synthesizer design in which only the output divisor N is varied. This error reduction of more than an order of magnitude may, in some cases, permit ripple compensation mechanisms to be dispensed with, particularly when the sequence of the integer pairs (N1, M1) and (N2, M2) is optimized to spectrally disperse the ripple error.

FIG. 4

is a flowchart outlining general but nonetheless example procedures which may be implemented by the controller

42

to determine optimum values for the integer pairs (N1, M1) and (N2, M2). Routine

50

may be used by computational circuitry for example to generate a look-up table similar to Table 1 described above. In block

52

, the selected frequency channel F

vco

for which optimal values for the integer pairs (N1, M1) and (N2, M2) are to be determined is detected. The values of the integer pairs (N1, M1) and (N2, M2) are then determined by the using the above equations (5) and (6).

The calculations of the values of integer pairs (N1, M1) and (N2, M2) are accomplished m in block

54

. Of course, if either of the values for the below and above frequencies F

vco

(below) and F

vco

(above) are equal to the desired output frequency F

vco

, the corresponding values of the reference and output integers M and N are used as in a non-fractional synthesizer in that their values are constant for that particular output frequency F

vco

or channel.

The values of the integer pairs (N1, M1) and (N2, M2) determined in block

54

are stored in a look-up table for the particular selected output frequency F

vco

in block

56

. A decision is made in block

58

whether another frequency channel is to be analyzed. If so, the previous output frequency (or channel) F

vco

is incremented to the next channel frequency in block

60

and control returns to the block

52

.

Thus, the general technique includes varying the reference and output divisors (N, M) between two pairs of associated, predetermined values of the integer pairs (N1, M1) and (N2, M2) determined by solving equations (5) and (6). The values of the integer pairs (N1, M1) and (N2, M2) that result in the below and above frequencies F

vco

(below) and F

vco

(above) closest to the desired output frequency F

vco

are stored in the look-up table. Determining an optimum sequence/pattern comprised of the values of the integer pairs (N

1,

M1) and (N2, M2) is referred to as “sequential fraction approximation” and the method of determining the sequences is further discussed below.

If the entries in Table 1 are extended, the approximated errors remain relatively small up to a selected output frequency F

vco

of around 1000.800 MHz The immediately following channels, however, are numerically more difficult to approximate by integers within the specified range. This difficulty is limited to a range of channels and it is eventually possible to continue the table with low approximation errors. Such regions of difficulty are associated with restrictions placed on allowable values of the output and reference integers N and M. These restrictions are typically design restrictions based on circuit parameters and the like. By relaxing these design restrictions, the difficulty in approximating the values of the integers (N, M) can be made less troublesome as described below.

A strategy for selecting values for the integer pairs (N, M) for a particular division cycle may be based on minimizing the integral of accumulated phase error or of minimizing the instantaneous value of the phase error as in the above method. An advantage of minimizing “integrated phase error” is that the low-frequency spectral content of the fractional ripple is reduced. Minimizing integrated phase error generally requires that the number of integer pairs (N, M) used not be restricted to the two pairs determined using the

FIG. 4

procedure. In a further generalization of the sequential fraction approximation technique, therefore, there is no restriction on the number of different values of the integer pairs (N, M) that can be invoked during the synthesis of a particular frequency. In general, a different pair of integers, not restricted to only two pairs, can be selected for each division cycle.

The following restrictions on the acceptable values of the integers (N, M) may apply in certain practical implementations, however:

(a) the reference integer M should be less than some specified maximum, i.e., phase comparisons should take place with at least a minimum frequency; and

(b) a minimum value of the output integer N may be set, so that the divider

34

may more easily be constructed to operate at high speeds with the aid of a prescaler.

An alternative view of the function of the dividers

30

and

36

in terms of their “selecting cycles” for comparison will now be outlined as an aid to understanding the invention. When the output frequency F

vco

is divided by the output divisor N having a value equal to the output integer N, cycles of the output frequency F

vco

are effectively being counted, i.e., cycle 1, cycle 2, cycle 3, . . . cycle N, at which point the cycle count repeats itself. However, the variable VCO divider

34

only transmits one output pulse to the phase detector

16

when the cycle count reaches the output integer N

o

In effect, programming the VCO divider

34

to divide by the output integer N for this division is equivalent to ignoring the intervening cycles 1, 2, 3, . . . N−1 and selecting the cycle which is N cycles in the future for performing the next phase comparison with a reference cycle. Likewise, in the variable reference divider

30

when the reference divisor M equals the reference integer M, cycles 1, 2, 3, . . . M−1 of the reference frequency F

ref

are effectively ignored as there is an output pulse only after M cycles. Thus, the reference divider

30

effectively selects a reference cycle which is M cycles in the future to compare with a VCO output cycle which is N cycles in the future.

Therefore, selecting values for the integers N and M is effectively selecting a reference cycle M ahead and an output cycle N ahead for phase comparison in the phase detector

16

. Phase comparison is equivalent to measuring the time difference between the positive going (from negative to positive) zero crossings of the Mth reference cycle and the Nth output cycle. If the zero crossings do not exactly coincide, there is a positive or negative phase error depending upon which zero crossing firs occurred. When viewed in this framework, a cycle selection feature of the present invention endeavors to determine which future zero crossings of the reference frequency F

ref

and of the output frequency F

vco

most closely coincide within a selected maximum time limit, thereby determining the values of M and N to use for the current divide cycle.

FIG. 5

illustrates the concept of a highest common subperiod between two signals having different frequencies, such as the reference frequency F

ref

and the output frequency F

vco

. In the example shown in

FIG. 5

, pulses (or edges of pulses) of the reference frequency F

ref

are set equal to 39 MHz (shown at line A) and pulses of the output frequency F

vco

are set equal to 325 MHz (shown at line B). The highest common factor between 39 MHz and 325 MHz is 13 MHz, i.e., 39 MHz=3×13 MHz and 325 MHz=25×13 MHz As the highest common factor, 13 MHz is established as the “frequency unit”. Accordingly, the reference frequency F

ref

is 3 frequency units and the output frequency F

vco

is 25 frequency units. As should be noted, dividing 39 and 325 by the common factor of 13 results in mutually prime numbers (3 and 25). Mutually prime numbers, as is known, have no common factor.

The product of the reference and output frequencies F

ref

and F

vco

(in frequency units) is 3×25, or 75 frequency units, corresponding in hertz to 975 MHz. The edges of such a 975 MHz signal are shown at line C in FIG.

5

. As shown, the edges/pulses numbered 0, 75, 150 . . . etc. of the 975 MHz signal coincide with the edges/pulses of both the reference frequency F

ref

(line A) and the output frequency F

vco

(line B). Accordingly, 975 MHz is the lowest frequency common multiple of both the reference and output frequencies F

ref

and F

vco

. The cycle period of the 975 MHz signal is thus the “highest common subperiod” of the reference and output frequencies F

ref

and F

vco

. An edge of the reference frequency F

ref

and an edge of the output frequency F

vco

therefore coincide at a regular interval which is an integer multiple of this highest common subperiod. These zero crossing coincidences are the preferred edges upon which to perform a phase comparison since, at these coincidences, the expected timing error is zero.

Unfortunately, such zero crossing coincidences at an integer multiple of the highest common subperiod may not occur frequently enough. In the example shown in

FIG. 5

, the numbers have been chosen to illustrate zero crossing coincidences at a conveniently visible number of common subperiods. However, if the desired output frequency F

vco

was not 325 MHz but was 324.95 MHz, the lines A, B and C would have to be significantly longer to illustrate just two consecutive zero crossing coincidences. Such prolonged periods between phase comparisons are typically unsatisfactory.

In the example shown in

FIG. 5

, it might be desired to perform phase comparisons at the more frequent intervals of reference signal zero crossings occurring at 0, 25, 50, 75, 100, 125 and 150 common subperiods, of which only those at 0, 75 and 150 are “ideal” positions that exactly coincide with a zero crossing of the VCO output frequency. The cycles of the VCO output frequency most closely coinciding with the “non-ideal” phase comparisons at 25, 50, 100 and 125 common subperiods have zero crossings at 24, 51, 99 and 126 common subperiods respectively, which are respectively one subperiod early, one subperiod late, one subperiod early and one subperiod late relative to the reference signal zero crossings at 25, 50, 100 and 125 subperiods. The expected timing error sequence starting at zero is thus 0, +1, −1, 0, +1, −1, 0 . . . , where a+1 indicates that the edge of the output frequency F

vco

occurs one common subperiod earlier than the compared edge of the reference frequency F

ref

and a −1 indicates that the edge of the output frequency F

vco

occurs one common subperiod later than the compared edge of the reference frequency F

ref