专利汇可以提供PHASE-LOCKED CIRCUIT EMPLOYING CAPACITANCE MULTIPLICATION专利检索,专利查询,专利分析的服务。并且A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.,下面是PHASE-LOCKED CIRCUIT EMPLOYING CAPACITANCE MULTIPLICATION专利的具体信息内容。
What is claimed is:
The present invention relates to phase-locked loop (PLL) circuits, and, more particularly, to charge-pump PLLs.
A phase-locked loop circuit is a circuit that generates, or synthesizes, a periodic output signal that has a constant phase and frequency with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-locked loop is the charge-pump PLL.
One issue of designing charge pump PLL is stability. As the stability of charge pump PLL increases when the capacitance increases, the capacitance of the integral charge pump path needs to be as large as possible. A satisfactory capacitance is typically large, hence, costs are increased.
Accordingly, a charge pump phase-locked loop circuit with a smaller area is provided. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.
The invention also provides another phase-locked loop circuit. The phase-locked loop circuit comprises a first and second decimator, a first and second phase detector, a proportional charge pump, an integral charge pump, and a voltage-controlled oscillator. The first decimator receives a reference signal to generating a decimated version of a reference signal by a decimation factor N. The second decimator receives a clock signal to generate a decimated version of a clock signal by a decimation factor of N. The first phase detector obtains first phase error information according to a phase difference between the decimated version of the reference signal and the decimated version of the clock signal input to the first phase detector. The second phase detector obtains second phase error information according to a phase difference between the reference signal and the clock signal input to the second phase detector. The proportional charge pump generates a first voltage according to the second phase error information. The integral charge pump generates a second voltage according to the first phase error information. The voltage-controlled oscillator (VCO) generating the clock signal according to a combination of the first and second voltages.
The invention will become more fully understood from the detailed description, given herein below, and the accompanying drawings. The drawings and description are provided for purposes of illustration only, and, thus, are not intended to be limiting of the present invention.
In some embodiments of the invention, C1 may be formed in an integrated circuit, thus, the inner loop is achieves the desired stability for all operating frequencies of the PLL. If capacitor C1 is an external component of an integrated circuit, capacitor Cl might be set as large as is required for a given implementation in order to satisfy the stability requirement, but if capacitor C1 is formed in an integrated circuit, limits might be imposed on the value of C1.
Employing decimator 204 allows for capacitance multiplication. Capacitance multiplication is a characteristic of a circuit that makes a capacitance value appear to be larger than the actual capacitance of a circuit component. By decimating N times of charge from integral charge pump 204, the value of capacitance C1 is equivalent to N times. For example, if the capacitor C1 in
In some embodiments of the invention, the phase error information comprises an up signal and a down signal, both having a series of pulses, representing the clock signal leading and falling behind the reference signal respectively.
In another embodiment of the invention, the phase error information is a number representing the amount of the phase error. The decimator is a divider dividing the number by the factor N to generate the decimated version of the phase error information.
In some embodiments, the second phase error information comprises an up signal and a down signal, having a series of pulses, representing the clock signal leading and falling behind the reference signal respectively, as depicted in
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
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