Modular bcd and binary arithmetic and logical system专利检索-逻辑单元号资料储存系统专利检索查询-专利查询网

Modular bcd and binary arithmetic and logical system

阅读：361发布：2023-05-10

专利汇可以提供Modular bcd and binary arithmetic and logical system专利检索，专利查询，专利分析的服务。并且An arithmetic and logical unit for receiving four bit portions (quartets) of two input operands, a carry-in and several function control signals generates selectively several functions of the operands, including decimal and binary addition and subtraction functions or a desired logical function and provides carry lookahead and carry signals. A set of conversion gates selectively provides either a true or an excess-6 form of the first operand quartet while a complementation set of gates selectively provides a true or 1''s complement form of the second operand quartet. Bit pairs, from the corresponding positions in the resulting quartets, are combined to produce elementary logical functions, including the AND, inclusive OR and exclusive OR functions. In parallel, these elementary functions, an input carry bit, a set of carry look-ahead gates, a set of adder gates and a pair of control signals respectively provide carry signals and the selected function of the operands. A set of decimal correction gates, responsive to the carry signals, are used to correct the adder gate output for decimal addition and subtraction, when necessary.，下面是Modular bcd and binary arithmetic and logical system专利的具体信息内容。

权利要求

1. A function generator module comprising: A. a set of conversion gates, responsive to a first input quartet operand, for selectively adding the value six to said first operand; B. a set of elementary logical gates, responsive to the outputs of said set of conversion gates and a second input quartet of bits, for generating sets of functions, for respective bit pairs, each set of functions providing a complete logic set; C. logical gate means, responsive to the outputs of said set of elementary logical gates and a carry-in signal, for selectively generating the binary sum bits of the input operands and the carry-in or a selected logical function; D. a set of decimal correction gates, connected to said logical gate means for selectively adding ten modulo sixteen to said sum bits; E. a set of carry look-ahead gates, connected to said set of elementary logical gates, for generating a carry-out for said module; F. logic control means, responsive to input function selection signals, for selecting the desired logical gate means output, and for enabling said set of decimal correction gates for decimal arithmetic.

2. The function generator of claim 1 further comprising: G. logic in said set of carry look-ahead gates for generating carry propagate and generate signals for the function generator.

3. The function generator of claim 2 further comprising: H. a set of complement gates, responsive to said second input quartet of bits and said logic control means for selectively complementing said second input.

4. A function generator for performing signed binary and decimal arithmetic operations, together with basic logical operations on a pair of bit quartet operands comprising: A. conversion operand gating means, responsive to a first input bit quartet operand, for selectively generating four bit signals representing either the excess-6 coded representation or the true representation of a first input operand; B. first input control means responsive to input control signals representing binary/decimal and add/subtract functions and connected to said first operand gating means for selecting the excess-6 coded representation if and only if a decimal add operation is specified by the input control signals; C. complement operand gating means, responsive to a second input bit quartet operand, for selectively generating four bit signals representing either the second operand or its 1''s complement in accordance with input control signals specifying an add or subTract operation; D. logical gating means responsive to the outputs of said conversion and complement operand gating means for generating four sets of signals, each set being derived from a pair of input signals, one each from said respective operand gating means, said set including the inclusive OR and AND functions of each of said pair of input signals; E. carry gating means responsive to the outputs of said logical gating means for generating a carry-out signal; F. adder means responsive to the outputs of said logical gating means and a carry-in to the function generator for selectively generating the binary sum of or a logical function of the outputs of said first and second operand gating means, in accordance with the input control signals; G. decimal correction means connected to said adder means for correcting the adder output in response to said carry-out signal representing no carry.

5. The function generator of claim 4 further comprising: H. first level logic in said logical gating means for generating the AND and OR functions of respective bit pairs of said input operands; I. logic in said carry gating means, responsive to the outputs of said first level logic, for generating carry propagate and generate signals for the function generator.

说明书全文

相关专利内容

标题	发布/更新时间	阅读量
反激变换拓扑架构的LED恒流控制电路及谐波失真优化方法	2020-05-08	62
一种适用于高速模数转换器的预处理时序控制电路	2020-05-12	754
配置用于输入/输出操作的对象存储系统	2020-05-08	2
一种可变编程次数的多次可编程存储器	2020-05-08	752
一种基于SoC的多传感器融合飞行控制器	2020-05-11	301
基于异构多核的卫星气象数据喷泉解码算法硬件化系统	2020-05-08	715
控制电路及用于向加热元件递送电力的方法	2020-05-11	541
一种继电保护装置逻辑仿真及校验系统	2020-05-08	850
基于FPGA-CPU异构环境的大规模数据查询加速装置及方法	2020-05-11	748
一种双电机双滚筒输送机变频驱动系统	2020-05-08	380

高效检索全球专利

专利汇是专利免费检索,专利查询,专利分析-国家发明专利查询检索分析平台，是提供专利分析，专利查询，专利检索等数据服务功能的知识产权数据服务商。

我们的产品包含105个国家的1.26亿组数据，免费查、免费专利分析。

申请试用

分析报告

专利汇分析报告产品可以对行业情报数据进行梳理分析，涉及维度包括行业专利基本状况分析、地域分析、技术分析、发明人分析、申请人分析、专利权人分析、失效分析、核心专利分析、法律分析、研发重点分析、企业专利处境分析、技术处境分析、专利寿命分析、企业定位分析、引证分析等超过60个分析角度，系统通过AI智能系统对图表进行解读，只需1分钟，一键生成行业专利分析报告。

申请试用

逻辑单元号热门专利

热门分类

Modular bcd and binary arithmetic and logical system

该功能需要专业版企业版VIP权限，您可以：