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Bin address memory system

阅读：850发布：2023-08-21

专利汇可以提供Bin address memory system专利检索，专利查询，专利分析的服务。并且A computer-controlled warehousing stacker bin address memory system using clock signals, and comprising a keyboard or the like for introducing binary bin address data into the system and for issuing command signals and enable signals to a control circuit comprising a priority encoder and a preset read only memory. One set of shift registers, with digital display, is enabled to receive input address data. Thereafter, command and enable functions cause data from the display registers to be issued through a set of execute shift registers to a data transmitter which controls operation of the stacker crane and, where preservation of an address is needed, as when the tote pan is being delivered to the picking station, to place said data in a predetermined one of a plurality of sets of storage shift registers, from which the data is likewise, thereafter, transmitted to the E registers to cause the stacker crane to return the tote pan to storage upon command.，下面是Bin address memory system专利的具体信息内容。

权利要求

1. A method of controlling an automated warehousing system comprising a stacker crane, storage bins and tote pans, the steps of: issuing binary bin address signals identifying the storage bin location of a tote pan desired to be retrieved on either side of a stacker crane traversing aisle; communicating said binary address signals to gating means; issuing enable signals to the gating means; gating said bin address signals to a first memory; issuing tote pan retrieve command signals from control means to said first memory causing the bin address data to be fed back and gated through said gating means to both a storage memory and through an additional third memory to a data transmitter which controls the stacker crane to retrieve the desired tote pan and locate the same at a picking station.

2. A method of controlling an automated warehouse system comprising a stacker crane, storage bins, tote pans and a plurality of memory means, comprising the steps of: providing command signals and sets of binary address data; priority encoding said command signals; gating said sets of binary bin address data sequentially to an initial memory location; selectively processing said priority encoded signals to initiate ultimate successive retrieval of up to three tote pans from storage bins respectively corresponding in location to said successive sets of binary bin address data; serially gating said successive sets of binary bin address data from said initial memory location to both (a) another memory location and (b) an output location by which retriEval movement of the stacker crane is controlled; communicating processed priority encoded command signals to said output location commanding retrieval of said tote pans at said bin address locations respectively to a picking location; returning retrieved tote pans from said picking location to their respective bin address locations by separately gating said sets of binary bin address data from said other memory location to said output location and from thence to the stacker crane by which restorative movement of said stacker crane to return said tote pans to said storage bins is controlled.

3. The method of claim 2 comprising deriving enabling signals from said priority encoded signals to control said gating steps.

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