Apparatus for receiving encoded facsimile signals with minimized effect of pulse jitter introduced during transmission
阅读：814发布：2021-01-22
专利汇可以提供Apparatus for receiving encoded facsimile signals with minimized effect of pulse jitter introduced during transmission专利检索，专利查询，专利分析的服务。并且Black and white runs of scanned image signals are encoded into binary information at a transmitting station, transmitted over a transmission link and received by apparatus at a receiving station. Jitter introduced during the transmission is detected by the apparatus prior to the decoding of the received signal to produce an error indicating pulse which is utilized to effect erasure of the image signals of the line scan in which the jitter has occurred to leave the line as a white run. As an alternative, the erased line is filled with the signals on the next line scan to thereby visually improve the quality of reproduced image.，下面是Apparatus for receiving encoded facsimile signals with minimized effect of pulse jitter introduced during transmission专利的具体信息内容。
1. Apparatus for a facsimile communication system receiving station receptive in operation of digital image signals comprising a sequence of synchronization signals and line scan signals synchronized with said synchronization signals, each line scan signal comprising pulses jointly representative of the brightness of an image along one dimension thereof at a given point along another dimension of said image, wherein said apparatus comprises: means receptive of said digital image signals for detecting pulse jitter of said pulses comprising said line scan signals; means receptive of said digital image signals for detecting said synchronization signals; and means having an output, and receptive of said digital image signals and cooperative with said pulse jitter detecting and synchronization signal detecting means for gating said image signals to said output in the absence of pulse jitter and for inhibiting all the remaining pulses in a given line scan signal from appearing at said output upon detection of pulse jitter in said given line scan signal.
2. An apparatus according to claim 1 further comprising, a code recognition circuit receptive of said digital image signals for changing the format of said pulses comprising said line scan signals to a format suitable for decoding and means for applying said pulses in the changed format to said means for gating said image signals.
3. An apparatus according to claim 1 further comprising, means receptive of the gating means output pulses for decoding the gating means output pulses to develop signals having amplitude variations corresponding to the brightness variations of the image represented by said line scan signals.
4. An apparatus according to claim 3 further comprising, display means receptive of said decoder means output signals and synchronization signal detection means output signals for displaying visual signals each having brightness variations along a first direction corresponding to the amplitude variations of one of said decoder output signals.
5. An apparatus according to claim 1 further comprising, delay means receptive of said digital image signals for delaying said digital image signals for a period of time equal to the duration of one line scan signal, and means for applying said delayed image signals to said gating means whereby the entire line scan signal including a pulse having pulse jitter is inhibited from appearing at said output.
6. An apparatus according to claim 5 further comprising, second gating means having an output and receptive of the output signals of said first gating meaNs and cooprative with said pulse jitter detector and said synchronization signal detector for applying said output signals to said second gating means output, said second gating means having means for storing successive line scan signals and for applying the previously stored line scan signal to said second gating means input when one of said line scan signals is inhibited by said first gating means.
7. An apparatus according to claim 3 wherein said second gating means comprises, and Or gate receptive of the output of said first gating means, a read-out gate having an output connected to an input of said Or gate, a delay circuit for applying the output of said Or gate to an input of said read-out gate after a delay equal to the duration of one line scan signal, and means cooperative with said pulse jitter detector and said synchronization signal detector for enabling said read-out gate to apply the output of said delay circuit to an input of said Or gate when said first gating means is inhibited.
8. An apparatus according to claim 7 wherein said means for enabling said read-out gate comprises, a flip-flop having a first input connected to the output of said pulse jitter detector and a second input connected to the output of said synchronization signal detector, a monostable multivibrator receptive of the output of said flip-flop, and means for applying the output of said monostable multivibrator to enable said read-out gate.
9. An apparatus according to claim 8 wherein said means for applying the output of said monostable multivibrator comprises a second flip-flop and a second monostable multivibrator in cascade.
10. Apparatus as claimed in claim 1 further comprising, means for generating timing pulses in synchronism with the pulses comprising said line scan signals, and wherein said pulse jitter detecting means includes a plurality of comparing means receptive of said timing pulses and said pulses comprising said line scan signals for producing an error signal when the pulses comprising said line scan signals are outside of predetermined ranges of amplitude level.
11. Apparatus as claimed in claim 10, wherein said jitter detecting means includes a first comparator having a first predetermined reference level for producing a first error signal when said pulses comprising said line scan signals exceed said first reference level, a second comparator having a second reference level for producing a second error signal when said pulses comprising said line scan signals are below said second reference level, a third comparator having a third reference level for producing a third error signal when said pulses comprising said line scan signals exceed said third reference level, a fourth comparator having a fourth reference level for producing a fourth error signal when said pulse comprising said line scan signals are below said fourth reference level, a first And gate coupled to said second and third comparators to receive said second and third error signals respectively, an Or gate coupled to said first and fourth comparators and said first And gate to receive said first and fourth errors signals, respectively, and the output of said first And gate, and a second And gate coupled to said Or gate to receive the output thereof and receptive of said timing pulses.
12. Apparatus as claimed in claim 1, wherein said pulse jitter detecting means includes means for differentiating said pulses comprising said line scan signals, a full-wave rectifier coupled to said differentiating means, means receptive of said pulses comprising said line scan signals for generating regularly occurring pulses having a predetermined pulse width, and an And gate coupled to said full-wave rectifier and said pulse generating means for receiving the outputs thereof.
13. Apparatus as claimed in claim 1 further comprising, means for generating timing pulses in synchronism with the pulses comprising said line scan signals, and wherein said pulse jitter detecting means inclUdes a plurality of comparing means receptive of said timing pulses producing an error signal when said pulses comprising said line scan signals exceed predetermined levels of amplitude, means for differentiating said digital image signals, a full-wave rectifier coupled to said differentiating means, means receptive of said timing pulses for generating second regularly occurring pulses having a predetermined pulse width, and an And gate coupled to said full-wave rectifier and to said pulse generating means for receiving the outputs thereof.
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