Monolithic semiconductor memory
阅读：845发布：2023-09-11
专利汇可以提供Monolithic semiconductor memory专利检索，专利查询，专利分析的服务。并且This specification discloses a storage cell which employs inversely operated and transverse transistors to reduce storage cell size accessing times and power consumption when the cell is fabricated in monolithic form. Two cross-connected transistors are inversely operated so that they share a common emitter region with a separate base region and collector region for each of the cross-connected transistors. In this way, the transistors can be fabricated in a single diffusion region. The collector of each of the cross-connected transistors is connected to the collector of a load transistor of the opposite type transistor and to the base of an addressing transistor having its emitter connected to the sense line and its collector connected to the base of the load transistors. The two addressing and load transistors are formed in a single isolation zone with collector and base regions of the addressing transistors serving also as the base and collector regions respectively of the load transistors which are fabricated as transverse transistors with a common emitter region.，下面是Monolithic semiconductor memory专利的具体信息内容。
1. In a memory cell having a pair of cross-coupled bipolar transistors each connected by a load impedance to a source of potential, the improvement comprising a separate load impedance transistor of the opposite conductivity kind from the crosscoupled transistors connecting the collector of each of the cross-coupled transistors to the source of potential with the collectors of the load impedance transistors connected to the collectors of the cross-connected transistors and the emitters of the load impedance transistors connected to the source of potential, and a separate addressing transistor with its base connected to the collector of each of the cross-connected transistors, its emitter connected to a bit line servicing the memory cell and its collector connected to the bases of the load transistors.
2. The memory cell of claim 1 wherein said load impedance transistors are lateral transistors.
3. The memory cell of claim 1 wherein said cross-connected transistors are formed in a common emitter zone.
4. The memory cell of claim 1 wherein the bases of the load transistors and the collectors of the addressing transistors are connected together and to the emitters of the cross-connected transistors.
5. The memory cell of claim 1 wherein said load impedance transistors are lateral transistors and said addressing transistors are vertical transistors.
6. The memory cell of claim 5 wherein said load impedance transistors and said addressing transistors are formed in a single isolation zone of one conductivity type which serves as the collector of the addressing transistors and the bases of thE load impedance transistors; two zones of opposite conductivity type are positioned in that isolation zone and serve as bases of the addressing transistors and the collectors of the load impedance transistors; a zone of the first conductivity type is located in each of the zones of the opposite conductivity type and serve as the emitters for the addressing transistors; and a third zone of the opposite conductivity type which serves as the common emitters of the two load impedance transistors.
7. The memory cell of claim 6 wherein said cross-connected transistors are formed in a common emitter zone of one conductivity type.
8. The memory cell of claim 6 wherein said common emitter zone has therein two base zones of opposite conductivity type each of which in turn contain a collector zone of the said one conductivity type.
9. A monolithic memory comprising: a first plurality of parallel isolation zones each containing a plurality of cross-connected transistors with each said parallel diffusion serving as the emitter zone of all the transistors in the diffusion; a second plurality of parallel isolation zones with individual ones of said second plurality positioned between each two of said first plurality and containing load devices for each of the cross-connected transistors; and metallization means connecting the load transistors to the collectors of the cross-connected transistors.
10. The monolithic memory of claim 9 wherein each isolation zone in the second plurality contains the load transistors for the cross-connected transistors contained in the isolation zones of the first plurality on both sides of it.
11. The monolithic memory of claim 10 wherein said second plurality of parallel isolation zones contains addressing transistors for coupling the collectors of the cross-connected transistors to bit lines for accessing the memories.
12. The monolithic memory of claim 11 wherein: said second isolation zone is of one conductivity type and serves as the collectors of all the addressing transistors and the bases of all the load transistors therein.
13. The monolithic memory of claim 12 wherein: two zones of the opposite conductivity type are positioned on each of the second isolation zones for all the load transistors and addressing transistors serving each pair of cross-connected transistors and serves as the bases of the addressing transistor and the collectors of the load transistors; a zone of the first conductivity type is located in each of the two zones of the opposite conductivity type and serve as the emitters for the addressing transistors; and a third zone of the opposite conductivity type serving as the common emitters of the load transistors.
14. In a memory cell having a pair of cross-connected transistors each having their collectors connected to a source of potential by a load and having their emitters connected together, the improvement comprising a separate load transistor connecting the collector of each of the cross-connected transistors to the source of potential with the base of load devices being connected to the emitters of the cross-connected devices.
15. The memory cell of claim 14 wherein the collectors of the load devices are connected to the collectors of the cross-connected devices and the emitters of the load transistors are connected to the source of potential.
16. The memory cell of claim 15 including a separate addressing transistor with a base connected to the collector of each of the cross-connected transistors, an emitter connected to a bit line servicing the memory cell and a collector connected to the bases of the load transistors.
17. The memory cell of claim 16 wherein said load transistors are lateral transistors and said addressing transistors are vertical transistors.
18. A monolithic memory cell comprising: a zone of one conductivity kind serving as the emitters of two transistors with their bases and collectors cross-connected, as thE collectors of two address transistors for coupling the monolithic memory cell to bit lines for addressing the memory cell and as the bases of two transistors acting as loads to the cross-connected transistors, and two zones of opposite conductivity kind within the first mentioned zone each serving as the base of one of the transistors whose bases and collectors are cross-connected, as the base of one of the address transistors and as the base of one of the transistors serving as a load to one of the cross-connected transistors.
19. The memory cell of claim 18 including: cross-connected a third zone of opposite conductivity kind in the first-mentioned zone, said third zone of opposite conductivity kind serving as the emitters of the two transistors serving as load devices for the cross-connected transistors.
20. The memory cell of claim 19 including: two zones of the first conductivity kind in each of said two zones of the opposite conductivity kind one of said zones of the first conductivity kind in each of said two zones of opposite conductivity kind being the collector of one of the transistors with their collectors and emitters cross-connected and the other zone of the first conductivity kind in each of said two zones of opposite conductivity kind being the emitter one of the addressing transistors.
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