Data entry terminal having data correction means
阅读：279发布：2022-03-15
专利汇可以提供Data entry terminal having data correction means专利检索，专利查询，专利分析的服务。并且A data entry terminal is disclosed for use in a data communication system. The terminal includes a content addressable memory for storing a variable character length data field and an associated field separator. A message comprised of at least one data field and a separator is outputted from the memory in a character series sequence in the order in which the characters were entered into the memory. The length of the message may be shortened by deleting the data characters in the last entered data field.，下面是Data entry terminal having data correction means专利的具体信息内容。
1. A data entry terminal comprising: content addressable memory means for storing a variable length message comprised of data characters entered therein and including at least one variable character length data field and a field separator; data entry means for entering a said message into said memory means so that said message includes at least one said variable character length data field and a said field separator; means for outputting a said message from said memory means in such a manner that the data characters are outputted in a series sequence in the order in which they were entered into said memory means and such that a said field separator precedes the first entered character in an associated variable character length data field; means for re-entering a said outputted message into said memory means and including controllable gating means for passing data characters to be re-entered into said memory means in a said series sequence; message modifying means for deleting from a said outputted message the data characters in the last entered data field in repsonse to a clear command signal and including gate control means for controlling said controllable gating means to prevent re-entry of the last entered character in the last entered data field each time a said outputted message is re-entered into said memory means and independently of the character length of said data field until all of said data characters in said data field have been deleted from said message.
2. A data entry terminal as set forth in claim 1 wherein said terminal includes circuit means defining a series transmission path with said outputting means and said re-entering means, said transmission path normally having a first character length for storing at any one point in time a fixed number of said outputted data characters, said message modifying means including means for selectively shortening the length of said transmission path by at least one character length.
3. A data entry terminal as set forth in claim 2, wherein said data transmission path includes a plurality of character storage registers connected in series for sequentially storing said outputted data characters, a plurality of said controllable gating means each being interposed between two successive character storage registers, said gate control means including means for controlling selected ones of said controllable gating means to prevent a data character in a first of said registers from being transferred to a second of said registers through a said controllable gating means.
4. A data entry terminal as set forth in claim 3, including register bypassing means for connecting the output of one of said registers with the input of another of said registers while bypassing an intermediate one of said registers so that data stored in said one register is transferred to said second register while bypassing said intermediate register.
5. A terminal as set forth in claim 4, whereIn said bypassing circuit means includes a normally disabled data entry gating means and wherein said gate control means includes means for selectively enabling a said normally disabled gating means for passing the said data character in said one register to said another register.
6. A data entry terminal as set forth in claim 2, wherein said data transmission path includes a plurality of shift registers for sequentially storing a like plurality of said outputted data characters in said series sequence with said registers being interposed between said outputting means and said re-entering means, at least one controllable intermediate gating means interposed between successive ones of said plurality of shift registers for normally passing a data character from the immediately preceding shift register into the immediately succeeding shift register; register bypassing circuit means for bypassing at least one of said shift registers and including gating means for connecting the output of a preceding shift register means with the input of a succeeding shift register means while bypassing at least one intermediate shift register means; said gate control means including circuit means for controlling said plurality of intermediate gating means and said bypass circuit gating means for effectively varying the length of said data transmission path.
7. A data entry terminal as set forth in claim 6, including a second register bypass path, said gate control means including means for selectively controlling said gating means in each of said register bypassing circuits.
8. A data entry terminal as set forth in claim 7, including circuit means for connecting the second register bypassing circuit means with the output of a said shift register bypassed by said first register bypassing circuit means.
9. A data entry terminal as set forth in claim 2, wherein said transmission path interconnects said outputting means and said re-entering means to define a recirculating path between the input of said memory means and the output thereof to thereby define a recirculating memory means, said recirculating memory means being comprised of static shift registers for sequentially shifting said characters in said series sequence from register to register in synchronism with shift pulses applied to said registers.
10. A data entry terminal as set forth in claim 9, wherein said recirculating memory means is comprised of a plurality of bit serial shift register means for shifting said data characters in said series sequence, each said data character being comprised of a plurality of bits with the bits of each charcter being shifted in series sequence with the most significant bit being shifted first.
11. A data entry terminal comprising; content addressable memory means for storing a variable length message comprised of data characters entered therein and including at least one variable character length data field and a field separator; data entry means for entering a said message into said memory means so that said message includes at least one said variable character length data field and a said field separator; means for outputting a said message from said memory means in such a manner that the data characters are outputted in a series sequence in the order in which they were entered into said memory means and such that a said field separator precedes the first entered character in an associated variable character length data field; means for re-entering a said outputted message into said memory means and including controllable gating means for passing data characters to be re-entered into said memory means in a said series sequence; message modifying means for deleting from a said outputted message the data characters in the last entered data field in response to a clear command signal and including gate control means for selectively controlling said re-entry gating means to prevent re-entry of the last entered character in the last entered data field Each time a said outputted message is re-entered into said memory means and independently of the character length of said data field until all of said data characters in said data field have been deleted from said message; said terminal includes circuit means defining a series transmission path with said outputting means and said re-entering means, said transmission path normally having a first character length for storing at any one point in time a fixed number of said outputted data characters, said message modifying means including means for selectively shortening the length of said transmission path by at least one character length, said transmission path interconnects said outputting means and said re-entering means to define a recirculating path between the input of said memory means and the output thereof to thereby define a recirculating memory means, said recirculating memory means being comprised of static shift registers for sequentially shifting said characters in said series sequence from register to register in synchronism with shift pulses applied to said registers, decoding means for decoding specific data characters shifted through a specific one of said registers, said specific data characters being respectively representative of an end of message indicator and a said clear command, each said indicator and each said command being defined by at least one coded multibit data character, said decoding means providing an output clear command signal in response to decoding a said clear command and a said end of message signal in response to decoding a said end of message indicator, said message modifying means including circuit means responsive to a said clear command signal for instituting operation to clear the data characters from the last entered data field and its associated field definer, and circuit means responsive to a said end of message signal indicative that said clearing operation has been completed.
12. A data entry terminal as set forth in claim 11, wherein said circuit means responsive to a said end of message signal includes circuit means deleting said clear command from said message.
13. A data entry terminal as set forth in claim 11, wherein said terminal includes circuit means for automatically entering a said end of message indicator into said memory means after each data character is entered into said memory means and circuit means for entering data characters into said memory means so as to effectively be written over the end of message indicator entered after the preceding data characters.
14. A data entry terminal comprising: content addressable memory means for storing a variable length message comprised of data characters entered therein and including at least one variable character length data field and a field separator; data entry means for entering a said message into said memory means so that said message includes at least one said variable character length data field and a said field separator; means for outputting a said message from said memory means in such a manner that the data characters are ouputted in a series sequence in the order in which they were entered into said memory means and such that a said field separator precedes the first entered character in an associated variable character length data field; means for re-entering a said outputted message into said memory means and including controllable means for passing data characters to be re-entered into said memory means in a said series sequence; message modifying means for deleting from a said outputted message the data characters in the last entered data field in response to a clear command signal and including control means for selectively controlling said reentry means to prevent re-entry of the last entered character in the last entered data field each time a said outputted message is re-entered into said memory means and independently of the character length of said data field until all of said data characters in said data fiEld have been deleted from said message, said data entry means including means for entering a clear command into said memory means wherein said clear command includes at least one multibit character, and decoding means for decoding said outputted data for the presence of a said clear command and providing a said clear command signal in accordance therewith.
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