Multi-processor system with multiple cache memories
阅读：449发布：2022-03-17
专利汇可以提供Multi-processor system with multiple cache memories专利检索，专利查询，专利分析的服务。并且A digital data multi-processing system having a main memory operating at a first rate, a plurality of individual processors, each having its own associated cache memory operating at a second rate substantially faster than the first rate for increasing the throughput of the system. In order to control the access of the main memory by one of the plural processors to obtain information which may not be present in its associated cache memory, a Content Addressable Cache Management Table (CACMT) is provided.，下面是Multi-processor system with multiple cache memories专利的具体信息内容。
1. In a multi-processor type digital computing system, the combination comprising: a. a plurality of individual requestor units, each including addressing means for fetching instructions to be executed and executing means for processing data in a sequence of operations in accordance with said instructions; b. a corresponding plurality of relatively low capacity, high cycle time cache memory units, each unit individually connected to a different one of said requestor units for storing at addressable locations therein a limited number of blocks of information words including operands and instructions to be processed, each said cache memory unit including means responsive to said addressing means for determining whether information sought by its respective requestor unit is available therein; c. a relatively large capacity low cycle time main memory unit for storing at addressable locations therein a complete complement of blocks of information words usable in the system; d. a content addressable cache management table connected intermediate said main memory and said plurality of cache memory units for storing a staTus control word for each block of information words currently stored in said plurality of said cache memory units, said status control words being referenced by a given requestor unit in order to access said main memory when information sought is not available in its associated cache memory unit; e. means for updating the status control word corresponding to a given block in one of said cache memory units at least the first time in said sequence of operations that a change is made in the information words stored in said given block in said one cache memory unit.
2. Apparatus as in claim 1 wherein each of said cache memory units comprises: a. a first plurality of storage registers, each adapted to store signals representing an individual block address, and each having a respective output line; b. a search register adapted to contain an address tag; c. means for simultaneously comparing the address tag stored in said search register with the contents of said plurality of storage registers and for producing an output signal on the respective output line associated with a storage register storing a block address matching said address tag; d. a second plurality of storage registers for containing a plurality of blocks of information words at addressable locations therein; and e. means responsive to said output signal and to the contents of said search register for uniquely selecting a given information word from said plurality of blocks of information words.
3. In a multi-processor digital computing system, the combination comprising: a. a plurality of individual processor units, each including addressing means for fetching instructions to be executed and arithmetic means for processing data in a sequence of operations in accordance with said instructions; b. a corresponding plurality of relatively small capacity, short cycle time cache memory units, each unit individually connected to a different one of said processor units for storing at addressable locations therein a limited number of blocks of information words including operands and instruction to be processed, each said cache memory unit including means responsive to said addressing means for determining whether information sought by its respective processor is available therein; c. a relatively large capacity, long cycle time main memory for storing complete sets of programs of instructions and operands at addressable locations therein; d. management table means connected intermediate said main memory and said plurality of cache memory units for storing a status control word for each block of information words currently stored in said plurality of cache memory units, said status control words being referenced by a given processor in order to access said main memory when information sought is not available in its associated cache memory unit; and e. means for updating the status control word corresponding to a given block in one of said cache memory units at least the first time in said sequence of operations that a change is made in the information words stored in said given block in said one cache memory unit.
4. Apparatus as in claim 3 wherein said management table means comprises: a. a content addressable memory adapted to store a plurality of status control words, each status control word including an address field and a plurality of identifier bits; b. means operative upon the determination that information being sought by a given processor is unavailable in the cache memory unit connected to that processor for searching said content addressable memory for a status control word having a given address field; and c. means responsive to the results of a search by said searching means for determining from said identifier bits whether said information being sought is contained in the cache memory unit associated with a processor other than the given processor.
5. Apparatus as in claim 3 and further including: a. a priority evaluation circuit Having a plurality of input ports adapted to receive request control signals from one or more of said cache memory units; b. switching means connected intermediate said main memory and said plurality of cache memory units; and c. means connecting said priority evaluation circuit to said switching means for establishing a communications path between said main memory and only one of said plurality of cache memory units at any given instant.
6. A computing system as in claim 3 wherein said plurality of cache memory units each comprise: a. a content addressable memory array for storing a plurality of block addresses; b. a word addressable memory for storing a plurality of blocks of information words in an array of word registers; c. search register means connected to receive address representing signals from an associated processor; d. signaling means connected to said content addressable memory array for indicating whether a block of information words having a predetermined relationship to said address representing signals contained in said search register means is stored in said word addressable memory array; e. digital logic means connected to said content addressable memory array and said search register means for selecting one of said word registers in said array; and f. data register means connected to said word addressable memory array adapted to temporarily store information words read out from or to be entered into said selected one of said word registers.
7. Apparatus as in claim 6 and further including control means in said management table means responsive to the output from said signaling means and to the contents of said search register means for searching the contents of said management table means for a given status control word when said signaling means indicates that said block of information sought in said content addressable memory means is not present therein.
8. A method of operating a digital computing system of the type including a plurality of independent processor units, each including means for accessing instructions and operands and means for executing said instructions, a corresponding plurality of low cycle time, low capacity cache memories, with one of said memories connected in a communicating relationship with one of said processor units, a relatively high capacity, high cycle time main memory for storing instructions and operands, and a management table for storing status control words corresponding to groups of information words stored in said plurality of cache memories including the steps of: a. sending a request control signal and an address tag from at least one of said processors to its associated cache memory; b. searching said associated cache memory to determine whether an item of information having said address tag is resident in said associated cache memory; c. transmitting said request control signal and said address tag to said management table when the searching of said associated cache memory reveals that said item of information is not resident in said associated cache memory; d. searching said management table for a status control word corresponding to the group of information words including the word requested by said one of said processors; e. updating said status control word to indicate a change in the information content in said associated cache memory; f. forwarding said request signal and said address tag from said management table to said main memory; g. reading out from said main memory the group of information words specified by said address tag; and h. transmitting said group of information words from said main memory to said associated cache memory for storage therein.
9. The method as in claim 8 and further including the step of: a. examining the bits of said status control word; and b. signaling the processor sending said request control signal that the item of information being requested is unavailable to the requEsting processor when said status control word bits are of a predetermined combination.
10. The method as in claim 8 and further including the steps of: a. determining whether said associated cache memory has unallocated storage space available in which information from said main memory may be stored; b. selecting by a predetermined algorithm a group of information words to be discarded from said associated cache memory upon the determination that said associated cache memory contains no unallocated storage space; and c. changing the status control word in said management table assigned to said group of information words to reflect the discarding of said group by said associated cache memory.
11. A method of operating a digital computing system of the type including a plurality of individual processor units each including instruction acquisition and instruction execution means, an equal plurality of cache memory units for storing a predetermined number of blocks of information including instructions and operands, there being one such cache memory unit associated with each of said processor units, a main memory having a high capacity and high cycle time compared to that of said cache memory units, and a content addressable cache management table for storing one status control word for each block of information stored in all of said plurality of cache memory units, said status control words each including an address tag corresponding to block addresses in said cache memory units and said main memory and a plurality of control bits, the steps comprising: a. generating a request control signal and an address tag in one of said plurality of processors; b. searching the contents of the cache memory unit associated with said one processor for a block having said address tag; c. transferring a word of data from said one processor into said block having said address tag; d. searching said content addressable cache management table for a status control word associated with said block having said address tag; e. examining said plurality of control bits of the status control word resulting from the preceding step for determining whether said block is stored in the cache memory unit of other than said one of said plurality of processors; and f. notifying such other processors that the block of information specified by said address tag has been changed.
12. The method as in claim 11 and upon the determination that the block of information specified by said address tag is not resident in the cache memory unit associated with said one processor, further including the steps of: a. searching said content addressable cache management table for a status control word having the same address tag as that generated by said one processor; and b. examining said plurality of control bits for determining whether said block of information located in said main memory is available to said one processor.
13. The method as in claim 12 and further including the steps of: a. examining said plurality of control bits for determining whether said block of information specified by said address tag is resident in the cache memory units associated with other than said one processor; and b. based upon the outcome of the preceding step, notifying such other processors that said block of information is in the process of being modified.
14. The method as in claim 12 and further including the steps of: a. transmitting said request control signal and said address tag to said main memory; b. reading out the block of information specified by said address tag from said main memory; c. routing said block of information from said main memory to the cache memory unit associated with said one processor which generated said request control signal for storage therein at the address specified by said address tag; d. modifying said control bits of the status control word associated with said block of information to indicate the presence of Said block of information in the cache memory unit associated with said one processor; and thereafter e. transferring a data word from said one processor to a predetermined address within said block of information now contained in said cache memory unit associated with said one processor.
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