Memory system exerciser
阅读：53发布：2022-03-23
专利汇可以提供Memory system exerciser专利检索，专利查询，专利分析的服务。并且Memory systems are tested using an exerciser in which stored program instructions direct data generation, memory addressing, read/write operation and data or address comparison. For data generation, a test word register (the T-register) contains a word to be written into the memory under test at an address stored in an address register (the A-register). The T-register contents can be modified, interchanged with a background word register (the Bregister), shifted or used for pseudo-random sequence generation. Data read from the memory under test is placed in a memory register (the M-register) for comparison with the contents of the T-register. Certain stored program instructions are conditioned by the results of this data comparison. The A-register contents can be modified, stored in a pointer register (the X-register), or compared with the pointer address or with another address indicative of the memory size. Other program instructions are conditioned by the results of such address comparison. Typical memory test programs, including ''''galloping'''' and ''''walking'''' data routines and random sequence routines, illustrate operation of the memory system exerciser. The exerciser can be used independently or as a component in a larger test system.，下面是Memory system exerciser专利的具体信息内容。
1. A system for exercising a memory under test, comprising: address generation means for addressing data storage locations in said memory under test, data generation means for providing data to be entered into said memory under test and for receiving data read from said memory under test, control means operatively connected to said address and data generation means for commanding, under program control, entry of data into addressed locations of said memory under test, said control means comprising; a stored program memory containing a set of instructions, and program control logic for providing commands which direct said address and data generation means independently and selectively to modify said data to be entered and/or said addressed storage locations in accordance with instructions accessed from said stored program memory.
2. A system according to claim 1 wherein said data generation means includes a T-register for storing a test word for entry into said memory under test.
3. A system according to claim 2 wherein said data generation means further comprises logic circuitry, operatively connected to said T-register and under program control, for modifying the contents of said T-register.
4. A system according to claim 2 wherein said data generation means includes a B-register for storing another data word, and wherein said control means may command transfer or comparison of data between said B-register and said T-register under stored program control.
5. A system according to claim 2 wherein said data generation means further comprises means, under program control, for feedback shifting said T-register to generate a pseudo-random data sequence.
6. A system according to claim 1 wherein said control means also commands readout of data from addressed locatIons of said memory under test.
7. A system according to claim 6 wherein said data generation means further comprises a data comparator for comparing data read out from said memory under test with data provided thereto and for supplying to said control means a data comparison signal indicative of the results of said comparison.
8. A system according to claim 7 wherein said stored program includes one or more instructions conditioned by the status of said data comparison signal.
9. A system according to claim 7 wherein said data generation means further comprises a T-register containing data to be entered into said memory under test and an M-register receiving data from said memory under test, said comparator comparing the contents of said T-register and said M-register.
10. A system according to claim 9 wherein said data generation means further comprises an I-register operatively connected to said comparator, to inhibit comparison of those portions of said T-register and M-register contents specified by the contents of said I-register.
11. A system according to claim 1 wherein said address generation means comprises an A-register storing the address of the memory storage location to which data is to be entered or from which data is to be read out.
12. A system for exercising a memory under test, comprising: address generation means for addressing data storage locations in said memory under test, and comprising an A-register storing the address of the memory storage location to which data is to be entered or from which data is to be read out, and logic circuitry, operatively connected to said A-register and under program control, for modifying the contents of said A-register, data generation means for providing data to be entered into said memory under test and for receiving data read from said memory under test, and control means operatively connected to said address and data generation means for commanding, under program control, entry of data into addressed locations of said memory under test.
13. A system according to claim 12 wherein said address generation means further comprises an address comparator for comparing the address in said A-register with another address and for supplying to said control means an address comparison signal indicative of the results of said comparison.
14. A system according to claim 13 wherein said address generation means further comprises an N-register for storing the address of the highest data storage location in said memory under test, and wherein said other address corresponds to the contents of said N-register.
15. A system according to claim 13 wherein said address generation means further comprises an X-register for storing a pointer address, and wherein said other address corresponds to said pointer address.
16. A system according to claim 13 wherein said stored program includes one or more instructions conditioned by the status of said address comparison signal.
17. A system for exercising a memory under test in response to programmed commands supplied by a processor, comprising: first register means for storing data to be entered into said memory, first logic means for modifying the contents of said first register means in response to certain of said commands, second register means for storing the address of a memory storage location, second logic means for modifying the contents of said second register means in response to other of said commands, and means for entering said data stored in said first register means into the memory storage location identified by the address in said second register means in response to a write command supplied by said processor.
18. A system according to claim 17 further comprising: third register means for receiving data read from said memory, and means for reading data from the memory storage location identified by the address in said second register means into said third rEgister means in response to a read command.
19. A system according to claim 18 further comprising: data comparator means for comparing the data received by said third register means with the data originally entered into the memory storage location from which said received data was read, said data comparator means providing a data comparison signal to said processor indicative of the results of said comparison.
20. A system according to claim 19 further comprising: additional register means for storing the address of the lowest memory storage location, the highest memory storage location or another specified memory storage location, and address comparator means for comparing the address stored by said second register means with an address stored by said additional register means, said address comparator means providing an address comparison signal to said processor indicative of the results of said comparison.
21. A system accroding to claim 20 wherein certain of said programmed commands are conditioned by said data comparison signal or said address comparison signal.
22. A processor for providing programmed commands to the system of claim 17, comprising: a stored program memory containing a set of instructions specifying a program for exercising said memory under test, program register means for directing access from said program control memory of the instructions in said set, and program control logic means for interpreting said accessed instructions and for providing to said system the commands specified by said instructions.
23. A processor according to claim 22 wherein each instruction contains a first field controlling data generation by said first register means and said first logic means and a second field controlling address generation by said second register means and said second logic means.
24. In a computer directed system for testing a memory device: a first means for loading a background word into all locations of said memory under test, a second means for entering a test word at a single location in said memory, and a third means for reading out each memory location storing said background word in alternation with readout of said single location storing said test word, and for indicating an error when incorrect data is read from any location.
25. A system according to claim 24 further comprising: fourth means for directing said second and third means to operate repeatedly a number of times equal to the number of storage locations in said memory under test, said second means entering said test word in a different single location during each repetition.
26. A system according to claim 25, wherein said first through fourth means operate twice, said background word being interchanged with said test word during said second operation.
27. A system according to claim 24 wherein said thrid means reads out from memory location storing said background word twice, one before and once after said alternate readout of said single location.
28. In a computer directed system for testing a memory device: a first means for entering a background word into all locations of said memory under test, a second means for entering a test word at a single location in said memory, a third means for reading back all other memory locations except said single location and for indicating an error if the data read back from any such location differs from said background word.
29. A system according to claim 28 further comprising fourth means for directing said second and third means to operate repeatedly a number of times equal to the number of storage locations in said memory under test, said second means entering said test word in a different single location during each repetition, said first means entering said background word in said previous single location to replace said test word.
30. A system according to claim 29 wherein during each repetition said third means consecutively reAds out the memory locations having addresses both lower than and higher than said single location.
31. A system according to claim 29 wherein said first through fourth means operate twice, said background word being interchanged with said test word during said second operation.
32. In a computer directed memory exercise system: a first means for generating a pseudo-random data sequence and for entering data in said sequence into locations of a memory under test, and a second means, operative upon completion of data entry, for regenerating said same pseudo-random data sequence while reading out said entered data from said memory, and for indicating an error should said read out data differ from said regenerated sequence.
33. A system according to claim 32 further comprising third means for directing said first and second means to operate respectively a number of times equal to the number of storage locations in said memory under test, a different pseudo-random data sequence being generated during each repetition.
34. A memory exerciser comprising: program control means for storing and interpreting a set of instruction words each designating one or more selected memory exercise operations selected from the group consisting of data generation, address generation, memory read/write control, data comparison and address comparison, and memory exercise means, operatively connected to said program control means, for selectively addressing and exercising said memory as designated by said interpreted instruction words, and for modifying data supplied to said memory during exercise thereof in accordance with interpreted data generation instruction words.
35. A memory system exerciser according to claim 34 wherein each instruction word contains a field allocated to data generation, address generation,memory read/write control and data or address comparison.
36. A memory system exerciser comprising: program control means for interpreting a set of instruction words each designating one or more selected memory system exercise operations selected from the group consisting of data generation, address generation, memory read/write control, data comparison and address comparison, memory exercise means, operatively connected to said program control means, for selectively addressing and exercising said memory system as designated by said interpreted instruction words, said memory exercise means including a data generation section comprising: test word register means containing data to be written to, or compared with data read from, an addressed storage location of said memory system, and data modification means for modifying the contents of said test word register means in response to data generation operations designated by said instruction words.
37. A memory system exerciser according to claim 36 wherein data contained in said test word register means is written to said addressed storage location in response to a memory write operation designated by an interpreted instruction word.
38. A memory system exerciser according to claim 36 wherein said data generation section further comprises: data comparator means for comparing data read from said memory system with data contained in said test word register means, and wherein interpretation by said program control means of an instruction word designating a data comparison operation is conditioned by the results of comparison in said data comparator means.
39. A memory system exerciser according to claim 38 wherein data is read from said addressed storage location in response to a read operation designated by an interpreted instruction word.
40. A memory system exerciser according to claim 34 wherein said memory exerciser means includes an address generation section comprising: address word register means containing the address of a memory system storage location to which data is to be written or from which data is to be read, and address modification Means for modifying the contents of said address word register means in response to address generation operations designated by said instruction words.
41. A memory system exerciser according to claim 40 wherein said address generation section further comprises: at least one other address-containing register, address comparator means for comparing the address contained in said address word register means with the address stored in one of said other address-containing registers, and wherein interpretation by said program control means of an instruction word designating an address comparison operation is conditioned by the results of comparison in said address comparator means.
42. A memory system exerciser according to claim 41 wherein said one or more address-containing registers respectively store a pointer address, the lowest address of said memory system, and the highest address of said memory system.
43. A memory system exerciser according to claim 40 wherein said memory exercise means further includes a data generation section comprising: test word register means containing data to be written to, or compared with data read from, the memory system storage location specified by the address contained in said address word register means, and data modification means for modifying the contents of said test word register means in response to data generation operations designated by said instruction words.
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