Instruction pre-reading controller
专利汇可以提供Instruction pre-reading controller专利检索，专利查询，专利分析的服务。并且PURPOSE: To eliminate the waiting control for initialization by using an instruction selector which transfers the data addressed by an address register AR directly to an instruction register and a data bus which transfers the contents of the AR to pre-fetching register.
CONSTITUTION: When a branch instruction is transferred to an instruction register IR5, a branching destination address is calculated by an operator 9. Thus calculated value is transferred to an AR2 to start an input action for the data on the address designated by the AR2. In this case, the storing destination of data is headed directly toward the IR5 via an internal bus 11. While a micro- code for execution of a normal input/output action is delivered to a microinstruction register 7 for execution of the data input action. A decoding signal F of the microcode is used for control of a buffer 12, an instruction selector 14 and an address selector 3 respectively. For the next instruction of the head address of the branching destination, the contents of the AR2 are sent to a pre- fetching register 1 via a data transfer bus 13 and in parallel to the data transfer cycle to the IR5 since a pre-reading action is performed by the register 1.
COPYRIGHT: (C)1985,JPO&Japio，下面是Instruction pre-reading controller专利的具体信息内容。
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