专利汇可以提供SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES专利检索,专利查询,专利分析的服务。并且A system memory (11) for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. In order to accommodate the scanning of a number of storage locations in parallel, the system memory (11) is divided into a node memory (84) and the mark bit memory (83) so that the mark bits for a number of sequential storage locations can be examined in parallel to determine which node locations are free for use by the graph manager (10).,下面是SYSTEM MEMORY FOR A REDUCTION PROCESSOR EVALUATING PROGRAMS STORED AS BINARY DIRECTED GRAPHS EMPLOYING VARIABLE-FREE APPLICATIVE LANGUAGE CODES专利的具体信息内容。
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