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Wheel slip detector having fluid logic devices

阅读:621发布:2022-07-26

专利汇可以提供Wheel slip detector having fluid logic devices专利检索,专利查询,专利分析的服务。并且A fluidic wheel slip detector circuit for monitoring the synchronization or relative frequency of rotation of wheel/axle units of a railway vehicle by comparing the relative condition of a pair of fluidic binary counters driven in accordance with the rotational speed of the wheel/axle unit with which each counter is associated. Fluidic digital decoding circuitry is provided to continuously sense and indicate the progression of the counters. Fluidic decision logic circuitry including comparator means responds to a predetermined signal from the decoding circuitry for comparing the progression of the respective counters associated with each wheel/axle unit and controls fluidic memory means which produces an indication of which wheel/axle unit is rotating at the higher frequency in the absence of synchronization therebetween and maintains the signal until synchronization is restored. The decision logic circuitry also includes fluidic reset means responsive to another predetermined signal from the decoding circuitry to assure that the counters are reset in phase each cycle when either one of the counters first reaches a predetermined count.,下面是Wheel slip detector having fluid logic devices专利的具体信息内容。

1. A system for indicating a difference in the rate of rotation of either one of a pair of rotatable members relative to the other, each member having associated therewith appAratus comprising: a. a pulse generator for producing a train of pulses varying in frequency according to the rate of rotation of a different one of said members, b. a binary counter responsive to said train of pulses for sequential advancement to different ones of a plurality of stages, c. a logic circuit including: i. an OR gate having an output for providing a first signal in response to said counter being in a first stage of advancement, ii. a first AND gate having an output for providing a second signal in response to said counter being in a third stage of advancement, and d. a comparator AND gate having a pair of inputs, one of which is connected to the output of said OR gate in said logic circuit associated with said one of said members and the other of which is connected to the output of said first AND gate in said logic circuit associated with the other one of said members, and an output for providing an error signal when said first and second signals from the logic circuits associated with said one and said other member respectively are concurrently effective, in accordance with said one member rotating at a predetermined lower rate than said other member.
2. The system as recited in claim 1, wherein said apparatus associated with each member further comprises a bistable flip-flop element having opposing inputs connected respectively to the outputs of said comparator AND gate and said first AND gate associated with a corresponding one of said members and an output providing a memory signal in response to said error signal, said memory signal at said flip-flop being removed in response to said second signal being provided thereat in the absence of said error signal.
3. The system as recited in claim 2, further characterized in that means is provided for reducing the level of said second signal at one of said opposing inputs of said flip-flop so that when said error signal is concurrently effective at the other one of said opposing inputs, said memory signal is provided.
4. The system as recited in claim 1 wherein said system further comprises: a. said logic circuits each including a second AND gate having an output for providing a third signal in response to said counter being in a fourth stage of advancement, b. OR gate means subject to said third signal provided by said second AND gate of either one of said logic circuits for providing a reset signal, and c. said counters having reset port means subject to said reset signal for simultaneously resetting each of said counters from any stage of advancement to said first stage.
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