BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to radio receivers. More specifically, this invention relates to communications modems which incorporate frequency tracking systems.

While the present invention is described herein with reference to particular embodiments and applications, it is to be understood that the invention is not limited thereto. Those of ordinary skill in the art having access to the teachings of this invention will recognize additional applications and embodiments within the scope thereof.

2. Description of the Prior Art

Remotely piloted aircraft or drones may be utilized to provide effective reconnaisance of an enemy position at the forward edge of a battle area. In hostile environment, the drones are subject to destruction by counterfire or being jammed by electronic countermeasures. As a result, it has come to be recognized that such remotely piloted aircraft should be equipped with minimally expensive dispensable hardware, sufficiently sophisticated to penetrate the enemy's electronic defenses.

Drones are currently guided by signals transmitted at relatively low data rates. The rate of transmission typically is on the order of a few hundred bits per second or less. When the aircraft is in flight, the transmitted signals experience Doppler shift in the carrier signal which induces drift or frequency offset in the demodulated data signal. With a carrier signal on the order of 10GHz and the drone flying at a velocity of a few hundred miles per hour, the Doppler shift is on the order of the data rates. The Doppler effect thus interferes with the capability of the drone to receive and interpret guidance commands.

Systems which employ phase lock loops (including decision directed loops) to track the carrier frequency are effective in overcoming the effect of Doppler shift. However, such systems are typically limited in operation to coherent signals, i.e., those having long term phase continuity relative to the time constant of the phase lock loop.

These systems would provide adequate frequency tracking were it not for the desirability of hardening the drone against countermeasures. Unfortunately, some very effective counter-countermeasures, particularly frequency hopping, render the received signal substantially noncoherent.

It is therefore desirable to provide an inexpensive communications modem for use in remotely piloted vehicles which is capable of compensating for Doppler shift in the carrier frequency while being compatible with conventional electronic counter-countermeasure signal preprocessing techniques.

SUMMARY OF THE INVENTION

The present invention is an adaptive recursive frequency offset tracking system for effectively acquiring and tracking coherent and well as non-coherent electromagnetic data signals.

The system includes circuitry for eliminating the carrier frequency and generating complex samples of the baseband signal.

The system compares the phase of a sample to that of the previous sample to extract signals representing the phase difference between the two. The signals representing the phase difference are then converted to phasor signals and filtered to eliminate any noise component.

The phase difference signals are derived from the phasor signals and accumulated to derive signals representing the frequency offset of the received data signal.

The frequency offset signal is then provided to a phase shifter to correct for the effect of Doppler shift on the received data signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The FIGURE is a block diagram of an illustrative embodiment of the present invention.

DESCRIPTION OF THE INVENTION

The illustrative embodiment of the present invention 10 is shown in the FIGURE. The radio frequency subsystem 12, though not part of the invention, is shown for the purpose of illustration. Radio signals received by an antenna are amplified and converted to an intermediate frequency ω_o by the RF subsystem 12, and are fed into demodulators 14 and 16 which are driven by the cosine and sine of ω_o t and respectively. The sin ω_o t and cos ω_o t are generated by the π/2 phase splitter (quadrature hybrid) 20 which operates on the output of the local oscillator 18. The carrier signal is removed by the demodulators 14 and 16 which serve to generate the complex representation of the received signal. The outputs of demodulators 14 and 16 are input to low pass filters 22 and 24. The outputs of filters 22 and 24 are switched by gates 26 and 28 respectively which operate under the control of a clock 27. Note that in cases where the frequency ω_o is not constant (as would be the case for a frequency hopped signal) a timing recovery mechanism (not shown) would be required to synchronize the sampling clock with the local oscillator. (For the purposes of illustration, the remaining clock connections are not shown to the circuits of the present invention. The timing and clocking of the present invention is obvious to one of ordinary skill in the art.) The outputs of sampling gates 26 and 28 are input to analog-to-digital (A/D) converters 30 and 32 respectively. The outputs of the A/D converters 30 and 32 are input to a phase shifter 34 via lines 36 and 38 respectively. The real part of the complex digital data signal is provided on line 36. The imaginary part of the complex digital data signal is provided on line 38.

The phase shifter 34 effectively corrects the phase of the signal received on lines 36 and 38 by an amount determined by the circuitry to be discussed more fully below. The real part of the signal shifted by the phase shifter 34 appears on line 40 and is input to a phase detector 44. The imaginary part of the signal shifted by the phase shifter 34 appears on line 42 and is also input to the phase detector 44. The phase detector 44 extracts the phase angle of the shifted signal. This output is applied to a modulo 2π phase differentiator 46, which supplies one output sample for each pair of input samples. The output of the modulo 2π phase differentiator 46 is input to a converter 52. The converter 52 converts the signals to phasor form. The cosine of the converted signal appears on line 54 and the sine of the converted signal appears on line 56. Line 54 feeds a summer 58 while line 56 feeds a squaring operator 60 and a phase detector 62. The output of the summer 58 is input to the phase detector 62 and a second squaring operator 64. The squaring operators 60 and 64 input to a summer 66. The square root operator 68 operates on the output of the summer 66 to provide a signal to a damping amplifier 70. This square root of the sum of the squares equals the magnitude of the complex signal applied to the phase detector 62. The damping factor F is introduced by the amplifier 70 as a design parameter to control the loop bandwidth. The output of the amplifier 70 is input to a delay circuit 74. The output of the delay circuit is fed into the summer 58.

For reasons which will be more evident from the discussion of the operation of the invention below, the output of the phase detector 62 is input to a summing circuit 76. The summer 76 adds to the output of the phase detector 62 a signal equal to the previous output of the summer 76 which is provided by the delay circuit 80. The output of the summer 76 is sampled and held by circuit 78 which provides a 1:2 resampling of the signal. A summer 82 then sums the sampled and held signal with its previous output as provided by the delay circuit 84 and provides the phase shift correction to the phase shifter 34.

The operation of the present invention can best be understood with reference to the following mathematical discussion. The signals received by the RF subsystem 12 can be assumed to have the form Z(t). This represents a signal at a center carrier frequency of ω_o ; the signal is assumed to be continuous over two consecutive sampling intervals. The demodulators 14 and 16 operate with the local oscillator 18 and the phase shifter 20 to remove the carrier signal and create a complex baseband signal from the received signal.

The low pass filters 22 and 24 average the received signals Z(t) by integrating over a time interval T_s (one sampling interval). Switches 26 and 28 are clocked to sample the complex baseband signal to derive a plurality of complex samples. The l^th sample of the complex baseband signal may be expressed by the following equation. ##EQU1## Multiplication by e^-jω.sbsp.o^t' represents the action of the demodulators 14 and 16. The integral is evaluated at a time t which is equal to the product of the sample number l times the sampling interval T_s.

The angular frequency offset δ which the system 10 of the present invention substantially compensates for is equal to the phase difference due to frequency offset between successive samples ψ divided by the sampling interval T_s or ##EQU2## The frequency offset δ is assumed to remain essentially constant. The first two samples are passed through the phase shifter 34 to the phase detector 44 without correction. The modulo 2π phase differentiator 46 compares the phase angle of one sample to that of the previous sample. That is, the first and second samples are compared. The phase differentiator 46 stores a first phase angle within a pair and subtracts it from the second phase angle within a pair to provide an output to the converter 52 which is equal to the phase difference therebetween. Note that there will be half as many outputs from the phase differentiator 46 as there are samples as it requires two samples to provide a single output. The phase detector 44 and the phase differentiator 46 together provide means for comparing the phase of successive samples to extract signals representing the phase difference between two samples.

The phase difference φ is converted to a phasor e^jφ by converter 52. Note that conventional systems filter the phase difference signal at this processing stage. As a result, conventional systems are inclined to suffer from a momentary inability to correctly compute the proper correction when the phase difference is π or -π; this is due to confusion as to which sign the correction should have. For further discussion see Gardner, F. L., "Hangup in Phase Locked Loops", IEEE Trans. on Communications COM-25, No. 10, pp. 1210-1214, October 1977. Conversion to a phasor signal at this point is advantageous relative to the systems of the prior art insofar as the phasor output for a phase difference of π is identical from that for a phase difference of -π. As a result, the system of the present invention will not get confused and therefore is expected to exhibit markedly smaller acquisition time than such prior art systems.

In addition, conversion to phasor signals allows the loop bandwidth to be adjusted dynamically, based on a track quality indication, as is explained below.

The phasor signals representing the phase difference between successive samples are provided as outputs on lines 54 and 56. By Euler's equation, e^jφ =cos φ+j sin φ where j is equal to the square root of -1. Accordingly, the cos φ appears on line 54 and the sin φ appears on line 56.

The summing circuit 58, squaring operators 60 and 64, phase detector 62, summing circuit 66, squaring operator 68, damping amplifier 70, and delay operator 74 provide means for filtering the phasor signals to remove the effects of noise. The output of the low pass filter is given by the following equation: ##EQU3## where ρ_k e^jψ.sbsp.k is the output of the low pass filter expressed as a complex quantity; ψ_k is the phase of the filter output and ρ_k is the magnitude of the filter output. F is the damping factor of the filter chosen as a system parameter to determine filter averaging time and thus to control the loop bandwidth.

The low pass filter operation may be best explained in polar coordinates. Equation [3] is equivalent to equations [4] and [5] below. That is, to examine the magnitude ρ_k of equation [3], one may multiply the right hand side of the equation by the term _e ^jψ k-1. Since this term is an argument term, it does not affect the magnitude ρ_k which may therefore be expressed by equation [4] below.

ρk =∥Fρk-1 +ej(φ.sbsp.k-ψ.sbsp.k-1.sup.) ∥[4]

Equation [4] provides the magnitude of the filter output and equation [5] below provides the phase. The phase ψ_k is equal to the argument of equation [4] plus a term which compensates for the multiplication at the right hand side of equation [3] by _e ^-jψ k-1. Thus, ##EQU4## ψ_k is therefore the estimate at time t=2kT_s of the phase difference between samples of the input signal Z and Fρ_k-1 is the bandwidth control and loop tracking quality indicator.

Squaring operators 60 and 64, summer 66 and square root operator 68 cooperate to provide the magnitude of the phasor output of the converter 52. The damping factor is applied by the amplifier 70 and fedback to delay operation 74 so that Fρ_k is stored and becomes Fρ_k-1 for the subsequent iteration.

The phase detector 62 provides means for extracting the phase difference signals from the phasor signal to provide the estimate of phase difference ψ_k of equation [5]. It provides the argument of the sum of the current phasor and the previous filter output. See equation [3].

The estimate of phase difference between successive samples of the input signal Z(t) is provided by the phase detector 62 as an input to the summing circuit 76. The previous output of the summing circuit 76 is fed back to the summer 76 via delay operator 80. The absolute phase estimate θ referenced to a k index can be expressed by equations [6] and [7] below:

θ2k+2 =θ2k+1 +ψk            [ 6]

θ2k+1 =θ2k +ψk              [ 7]

Thus, ψ_k is the phase increment used to accumulate the absolute phase correction θ_l. There are two equations here because one new value of ψ_k generates two values of θ_l. The k index arises from the condition that two k samples are required for each l correction. The 1:2 sample and hold circuit 78 facilitates the conversion from the k index to the l index. The equivalent equation referenced to the l index is:

θl =θl-1 +ψk                [ 8]

where l=2k+2 or l=2k+1.

Summer 82 and delay operator 84 cooperate to input to the phase shifter 34 the previous absolute phase estimate θ_l-1 plus the estimate of the phase difference between successive samples ψ_k as required by equation [8]. Thus summer 76, sample and hold circuit 78, delay operator 80, summing circuit 82, and delay operator 84 cooperate to provide means for accumulating the extracted phase difference signals to derive signals representing the frequency offset of the received data signal.

Recalling equation [2], the frequency offset δ is equal to the phase difference ψ divided by the sampling interval T_s. The measurement Δψ_k is computed as ##EQU5## which is equivalent to what was given above because

ψk-1 =θ2k -θ2k-1 and        [10]

φk =arg{Z2k }-arg{Z2k-1 }               [11].

The phase shifter 34 provides means for shifting the phase of the received data signal in response to the accumulated phase difference signals to substantially compensate for the frequency offset. The resulting phase estimate θ_l is applied to the input signal Z_l such that the output of the phase shifter 34 is the corrected signal Z₁ e^-jθ_l.

The embodiment of FIG. 1 is referred to as an illustrative embodiment for two reasons. First, the demodulator subsystem (components 14 through 32) may vary in its detailed configuration depending on the nature of the signals whose frequency offset is to be estimated. Second, the preferred embodiment of the tracking subsystem (components 34 through 84) would be implemented on a digital computer by means of a program. The listing of one such program (written in the language PASCAL) is attached. The inputs to this program are the signals on data lines 36 and 38 and the outputs are the signals on data lines 40 and 42.

While the present invention has been described above with reference to particular embodiments and applications, it is to be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings of the present invention will recognize additional embodiments and applications within the scope thereof. It is contemplated by the appended claims to cover any and all such applications. ##SPC1## ##SPC2## ##SPC3## ##SPC4## ##SPC5## ##SPC6##