Printer with high speed tabulation rack and method for locating the next tabulation stop in such a printer

Technical Field of the Invention

This invention relates generally to electronic tabulation racks. More specifically, the invention relates to accessing tabs set in an electronic tabulation rack in a high speed processor controlled printer.

Description of the Background Art

The most pertinent prior art relating to electronic tab racks is the widely known method of setting one bit for each possible escapement position in an electronic tab rack memory as disclosed in Patent US-A-4,031,996. Thereafter, during printing when the print controller receives a tab signal, a search is initiated to find the next bit in the memory indicating the next escapement position. This search is conducted by serially looking at each bit in the tab rack. The horizontal motion then required of the print mechanism carrier is calculated as the difference between the next tab position and the present position of the print mechanism and moved accordingly. For typewriters and slow interactive printers this search technique is adequate. However, a bit-by- bit search requires time not available in high speed trail printers, such as those used in word processing applications.

Summary of the Invention

It is therefore, the object of this invention to overcome the aforementioned disadvantage of the prior art by decreasing tab stop search access time in an electronic tab rack and by determining tab stop location in an improved manner.

The improvement in electronic tabulation racks in accordance with the present invention comprises a second, condensed tabulation rack where one bit represents the logical OR of one multibit block of the complete, or basic, tubulation rack. This improvement in accordance with the invention is defined by the features of claim 1. The condensed tab rack is an addressing expedient for the basic tab rack which enables search time for the next tab stop to be decreased since fewer bits must be examined. The present invention facilitates determination of the location of the next tab by first checking the currently accessed basic tab rack block for any more tabs, then the condensed tab rack for the next "1" bit, which may indicate a block quite removed from the present one.

The foregoing and other objects, features and advantages of the instant invention will be apparent from the following more particular description of a preferred embodiment, as illustrated in the accompanying drawing.

Brief Description of the Drawing

• FIG. 1 is block diagram of the overall system in which the instant invention operates.
• FIG. 2 schematically illustrates the structure and relationship between the basic and condensed tab racks.
• FIG. 3 is a block diagram of the tab rack setup.
• FIG. 4 is a block diagram of the tab stop determination.
• FIG. 5 shows the logic details of block search.
• FIG. 6 illustrates the logic of the condensed tab rack search.

Description of the Preferred Embodiment

Referring now to FIG. 1, the system will be described. The instant invention is utilized in the control of high speed printers, for example. In word processing systems. To that end, input to the system may come from one of several sources such as directly from a keyboard 2, a memory 6, or over transmission line 10. Any of these three represents a print image source, and this image is conveyed over lines 4, 8 or 12 to input decode logic 14. No great detail is thought necessary to be set forth as this is conventional in the printer control art. Outputs from logic block 14 include indications of whether a particular data stream is a character on line 16, an index code on line 18, or a tabulate control code on line 20. Character and index codes on lines 16 and 18, respectively, are input to control and format logic 22 which preprocesses the data received on lines 16 and 18 for compatibility with the device. Format logic 22 then converts this data to control sequences recognized by the printer mechanism. Again, this is conventional and well understood by those skilled in the art. Outputs on lines 24 and 26 are fed to logic blocks 30 and 31 which executes the control sequences from 22. The output of logic blocks 30 and 31 goes on lines 32 and 34, respectively, to the actual printer mechanism itself, represented by block 36. Line 28 is the third output from control and format logic 22 and is input to escapement control logic block 38 which interacts with the printer mechanism over line 40. The present invention is more particularly related to tabulation control as determined in input logic 14 in a high speed printer control. Any tabulation control signal decoded in input logic 14 is output on line 20. Line 20 is actually a plurality of lines which contain any data necessary to describe the tabulation function. These include the location of tab stops for the current document (tab rack image) and the requirement to tab (tab character). Line 20 is input to tabulation control block 42 which has an output on line 44 to escapement control logic 38. Blocks 14, 22, 42, 30, 31 and 38 can be implemented in either logic or microcode or an integration of both.

FIG. 2 schematically illustrates the relationship between the basic tab rack 46 ana the condensed tab rack 48 of the instant invention. The basic tab rack, indicated generally at 46, consists of N blocks where each block contains an equal number of bits. Condensed tab rack 48 has one bit for each block that is present in basic tab rack 46. Each corresponding bit in condensed tab rack 48 is set "ON" if at least one bit is on in its correlative block in tab rack 46. Whether any given bit in condensed tab rack 48 is "ON" or "OFF" simplifies the search through basic tab rack 46 since all bits in the corresponding basic tab rack block may be skipped for every zero found in the condensed tab rack. While the invention has been described in terms of eight bit bytes it is, of course, understood by those skilled in the art that other convenient byte or block sizes may be used without departing from the scope of the invention.

FIGS. 3, 4 and 5 together make up the tab control logic indicated by block 42 in FIG. 1. Referring now to FIG. 3, a more detailed description of logic block 42 in FIG. 1 will be presented. FIG. 3 shows the logic used to set up tab racks 46 and 48 in FIG. 2. Tab control decode logic 50 utilizes input on line 20 to determine whether the tab indication is a tab character, a tab rack image, or a clear signal and to output such on lines 52, 54 and 56, respectively. On line 52 is a tab character indication and it will be processed by logic 53 shown expanded and described in connection with FIG. 4. Clear signal on line 54 is input to clear basic tab rack memory 60 or condensed tab memory 62. Tab rack image on line 56 indicates that the positions at which tabs are desired to be set is currently present on line 20; line 56 is input to delay 58 as well as basic tab rack address decode logic 66 and the basic bit in block decode 70. A second input to basic address decode 66 and bit in block decode 70 is line 20. The basic address decode block 66 will be activated by the tab rack image signal 56 and will decode the signal line 20 into the associated address in the basic tab rack memory 60 and then control the fetching of this decoded location from that memory. There are two outputs from decode logic 66: one output is a read signal on line 68 for reading from basic tab rack memory 60 and from the condensed tab rack memory 62. Tab rack image on line 56 also activates decode logic block 70 for determining in which bit within the basic tab rack block addressed by block 66 is the bit representing where a tab is desired to be set. This block is activated by a signal on line 56 and decodes the data on line 20. Output on line 72 is a plurality of signals equal in number and format to one basic tab rack memory block. Each signal is zero with the exception of that signal representing the bit decoded by block 70. This bit is a one. Output line 72 is one input to OR gate 74. It is to be noted here that details of the read/write control from memories 60 and 62 is not described as it will be appreciated to be conventional by those skilled in the art.

The other of the two aforementioned outputs from basic address decode logic block 66 is on line 78 and is an address used to access basic tab rack memory 60. This address is also input to logic 80 for decoding the corresponding bit location in condensed tab rack memory 62. The output of decode logic 80 on line 82 is input to OR gate 84. Line 82 is actually a plurality of lines equal in number and format to condensed tab rack memory 62. Each signal is zero with the exception of that signal corresponding to location in condensed tab rack memory 62, as decoded by block 80.

A multi-bit block of data which has been retrieved from basic tab rack memory 60 is on line 86 and is the second input to OR gate 74. When OR gate 74 is activated, there is a signal on line 88 which comes back to the Data In input of basic tab rack memory 60. Similarly, the contents of the bits in condensed tab rack memory 62 which has been fetched by a signal on 68 makes the second input to OR gate 84 on line 90 resulting in an output signal on line 92 which is the Data In input to condensed tab rack memory 62.

Line 94 has the tab rack image signal which was delayed in delay means 58. On line 94 is a pulse which is the Write signal for both basic tab rack memory 60 and condensed tab rack memory 62. Delay means 58 is such that the Write signal on line 94 is generated after the memory access to memories 60 and 62 is complete and the ORing process in Blocks 74 and 84 is complete. Thus, the tab rack image is decoded and the corresponding locations in the tab rack memories are fetched, updated, and stored.

Fig. 4 shows details of find tab stop logic 53 from FIG. 3. One input to find tab stop logic 53 is the contents of the on-line register which is a part of escapement logic 38 in FIG. 1. The contents of this register, which indicates the current escapement position, is on line 100. Both tab character indication on line 52 and data on line 100 are input to decode logic 102 for determining tab block address in the basic tab rack memory 60 and to decode logic 104 for determining bit address within the block. The address decoded by logic 102 is on line 106 and is input to decode logic 108 for determining bit location in condensed tab rack memory 62. The address on line 106 is also an input to adder 110.

The decoded address on line 106 is the address in the basic tab rack memory where the search for the next tab stop will be started. The decoded output from decode logic 108 on line 112 is the starting point for searching in the condensed tab rack memory 62. This address is one input to condense tab rack memory search block logic 114 which will be described in detail with reference to FIG. 6.

The decoded address in the basic tab rack memory 60 on line 106 is also input to set latch 116 in order to maintain this address through the memory operation. Output of latch 116 on line 118 is used to access a block in basic tab rack memory 60.

Logic 104 is provided for decoding tab character information on line 52 to determine the search starting point within the basic block addressed by line 106. Therefore, when a tab character is decoded on line 52, the current escapement position of the printer on line 100 is used to determine the location in the basic and condensed tab racks via Decodes 102, 104 and 108. In addition, the block of data within the basic tab rack 60 is fetched and presented to the search logic 126. Logic 104 places this information on line 120 which sets latch 122 in order to allow this value to be maintained during the search operation. This search start address is fed by line 124 from latch 122 to logic block 126. Logic 126 is the search basic tab rack memory 60 logic and is described in detail below in connection with FIG. 5.

The other output from basic address decode logic 102 is a Read command on line 128 which sets latch 130 and held through the Read operation. Output from latch 130 is the memory read command MEMREAD on line 132 which is used to retrieve from basic tab rack memory 60 a multibit block of data and place it on line 134. Data on line 134, along with MEMREAD on line 132, is input to search logic 126. Outputs from search logic 126 include a signal BFIND on line 136 indicating if another tab stop has been found in the block of basic tab rack memory 60 currently being accessed. A signal BCOUNT on line 138 gives the count of the tab location searched before the tab stop was found or the count of tab locations searched by the time the block was completely searched without finding a tab stop. The third possible output from logic 126 is a signal B-NOT FIND on line 140 which indicates that no other bits were found to be on in the currently accessed multi-bit block from basic tab rack memory 60. A signal on line 140 thus means there is a need to search in condensed tab rack memory 62 to obtain a pointer to the next block in basic tab rack memory 60 having a bit set "on". Signals on lines 136 and 140 are the inputs to OR gate 142 which produces a reset signal RST on line 144 to reset latches 116, 122, 130, and 126 which hold basic tab rack address, search start point, memory read signals and basic search block signals, respectively. That is, the read operation activated by a signal on line 52 as described above is reset when the search operation of block 126 is complete.

Output 140 of block 126 is also an input to the read input of the condensed tab rack 62. Therefore, the contents of the condensed tab rack 62 is passed to the condensed search block 114 when there are no additional tab stop locations found by search block 126.

Output from search logic 114 may be one of three signals. If no bit was found "ON" in the condensed tab rack data searched, a signal C-NOT FIND on line 148 so indicates. This signal is input to error logic 150 which may communicate with the printer operator in any desired manner. The second possible output from logic 114 is a count of bits passed in condensed tab rack memory 62 from the search start point indicated on input 112 until a bit was found to be "ON" or the entire memory was searched. The signal carrying this count, C-COUNT, is on line 152. The third output is the C-FIND signal on line 154 which indicates that a bit was found "ON" meaning that another block containing at least one tab stop exists.

C-NOT FIND on line 148 and C-FIND on line 154 are inputs to OR gates 164. The output on line 166 is a STOP signal whose function will be described in connection with FIG. 6.

C-FIND is delayed in delay means 156 in order to allow time for adder 110 to function. The output of delay means 156 called C-FIND DLY on line 158 is an input to latch 130 which via output 132 causes a second read of the basic tab rack. Further, signals on lines 152 and 154 are input to Adder 110. C-FIND signal 154 is used to activate Adder 110. The value on line 152 when the adder is activated is equal to the number of zeros encountered by the search logic 114. This will be added to the basic starting address, line 106, as determined by the current escapement position, line 100, via decode logic 102. Input line 160, assures that an additional value of one is added to the result to account for the fact that the count 152 represents only blocks skipped and does not account for the block to be addressed. Thus the output 162 becomes an input to latch 116. The address on line 162 latched in 116 coupled with the signal on line 158 latched in 130 causes the newly calculated block in the basic tab rack 60 to be fetched and it is passed along line 134 to the basic search block 126. The input to block 126 on line 124 is zero as latch 122 has been reset by line 144. Therefore the search conducted by block 126 will begin at the first bit location and proceed until a one bit is detected. This will result in a signal on line 136 and a count on line 138. This count represents the number of tab locations from the beginning of the block being searched to the first tab stop prescribed by the presence of a one bit.

B-FIND and B-NOT FIND signals on lines 136 and 140, respectively, are input to OR gate 142 the output of which RST on line 144 is one input to AND gate 174. The B-COUNT signal on line 138 is the other input to AND gate 174, the output of which on line 176 forms an input to OR gate 186. C-FIND on line 154 is delayed by delay means 156 and becomes signal C-FIND DLY on line 158 and is one input to AND gate 182. C-COUNT line 152, the number of bits passed in searching through condensed tab rack memory 62, is multiplied by the number of bits comprising a block in multiplier 178. The product on line 180 represents the number of tab position skipped while searching condensed tab rack memory 62. Line 180 is the other input to AND gate 182. Output of AND gate 182.on line 184 is the other input to OR gate 186, the output of which on line 188 is input to Adder 190. The sum on line 192 goes into results register 194 and back into Adder 190 via line 196. Results register 194 is reset when read line 128 is active at the beginning of the cycle. The sum on line 196 is also input to logic 202 to convert those bits to escapement units. This conversion, of course, is a function of the specific print control system being used.

The other input on line 200 to logic 202 is a delayed B-FIND signal B-FIND DLY developed by delaying the signal on line 136 in delay means 198. Output from delay means 198 is on line 200 and is input to conversion logic 202. B-FIND DLY signal on line 200 is further delayed in delay means 204 and the output on line 206 is a memory reset signal MEM RST. The actual number of escapement units from logic 202 is on line 44 and is input to escapement control 38 as shown in FIG. 1. MEM RST on line 206 is also used to reset search logic 114.

Line 144 becomes active when search block 126 is activated via the first search of the basic tab rack (as activated by a decode of the tab character via block 102, etc.). Therefore, the results of this search are gated through AND gate 174 and OR gate 186 to adder 190. Since the results register 194 was reset when the search began, the other input 196 is a zero. The result of this add is to place the first search value in the results register 194. Now if the search were successful, B-FIND line 136 would be active. This line delayed through block 198 to line 200 would cause the value in results register 194 via line 196 to be converted to escapement units via block 202.

If the initial search was not successful, this conversion would not take place as no signal would be generated on line 200. Instead a search of the condensed tab rack would be activated via a signal along line 140 as described above. If the results of this search result in finding a bit "ON" in the condensed tab rack, then line 154, is active and the count value C-COUNT on line 152 converted to the number of skipped tab positions by block 178 is gated through AND gate 182 and OR gate 186 to Adder 190. This value is added to the results register 194 (i.e., the value of the initial search of the basic tab rack block), and the results placed back in the results register 194.

Having completed the search of condensed tab rack 62, the second search of the basic tab rack is initiated as described above via signals along line 158 to latch 130 and line 162 to latch 116. When this search is completed, RST signal on line 144 is active causing the newly determined count value B-COUNTto be gated through AND gate 174 and OR gate 186 to Adder 190. This value on line 188 represents the number of tab positions searched in this second search operation. This value is summed by adder 190 to that in results register 194 and the sum is returned to the results register 194. Results register 194 now contains the sum of three values: 1) the number of tab positions in the first basic tab rack block searched which contained no tab stop; 2) the number of tab stops skipped as a result of the search of the condensed tab rack; and 3) the results of the second basic tab rack block search which contained a tab stop. This is equal to the number of tab positions until the next tab stop. Since a find is guaranteed for this second search, line 136 is active and is delayed through delay means 198 to block 202 via line 200. Therefore, the sum is converted to escapement units in block 202 and passed to printer mechanism 36 via line 44.

FIG. 5 shows in detail the logic represented by block 126 in FIG. 4. The multi-bit block retrieved from basic tab rack memory 60 on line 134 is input in parallel to shift register 210. The memory read signal MEM READ on line 132 is used to start shift clock 212 so that pulses B-SHIFT appear on line 214 for shifting bits out of shift register 210. RST on line 144 is used to stop shift clock 212. Bits are shifted out from shift register 210 onto line 216. The least significant bit is shifted out first to sample register 218. This bit is then output from sample register 218 on line 220 as the A operand to comparator 224. The B operand of comparator 224 is a hard wired one (+1) on line 222. Output from comparator 224 indicates that the sampled bit was "ON" and this signal on line 226 is input to AND gate 230 along with B-NOT SHIFT signal on line 208, the inverse of the B-SHIFT signal on line 214. The other input to AND gate 230 is on line 240 and will be described below. The output of AND gate 230 is the B-FWD signal on line 136. SSP, or search start point signal, on line 124 is the A operand input to comparator 234 which determines whether the A operand is greater than the B operand. SSP, which is in fact a numeric value equal to the location in the block represented by the current carrier position, is also the A operand input to arithmetic unit 248 on line 124. B-SHIFT signal on line 214 is also input to counter 236 which determines how many shifts have occurred. Counter 236 output is on line 238 and is the B operand input to comparator 234. Output from comparator 234 on line 240 is the third input to AND gate 230. Shift count on line 238 is the B operand input to arithmetic unit 248, is an input to comparator 234 as the B operand, and is the A operand input to comparator 242.

The B operand for comparator 242 is a constant indicating block size on line 244. The block size constant is the number of bits in a multi-bit block in basic tab rack memory 60 and would, of course, vary in accordance with implementation choices. Comparator 242 puts output on line 140 if shift count is greater than block size. It is B-NOT FIND, the signal indicating that no further tab bits were found "ON" in the currently accessed block from basic tab rack memory 60.

B-NOT FIND signal on line 140 as well as the B-FIND signal on line 136 are the two inputs to OR gate 246, the output of which is the activate signal 144 for arithmetic unit 248. Arithmetic unit 248 performs the operation of subtracting the A operand on line 124 from the B operand on line 238, that is, shift count minus search start point. The result is B-COUNT signal on line 138 which tells the number of tab positions searched during this operation.

Comparator 224 searches for a one bit within a block of the basic tab rack. When a one bit is found beyond the search start point as determined by comparator 234, AND gate 230 is active which puts B-FIND signal on line 136 thus indicating a tab stop was found. If a one bit is not found, the count in counter 236 will exceed the block size on line 244 and comparator 242 will place a B-NOT FIND signal on activate line 140 thus indicating that no tab stop was found. When either of lines 136 or 140 is active, arithmetic unit 248 is activated in order to subtract search start point on line 124 from shift count value on line 238. The difference yields the number of tab positions determined by the search.

FIG. 6 shows the details of logic block 114 from FIG. 4. B-NOT FIND on line 140 is also the condensed read signal, indicating that no "ON" bits were found in the currently accessed multi-bit block from basic tab rack memory 60. This signal on line 140 is used to start shift clock 250 placing C-SHIFT pulses on line 252. Data from condensed tab rack 62 on line 146 is input to shift register 254. A C-SHIFT pulse on line 252 causes one bit to be shifted out of the shift register 254 via line 256 to sample register 258. This bit from register 258 goes over line 260 to the A operand .input of comparator 262. Comparator 262 requires equal A and B operands before generating an output. The B operand is a constant +1 on line 222. Output from comparator 262 indicates that there is at least one tab set in the corresponding basic tab rack memory 60 block. This output on line 264 is one input to AND gate 268. Another input to AND gate 268 is C-NOT SHIFT, the inverse of C-SHIFT, on line 266. The development of the third input to AND gate 268 will be described below. Output from AND gate 268 is the C-FIND signal on line 154 which, along with the C-NOT FIND signal on line 148, gated through OR gate 164 in FIG. 4, is used on line 166 to stop the shifting of shift clock 250.

The starting point address for looking in condensed tab rack memory 62 is on line 112. Line 112 is the A operand input to comparator 274 and is also the B operand input to arithmetic unit 278. Comparator 274 compares to determine whether operand A is equal to or greater than operand B in this case whether the starting point for searching in condensed tab rack memory 62 is higher than or equal to the number of shift pulses. Counter 270 is provided for counting the number of pulses which appear on line 252 from C-SHIFT clock 250. This number is output on line 272 and is the B input to comparator 274. Output of comparator 274 on line 276 is the third input to AND gate 268. The shift count on line 272 is also input to the A input of arithmetic unit 278 which upon receipt of an activate signal from AND gate 268 on line 154, subtracts the B operand from the A and outputs the difference on line 152. The output on line 152 represents the difference between the number of shift pulses on line 252 and the search start point in condensed tab rack memory 62 (C-COUNT).

The highest, or maximum, address in condensed tab rack 60 is hardwired on line 284 and is the B operand for comparator 280. The output of comparator 280 is C-NOT FIND signal on line 148. The C-COUNT signal on line 152 is the output of arithmetic unit 278 which is activated by the C-FIND signal on line 154.

Comparator 262 indicates with a pulse on line 264 when a one bit is found in condensed tab rack memory 62. If this bit position is encountered beyond the search start point indicated on line 112 as determined by comparator 274 AND gate 268 is activated which activates line 154 thus indicating that an "ON" bit was found in condensed tab rack memory 62. When this occurs, arithmetic unit 278 is activated to subtract the start point on line 112 from the count value in counter 270 yielding the number of condensed tab rack bits from the starting point. If no "ON" bit is found then the count value in block 270 will exceed that of the maximum size of the condensed tab rack as indicated on line 284. Thus comparator 280 has an output pulse on line 148 indicating that no more tabs occur in basic tab rack memory 60. The counter 270 is reset by a signal on line 206 MEM RST.