TRANSACTION IDENTIFICATION SYNCHRONIZATION |
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| 申请号 | US15417984 | 申请日 | 2017-01-27 | 公开(公告)号 | US20180219562A1 | 公开(公告)日 | 2018-08-02 |
| 申请人 | Futurewei Technologies, Inc.; | 发明人 | Xiaobing Lee; Feng Yang; Shaojie Chen; | ||||
| 摘要 | Various embodiments include methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. Additional apparatus, systems, and methods can be implemented in a variety of applications. | ||||||
| 权利要求 | |||||||
| 说明书全文 | |||||||
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