Method and device for trellis encoding for fractional bit rate专利检索- .由信号空间编码进行的检错或前向纠错即在信号丛中增加冗余项例如梳状编码调制专利检索查询-专利查询网

Method and device for trellis encoding for fractional bit rate
申请号	JP13865490	申请日	1990-05-30	公开(公告)号	JPH0311829A	公开(公告)日	1991-01-21
申请人	American Teleph & Telegr Co ;			发明人	RII FUAN UEI;
摘要	PURPOSE: To reduce the number of constitutional elements in two-dimensional(2D) arrangement by identifying a point only from the selected combination of groups in each 2D subset. CONSTITUTION: A flow of output bits scrambled by a scrambler 120 provides twenty-one output bits to leads 131 to 139 in parallel through a series/parallel(S/ P) transformer 130. Eight bits appearing on the leads 133, 135, 137, 139 are passed through a preencoder 141 without being processed by it. Other thirteen bits appear on the leads 131, 132, 134, 136, 138, nine non-trellis encoded bits are applied to an inside/outside encoder 141 and a 3-bit word is outputted to a set of four leads 142 to 145. In this case, a 4-bit word consists of three bits on the lead 142 and one bit on the lead 132 to identify one specific symbol in eight 2D subsets. COPYRIGHT: (C)1991,JPO
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