Broadband differential amplifier |
|||||||
申请号 | EP87303393.0 | 申请日 | 1987-04-16 | 公开(公告)号 | EP0244973A2 | 公开(公告)日 | 1987-11-11 |
申请人 | TEXAS INSTRUMENTS INCORPORATED; | 发明人 | Zimmerman, Dale E.; | ||||
摘要 | A differential amplifier (230) with input differential dual gate FETs (232, 234) with one pair of gates (235, 237) tied together, with sources tied together, and with a current source (236, 238) for each of the FETs and inputs at the current source terminals is disclosed. These amplifiers provide large CMRR at frequencies to a few GHz, and fabrication in gallium arsenide is disclosed. A push-pull single-ended output stage provides good power handling and VSWR. | ||||||
权利要求 | |||||||
说明书全文 | The present invention relates to semiconductor electronic devices, and, more particularly, to broadband microwave differential amplifiers. A differential amplifier provides voltage gain to the difference between signals applied to its two input terminals while responding with much lower gain or attenuation to voltages common to the two inputs. Thus desired differential signals are amplified with little effect from extraneous common mode signals. Such extraneous signals frequently arise from signal current flow in long lines or from noise pickup, but they are essentially rejected by the differential amplifier. Further, the differential amplifier provides isolation of input and output quiescent voltage levels by its common mode signal characteristics. Consequently, operational amplifiers. which are basic building blocks for electronic circuits. tyically have differential amplifier input stages. See, generally. J.Graeme and G.Tobey. Eds.. Operational Amplifiers: Design and Applications (McGraw-Hill 1972). The common-mode rejection ratio (CMRR) is a figure of merit for a differential amplifier that compares the gain of signals common to both inputs to the gain of the difference between the signals applied to the inputs. The CMRR is defined as follows: let vil and vi2 be small signal voltages applied to inputs 1 and 2, respectively, of a differential amplifier, and vo1 and vo2 the output voltages at outputs 1 and 2. respectively; then the differential-mode voltage gain is For a single ended output the same definitions apply but with vo1 the output and vo2 = 0. Commerically available operational amplifiers may have a CMRR in the order of 100 dB; however, such operational amplifiers are effectively limited to operation at low frequencies (below about 100 MHz). But many signal processing and instrumentation systems require a broadband high frequency differential amplifier with a large CMRR; typically a low level signal (differential-mode) must be separated from a large interference signal which is common to both inputs (common-mode) at frequencies above 1 GHz. Figure 1 is an example of a signal processing application of a differential amplifier in which the output of a surface acoustic wave (SAW) device is detected at frequencies from 100 MHz to 2 GHz. Such amplifiers are not commercially available. and it is a problem to provide a simple, high frequency, large CMRR broadband differential amplifier. The present invention provides high frequency, broadband differential amplifiers with large CMRR and simple topology by use of an input differential pair of dual gate field effect transistors with the second gates tied together and with a separate zero-biased field effect transistor as current source for each dual gate FET. The return path for the current sources is through the inputs (as opposed to ground) to avoid the low FET source-drain impedance as a path to ground. The output stages may be single-ended with push-pull FETs to obtain high power and good VSWR. Preferred embodiments are fabricated monolithically on gallium arsenide. These differential amplifiers solve the problems of large CMRR in a simple topology, broadband amplifier. The drawings are schematic for clarity.
A differential amplifier or operational amplifier input stage is typically a pair of transistors (one for each of the inputs) biased into the active region and tied together to share a common current. Figure 2 illustrates a pair of field effect transistors (FETs) 32, 34 with their sources tied together to form a differential pair; generally denoted 30, and with zero-biased FET 36 providing the sum of the source-drain currents of FETs 32, 34. The use of FETs instead of the bipolar transistors typically found in commerical operational amplifiers is in preparation for discussion of the preferred embodiments which use gallium arsenide FETs monolithically integrated for high frequency operation. In particular. microwave FETs are typically gallium arsenide MESFETs with gates 1-2 µm long and hundreds of µm wide to provide sufficient transconductance. The CMRR of stage 30 can be approximated for low frequencies (< 100 MHz) from the simplified small-signal equivalent circuit shown in Figure 3 in which Gm is the transconducrance of each of FETs 32. 34 and Zcs is the small signal impedance of the current source FET 36. The result is Figure 5 illustrates some of the various connections for applications of a differential pair. Note that the differential pair may be connected as a 180 degree combiner. 180 degree splitter. or differential input/differential output amplifier as illustrated. A first preferred embodiment differential pair input stage, generally denoted 130 and illustrated in Figure 6, avoids the low impedance to ground of current source 36 by using a separate current source for each FET of the differential pair and having the current sources terminate at the inputs. In particular, the differential pair is the pair of n-channel FETs 132, 134. and FET 132 has zero-biased n-channel FET 136 as current source, and FET 134 has zero-biased n-channel FET 138 as current source. The gate width of FETs 132, 134 is about three times the gate width of FETs 136. 138 which are biased at IDSS: thus FETs 132, 134 are biased to about 33% of IDSS. Diodes 142 and 144 shift the level of the quiescent gate voltage on FETs 132. 134 so that VDS of current source FETs 136, 138 leads to good current regulation. Connection 140 ties the two current sources 136, 138 together at their drains; so the differential pair FETs 132, 134 are still splitting a common source current. The inputs are at the sources of current source FETs 136. 138 and the negative voltage supply: thus there is no direct path to ground through Zcs. Approximation of the CMRR for stage 130 by calculation with the simplified small-signal equivalent circuit shown in Figure 7 yields: A second preferred embodiment differential pair input stage, generally denoted 230 and illustrated in Figure 8. overcomes the drag on CMRR from the drain-source impedance of the differential pair FETs 132, 134 of stage 130 by use of dual gate FETs for the differential pair FETs with the second gates tied together. Note that the drain-source impedance of a dual gate FET is related to the drain-source impedance of a single gate FET by: Figure 10 is a simplified schematic diagram of stage 230; and Figure 11 a layout for stage 230. The quiescent voltages and currents are as indicated in Figure 10; current source FETs 236, 238 each operate at IDSS, which equals 33 mA, and thereby biases differential FETs 232, 234 to operate at 33% of IDSS because the gates of FETs 232, 234 are three times as wide as the gates of FETs 236, 238. Diode stacks 242, 244 raise the VDS of current source FETs 236, 238 to about 4.3 V (because VG1S for FETs 232, 234 equals -2.2 V for IDS = 33%IDSS) which insures good current source operation. Diode stack 246 raises the VG2S to about 2.1 V to maximize Zds of the dual-gate FETs 232, 234. Stage 230 may be fabricated monolithically on semi-insulating (chromium doped) GaAs as follows. First, the active areas are formed by ion implantation with silicon to a concentration of 2 × 1O17/cm3 to a depth of 0.4 µm. Next, the active areas are isolated as mesas, and Ti/Pt/Au deposited. The FET gates and diode anodes are defined in the Ti/Pt/Au by optical lithography and formed by plasma etching. Note that the resistivity of the active area is about 10-2Ω-cm. so the sheet resistance is about 400 Ω/□ and the bias resistors may be meanders in the active area; see Figure 11. Ohmic contacts are formed by liftoff of gold/germanium/nickel; and passivation is by plasma deposition of Si3N4. Figure 12 are simulations that compare the CMRR of differential pair stages 30. 130, and 230 up to 2 GHz. For the simulations. the outputs were presumed connected to microstrip transmission lines with characteristic impedances of 50 Ω and matched loads and the inputs were presumed to have generator impedances of 50 Ω. Figure 13A shows the differential mode and common mode gain up to 2 GHz and for mismatches of 0%, 5%, and 10% of FETs 232, 234 for stage 230 connected as a 180 degree combiner; and Figure 13B shows the same data for connection as a 180 degree splitter. The relative insensitivity of the CMRR to device mismatch is apparent. The curves of Figures 12 and 13A-B are simulations based on the equivalent circuits of Figures 4 and 9. Note that at low frequencies (< 100 MHz) the -9.0 V power supplies (which supply current through an inductor) may provide a low impedance to ground, so the corresponding portion of Figures 12 and 13A-B would be modified. Figure 14 is a schematic diagram of a push-pull differential amplifier, generally denoted 330, with single-ended output, and Figure 15 is a simplified small-signal equivalent circuit for amplifier 330. Amplifier 330 is fabricated in gallium arsenide analogous to stages 130 and 230 and includes FETs 332, 334 with 1.5 µm long and 300 µm wide gates, diode stack 336 of seven diodes with anodes 1.5 µm by 300 µm, 3 kΩ resistor 342, and 120 Ω resistor 344. Diodes 336 shift the inverting input 346 to the same quiescent level as the noninverting input 348; namely 3.1 V. The quiescent output level is 4.9 V. The CMRR calculated from Figure 15 is Figure 16 shows a simulation for amplifier 330 CMRR based on the FET small-signal equivalent circuit of Figure 4 with 300 µm wide and 1.5 µm long gates and seven diodes 336 with anodes 100 µm by 1.5 µm and drawing 2.4 mA bias current. For the simulations the output was presumed connected to a microstrip transmission line with 50 Ω characteristic impedance and terminated by a matched load, and the inputs were similarly presumed from a generator with 50 Q impedance; note that the inputs also are 3.1 V power supplies which have large chokes to prevent a-c shorting to ground. Simulations also indicate output VSWR for amplifier 330 is less than 2:1 up to 2 GHz and power output is about 20 dBm at 1 dB compression. Differential pair input stage 230 can be directly cascaded with push-pull amplifier 330 and the resulting two stage amplifier has about 10 dB differential-mode gain (note that the outputs of stage 230 are loaded by push-pull 330 inputs and not 50 Q) and CMRR of at least 35 dB even for 10% device mismatch. Figure 17 shows simulation results for the cascaded amplifier and indicates the dependence of CMRR on mismatch. Various modifications of the preferred embodiment amplifiers may be made while retaining the separate current sources coupled to the differential inputs feature of the amplifiers. For example, the dimensions and shapes of the FETs can be varied such as shorter and wider gates; the materials can be varied such as silicon instead of gallium arsenide substrate and aluminum instead of titanium/platinum/gold gates and anodes; the FETs can be replaced in whole or in part by bipolar or even heterojunction bipolar transistors; the push-pull output stage can be replaced by a differential output stage; and differential amplifier stages can be inserted between the differential input and the output stage to increase the overall gain. For higher frequency operation, the separate current sources could be inductors; such inductors could be fabricated as microstrip transmission lines on a gallium arsenide substrate. The advantages of the present invention include a simple topology for a broadband. high CMRR differential amplifier. |