Contactless IC card system

This is a divisional of application Ser. No. 09/751,140, filed Dec. 29, 2000, now U.S. Pat. No. 6,586,988, which is a divisional of application Ser. No. 09/327,757, filed Jun. 7, 1999 and issued as U.S. Pat. No. 6,198,361 on Mar. 6, 2001.

BACKGROUND OF THE INVENTION

The present invention generally relates to a contactless IC card system. More specifically, the present invention is directed to an amplifying circuit, a modulating circuit, a demodulating circuit, a transmitter apparatus, and a receiver apparatus, applicable to a contactless IC card capable of reading/writing various sorts of data in a contactless manner, and is also applicable to an IC card reader/writer capable of communicating data with this contactless IC card.

Conventionally, in IC card systems which employ IC cards, these IC card systems are applied to ticket inspection systems used in transportation facilities, and person entrance/exit management systems for rooms. Such conventional IC card systems utilize IC cards carried by users and IC card readers/writers capable of transmitting/receiving various sorts of data between the IC cards and the readers/writers. These data may be transmitted/received in the contactless manner between the IC cards and the IC card readers/writers.

In other words, in this sort of IC card system, an IC card reader/writer modulates a carrier wave having a preselected frequency by using a desired data stream so as to produce a transmission signal, and then transmits this produced transmission signal to the IC card.

The IC card receives this transmission signal via an antenna, and then demodulates this transmission signal to decode the data sent from the IC card reader/writer. Furthermore, the IC card modulates internally saved data, such as personal data, by using a preselected carrier wave in response to this received data, and then sends out the modulated data to the IC card reader/writer.

Then, the IC card reader/writer receives the data sent from this IC card. Based upon this received data, a door of a ticket inspection machine is opened/closed. Also, any person is allowed to enter into a room, and/or to come out from this room.

In such a conventional IC card system, these data are modulated by the ASK (Amplitude Shift Keying) modulating method, and then the ASK-modulated data is transmitted/received between the IC card and the card reader/writer. Conventionally, as such a modulating means for an ASK modulation signal, a modulating circuit with using a variable gain amplifying circuit, and a multiplying circuit is employed. Also, as such a demodulating means for the ASK modulation signal, a demodulating circuit with using an envelope detecting circuit constructed of a diode, and using a synchronization detecting circuit is employed.

FIG. 1

is a schematic block diagram for showing one conventional modulating circuit constructed of this variable gain amplifying circuit. In this modulating circuit

1

, the gain of the variable gain amplifying circuit

2

is switched in response to a logic level of a data stream D to be sent. Also, a carrier signal SC is amplified by this variable gain amplifying circuit

2

. As a result, this modulating circuit

1

modulates the amplitude of the carrier signal SC outputted from the variable gain amplifying circuit

2

in response to the logic level of the data stream D so as to produce an ASK modulation signal SM.

Also,

FIG. 2

is a schematic block diagram for indicating another conventional modulating circuit arranged by a balanced modulating circuit with employment of a multiplying circuit. In this modulating circuit

3

, the carrier signal SC is multiplied by the data stream D in the multiplying circuit

4

, and while the amplitude of this carrier signal SC is varied in response to the logic level of the data stream D, the ASK modulation signal SM is produced.

In contrast,

FIG. 3

is a schematic block diagram for showing one conventional demodulating circuit arranged by an envelope detecting circuit with employment of a diode. In this demodulating circuit

6

, the ASK modulation signal SM is rectified by employing the diode D. Furthermore, this rectified ASK modulation signal SM is entered into a smoothing circuit having a predetermined time constant defined by a resistor R and a capacitor C. As a result, the envelope-detected output of the ASK modulation signal is outputted as the demodulation signal SD.

FIG. 4

is a schematic block diagram for representing another conventional demodulating circuit arranged by a synchronization detecting circuit. In this demodulating circuit

8

, a carrier signal component SCC is extracted from the ASK modulation signal SM by employing a phase-synchronization system circuit

9

arranged by, for example, a filter circuit arrangement and a PLL circuit arrangement. Both this carrier signal component SCC is multiplied by the ASK modulation signal SM by a multiplying circuit

10

. In the demodulating circuit

8

, a baseband component is extracted from the multiplied result of this multiplying circuit

10

by a low-pass filter (LPF)

12

to thereby be outputted as the demodulation signal SD.

On the other hand, the following demands are made in these conventional IC card systems. That is, these modulating circuits and demodulating circuits can be simply and readily manufactured in the IC form in combination with other circuit blocks. Moreover, these modulating/demodulating circuits can be operated in high efficiencies.

Moreover, these modulating circuits and demodulating circuits with employment of the conventional circuit arrangements can hardly satisfy the necessary items for the IC card systems.

In further detail, in the modulating circuit arranged by the variable gain amplifying circuit, the voltage range which can be effectively utilized by the variable gain amplifying circuit is limited. This voltage range limitation causes the lower power efficiency of the conventional modulating circuit. Also, as to the modulating circuit with employment of the multiplying circuit, there are such drawbacks that the circuit arrangement becomes complex, and this complex modulating circuit cannot be simply and readily manufactured in the IC form.

For instance, also in the power amplifying circuit for the ASK modulation signal, which is similarly required to be manufactured in the IC form similar to such modulating circuits, the ASK modulation signal must be amplified while saving a change contained in the amplitudes of this ASK modulation signal. After all, this power amplifying circuit must be operated in the better linearity region. This causes a power efficiency to be lowered also in the power amplifying circuit. Also, this power amplifying circuit has a drawback in that in order to transmit sufficiently high power, the active elements capable of satisfying the necessary allowable current and the allowable loss must be used instead of commercially available general-purpose electronic components.

In contrast, the demodulating circuit arranged by the envelope detecting circuit with employment of the diode owns such a drawback that a leakage current is produced in the diode when this demodulating circuit is manufactured in the IC form, and therefore, the detection efficiency of the ASK modulation signal is considerably lowered. In other words, as shown in

FIG. 5

, when an envelope detecting circuit with employment of a diode is manufactured in the IC form, both polarities must be set to floating potentials at the diode D. As a result, a stray transistor is necessarily produced. Accordingly, as represented in

FIG. 6

, a leakage current is produced.

On the other hand, in the conventional demodulating circuit arranged by the synchronization detecting circuit, there is another drawback in that the circuit arrangement of the phase synchronization system circuit

9

becomes complex.

SUMMARY OF THE INVENTION

The present invention has been made to solve the above-explained drawbacks of the prior art, and therefore, has an object to provide a modulating circuit, a demodulating circuit, an amplifying circuit used in this modulating circuit, and furthermore, a transmitter apparatus as well as a receiver apparatus with employment of these modulating circuit and demodulating circuit, which can be simply and easily manufactured with an IC form in combination with other circuit blocks, and also which can be operated in high efficiencies.

Another object of the present invention is to provide the following modulating circuit, amplifying circuit applicable to this modulating circuit, and also a transmitter apparatus with using this modulating circuit. That is, first and second output signals having predetermined phases with respect to an input signal are added to each other, and the added result is outputted. At least, the second output signal is gated in response to the input data. Also, on the output side of a power amplifying circuit, the power-amplified results are attenuated in accordance with the input data so as to produce an amplitude-modulated signal. This circuit arrangement can be simply and readily manufactured in the IC form together with other circuit blocks.

Also, since amplitude-modulated signals are biased to be amplified, or clamped, a demodulating circuit and a receiver apparatus with using this demodulating circuit can be simply and easily manufactured in the IC form in combination with other circuit blocks.

Furthermore, amplitude-modulated signals are clamped, polarities of these amplitude-modulated signals are judged to multiply the polarity judgment result by the amplitude-modulated signals, and furthermore, the amplitude-modulated signals are selectively outputted based upon the polarity judgment results of the amplitude-modulated signals. As a result, another demodulating circuit and another receiver apparatus with using this demodulating circuit can be simply and readily manufactured in the IC form together with other circuit blocks.

To achieve the above-described objects, a modulating circuit, according to a first aspect of the present invention, includes:

first signal output means for outputting a first output signal having a predetermined phase with respect to that of an input signal;

a second signal output means for outputting a second output signal having a predetermined phase with respect to that of the input signal;

gate means for gating at least the second output signal;

calculation means for adding, or subtracting the first output signal and the second output signal; and

control means for controlling the operation of the gate means in response to a logic level of input data.

Also, a modulating circuit as recited in the first aspect, according to a second aspect, is configured so that:

the first signal output means outputs the first output signal having the same phase as that of the input signal; and

the second signal output means outputs the second output signal having the phase opposite to that of the input signal.

Another aspect of the above-described modulating circuit as recited in the first aspect, according to a third aspect, is configured so that:

the first signal output means power-amplifies the first output signal to output the power-amplified first output signal; and

the second signal output means power-amplifies the second output signal to output the power-amplified second output signal.

A modulating circuit as recited in the first aspect, according to a fourth aspect, includes features wherein:

the input signal is constituted by a sine wave signal having a single frequency.

A modulating circuit as recited in the first aspect, according to a fifth aspect, includes features wherein:

the input signal is constituted by a rectangular wave signal having a single frequency.

A modulating circuit as recited in the fifth aspect, according to a sixth aspect, includes features wherein:

the second signal output means outputs the second output signal having the phase opposite to that of the input signal by inverting the logic level of the input signal.

A modulating circuit as recited in the third aspect, according to a seventh aspect, includes features wherein:

the gate means controls to stop the power amplifying process operation by the second signal output means so as to gate the second output signal; and

the second signal output means maintains an impedance of an output terminal at a high impedance for a time period during which the power amplifying process operation is stopped.

A modulating circuit as recited in the third aspect, according to an eighth aspect, includes features wherein:

both the first output signal means and the second output signal means are arranged by a switching circuit for switching operations in response to the input signal.

A modulating circuit as recited in the third aspect, according to a ninth aspect, includes features wherein:

at least the second signal output means and the gate means are tri-state buffer circuits.

A modulating circuit as recited in the first aspect, according to a tenth aspect, includes features wherein:

the first signal output means outputs the first output signal from a first antenna;

the second signal output means outputs the second output signal from a second antenna; and

the calculation means is formed by way of an electromagnetic coupling between the first antenna and the second antenna.

Also, to achieve the above-described objects, an amplifying circuit, according to an eleventh aspect of the present invention, includes an amplifying circuit in which an operation of a field-effect transistor is switched in response to an input signal so as to output a power-amplified signal of the input signal from the field-effect transistor, comprising:

a drive circuit for switching the operation of the field-effect transistor by applying a voltage to a gate of the field-effect transistor, the voltage being higher than, or equal to a source-to-drain voltage of the field-effect transistor.

An amplifying circuit as recited in the eleventh aspect, according to a twelfth aspect, includes features wherein:

an output terminal is constituted in such a manner that the output terminal can be set to a high impedance.

Further, to achieve the above-explained objects, an amplifying circuit, according to a thirteenth aspect of the present invention, includes:

first variable resistor means, one end of which is held at a first potential, and the resistance value of which is varied in response to a first control signal;

second variable resistor means, one end of which is connected to the other end of the first variable resistor means, the other end of which is held at a second potential different from the first potential, and the resistance value of which is varied in response to a second control signal; and

control means for switching a signal level of the first control signal and a signal level of the second control signal so as to switch a potential at a connection center point between the first variable resistor means and the second variable resistor means to another potential corresponding to the first and second potentials, and also so as to switch an impedance of the connection center point to a high impedance in response to both an input signal and a control signal.

An amplifying circuit as recited in the thirteenth aspect according to a fourteenth aspect, includes features wherein:

the first variable resistor means and the second variable resistor means are field-effect transistors.

An amplifying circuit as recited in the fourteenth aspect according to a fifteenth aspect, includes features wherein:

the control means switches the signal level of the control signal and the signal level of the second control signal to a voltage higher than, or equal to a source-to-drain voltage of the field-effect transistor.

To achieve these objects, a transmitter apparatus, according to a sixteenth aspect of the present invention, includes a transmitter apparatus for amplitude-modulating input data by using a modulating circuit to thereby transmit the amplitude-modulated input data, wherein:

the modulating circuit is comprised of:

first signal output means for outputting a first output signal having a predetermined phase with respect to that of an input signal;

a second signal output means for outputting a second output signal having a predetermined phase with respect to that of the input signal;

gate means for gating at least the second output signal;

calculation means for adding, or subtracting the first output signal and the second output signal; and

control means for controlling the operation of the gate means in response to a logic level of input data.

A transmitter apparatus as recited in the sixteenth aspect, according to a seventeenth aspect, includes features wherein:

the first signal output means outputs the first output signal from a first antenna;

the second signal output means outputs the second output signal from a second antenna; and

the calculation means is formed by way of an electromagnetic coupling between the first antenna and the second antenna.

Also, to achieve the objects, a transmitter apparatus according to an eighteenth aspect of the present invention, includes a transmitter apparatus for amplitude-modulating input data to thereby transmit the amplitude-modulated input data, which:

a first modulating circuit for producing a first amplitude-modulated signal in response to the input data; and

a second modulating circuit for producing a second amplitude-modulated signal made of a carrier wave having a phase opposite to that of the first amplitude-modulated signal; wherein:

each of the first modulating circuit and the second modulating circuit is comprised of:

first signal output means for outputting a first output signal having a predetermined phase with respect to that of an input signal;

a second signal output means for outputting a second output signal having a predetermined phase with respect to that of the input signal;

gate means for gating at least the second output signal;

calculation means for adding, or subtracting the first output signal and the second output signal; and

control means for controlling the operation of the gate means in response to a logic level of input data.

To achieve these objects, a modulating circuit, according to a nineteenth aspect of the present invention, includes:

a variable attenuator provided at an output terminal of a power amplifying circuit, for attenuating a power-amplified result of the power amplifying circuit in response to an input signal.

A modulating circuit as recited in the nineteenth aspect, according to a twentieth aspect, includes features wherein:

the signal amplified by the power amplifying circuit is constituted by a sine wave signal having a single frequency.

A modulating circuit as recited in the nineteenth aspect, according to a twenty-first aspect, includes features wherein:

the signal amplified by the power amplifying circuit is constituted by a rectangular wave signal having a single frequency.

Further, to achieve the above objects, a transmitter apparatus, according to a twenty-second aspect of the present invention, is featured by such a transmitter apparatus comprising a modulating circuit by way of an amplitude modulation, wherein:

the modulating circuit is includes:

a variable attenuator provided at an output terminal of a power amplifying circuit, for attenuating a power-amplified result of the power amplifying circuit in response to an input signal.

Also, to achieve these objects, a transmitter apparatus, according to a twenty-third aspect of the present invention, is featured by such a transmitter apparatus for amplitude-modulating an input signal to thereby transmit the amplitude-modulated input signal, includes:

a first modulating circuit for producing a first amplitude-modulated signal in response to the input signal; and

a second modulating circuit for producing a second amplitude-modulated signal made of a carrier wave having a phase opposite to that of the first amplitude-modulated signal in response to the input signal; wherein:

each of the first modulating circuit and the second modulating circuit includes:

a variable attenuator provided at an output terminal of a power amplifying circuit, for attenuating a power-amplified result of the power amplifying circuit in response to an input signal.

Also, to achieve the objects, a demodulating circuit, according to a twenty-fourth aspect of the present invention includes:

amplifying means for amplifying an input signal;

bias means for biasing the input signal; and

band limiting means for removing a component of the input signal from the output signal derived from the amplifying means.

A demodulating circuit as recited in the twenty-fourth aspect, according to a twenty-fifth aspect, includes features wherein:

the amplifying means corresponds to any one of an amplifying circuit with employment of a transistor, another amplifying circuit with employment of a field-effect transistor, and a differential amplifier circuit.

A demodulating circuit as recited in the twenty-fourth aspect, according to a twenty-sixth aspect, is featured by that:

the band limiting means corresponds to any one of a low-pass filter, a band-pass filter, and a trap filter.

also, to achieve the objects, a receiver apparatus, according to a twenty-seventh aspect of the present invention, is featured by such a receiver apparatus for demodulating sequentially-entered amplitude-modulated signals by using a demodulating circuit, wherein:

the demodulating circuit is comprised of:

amplifying means for amplifying the amplitude-modulated signal;

bias means for biasing the amplitude-modulated signal; and

band limiting means for removing a component of the amplitude-modulating signal from the output signal derived from the amplifying means.

Also, to achieve these objects, a demodulating circuit, according to a twenty-eighth aspect of the present invention, is featured includes:

a limiter for limiting an amplitude of an input signal; and

band limiting means for removing a component of the input signal from the output signal derived from the limiter.

A demodulating circuit as recited in the twenty-eighth aspect, according to a twenty-ninth aspect, includes features wherein:

the limiter is constituted by a series circuit formed by connecting a diode in series to a constant voltage power source.

A demodulating circuit as recited in the twenty-eighth aspect, according to a thirtieth aspect, includes features wherein:

the band limiting means corresponds to any one of a low-pass filter, a band-pass filter, and a trap filter.

Also, to achieve the objects, a receiver apparatus, according to a thirty-first aspect of the present invention, includes features for demodulating sequentially-entered amplitude-modulated signals by using a demodulating circuit, wherein:

the demodulating circuit includes:

a limiter for limiting the amplitude of the amplitude-modulated signal; and

band limiting means for removing a component of the amplitude-modulated signal from the output signal of the limiter.

Further, a demodulating circuit, according to a thirty-second aspect of the present invention, includes:

clamping means for clamping an input signal; and

band limiting means for removing a component of the input signal from the output signal of the clamping means.

A demodulating circuit as recited in the thirty-second aspect, according to a thirty-third aspect, includes features wherein:

the clamping means is constituted by a grounded type diode.

A demodulating circuit as recited in the thirty-second aspect, according to a thirty-fourth aspect, includes features wherein:

the band limiting means corresponds to any one of a low-pass filter, a band-pass filter, and a trap filter.

Also, to achieve the objects, a receiver apparatus, according to a thirty-fifth aspect of the present invention, includes features for demodulating sequentially-entered amplitude-modulated signals by using a demodulating circuit, wherein:

the demodulating circuit includes:

clamping means for clamping the amplitude-modulated signal; and

band limiting means for removing a component of the amplitude-modulated signal from the output signal of the clamping means.

Also, to achieve the object, a demodulating circuit, according to a thirty-sixth aspect of the present invention, is featured by such a demodulating circuit comprising:

signal processing means for producing first and second input signals having phases different from a phase of an input signal by approximately 180 degrees;

first clamping circuit for clamping the first input signal;

second clamping circuit for clamping the second input signal;

first band limiting means for removing a component of the first input signal from the output signal of the first clamping circuit;

second band limiting means for removing a component of the second input signal from the output signal of the first clamping means; and

calculating means for adding, or averaging the output signal of the first band limiting means and the output signal of the second band limiting means.

A demodulating circuit as recited in the thirty-sixth aspect, according to a thirty-seventh aspect, includes features wherein:

the first and second clamping means are constituted by a grounded type diode.

A demodulating circuit as recited in the thirty-sixth aspect, according to a thirty-eighth aspect, is featured by that:

the band limiting means corresponds to any one of a low-pass filter, a band-pass filter, and a trap filter.

To achieve the objects, a receiver apparatus, according to a thirty-ninth aspect of the present invention, features a receiver apparatus for demodulating sequentially-entered amplitude-modulated signals by using a demodulating circuit, wherein:

the demodulating circuit includes:

signal processing means for producing first and second amplitude-modulated signals having phases different from a phase of the amplitude-modulated signal by approximately 180 degrees;

first clamping circuit for clamping the first amplitude-modulated signal;

second clamping circuit for clamping the second amplitude-modulated signal;

first band limiting means for removing a component of the first amplitude-modulated signal from the output signal of the first clamping circuit;

second band limiting means for removing a component of the second amplitude-modulated signal from the output signal of the first clamping means; and

calculating means for adding, or averaging the output signal of the first band limiting means and the output signal of the second band limiting means.

Further, to achieve the objects, a demodulating circuit, according to a fortieth aspect of the present invention, includes:

signal processing means for producing first and second input signals having phases different from a phase of an input signal by approximately 180 degrees;

first clamping circuit for clamping the first input signal; second clamping circuit for clamping the second input signal;

calculating means for adding, or averaging the output signal of the first band limiting means and the output signal of the second band limiting means; and

band limiting means for removing a component of the input signal from the output signal of the calculating means.

A demodulating circuit as recited in the fortieth aspect, according to a forty-first aspect, includes features wherein:

the first and second clamping means are constituted by a grounded type diode.

A demodulating circuit as recited in the fortieth aspect, according to a forty-second aspect, includes features wherein:

the band limiting means corresponds to any one of a low-pass filter, a band-pass filter, and a trap filter.

To achieve the objects, a receiver apparatus, according to a 43rd aspect of the present invention, includes features for demodulating sequentially entered amplitude-modulated signals by using a demodulating circuit, wherein:

the demodulating circuit includes:

signal processing means for producing first and second amplitude-modulated signals having phases different from a phase of the amplitude-modulated signal by approximately 180 degrees;

first clamping circuit for clamping the first amplitude-modulated signal;

second clamping circuit for clamping the second amplitude-modulated signal;

calculating means for adding, or averaging the output signal of the first band limiting means and the output signal of the second band limiting means; and

band limiting means for removing a component of the amplitude-modulated signal from the output signal of the calculating means.

To achieve the objects, a demodulating apparatus, according to a forty-fourth aspect of the present invention, a demodulating apparatus including:

polarity judging means for judging a polarity of an amplitude-modulated signal to thereby output a polarity judgment result;

multiplying means for multiplying the polarity judgment result by the amplitude-modulated signal to thereby output a multiplication result; and

band limiting means for removing a component of the amplitude-modulated signal from the multiplication result.

A demodulating circuit as recited in the forty-fourth aspect, according to a forty-fifth aspect, includes features wherein:

the polarity judging means is constituted by a limiter for limiting the amplitude of the amplitude-modulated signal on a positive side and on a negative side.

A demodulating circuit as recited in the forty-fourth aspect, according to a forty-sixth aspect, includes features wherein:

the multiplying means is constructed of a double balanced mixer.

A demodulating circuit as recited in the forty-fourth aspect, according to a forty-seventh aspect, is featured by that:

the band limiting means corresponds to any one of a low-pass filter, a band-pass filter, and a trap filter.

Furthermore, to achieve the objects, a receiver apparatus, according to a forty-eighth aspect of the present invention, is featured by such a receiver apparatus for demodulating sequentially-entered amplitude-modulated signals by using a demodulating circuit, wherein:

the demodulating circuit includes:

polarity judging means for judging a polarity of an amplitude-modulated signal to thereby output a polarity judgment result;

multiplying means for multiplying the polarity judgment result by the amplitude-modulated signal to thereby output a multiplication result; and

band limiting means for removing a component of the amplitude-modulated signal from the multiplication result.

Moreover, to achieve the objects, a demodulating circuit, according to a forty-ninth aspect of the present invention, includes:

signal producing means for producing first and second amplitude-modulated signals having phases inverted from each other from an amplitude-modulated signal;

polarity judging means for judging a polarity of one of the amplitude-modulated signal, the first amplitude-modulated signal, and the second amplitude-modulated signal to thereby output a polarity judgment result;

selecting/outputting means for selectively outputting the first amplitude-modulated signal and the second amplitude-modulated signal based upon the polarity judgment result; and

band limiting means for removing a component of the amplitude-modulated signal from the output signal of the selecting/outputting means.

A demodulating circuit as recited in the forty-ninth aspect, according to a fiftieth aspect, includes features wherein:

the band limiting means corresponds to any one of a low-pass filter, a band-pass filter, and a trap filter.

Also, to achieve the objects, a receiver apparatus, according to a fifty-first aspect of the present invention, includes a receiver apparatus for demodulating sequentially-entered amplitude-modulated signals by using a demodulating circuit, wherein:

the demodulating circuit is comprised of:

signal producing means for producing first and second amplitude-modulated signals having phases inverted from each other from an amplitude-modulated signal;

polarity judging means for judging a polarity of one of the amplitude-modulated signal, the first amplitude-modulated signal, and the second amplitude-modulated signal to thereby output a polarity judgment result;

selecting/outputting means for selectively outputting the first amplitude-modulated signal and the second amplitude-modulated signal based upon the polarity judgment result; and

band limiting means for removing a component of the amplitude-modulated signal from the output signal of the selecting/outputting means.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention, reference is made of a detailed description to be read in conjunction with the accompanying drawings, in which:

FIG. 1

is a schematic block diagram for showing a conventional modulating circuit with using a variable gain amplifying circuit;

FIG. 2

is a schematic block diagram for indicating another conventional modulating circuit with using a multiplying circuit;

FIG. 3

is a schematic block diagram for representing a conventional demodulating circuit with employment of a diode by way of an envelope detection;

FIG. 4

is a schematic block diagram for indicating another conventional demodulating circuit by way of a phase synchronization detection;

FIG. 5

schematically shows an integrated circuit arrangement of the conventional demodulating circuit shown in

FIG. 3

;

FIG. 6

is a connection diagram for schematically indicating an equivalent circuit of the integrated demodulating circuit shown in

FIG. 5

;

FIG. 7

is a schematic block diagram for representing an overall arrangement of an IC card system according to a first embodiment of the present invention;

FIG. 8

is a schematic block diagram for showing a modulating/demodulating circuit of the IC card system according to the first embodiment;

FIG. 9

is a schematic block diagram for indicating a basic structure of a modulating circuit applied to an IC card reader/writer according to a first embodiment of the present invention;

FIG. 10

is a table for explaining operation of the modulating circuit shown in

FIG. 9.

;

FIGS.

11

(A)-

11

(D) are time charts for describing the operation of the modulating circuit indicated in

FIG. 9

;

FIG. 12

is a schematic block diagram for indicating a concrete circuit arrangement of the modulating circuit shown in

FIG. 9

;

FIG. 13

is a connection diagram for representing a power amplifying circuit shown in

FIG. 12

;

FIG. 14

is a table for explaining operation of a control logic of the power amplifying circuit shown in

FIG. 12

;

FIG. 15

is a schematic block diagram for representing a modulating circuit applied to an IC card reader/writer, according to a second embodiment of the present invention;

FIG. 16

is a schematic block diagram for representing a basic structure of a modulating circuit applied to an IC card reader/writer, according to a third embodiment of the present invention;

FIG. 17

is a connection diagram for explaining a variable attenuator shown in

FIG. 16

;

FIG. 18

is a connection diagram for explaining a grounded type variable attenuator as to the variable attenuator of

FIG. 16

;

FIG. 19

is a connection diagram for explaining a combined structure between the arrangement shown in FIG.

17

and the arrangement shown in

FIG. 18

as to the variable attenuator of

FIG. 16

;

FIG. 20

is a schematic block diagram for showing a concrete circuit arrangement of the modulating circuit shown in

FIG. 16

;

FIG. 21

is a schematic block diagram for indicating a modulating circuit applied to an IC card reader/writer, according to a fourth embodiment of the present invention;

FIG. 22

is a schematic block diagram for showing a basic structure of a demodulating circuit applied to an IC card reader/writer, according to a fifth embodiment of the present invention;

FIG. 23

is a characteristic curve diagram for explaining a bias of a modulation signal used in

FIG. 22

;

FIG. 24

is a schematic block diagram for showing a circuit arrangement constituted by replacing the bias of the demodulating circuit shown in

FIG. 22

by a limiter;

FIG. 25

is a characteristic curve diagram for explaining an amplitude limiter in the circuit arrangement of

FIG. 24

;

FIG. 26

is a schematic block diagram for representing a concrete arrangement of the demodulating circuit shown in

FIG. 22

;

FIG. 27

is a schematic block diagram for indicating a modulating circuit applied to an IC card reader/writer, according to a sixth embodiment of the present invention;

FIG. 28

is a schematic block diagram for showing a demodulating circuit applied to an IC card reader/writer, according to a seventh embodiment of the present invention;

FIG. 29

is a schematic block diagram for showing a basic structure of a demodulating circuit applied to an IC card reader/writer, according to an eighth embodiment of the present invention;

FIG. 30

is a schematic block diagram for representing a concrete arrangement of the demodulating circuit shown in

FIG. 29

;

FIG. 31

is a schematic block diagram for showing a demodulating circuit applied to an IC card reader/writer, according to a ninth embodiment of the present invention;

FIG. 32

is a schematic block diagram for representing a concrete arrangement of the demodulating circuit shown in

FIG. 31

;

FIG. 33

is a schematic block diagram for showing a demodulating circuit applied to an IC card reader/writer, according to a tenth embodiment of the present invention;

FIG. 34

is a schematic block diagram for showing a basic structure of a demodulating circuit applied to an IC card reader/writer, according to an eleventh embodiment of the present invention;

FIG. 35

is a schematic block diagram for representing a concrete arrangement of the demodulating circuit shown in

FIG. 34

;

FIG. 36

is a schematic block diagram for showing a basic arrangement of a demodulating circuit applied to an IC card reader/writer, according to a twelfth embodiment of the present invention;

FIG. 37

is a schematic block diagram for indicating a concrete arrangement of the demodulating circuit shown in

FIG. 36

; and

FIG. 38

is a connection diagram for representing a switch circuit of FIG.

37

.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to drawings, various preferred embodiments of the present invention will be described.

Circuit Arrangement of First Embodiment

FIG. 7

is a schematic block diagram for showing an IC (Integrated Circuit) card system

21

according to a first embodiment of the present invention. This first IC card system

21

is applied to, for example, a ticket inspection system of transportation facilities. In this IC card system

21

, data is communicated between an IC card

22

and an IC card reader/writer

23

.

In this case, the IC card

22

is formed in a card shape in such a manner that a (circuit) board on which an integrated circuit is mounted is stacked with a protection sheet. In this IC card

22

, a loop antenna

24

is formed by a wiring pattern formed on this board. Also, a modulating/demodulating circuit

25

and a signal processing circuit

26

are constituted by the integrated circuit mounted on this board.

In this embodiment, the loop antenna

24

is coupled to another loop antenna

28

of the IC card reader/writer

23

so as to receive a transmission signal transmitted from this loop antenna

28

, and also to radiate a response (acknowledge) signal produced by the modulating/demodulating circuit

25

.

The modulating/demodulating circuit

25

produces electric power, a clock signal, and the like, which are required for the operations of this IC card

22

by using the transmit signal received by the loop antenna

24

. Furthermore, the modulating/demodulating circuit

25

is operated by using this electric power and the clock signal to demodulate a data stream “D(R C)” transmitted from the reader/writer

23

(will be referred to as a “transmit data stream” hereinafter), and then outputs the demodulated data stream to the signal processing circuit

26

. In response to another data stream “D(C R)” entered from the signal processing circuit

26

and requested by the transmit data stream “D(R C)”, this modulating/demodulating circuit

25

produces a response signal based upon an ASK modulation signal. In response of this response signal, the modulating/demodulating circuit

25

drives the loop antenna

24

so as to radiate a response signal. This response data stream will be referred to as a “response data stream D(C R)” hereinafter.

The signal processing circuit

26

is operated by the electric power and the clock generated from the modulating/demodulating circuit

25

so as to analyze the transmit data stream D(R C), and to output the response data stream D(C R) saved in a nonvolatile memory build in this IC card to the modulating/demodulating circuit

25

, if required.

In the reader/writer

23

, the modulating/demodulating circuit

29

produces a transmit signal by the ASK modulation signal based upon a transmit data stream D(R C) entered from an SPU (signal process unit)

30

, and drives the loop antenna

28

by this transmit signal. Also, the modulating/demodulating circuit

29

performs a signal process operation of the response signal received by this loop antenna

28

so as to demodulate the response data stream “D(C R)” transmitted from the IC card

22

, and then outputs this demodulated response data stream D(C R) to the SPU

30

.

The SPU

30

is arranged by a calculation processing unit for executing a relatively simple process sequence. This SPU

30

sends out the transmit data stream “D(R C)” to the modulating/demodulating circuit

29

, and also processes the response data stream “D(C R)” entered from this modulating/demodulating circuit

29

. This transmit data stream D(R C) is to be transmitted to the IC card

22

. In this process operation, the SPU

30

causes a display unit

31

to display thereon a process history and a process result, if required. In response to a command supplied from an input unit

32

, the operations of the SPU

30

are switched so as to input/output data about the process sequence in/from an external apparatus

33

or the like, if necessary.

FIG. 8

is a schematic block diagram for partially indicating a circuit structure of the modulating/demodulating circuit

29

employed in the reader/writer

23

. As shown in this drawing, the modulating/demodulating circuit

29

is arranged by a transmission-sided block

45

and a reception-sided block

46

.

In this embodiment, the transmission-sided block

45

modulates the transmit data stream “(D(R C)” outputted from the SPU

30

in response to a control signal “RFoff” outputted from the SPU

30

to thereby send out the modulated transmit data stream D(R C) from the loop antenna

28

. As a result, the transmission-sided block

45

produces a carrier signal SC having a frequency of 13.56 [MHz] by operating an oscillator circuit built in this transmission-sided block

45

. Also, this transmission-sided block

45

decodes the transmit data stream “D(C R)” so as to be converted into a transmit data stream by the Manchester code.

In an ASK modulating circuit

47

of the transmission-sided block

45

, the carrier signal SC is ASK-modulated by using the transmit data stream “TX(D(R C)) “which is coded in this manner to thereby produce an ASK modulation signal “ISM”. Furthermore, this ASK modulation signal “SM” is amplified by a power amplifying circuit

48

to thereby drive the loop antenna

28

by this amplified ASK modulation signal “SM”.

The reception-sided block

46

processes the response signal SM obtained via the loop antenna

28

so as to demodulate the response data stream “D(C R)”. In other words, the reception-sided block

46

detects the response signal SM obtained via the loop antenna

28

so as to produce a detecting signal “SD” in the ASK (Amplitude Shift Keying) detecting circuit

49

. The signal level of this detection signal SD is changed in response to the logic level of the response data stream “D(C R)”. The reception-sided block

46

limits the pass band of this detection signal SD by a low-pass filter (LPF)

50

subsequent to the ASK detecting circuit

49

, and thereafter, amplifies the filtered detection signal by a predetermined gain using an amplifying circuit

51

and furthermore, digitalizes the amplified detection signal. Furthermore, the reception-sided block

46

decodes this binary-coded data, and thus, reproduces and outputs the response data stream “D(C R)” based on this binary-coded data.

Basic Circuit Arrangement of Transmitting Circuit

FIG. 9

is a schematic block diagram for showing a basic circuit arrangement of the above-described ASK modulating circuit

47

and power amplifying circuit

48

(will be referred to as a “transmitting circuit”

55

hereinafter). This transmitting circuit

55

contains two signal paths (systems) of processing circuits

55

A and

55

B, which each have a power amplifying circuit.

In this case, the first processing unit

55

A receives the carrier signal SC via a buffer amplifying circuit

56

, and then enters the output signal of the buffer amplifying circuit

56

into a second selection input terminal of a selecting circuit

57

. This output signal from the buffer amplifying circuit

56

has the same phase as that of the carrier signal SC. In this case, this selecting circuit

57

enters a signal having a phase opposite to that of the carrier signal SC into a first selection input terminal, and grounds the remaining third selection input terminal. This signal having the opposite phase is derived from the second processing circuit

55

B. The selecting circuit

57

switches contacts under control of a control circuit

58

, and a power amplifying circuit

59

provided subsequent to this selecting circuit

57

amplifies the output signal derived from the selecting circuit

57

.

As a result, the first processing circuit

55

A is arranged in such a manner that the selecting circuit

57

switches the first contact and the second contact, so that the signal having the phase opposite to that of the carrier signal SC can be gated. Similarly, this first processing circuit

55

A is so arranged that the selecting circuit

57

switches the second contact and the third contact, so that the signal having the same phase as that of the carrier signal SC can be gated.

In contrast, the second processing circuit

55

B enters the carrier signal SC into a buffer amplifying circuit

60

having the same amplification factor as that of the buffer amplifying circuit

56

, which is arranged by an inverting amplifying circuit. As a result, the second processing circuit

55

B produces a signal having a phase opposite to that of the buffer amplifying circuit

60

, and inputs this signal having the opposite phase into a first selecting input terminal of a selecting circuit

61

. In this case, this selecting circuit

61

enters a signal having a phase opposite to that of the carrier signal SC into a second selection input terminal, and grounds the remaining third selection input terminal. This signal having the opposite phase is derived from the first processing circuit

55

A. The selecting circuit

61

switches contacts under control of the control circuit

58

, and a power amplifying circuit

62

provided subsequent to this selecting circuit

61

amplifies the output signal derived from the selecting circuit

61

.

As a result, the second processing circuit

55

B is similarly arranged in such a manner that the selecting circuit

61

switches the first contact and the third contact, so that the signal having the phase opposite to that of the carrier signal SC can be gated. Similarly, this second processing circuit

55

B is so arranged that the selecting circuit

61

switches the second contact and the third contact, so that the signal having the same phase as that of the carrier signal SC can be gated.

The transmitting circuit

55

outputs the output-signals derived from the first and second processing circuits

55

A and

55

B by connecting these processing circuits to the antenna by way of a wiring line. As a result, as indicated in

FIG. 10

, the transmitting circuit

55

is arranged as follows. Assuming now that the power outputs of the power amplifying circuits

59

and

62

are set to “P1” and “P2”, when the contacts of either the selecting circuit

61

or the selecting circuit

57

are switched under such a condition that the contacts of either the selecting circuit

57

or the selecting circuit

61

are positioned on the ground side (namely, condition indicated by “OFF” in FIG.

10

), transmit outputs by the power outputs P

1

and P

2

can be obtained by the in-phase and the reverse phase.

Also, the transmitting circuit is so arranged as follows. When the remaining contacts of either the selecting circuit

61

or the selecting circuit

57

are switched to thereby gate the input signal of either the power amplifying circuit

62

or the power amplifying circuit

59

under such a condition that the contacts of either the selecting circuit

57

or the selecting circuit

61

are set to either the in-phase side or the opposite side, the power amplified results of the power amplifying circuits

59

and

62

are added to each other. Therefore, the transmit outputs outputted from the antenna can be switched. Accordingly, the transmitting circuit

55

can obtain the power-amplified ASK modulation signals SM from the output-terminals of the power amplifying circuits

59

and

62

.

The control circuit

58

switches the contacts of the selecting circuits

57

and

61

in response to the transmit data stream TX, so that the ASK modulation signal SM is produced from this transmit data stream TX. In other words, as shown in

FIG. 11

, under such a condition that the power output from the buffer amplifying circuit

56

is continuously selected on the side of the selecting circuit

61

(see FIG.

11

(C)), the control circuit

58

switches the contacts of the selecting circuit

57

in response to the logic level of the transmit data stream TX so as to gate the input signal (see FIG.

11

(A) and FIG.

11

(B)). As a result, the power-amplified ASK modulation signal SM is produced (see FIG.

11

(D)). It should be noted that although

FIG. 11

represents such a case that the contacts of the selecting circuit

57

are switched between the output of the buffer amplifying circuit

56

and the ground, the ASK modulation signal may be similarly produced by switching-the contacts between other combinations. Also, even when the selecting operations of the selecting circuits

57

and

61

are switched, or even when the contacts of the selecting circuits

57

and

61

are switched at the same time, the ASK modulation signal may be similarly produced.

Concrete Circuit Arrangements of Ask Modulating Circuit/Power Amplifying Circuit

FIG. 12

is a schematic block diagram for showing concrete circuit arrangements of the ASK modulating circuit

47

and the power amplifying circuit

48

according to the first embodiment. This transmitting circuit

65

contains two signal paths of a transmitting circuit

65

A and another transmitting circuit

65

B, which may drive both terminals of the loop antenna

28

. The above-described two signal paths of processing circuits

55

A and

55

B are equivalently arranged in the respective transmitting circuits

65

A and

65

B.

That is, the transmitting circuit

65

A enters thereinto the carried signal SC having the in-phase via the buffer amplifying circuit

66

, and then this carrier signal SC is entered into a power amplifying circuit

67

and another power amplifying circuit

68

. In this case, as represented in

FIG. 13

, the power amplifying circuit

67

, or

68

is constituted by a P-channel MOS field-effect transistor T

1

, an N-channel MOS field-effect transistor T

2

, and a control logic

70

.

Among these circuit elements, the P-channel MOS field-effect transistor T

1

is series-connected to the N-channel MOS field-effect transistor T

2

, and this series-connected transistors are arranged between the power supply and the ground, and also constitute a switching circuit for switching a potential at an output terminal arranged by a joint point in response to a gate voltage set by the control logic

70

.

As indicated in a truth table of

FIG. 14

, when a control terminal input “OEI” of the control logic

70

is set to as H (high) level, this control logic

70

sets the gate terminals of the respective field-effect transistors T

1

and T

2

to an H level and an L(low) level. In this case, the control logic

70

sets the logic levels of the gate terminals by varying the voltages at the gate terminals, higher than the drain-to-source voltage of each of the field-effect transistors T

1

and T

2

. As a consequence, the control logic

70

stops the power amplifying process operation, and further holds the output terminal at the high impedance.

Also, when the control logic

70

sets the control terminal input OEI to an L level, this control logic

70

switches the gate terminals of the field-effect transistors T

1

and T

2

in response to a logic level appearing at the input terminal “in” thereof. As a result, the control logic

70

controls to stop the processing operation of the power amplification in response to the logic level of the input terminal “in”, so that the output signal of the power amplifying circuit can be gated in response to the logic level of the input terminal “in”.

The power amplifying circuit

67

can stop the power amplifying process operation by switching a control signal “RFoff”, if required, while this control signal RFoff is entered to the control terminal input OEI of this control logic

70

. Since the power amplifying process operation can be stopped, the resultant power consumption can be reduced.

While the logical OR output of the control signal “RFoff” obtained via an OR gate

75

and the transmit data stream TX are entered into the control terminal input OEI of the control logic

70

, the power amplifying circuit

68

can stop the power amplifying operation in conjunction with the above-described power amplifying circuit

67

. Also, while the power amplifying circuit

67

executes the power amplifying process operation, the power amplifying circuit

68

stops the power amplifying process operation in response to the logic level of the transmit data stream TX, and also gates the power amplified output having the same phase as that of the power amplified output by the power amplifying circuit

67

. In the case that the power amplifying process operation is stopped in response to the logic level of this transmit data stream TX, since the output terminals of the field-effect transistors T

1

and T

2

are maintained as high impedances, these field-effect transistors T

1

and T

2

do not give the load to the power amplifying circuit

67

.

As a consequence, both the power amplifying circuits

67

and

68

may each constitute a tri-state buffer circuit.

The first transmitting circuit

65

A supplies the power amplified output of the power amplifying circuit

68

to one terminal of the loop antenna

28

, and also supplies via a resistor

69

, the power amplified output of the power amplifying circuit

67

to one terminal of this loop antenna

28

. As a result, the transmitting circuit

65

A adds the power amplified output of the power amplifying circuit

67

to the power amplified output of the power amplifying circuit

68

via this resistor

69

so as to produce an ASK modulation signal SMA. It should also be noted in the transmitting circuit

65

A that a monitor terminal TMA is arranged at the output terminal of the power amplifying circuit

67

.

In contrast to the above arrangement, the second transmitting circuit

65

B is constituted in the same manner to that of the first transmitting circuit

65

A except that a buffer amplifying circuit

71

constructed of an inverting amplifier circuit arrangement is arranged instead of the buffer amplifying circuit

66

employed in the first transmitting circuit

65

A, and furthermore, except that the power-amplified output is supplied to the other terminal of the loop antenna

28

. As a result, the second transmitting circuit

65

B produces another ASK modulation signal “SMB” whose phase is inverted in conjunction with the first transmitting circuit

65

A. This second transmitting circuit

65

B drives the loop antenna

28

by using this ASK modulation signal SMB.

Operations of First Embodiment

With employment of the above-described circuit arrangements, in the IC card system

21

(see FIG.

7

and FIG.

8

), the transmit data stream “D(R C)” which is sent from the IC card reader/writer

23

to the IC card

22

is ASK-modulated by the modulating/demodulating circuit

29

, and then, the ASK-modulated transmit data stream is transmitted via the loop antenna

28

.

As a result, when the IC card

22

is approached to the reader/writer

23

, the transmission signal SM is induced by this ASK modulation signal in the loop antenna

24

of this IC card

22

. A portion of this induced transmission signal SM is converted into electric power used in the IC card

22

. This converted electric power may drive the modulating/demodulating circuit

25

and the signal processing circuit

26

of the IC card

22

.

Furthermore, as to the transmission signal SM obtained from this loop antenna

24

, the transmit data stream “D(R C)” is demodulated by the modulating/demodulating circuit

25

, and this transmit data stream “D(R C)” is analyzed by the signal processing circuit

26

so as to produce the response data stream “D(C R)” which is transmitted to the reader/writer

23

. In the IC card

22

, this response data stream “D(C R)” is ASK-modulated by the modulating/demodulating circuit

25

, and as a result, this resulting ASK modulation signal SM is transmitted as a response signal from the loop antenna

24

.

As a consequence, the response data stream “D(C R)” is transmitted from the IC card

22

to the reader/writer

23

. The response signal SM which has been transmitted in this manner is received by the reader/writer

23

by way of the loop antenna

28

which is coupled to the loop antenna

24

. Then, the response data stream “D(C R)” is demodulated by the modulating/demodulating circuit

29

.

The transmit data stream “D(R C)” which are transmitted/received in this manner is ASK-modulated by the ASK modulating circuit

47

, and thereafter, the ASK-modulated transmit data stream is power-amplified by the power amplifying circuit

48

. Then, the amplified data stream is transmitted via the loop antenna

28

.

In accordance with this first embodiment, when the transmit data stream “D(R C)” is ASK-modulated by this ASK modulating circuit

47

and then, the ASK-modulated transmit data stream is power-amplified by the power amplifying circuit

48

(see FIG.

9

), with respect to the power-amplified output of the power amplifying circuit

59

for power-amplifying the carrier signal SC by a predetermined phase, the power-amplified output of the power amplifying circuit

62

for similarly power-amplifying the carrier signal SC by a preselected phase is gated to be added in response to the logic level of the transmit data stream “D(R C)”. As a consequence, the power-amplified ASK modulation signal is produced.

Accordingly, the respective power amplifying circuits

59

and

62

can be designed by mainly considering the power efficiency without considering the linearity thereof to some extent. Therefore, the power efficiencies of these power amplifying circuit

59

and

62

can be increased, as compared with those of the conventional power amplifying circuits. Also, these power amplifying circuits

59

and

62

may be constituted by employing the commercially available electronic components.

To the contrary, as to the ASK modulation, the output signals are merely gated in the power amplifying circuits

59

and

62

, so that the ASK modulation signal can be produced. Therefore, the output signals can be ASK-modulated by a simple circuit arrangement suitably manufactured as an integrated circuit. Also, the power efficiency can be increased.

Concretely speaking, with respect to both the power amplifying circuit

67

and the power amplifying circuit

68

, which are arranged by the tri-state buffer circuits, and amplify the carrier signal SC by the same phase (see FIG.

12

), in one power amplifying circuit

67

, when the transmit data stream “D(R C)” is sent out, the carrier signal SC is continuously power-amplified. In contrast thereto, in the other power amplifying circuit

68

, since the carrier signal SC is power-amplified in response to the logic level of the transmit data stream “D(R C)”, this power-amplified result is gated based on the logic level of the transmit data stream “D(R C)”, and then these power-amplified results of the power amplifier circuits

67

and

68

are added to each other via the resistor

69

, so that the loop antenna

28

is driven by this added signal. As a result, in both the terminals of the loop antenna

28

, the amplitude of the power-amplified carrier signal SC is varied in response to the logic level of the transmit data stream “D(R C)”, so that the loop antenna

28

is driven by both the ASK modulation signals SMA and SMB.

Accordingly, the respective power amplifying circuits

67

and

68

can be designed by mainly considering the power efficiency without considering the linearity thereof to some extent. Therefore, the power efficiencies of these power amplifying circuits

67

and

68

can be increased, as compared with those of the conventional power amplifying circuits. Also, these power amplifying circuits

67

and

68

may be constituted by employing the commercially available electronic components.

Also, as to the ASK modulation, the power amplifying process operation executed by the power amplifying circuit

68

is simply and intermittently controlled to be stopped and the output signal is merely gated, so that the ASK modulation signal can be produced. As a result, the ASK modulation can be carried out by using a simplified circuit arrangement suitable for manufacturing this circuit arrangement as the IC. Also, the power efficiency can be increased.

As previously explained, the power amplifying circuits

67

and

68

for power-amplifying the carrier signal are constituted by series-connecting the P-channel field-effect transistor T

1

to the N-channel field-effect transistor T

2

(see FIG.

13

). The power amplifying process operation may be stop-controlled by such a manner that while the gate voltages of these P-channel/N-channel field-effect transistors T

1

/T

2

are varied higher than, or equal to the source-to-drain voltage, these gate voltages are kept in the H level and the L level, respectively.

As a consequence, when the transmit data stream “D(R C)” is transmitted, in contrast to the power amplifier circuit

67

for continuously power-amplifying the carrier signal SC, in such a power amplifying circuit

68

for intermittently power-amplifying the carrier signal in response to the logic level of the transmit data stream “D(R C)”, the output terminal thereof is maintained under high impedance state within a time period during which the power amplifying process operation is stopped. The power-amplified output of the power amplifying circuit

67

is not consumed by the power amplifying circuit

68

whose amplifying operation is stopped. As a result, this control operation can increase the power efficiency. Also, since substantially no source currents of these field-effect transistors T

1

and T

2