Delay lock loop circuit专利检索- 使用无线电波的反射或再辐射的系统侧如雷达系统;利用波的性质或波长是无关的或未指明的波的反射或再辐射的类似系统专利检索查询-专利查询网

Delay lock loop circuit
申请号	JP1685578	申请日	1978-02-15	公开(公告)号	JPS54109392A	公开(公告)日	1979-08-27
申请人	Mitsubishi Electric Corp;			发明人	UCHIDA YOSHINORI; OKANO HIROSHI; ITOU HISAAKI;
摘要	PURPOSE:To reduce the error in the full temperature range with no adjustment, by adding the output of analog switch alternately selected with the modulated waves via the operation circuit. CONSTITUTION:Two analog switches 13 and 14 having two linear operators 11, 12 taking the output of the synchronous detector as common input signal a and constituted with MOSFET etc., select either one of the output of the circuits 11 and 12 with the control signals c, d of the PN generator 6, and the output of the switches 13 and 14 is added and fed to the loop filter 4 as the output signal a via the amplifying circuit 17. Thus, the switches 13, 14 pass the modulated wave as it is when they select the output of the circuit 12 and select the modulated signal for the phase by 180 deg. in selecting the output of the circuit 12. Accordingly, stable operation can be obtained and operation is made easier.
权利要求
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