Pll circuit |
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申请号 | JP969277 | 申请日 | 1977-02-02 | 公开(公告)号 | JPS5395675A | 公开(公告)日 | 1978-08-22 |
申请人 | Hitachi Ltd; | 发明人 | ENDOU AKIRA; | ||||
摘要 | PURPOSE:To make the output frequency of a phase locked loop PLL linear with respect to time with a simple constitution by inserting a constant current circuit whose earth potential is elevated and minemum voltage is low to a filter part. | ||||||
权利要求 | |||||||
说明书全文 |