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序号	专利名	申请号	申请日	公开（公告）号	公开（公告）日	发明人
1	用于处理数字数据的数字处理器和方法	CN200480043969.1	2004-07-12	CN101091157B	2010-09-01	哈利尔·基利克
本发明描述了一种新型计算机体系结构。数字处理器包括处理单元，所述处理单元包括用于把N-位数据字的第一部分解码成仅具有一位高度的数字代码。这些位在算术模块中被处理，所述算术模块接收来自两个处理单元的输出、以及由指令电路所生成的触发信号。该指令电路通过读取N-位数据字的第二部分而接收关于要处理的数据的经验。该第二部分可以被分成几个所谓的DNA组。所述DNA组包含有关要处理的数据的符号/值的类型的消息。利用关于数据的该经验，可以执行非常快速且简单的并行处理。
2	用于处理数字数据的数字处理器和方法	CN200480043969.1	2004-07-12	CN101091157A	2007-12-19	哈利尔·基利克
本发明描述了一种新型计算机体系结构。数字处理器包括处理单元，所述处理单元包括用于把N－位数据字的第一部分解码成仅具有一位高度的数字代码。这些位在算术模块中被处理，所述算术模块接收来自两个处理单元的输出、以及由指令电路所生成的触发信号。该指令电路通过读取N－位数据字的第二部分而接收关于要处理的数据的经验。该第二部分可以被分成几个所谓的DNA组。所述DNA组包含有关要处理的数据的符号/值的类型的消息。利用关于数据的该经验，可以执行非常快速且简单的并行处理。
3	Number storage apparatus and method	US66576257	1957-06-14	US3084859A	1963-04-09	SMITH OTTO J M

4	Subtraction circuits utilizing electrical delay lines	US76137058	1958-09-16	US2920822A	1960-01-12	GALLICHOTTE JOHN H

5	Electrical calculating machines	US25262251	1951-10-23	US2787416A	1957-04-02	SIEGFRIED HANSEN

6	METHOD FOR COMPUTERIZED ARITHMETIC OPERATIONS	US12177234	2008-07-22	US20100023569A1	2010-01-28	James Shihfu Shiao; Albert Shihyung Shiao
A method of computing arithmetic operations more efficiently than the conventional Arithmetic Logic Unit (ALU) is disclosed. By encoding both operands from Binary Coded Decimal (BCD) codes (0000, to 1001) into decimal digits (0 to 9), inputting them in the GerTh's™ look-up tables, which are made of an array of AND gates, the invention finds the answer more efficiently. This method finds the result in fewer steps than a traditional ALU by reducing the repetitive calculation steps and logic gates required. And this new method makes the unsolvable computerized binary floating-point multiplications and divisions back to the solvable GerTh's computerized decimal digits' (0-9) elementary arithmetic operations.
7	Decimal matrix adder utilizing gas discharge tubes	US3510638D	1967-02-09	US3510638A	1970-05-05	POND RICHARD F

8	Addition circuits utilizing electrical delay lines	US75807858	1958-08-29	US2920821A	1960-01-12	GALLICHOTTE JOHN H

9	JPS5222503B1 -	JP10073473	1973-09-06	JPS5222503B1	1977-06-17

10	DIGITAL PROCESSOR AND METHOD OF PROCESSING DIGITAL DATA	EP04748730.1	2004-07-12	EP1831782A2	2007-09-12	Kilic, Halil
The present invention describes a new computer architecture. A digital processor comprises processing units which comprise decoders for decoding a first part of the N- bit data word into digital code with only one bit high. These bits are processed in arithmetic modules, which receive outputs from two processing units, and an activation signal produced by an instruction circuit. The instruction circuit receives knowledge on the data to be processed by reading the second part of the N-bit data words. This second part may be divided into several so-called DNA groups. The DNA group contain information on the type of symbols/values of the data to be processed. Using this knowledge on the data, very fast and simple parallel processing can be executed.
11	Digital multidenominational scale modifying means	US3600564D	1968-03-11	US3600564A	1971-08-17	EVANS DAVID SILVESTER
The present invention relates to apparatus for modifying the reading of a multidenominational scale of a digital measuring system and in a practical embodiment this is achieved by classifying the figures of each denomination of the scale and of the figures by which they can be shifted into groups such that, in respect to some shifts, the result must necessarily give rise to a carry to the next higher denomination than the one in which the shift has been made, and in respect of other shifts, the result must necessarily fail to give rise to a carry to said next higher denomination, whereby only a number of shifts, considerably less than the total number possible, remain in respect of which the need exists to determine whether the radix of the denomination in question has been exceeded by the shift effected.
12	Decimal data-handling equipment	US3594561D	1968-11-04	US3594561A	1971-07-20	WHITWELL ARTHUR L
An arrangement for adding together two n-digit decimal numbers or subtracting one n-digit decimal number from another comprises 10-condition switch means, the 10 conditions corresponding respectively to digits in the range 0 to 9 to be added or subtracted, and means to determine the need for and to implement the necessary carries.
13	Transistor matrix	US3587052D	1968-10-28	US3587052A	1971-06-22	METCALF MICHAEL H
In a matrix of transistors, base and emitter elements are interconnected in first and second groups wherein each transistor is identified by a unique combination of input connections with respect to the first and second groups. Transistors, the combined input values of which add to the same sum, have common collector output means for providing an adding function. In an integrated circuit construction, the common collector output means comprise adjoining isolation regions, wherein several transistors may be disposed along each isolation region. Means interconnecting transistor emitters in first groups comprise conductors connecting the emitters of no more than one transistor in each isolation region. Dual base terminals permit conductors, which comprise the means to interconnect the transistor base terminals in second groups, to extend in between first group conductors, and from a transistor in one isolation region to a transistor in another isolation region, avoiding crossunders and the like.
14	Desk calculator for performing addition,subtraction,multiplication and division	US3513303D	1965-03-22	US3513303A	1970-05-19	KITZ NORBERT; LLOYD JOHN G; DRAGE JAMES J

15	Delay line arithmetic circuit	US39310964	1964-08-31	US3358128A	1967-12-12	OLIVER GLENN A

16	Parallel adder with fast carry network	US13202761	1961-08-17	US3192369A	1965-06-29	FRANCIS SCHMITT WILLIAM

17	Recirculating adder	US14239861	1961-10-02	US3155822A	1964-11-03	CHIANG FRANKLIN C

18	Serial delay line adder	US73704358	1958-05-22	US3070305A	1962-12-25	CHIANG FRANKLIN C

19	Addition and subtraction circuit utilizing electrical delay lines having a short-circuit termination	US76525358	1958-10-03	US2920823A	1960-01-12	GALLICHOTTE JOHN H

20	Variable frequency relaxation oscillator	US49143943	1943-06-19	US2453203A	1948-11-09	DICKINSON ARTHUR H

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