专利检索_ ..使用excess-3码即自然BCD+3的偏移在4位数16种可能的系列中呈现对称代码专利检索_ ..使用excess-3码即自然BCD+3的偏移在4位数16种可能的系列中呈现对称代码专利检索查询_ ..使用excess-3码即自然BCD+3的偏移在4位数16种可能的系列中呈现对称代码专利检索查询分析平台

序号	专利名	申请号	申请日	公开（公告）号	公开（公告）日	发明人
1	Adding system for binary coded excess three numbers	US22443162	1962-09-18	US3271566A	1966-09-06	GUNTER MARTENS

2	Data processing system	US11267761	1961-05-25	US3234520A	1966-02-08	RAKOCZI LASZLO L; FUH-LIN WANG
931,133. Electronic computer. RADIO CORPORATION OF AMERICA. May 8, 1962 [May 25, 1961], No. 17722/62. Class 106 (1). A data processing system comprises a plurality of processing stages connected in cascade, means for simultaneously transmitting control signals towards each of said stages and a plurality of circuits each arranged to supply a start signal to an associated processing stage, to which it is connected, in response to the receipt of both of one of said control signals and an output signal indicating that the immediately preceding stage has completed its operation. In the arrangement described, a computer instruction is applied over a lead 10, which may include 28 separate wires for a 28-bit instruction word, to an instruction register 12 whose outputs are decoded in a decoder 16 and supplied to generator 20 which produces the required pulses to the instruction. As described, simultaneous pulses a1, b1, f1, h1, Fig. 2, are produced on leads 22, 24, 26, 28 to control the operation of computer stages A-D. Computer stages A, C, and D are synchronous, i.e. require a predetermined time for completion of an operation therein but computer stage B is asynchronous, i.e. requires a variable operation time, a pulse being produced on a lead 38 when an operation therein has been completed. Due to variations the time of operation of gates in the circuitry and to variations in the delay produced by transmission leads of varying length, the control pulses arrive at their distinations at different times, as shown at a, b, f, h, Fig. 2. When signal a arrives at stage A, this stage operates and after a predetermined time produces an output word to the next stage at 44. The pulse a is supplied also to a delay 30 arranged to have a delay time equal to the operation time of stage A so that, simultaneously with the appearance the output word at 44, a delayed signal c is applied to a gate 32 which, being already or shortly afterwards enabled by the control signal b, produces an output at d to start the operation of stage B. Stage B is asynchronous and produces an output e applied to gate 34 when its operation has been completed. The gate 34 controls the operation of the next stage C. The control circuitry for stages C, D, is similar to that for stage A. In a practical example (Figs. 4-12, not shown), stage A is a synchronous switch for supplying two binary coded decimal excess-3 numbers to stage B, which is an asynchronous parallel adder, the output of which is converted to excess-3 form at stage C and applied by stage D, which is a synchronous switch, to one of two alternative accumulator registers.
3	Electronic adder-accumulator	US30425552	1952-08-14	US2705108A	1955-03-29	STONE JR JOSEPH J

4	Arithmetic circuit for simultaneous generation of sum and carry signals	US35801064	1964-04-07	US3369110A	1968-02-13	JACOB HEIJN HERMAN

5	Serial digital electronic computer	US9317261	1961-03-03	US3240922A	1966-03-15	MARIA SCHOLTEN JOHANUES HERMAN

6	Casing hook for drilling apparatus	US65306423	1923-07-23	US1536617A	1925-05-05	MONTGOMERY GUSTAVUS A

7	Serial adder-subtracter subassembly	US3631231D	1970-02-03	US3631231A	1971-12-28	LAGEMANN KLAUS; SCHENDEL BERND
An adder-subtracter subassembly for the arithmetic unit of a digital computer. The subassembly adds or subtracts two serially received binary digits by storing each in a one-bit input register and by selectively complementing and blocking each stored digit before it is introduced into a full adder. The output of the full adder is read into a clocked output register, the output of which is connected through a second selectively operated complementing circuit and blocking circuit to a second input of the full adder.
8	Serial-by-digit recirculating accumulating register	US3509331D	1966-10-24	US3509331A	1970-04-28	CUTAIA ALFRED

9	Reflexed binary adder with interspersed signals	US65187757	1957-04-10	US3116412A	1963-12-31	MORSE MINKOW

10	Digital computing systems	US47797554	1954-12-28	US3023963A	1962-03-06	SCHMITT EDWARD J; SMITH JAMES G

11	JPS5221863B1 -	JP2142872	1972-03-01	JPS5221863B1	1977-06-14
931,133. Electronic computer. RADIO CORPORATION OF AMERICA. May 8, 1962 [May 25, 1961], No. 17722/62. Class 106 (1). A data processing system comprises a plurality of processing stages connected in cascade, means for simultaneously transmitting control signals towards each of said stages and a plurality of circuits each arranged to supply a start signal to an associated processing stage, to which it is connected, in response to the receipt of both of one of said control signals and an output signal indicating that the immediately preceding stage has completed its operation. In the arrangement described, a computer instruction is applied over a lead 10, which may include 28 separate wires for a 28-bit instruction word, to an instruction register 12 whose outputs are decoded in a decoder 16 and supplied to generator 20 which produces the required pulses to the instruction. As described, simultaneous pulses a1, b1, f1, h1, Fig. 2, are produced on leads 22, 24, 26, 28 to control the operation of computer stages A-D. Computer stages A, C, and D are synchronous, i.e. require a predetermined time for completion of an operation therein but computer stage B is asynchronous, i.e. requires a variable operation time, a pulse being produced on a lead 38 when an operation therein has been completed. Due to variations the time of operation of gates in the circuitry and to variations in the delay produced by transmission leads of varying length, the control pulses arrive at their distinations at different times, as shown at a, b, f, h, Fig. 2. When signal a arrives at stage A, this stage operates and after a predetermined time produces an output word to the next stage at 44. The pulse a is supplied also to a delay 30 arranged to have a delay time equal to the operation time of stage A so that, simultaneously with the appearance the output word at 44, a delayed signal c is applied to a gate 32 which, being already or shortly afterwards enabled by the control signal b, produces an output at d to start the operation of stage B. Stage B is asynchronous and produces an output e applied to gate 34 when its operation has been completed. The gate 34 controls the operation of the next stage C. The control circuitry for stages C, D, is similar to that for stage A. In a practical example (Figs. 4-12, not shown), stage A is a synchronous switch for supplying two binary coded decimal excess-3 numbers to stage B, which is an asynchronous parallel adder, the output of which is converted to excess-3 form at stage C and applied by stage D, which is a synchronous switch, to one of two alternative accumulator registers.
12	JPS4811492B1 -	JP1183670	1970-02-12	JPS4811492B1	1973-04-13

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