| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | Combined binary/decimal fixed-point multiplier and method | US12329686 | 2008-12-08 | US08577952B2 | 2013-11-05 | Mark Alan Erle; Brian John Hickmann |
| A combined binary/decimal fixed-point multiplier that uses BCD-4221 recoding for the decimal digits. This allows the use of binary carry-save hardware to perform decimal addition with a small correction. The described designs provide an improved reduction tree organization to reduce the area and delay of the multiplier and improved reduction tree components that leverage the redundant decimal encodings to help reduce delay. A split reduction tree architecture is also introduced that reduces the delay of the binary product with only a small increase in total area. Area and delay estimates are presented that show that the proposed designs have significant area improvements over separate binary and decimal multipliers while still maintaining similar latencies for both decimal and binary operations. | ||||||
| 2 | Combined Binary/Decimal Fixed-Point Multiplier and Method | US12329686 | 2008-12-08 | US20100146030A1 | 2010-06-10 | Mark Alan Erle; Brian John Hickmann |
| A combined binary/decimal fixed-point multiplier that uses BCD-4221 recoding for the decimal digits. This allows the use of binary carry-save hardware to perform decimal addition with a small correction. The described designs provide an improved reduction tree organization to reduce the area and delay of the multiplier and improved reduction tree components that leverage the redundant decimal encodings to help reduce delay. A split reduction tree architecture is also introduced that reduces the delay of the binary product with only a small increase in total area. Area and delay estimates are presented that show that the proposed designs have significant area improvements over separate binary and decimal multipliers while still maintaining similar latencies for both decimal and binary operations. | ||||||
| 3 | Direct decimal number tripling in binary coded adders | US12329706 | 2008-12-08 | US08417761B2 | 2013-04-09 | Mark Alan Erle; Brian John Hickmann |
| The digital propagate, digit generate, sum+0, and sum+1 terms used in typical carry-propagate adders are generated directly off the multiplicand. During the direct generation, the logic takes into account that each digit will be tripled and if each digit's next less significant digit is greater than 4. Using this technique, the generation of the multiplicand is significantly faster and uses less circuitry. | ||||||
| 4 | Direct Decimal Number Tripling in Binary Coded Adders | US12329706 | 2008-12-08 | US20100146031A1 | 2010-06-10 | Mark Alan Erle; Brian John Hickmann |
| The digital propagate, digit generate, sum+0, and sum+1 terms used in typical carry-propagate adders are generated directly off the multiplicand. During the direct generation, the logic takes into account that each digit will be tripled and if each digit's next less significant digit is greater than 4. Using this technique, the generation of the multiplicand is significantly faster and uses less circuitry. | ||||||
| 5 | Quinary reduction stage and forward-reverse counter | US3577085D | 1969-01-09 | US3577085A | 1971-05-04 | STUTZ THEO |
| Two forms of a quinary reduction stage, for reducing the frequency of an input multiphase binary signal by a factor of five are illustrated. One corresponds to the use of a substantially minimum number of elements, while the other corresponds to use of identical binary circuits, all having the same number of inputs. By counting quarter periods of the input signal and half periods of the output signal, a decade reduction stage results. Further, each quinary reduction stage may be connected with a binary reduction stage thus furnishing a decade reduction stage, which may interconnect with other similar ones to constitute a decade forward-reverse counter.
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| 6 | Arrangement for counting signals of specific significance | US39299864 | 1964-08-24 | US3408484A | 1968-10-29 | THEO STUTZ |
| 7 | Parallel adder for binary coded numbers | US36544364 | 1964-05-06 | US3302009A | 1967-01-31 | THEO STUTZ |
| 8 | 4 22 1 code rapid carry circuit | JP11451175 | 1975-09-22 | JPS5238851A | 1977-03-25 | SUGIMURA YUUKICHI |
| PURPOSE:To speed up the addition by constituting 4221 code rapid carry circuit by use with half-adders at preceeding and latter stage. | ||||||
| 9 | 4221 code total register | JP8593275 | 1975-07-14 | JPS5210040A | 1977-01-26 | SUGIMURA YUUKICHI |
| PURPOSE:To tub register of 4221 code with mall difference of number of gates compairing with total register. | ||||||
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