| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | 用于十进制浮点数据逻辑提取的方法和装置 | CN201180076413.2 | 2011-12-23 | CN104137058A | 2014-11-05 | S·J·阔 |
| 描述了在计算机处理器中执行BIDSplit指令的系统、设备和方法的实施例。在一些实施例中，BIDSplit指令的执行测试二进制整数十进制源值的编码并将符号、指数和/或有效数提取到目的地。 | ||||||
| 2 | 用于检测十进制浮点量异常的方法和系统 | CN201110141919.9 | 2011-05-30 | CN102331921B | 2016-07-06 | 迈克尔.F.考利肖; 希尔维亚.M.米勒; 埃里克.施瓦兹; 菲尔.C.耶 |
| 一种用于检测十进制浮点数据处理异常的系统和方法。处理器接收至少一个十进制浮点运算数并且对该至少一个十进制浮点运算数执行十进制浮点运算以产生十进制浮点结果。进行关于该十进制浮点结果是否未能保持优选量的确定。该优选量指示该十进制浮点结果的有效数字的最低有效数位表示的值。响应于确定该十进制浮点结果未能保持优选量，提供用于指示量异常发生的输出。可以生成被立即捕获或者稍后检测的可掩码的异常以便控制条件性的处理。 | ||||||
| 3 | 用于十进制浮点数据逻辑提取的方法和装置 | CN201180076413.2 | 2011-12-23 | CN104137058B | 2017-03-22 | S·J·阔 |
| 描述了在计算机处理器中执行BIDSplit指令的系统、设备和方法的实施例。在一些实施例中，BIDSplit指令的执行测试二进制整数十进制源值的编码并将符号、指数和/或有效数提取到目的地。 | ||||||
| 4 | 用于检测十进制浮点量异常的方法和系统 | CN201110141919.9 | 2011-05-30 | CN102331921A | 2012-01-25 | 迈克尔.F.考利肖; 希尔维亚.M.米勒; 埃里克.施瓦兹; 菲尔.C.耶 |
| 一种用于检测十进制浮点数据处理异常的系统和方法。处理器接收至少一个十进制浮点运算数并且对该至少一个十进制浮点运算数执行十进制浮点运算以产生十进制浮点结果。进行关于该十进制浮点结果是否未能保持优选量的确定。该优选量指示该十进制浮点结果的有效数字的最低有效数位表示的值。响应于确定该十进制浮点结果未能保持优选量，提供用于指示量异常发生的输出。可以生成被立即捕获或者稍后检测的可掩码的异常以便控制条件性的处理。 | ||||||
| 5 | 演算回路及び演算回路の制御方法 | JP2012179400 | 2012-08-13 | JP6069690B2 | 2017-02-01 | 鴨志田 志郎 |
| 6 | Arithmetic device for floating decimal point | JP17140082 | 1982-09-30 | JPS5960637A | 1984-04-06 | SAKAMOTO TSUTOMU |
| PURPOSE:To reduce the number of adders required for making a mantissa part an absolute value and to shorten the arithmetic time, by installing shifting circuits which can make one digit of right and left sides shaft to the front and back of a rounding adder and placing the rounding adder in front of a nomralizing shifting circuit. CONSTITUTION:Data (a) and (b) are registered in registers 1 and 3 and 2 and 4, respectively, and the size discrimination and difference of their exponents are performed by an adder 5. The smaller data are inputted into a shifter 8 through a multiplexer 7 and their addition to or subtraction from the larger data is performed at an adder 9. In this case, it is detected by a zero detector 14 whether the content of the highest digit of the output is ''0'' or not and, when ''0'' is detected, a shifter 10 is shifted leftward by four bits (one digit). The rightward 4-bit shifting of the shifter 10 is controlled by the carry from the adder 9 and the data multiplexer 7 selects a rounding bit or ''1'' and gives it to the carry input terminal (CI) of an adder 11. A zero detecting circuit 15 detects the number of digits which continues from the most significant digit from the output of the adder 11. | ||||||
| 7 | Detection of decimal floating point quantum exception | JP2011116699 | 2011-05-25 | JP2011248890A | 2011-12-08 | ERIC MARK SCHWARTZ; HUI SHE YE; MICHAEL FREDERICK COWLISHAW; DR SILVIA MELITTA MULLER |
| PROBLEM TO BE SOLVED: To provide a system and method for detecting an exception to decimal floating point data processing.SOLUTION: The processor receives at least one decimal floating point operand, executes a decimal floating point operation on at least one decimal floating point operand and generates a decimal floating point result. It is determined whether the decimal floating point result can sustain a recommended quantum. The recommended quantum represents a value indicated by the least significant digit of the effective number of the decimal floating point result. In response to a determination that the decimal floating point result cannot sustain the recommended quantum, an output is provided and generation of a quantum exception is shown. A maskable exception, which is immediately trapped or is later detected and controls a conditional processing, can be generated. | ||||||
| 8 | Arithmetic unit | JP20489784 | 1984-09-29 | JPS6182233A | 1986-04-25 | ISHIKAWA TEI |
| PURPOSE:To support the decimal addition and subtraction by adding hardware a little by utilizing a mantissa adder-subtractor and an absolute value use adder- subtractor in a floating point operation, as an offset data use adder-subtractor and a BCD number use adder-subtractor in the decimal addition and subtraction. CONSTITUTION:In case of executing a floating point operation, an adder- subtractor 17 for executing addition and subtraction of a mantissa is utilized as an adder to which the first offset data OS1 which becomes 6(2) at the time of addition (subtraction), and also in the floating point operation, in case when a result of subtraction by the adder-subtractor 17 has become negative, an adder-subtractor 18 for taking its absolute value is utilized as an adder- subtractor for executing an actual addition and subtraction of a BCD number. Also, in order to return a result of operation of the adder-subtractor 18, this device is provided with a circuit 33 for generating the second offset data for correcting to the BCD number, and an adder 34 for executing addition between a lower rank data of an output data from the adder-subtractor 18 and the second offset data, and obtaining a result of decimal addition and subtraction. | ||||||
| 9 | DECIMAL FLOATING-POINT QUANTUM EXCEPTION DETECTION | EP10775821.1 | 2010-11-08 | EP2430522A1 | 2012-03-21 | SCHWARZ, Eric, Mark; YEH, Phil; COWLISHAW, Michael, Frederic; MUELLER, Silvia, Melitta |
| A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing. | ||||||
| 10 | Method and apparatus for decimal number multiplication using hardware for binary number operations | EP07251933.3 | 2007-05-10 | EP1857925A3 | 2008-12-10 | Cornea-Hasegan, Marius |
According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.
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| 11 | DECIMAL FLOATING-POINT QUANTUM EXCEPTION DETECTION | EP10775821.1 | 2010-11-08 | EP2430522B1 | 2017-07-19 | SCHWARZ, Eric, Mark; YEH, Phil; COWLISHAW, Michael, Frederic; MUELLER, Silvia, Melitta |
| 12 | Method and apparatus for decimal number multiplication using hardware for binary number operations | EP07251933.3 | 2007-05-10 | EP1857925B1 | 2011-10-26 | Cornea-Hasegan, Marius |
| 13 | Method and apparatus for decimal number multiplication using hardware for binary number operations | EP07251933.3 | 2007-05-10 | EP1857925A2 | 2007-11-21 | Cornea-Hasegan, Marius |
According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.
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| 14 | Operation circuit and control method for operation circuit | JP2012179400 | 2012-08-13 | JP2014038413A | 2014-02-27 | KAMOSHIDA SHIRO |
| PROBLEM TO BE SOLVED: To provide an operation circuit that can generate an error detection code having a small number of bits and/or a high error detection rate.SOLUTION: An operation circuit comprises: a register (111) that has a code field (S), a combination field (G) and a subsequent mantissa field (T) and holds a decimal floating point number in a DPD (densely-packed decimal) format 10; a first logical operation circuit (601) that executes an operation including an exclusive OR operation and a modulo operation to a value of the combination field; a second logical operation circuit (602) that executes the operation including the exclusive OR operation and the modulo operation to a value of the subsequent mantissa field; and third logical operation circuits (603 and 604) that execute a logical operation to a value of the code field, a result of the operation by the first logical operation circuit and a result of the operation by the second logical operation circuit. | ||||||
| 15 | Decimal floating point of quantum exception detection | JP2011116699 | 2011-05-25 | JP5005102B2 | 2012-08-22 | エリック・マーク・シュワルツ; ドクター・シルビア・メリタ・ミューラー; フィル・シー・イェ; マイケル・フレデリック・カウリショウ |
| A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing. | ||||||
| 16 | JPS584369B2 - | JP5903078 | 1978-05-19 | JPS584369B2 | 1983-01-26 | GUREN JOOJI RANGUDAN JUNIA |
| 17 | Device for tracing effective digit | JP5903078 | 1978-05-19 | JPS5412236A | 1979-01-29 | GUREN JIYOOJI RANGUDAN JIYUNIA |
| 18 | 십진 부동소수점 퀀텀 익셉션 검출 | KR1020110050939 | 2011-05-27 | KR1020110131139A | 2011-12-06 | 쉬바르츠에릭마크; 예필씨; 카울리쇼마이클프레데릭; 무엘러실비아멜리타 |
| PURPOSE: A decimal floating point quantum exception detection is provided to efficiently reduce efficient accuracy for emulation of one decimal floating point by using the highest significant position number as an indicator of potential scale loss. CONSTITUTION: A decimal floating point operand is received(202). The decimal floating point operand is performed by the decimal floating point operand(210). Output is supplied for displaying quantum exception(220). The preference quantum displays a definition value by the lowest floating point of significant. The quantum exception is generated in response to a decimal floating point result. | ||||||
| 19 | 십진 부동소수점 퀀텀 익셉션 검출 | KR1020110050939 | 2011-05-27 | KR101464810B1 | 2014-11-24 | 쉬바르츠에릭마크; 예필씨; 카울리쇼마이클프레데릭; 무엘러실비아멜리타 |
| 십진 부동소수점 데이터 프로세싱 익셉션을 검출하기 위한 시스템 및 방법이 제공된다. 프로세서는 적어도 하나의 십진 부동소수점 오퍼랜드를 받아들이고, 상기 적어도 하나의 십진 부동소수점 오퍼랜드에 대해 십진 부동소수점 연산을 수행하여 십진 부동소수점 결과를 산출시킨다. 십진 부동소수점 결과가 선호 퀀텀을 유지하지 못하는지 여부에 대한 판단이 행해진다. 선호 퀀텀은 십진 부동소수점 결과의 유효수(significand)의 최하위 자리수에 의해 표현된 값을 표시한다. 십진 부동소수점 결과가 선호 퀀텀을 유지하지 못한다라는 판단에 응답하여, 퀀텀 익셉션의 발생을 표시하는 출력이 제공된다. 조정적인 프로세싱을 제어하기 위해 즉시 트래핑되거나 또는 후에 검출되는 마스크가능 익셉션이 생성될 수 있다.
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| 20 | Detection of potential need to use a larger data format in performing floating point operations | US14193322 | 2014-02-28 | US09880840B2 | 2018-01-30 | Michael F Cowlishaw; Shawn D Lundvall; Ronald M Smith, Sr.; Phil C Yeh |
| Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results. | ||||||
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