| Document | Document Title |
|---|---|
| US11855471B2 |
Power supply architecture with bidirectional battery idealization
A power management system for use in a device comprising a battery and one or more components configured to draw electrical energy from the battery may include a first power converter configured to electrically couple between charging circuity configured to provide electrical energy for charging the battery and the one or more downstream components and a bidirectional power converter configured to electrically couple between the charging circuitry and the battery, wherein the bidirectional power converter is configured to transfer charge from the battery or transfer charge from the battery based on a power requirement of the one or more components and a power available from the first power converter. |
| US11855469B1 |
Systems and methods for bidirectional charging
Aspects relate to a system for discharging a power source of an electric aircraft. System may be configured to transfer power from the electric aircraft via a charging connection. In one or more embodiments, a charging station in electric communication with the power source may discharge the power source. For example, a controller communicatively connected to the electric aircraft may be configured to receive a supply request from a user and subsequently, generate a control signal that initiates a transfer of electrical power from the power supply to discharge the power source so that power data associated with the discharge may be collected and transmitted to the controller or a remote device of the user. |
| US11855468B2 |
Battery charger including an isolating member
A battery charger may include a printed circuit board (PCB) having a first portion supporting alternating current (AC) electrical components and a second portion supporting direct current (DC) electrical components; an indicator including a light-emitting diode (LED) supported on the first portion of the PCB and operable to emit light; and an isolating member positioned on the first portion between the AC electrical components and the LED. A trace on the PCB may be electrically connected to the second portion of the PCB, the trace extending from the second portion and along the first portion, and the LED may be electrically connected to and receiving DC power through the trace, the LED being selectively positioned along a length of the trace. The LED may be positioned more than about 8 mm from the AC electrical components. |
| US11855465B1 |
Full current balancing method of state of charge for energy storage system
A full current balancing method of SOC for an energy storage system is provided. DC output terminals of each battery pack are connected in parallel with a half-bridge control circuit to form a battery module, positive and negative electrodes of battery modules are successively connected in series to form a battery cluster. In operation, SOCs of the battery modules are sorted, battery modules with lower SOCs are put in operation first when charging, and the battery modules with higher SOCs are put in operation first when discharging, thereby achieving full current balancing of SOC among the battery packs in the battery cluster. After multiple battery clusters are connected in parallel to form a battery stack, current of the battery cluster with a low SOC is increased, and current of the battery cluster with a high SOC is decreased, thereby achieving balancing of SOC among the battery clusters. |
| US11855462B2 |
Method for controlling an induction coil, and induction coil apparatus
A method for controlling an induction coil on an induction hob involves a power generation for a primary power on the induction coil for power transmission to an electrical consumer put onto a cover above the induction coil, which consumer has a receiver coil and an electrical load connected thereto, being adjusted. The induction coil forms a primary-side resonant circuit with a capacitance connected in series, and the induction coil and the receiver coil are coupled in the style of a transformer such that a current in the induction coil induces a voltage in the receiver coil with a flow of current and generation of the secondary power in the load of the electrical consumer. The control means can attempt to adjust the desired secondary power to a steady state using maximum modulation of the voltage effectively applied to the primary-side resonant circuit, as second manipulated variable. The primary power is decreased in a first step by virtue of the voltage effectively applied to the primary-side resonant circuit, as second manipulated variable, being decreased before the operating frequency as first manipulated variable is increased in a second, subsequent step. |
| US11855456B2 |
Method of controlling charging of plurality of batteries and electronic device to which the same is applied
A method of controlling charging of a plurality of batteries and an electronic device to which the same is applied are provided. The electronic device includes a housing, a plurality of batteries arranged in the housing, a power management module that controls the plurality of batteries, a plurality of current limiting ICs that limits a maximum intensity of a current flowing into each of the plurality of batteries, and at least one processor operationally connected to the plurality of batteries, the power management module and the plurality of current limiting ICs. The at least one processor may set a total charging current output from the power management module, set an individual charging current flowing into each of the plurality of batteries in proportion to a total capacity of each of the plurality of batteries, and recalculate the individual charging currents when the total charging current changes. |
| US11855455B2 |
Systems and methods for power start up in a multi-unit power distribution network
Systems and methods for power start up in a multi-unit power distribution network contemplate selectively disconnecting and reconnecting a remote subunit from a power conductor in a power distribution network at a relatively low frequency while providing short current pulses (at a low duty cycle) with enough energy transfer to power conditioning elements within the remote subunit during a start-up sequence. Once the power conditioning elements are properly charged, the remote subunit may change frequencies of the disconnecting and reconnecting so as to synchronize such disconnections to an expected frequency at the power source. Circuitry at the power source may measure activity on the power conductors regardless of frequency to detect an unwanted load on the power conductors (e.g., a human contacting the power conductors). |
| US11855454B2 |
Power supporting arrangement for a power grid operated as a virtual synchronous machine
A method can be used to control a voltage source converter of a power supporting arrangement to act as a virtual synchronous machine. The method includes obtaining a measured power level of the converter, processing the measured power level using a differential equation of an angular velocity of the virtual synchronous machine in order to obtain a control contribution, providing a phase angle of a physical quantity used to control the converter based on the control contribution, monitoring the ability of the converter to act as a virtual synchronous machine, determining that the ability of the converter to act as a virtual synchronous machine is deemed insufficient, and adjusting the control contribution by increasing the damping term and/or decreasing the moment of inertia term in response to determining that the ability of the converter to act as a virtual synchronous machine is deemed insufficient. |
| US11855452B2 |
Power clamp
An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node. |
| US11855450B2 |
ESD protection circuit with GIDL current detection
An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path. |
| US11855448B2 |
Control device and failure determination method for determining a failure in a switching circuit
Provided is a vehicular control device that is provided with a switching circuit, and for opening/closing a connection between a starter including a capacitor that is to be connected to one end portion of the switching circuit and an in-vehicle battery that is to be connected to another end portion of the switching circuit by controlling an on/off state of the switching circuit. The control device includes a voltage detection unit configured to detect a voltage of the one end portion, and a control unit configured to control the switching circuit to turn off from on, and determine whether there is a failure in the switching circuit, based on a voltage detected by the voltage detection unit when a predetermined time has elapsed from when the switching circuit is controlled to turn off from on. |
| US11855445B2 |
Power conversion device
Even when one power conversion device among a plurality of power conversion devices connected in parallel experiences a short circuit, the other power conversion devices having experienced no short circuit can be promptly restarted. Each power conversion device includes: a short circuit occurrence determination unit configured to determine, on the basis of a current value at an output terminal, whether or not a short circuit has occurred; a short circuit elimination determination unit configured to determine, on the basis of a current value and a voltage value at the output terminal, whether or not the short circuit has been eliminated; and a current interruption unit configured to, on the basis of determination by the short circuit occurrence determination unit and determination by the short circuit elimination determination unit, interrupt current that flows from a power conversion unit to the output terminal or cancel the interruption. |
| US11855443B2 |
Control system and method for double check
Provided in this disclosure is a control system and method that monitors current in a spreader motor to accurately detect a mechanical overload condition. The invention distinguishes between a short duration high current transient spike caused by sparking of brushes in the DC motor, and a long duration continuous high current caused by a mechanical overload condition in the DC motor. The control system momentarily deactivates and reactivates the motor. If high current is no longer detected, the control system construes this as a transient spike and no fault condition is indicated. If high current persists, the control system construes this as an actual overload condition, and a fault condition is indicated to the operator. In this manner, a selected default current level can be established in the control system which can be selectively reestablished if conditions within the device change over time. |
| US11855438B2 |
Multi-circuit DC breaking system
A multi-circuit DC breaking system is proposed. According to an exemplary embodiment of the present technique, there may be an advantage that by combining current-limiting technology and multi-circuit breaking technology, a failure may be quickly detected, a magnitude of a fault current may be firstly limited, and a breaking operation is performed, in a range of various fault currents, by distributing the fault currents to some circuits of multi-circuits configured in parallel, thereby easily increasing the capacity thereof. |
| US11855437B2 |
Electrical receptacle fault protection
An electrical receptacle contains a plug outlet that has a pair of contacts for electrical connection to respective hot and neutral power lines. A controlled switch, such as a TRIAC, is connected in series relationship between the outlet contact and the hot power line. Sensors in the receptacle outputs signals to a processor having an output coupled to the control terminal of the controlled switch. The processor outputs an activation signal or a deactivation signal to the controlled switch in response to received sensor signals that are indicative of conditions relative to the first and second contacts. |
| US11855435B2 |
Arc flash accessory module
Systems and methods for tripping open circuit interrupters based on the detection of an arc flash using an accessory arc flash detection module are disclosed. The housing of the arc flash detection module is structured to be installed within the frame of a circuit interrupter. The detection module communicates with light sensors structured to detect light from arc flash events, and includes a controller configured to communicate with an electronic trip unit of the circuit interrupter. In one embodiment, the detection module is configured to alert the electronic trip unit that light indicative of arc flash conditions has been detected such that the electronic trip unit can determine whether or not to initiate a trip after determining the magnitude of current flowing through the circuit interrupter. In another embodiment, the detection module is configured to directly actuate a trip of the circuit interrupter based on the detection of light. |
| US11855432B2 |
Cable management brackets
A cable management bracket including a cable management base, one or more cable clamps, and a cable distribution block is disclosed. The cable management base has a base panel, and a first sidewall and a second sidewall between a front end and a rear end of the base panel. The first sidewall and the second sidewall extend from and along opposite sides of the base panel. The one or more cable clamps are disposed on the base panel. Each cable clamp has two opposing arms separated by a slot. Each of the two opposing arms are flexibly movable to accommodate a cable in the slot. The cable distribution block is disposed at the rear end of the base panel. The cable distribution block has a plurality of through holes, each through hole configured to accommodate the cable through an opening that is flexibly movable in a horizontal direction. |
| US11855431B2 |
Modular electronics roofing attachment and methods of use thereof
A ridge vent may cover a ridge slot in a roof of the structure to provide ventilation. A housing having a length, a width and a height that are sized to fit through a ridge slot of the roof includes a top portion proximal to the ridge vent, a bottom portion proximal to the interior of the structure and opposite to the top portion, and at least one wall extending between the top portion and the bottom portion. A securing mechanism is connected to the top portion of the housing to secure the housing within the ridge slot. An electronics bus is positioned within the housing and has an interface that enables operation of modular electronic devices that are removably positioned within the housing. |
| US11855430B2 |
Junction box
The invention relates to a junction box (10) with a base part (20) and a cover part (30) arranged pivotably on the base part (20), wherein a spring element (40) is arranged between the base part (20) and the cover part (30), which is preloaded in such a way that it transfers the cover part (30) from an open position to a closed position, wherein a locking element (50) is arranged on the junction box (10), which element is movable between a first position and a second position, and which in the first position locks the cover part (20) against the spring force of the spring element (40) in the open position and allows the cover part (20) to be transferred from the open position to the closed position in the second position. |
| US11855419B2 |
Relay module structure
The disclosure is a relay module structure. A relay includes a main body and multiple pins connected to the main body. A loading box includes a box body receiving the main body and a flexible latch portion connected to the box body. The box body has a force exerting portion and multiple slots. The pins project from the slots. A relay seat includes a seat body having a recess, a positioning portion, and terminal holes. The loading box is inserted in the recess by engagement between the flexible latch portion and the positioning portion. The pins are inserted in the terminal holes. The flexible latch portion is separated from the positioning portion by exerting a force on the force exerting portion to make the loading box separate from the relay seat. |
| US11855417B2 |
Spark plug and method for producing a spark plug
Spark plug for igniting a combustible fuel in an internal combustion engine, wherein the spark plug has an igniter arranged at an end of the spark plug facing the combustion chamber, when the spark plug is mounted in the internal combustion engine. The spark plug includes a wall and a sealing area. The wall at least partially surrounds the igniter. The sealing area is used for sealing the combustion chamber against the environment. The wall has the sealing area located at an end of the wall, which end faces the combustion chamber when the spark plug is mounted in the internal combustion engine. |
| US11855415B2 |
High frequency signal coupling to surface emitters
To reduce crosstalk between bond wires, one illustrative integrated circuit includes an array of photoemitters arranged along a centerline, with adjacent photoemitters having contact pads on opposite sides of the centerline. An illustrative assembly includes an integrated circuit chip having an array of photoemitter contact pads; a printed circuit board having a recess in which the integrated circuit chip is mounted; and bond wires connecting the contact pads with respective contact pads on the printed circuit board. An illustrative cable connector includes a module that optically couples optical fibers to an array of photoemitters on an integrated circuit chip mounted to a printed circuit board. Each photoemitter has contact pads connected to the printed circuit board contact pads by bond wires, the bond wires for each photoemitter being routed in an opposite direction relative to the bond wires for any adjacent photoemitters in the array. |
| US11855413B2 |
Vertical-cavity surface-emitting laser array with isolated cathodes and a common anode
A vertical-cavity surface-emitting laser (VCSEL) array may include an n-type substrate layer and an n-type metal on a bottom surface of the n-type substrate layer. The n-type metal may form a common anode for a group of VCSEL. The VCSEL array may include a bottom mirror structure on a top surface of the n-type substrate layer. The bottom mirror structure may include one or more bottom mirror sections and a tunnel junction to reverse a carrier type within the bottom mirror structure. The VCSEL array may include an active region on the bottom mirror structure and an oxidation layer to provide optical and electrical confinement. The VCSEL array may include an n-type top mirror on the active region, a top contact layer over the n-type top mirror, and a top metal on the top contact layer. The top metal may form an isolated cathode for the VCSEL array. |
| US11855412B1 |
Tunable laser
A method, apparatus, and system for an external cavity laser with a Michelson Interferometer. |
| US11855407B2 |
Fast intensity stabilization of multiple controller beams with continuous integrating filter
Aspects of the present disclosure describe techniques for fast stabilization of multiple controller beams with continuous integrating filter. For example, a method is described for intensity stabilization of laser beams (e.g., ion controller beams) in a trapped ion system, where the method includes applying a linear array of laser beams to respective ions in a linear array of ions in a trap, performing, in response to the laser beams being applied, parallel measurements on the ions, the parallel measurements including multiple, separate measurements on each of the ions to identify fluctuations in intensity in the respective laser beams at each ion, and adjusting the intensity of one or more of the laser beams in response to fluctuations being identified from the parallel measurements. A corresponding system for intensity stabilization of laser beams in a trapped ion system is also described. |
| US11855404B2 |
Wire terminal block coupling separation member
A terminal block structure (1, 1A) is provided and includes an insulative housing (10), separation members (20, 20A) and conductive wire and terminal crimping members (30). The separation member (20, 20A) is secured to the insulative housing and includes a base (21) and a pressing mechanism (22) operably connected to the base (21). The pressing mechanism (22) includes a pressing portion (221) and a tail portion (222) extended outward from the pressing portion (221). The conductive wire and terminal crimping members (30) are arranged inside the insulative housing (10). When an acting force is exerted on the pressing portion (221), the pressing mechanism (22) generates deformation or rotation to drive the tail portion (222) to ascend. Accordingly, the pressing operation of the terminal block structure (1, 1A) is facilitated, and it is equipped with simple structure for easy installation. |
| US11855402B2 |
Connector structure and connector structure manufacturing method
A female connector structure is provided with a shielded cable configured such that an outer periphery of a coated wire including a core and an insulation coating is surrounded by a braided wire, a female terminal including a wire barrel and a connecting tube portion continuous with the wire barrel and to be connected to a mating terminal, an insulating dielectric, a front outer conductor including a front tube portion and a dielectric locking portion to be locked to at least a part of the dielectric, and a rear outer conductor 33 including a rear tube portion for surrounding the outer periphery of the coated wire 13 exposed from the braided wire, a shield crimping portion to be crimped to the braided wire from outside and a front outer conductor crimping portion to be crimped to the dielectric locking portion from outside. |
| US11855394B2 |
Electrical plug connector and electrical connecting arrangement
An electrical plug connector, having an insulating part and an inner-conductor contact element pair for differential signal transmission. The inner-conductor contact element pair comprises first and second inner-conductor contact elements, which extend through the insulating part. The inner-conductor contact elements, proximate a first end of the insulating part, have a contact section for contacting an inner conductor of a corresponding counterpart plug connector and proximate a second end of the insulating part, have a press-in pin for pressing into a metal-plated recess of an electrical assembly. The inner-conductor contact elements each have one support shoulder via which a pressing-in force can be introduced for pressing the press-in pin into the metal-plated recess. The support shoulder is along the central axis of the inner-conductor contact element. The inner-conductor contact elements each have a support surface averted from the support shoulder to support the inner-conductor contact element in the insulating part. |
| US11855393B2 |
Connector capable of connecting antenna and electronic device comprising same
Various embodiments of the disclosure relate to an electronic device comprising a connector capable of connecting an antenna. The electronic device may comprise a connector and a wireless communication circuit which can receive wireless communication data. The connector may comprise a housing which forms the outer surface of the connector and has an opening on at least a part of the outer surface so that an external connector can be coupled thereto in a first direction or a second direction, a plurality of first pins corresponding to the first direction, and a plurality of second pins corresponding to the second direction. The plurality of first pins may comprise at least one first ground pin which corresponds to a first frequency band and can be connected to the wireless communication circuit, and at least one second ground pin which corresponds to a second frequency band and can be connected to the wireless communication circuit. The plurality of second pins may comprise at least one third ground pin which corresponds to the first frequency band and can be connected to the wireless communication circuit, and at least one fourth ground pin which corresponds to the second frequency band and can be connected to the wireless communication circuit. Other embodiments are also possible. |
| US11855391B2 |
High speed electrical connector with reduced crosstalk
An electrical connector comprising a terminal module, which comprises a ground terminal and a signal terminal disposed side by side with the ground terminal. The ground terminal comprises a first contacting part. The signal terminal comprises a second contacting part. An outer diameter of the first contacting part is greater than an outer diameter of the second contacting part. The contacting end of the ground terminal is wider than the contacting end of the signal terminal. By increasing the width of the contacting end of the ground terminal, the distance between the contacting end of the signal terminal and the contacting end of the adjacent ground terminal can be shortened. In this way, the return path for the signal terminal can be shorter, and more energy can be bound between the signal terminal and the ground terminal to avoid excessive interference from the surrounding magnetic field. |
| US11855385B2 |
Electrical cord plug assembly
An electrical cord plug assembly for inhibiting a male electrical plug from being damaged includes a male electrical plug that is electrically coupled to an electrical cord. The male electrical plug can be plugged into a female electrical outlet. The male electrical plug has a pair of wings each extending laterally away from the male electrical plug. Each of the wings abuts a wall plate of the female electrical plug when the male electrical plug is plugged into the female electrical plug. Additionally, each of the wings extends in opposite directions from each other on the male electrical plug. In this way the wings inhibit the male electrical plug from being bent sideways in the female electrical plug. |
| US11855382B2 |
Loadbreak bushing
A female electrical connector for use in a separable connector assembly is provided. The female electrical connector includes an elongate insulative body and a female contact disposed within the body. The female electrical connector also includes a tubular support sleeve extending between a first end and a second end. The first end of the tubular support sleeve is connected to the female contact. The tubular support sleeve defines a cavity at the second end. The female electrical connector further includes an insulating coupling connected to the second end of the tubular support sleeve. The insulating coupling includes an insulating sleeve that is moveable between a retracted position, where the insulating sleeve is retracted within the cavity of the tubular support sleeve, and an extended position, where the insulating sleeve extends outward from the cavity and away from the second end of the tubular support sleeve. |
| US11855381B2 |
Chassis having an insertion key assembly for a pluggable module
Example implementations relate to an insertion key assembly for a pluggable module. The insertion key assembly includes a stopper element having a stopping tab, a biasing element, and a driver element having a driving tab. The biasing element is connected to the stopper element and the driver element. In a relaxed state of the biasing element: i) the stopper element is pushed outwards by the biasing element to protrude the stopping tab into a passageway defined by a plurality of walls of a chassis, to block insertion of the pluggable module inside the passageway, and ii) the driver element is pushed outwards by the biasing element to protrude the driving tab into adjacent passageway. In a biased state of the biasing element, the stopper element is pulled inwards by the biasing element to retract the stopping tab from the passageway to allow insertion of the pluggable module inside the passageway. |
| US11855378B2 |
Electrode connector structure and cable assembly
A connector assembly for coupling with one or more electrodes includes one or more cables with wires. A plug is electrically coupled with an end or ends of the cables. An electrode connector structure is electrically coupled with the cables and includes a body that is configured for forming an internal space. A cantilevered first arm has an end that cantilevers toward the internal space. The cantilevered first arm has a rest position and a flexed position. A stationary second arm and arm end extend into the internal space opposite the first arm. At least one of the ends of the cantilevered first arm and stationary second arm include an electrical contact. In the rest position, the end of the cantilevered first arm is positioned opposite the stationary second arm a first distance. In the flexed position, the cantilevered arm, moves away from the stationary second arm to separate the ends to a greater distance to receive the electrode and returns to the rest position to grip the electrode. |
| US11855377B2 |
Spring pin terminals for an electrical connector assembly that provides mechanical and electrical connections between two electrically conductive structures
An electrical connector assembly includes a housing defining an interior space and a slot and a spring pin terminal disposed within the slot of the housing. The spring pin terminal includes a first contact portion, a second contact portion, and an intermediate portion that extends between the first contact portion and the second contact portion. The first contact portion includes a contact point that engages a first electrically conductive structure and a retention force support that engages a portion of the intermediate portion of the spring pin terminal. The second contact portion includes a contact point that engages a second electrically conductive structure and a retention force and alignment support that engages the intermediate portion of the spring pin terminal. |
| US11855376B2 |
Coaxial contact having an open-curve shape
An example contact head includes coaxial contacts configured for transmission of radio frequency (RF) signals or digital signals between a test system and a device under test (DUT). Each of the coaxial contacts is configured to target a specific impedance. Each of the coaxial contacts includes a coaxial structure having an open-curve shape. The coaxial structure includes a spring material that bends in response to applied force and that returns to the open-curve shape absent the applied force. The coaxial structure includes a center conductor terminating in a contact pin and a return conductor separated by a dielectric from the center conductor. At least part of the center conductor and the return conductor include an electrically-conductive material. Flexible contacts on the coaxial contact include the electrically-conductive material. |
| US11855364B2 |
Microwave transformer and a system for fabricating the same
A conductive layer includes a microwave transformer for scaling the intensity of a microwave signal of a first frequency by a scaling factor. The transformer includes a first physical area delimited with a closed curve on the conductive layer for receiving the microwave signal from a first space angle and re-emitting a ray of the microwave signal to a second space angle. A ratio of the first physical area to the second physical area is smaller than 0.5. The ratio of the first effective area to the first physical area is larger than the ratio of the second effective area to the second physical area. The scaling factor is the ratio of the maximal intensity of the re-emitted ray and the intensity of a ray through an open aperture having a physical area equivalent to the second physical area in the same direction than the re-emitted ray. |
| US11855363B2 |
Antenna device
A first conductive plate (110) is located at a first surface (302) side of a substrate (300) away from the first surface (302) of the substrate (300). The first conductive plate (110) has an opening (112). A first conductive part (120) electrically connects the first conductive plate (110) and the substrate (300) to each other. A second conductive plate (210) is located at the first surface (302) side of the substrate (300) away from the first surface (302) of the substrate (300). A second conductive part (220) electrically connects the second conductive plate (210) and the substrate (300) to each other. The second conductive plate (210) is located inside the opening (112) of the first conductive plate (110). |
| US11855362B2 |
Half duplex mode digital beamforming device
In an embodiment, a device is included in a communications system, the device including a plurality of antenna elements configured in a phased array antenna; a plurality of integrated circuit (IC) chips, wherein each IC chip of the plurality of IC chips is associated with a respective subset of antenna elements of the plurality of antenna elements, and wherein, for each IC chip of the plurality of IC chips, the associated subset of antenna elements is used for transmitting and receiving radio frequency (RF) signals by the IC chip; and a local oscillator configured to generate a common local oscillator signal and provide the common local oscillator signal to each IC chip of the plurality of IC chips. |
| US11855361B2 |
Devices and methods related to switch linearization by compensation of a field-effect transistor
A method for fabricating a semiconductor die is provided. The method can include providing a semiconductor substrate, forming a set of field-effect transistors on the semiconductor substrate, each field-effect transistor in the set of field-effect transistors having a respective source, drain, gate, and body, forming a compensation circuit on the semiconductor substrate, and connecting the compensation circuit to the set of field-effect transistors in parallel, the compensation circuit configured to compensate a non-linearity effect generated by the set of field-effect transistors. |
| US11855360B1 |
Airborne mesh network forming phase array antenna
Disclosed herein is a method for communicating between platforms, comprising the steps of initializing a first platform and a second platform; optically tracking a movement of the second platform by the first platform; and optically communicating bi-directionally between the first platform and the second platform. Disclosed herein is an optical communication device comprising various elements including but not limited to: a processor configured to provide at least a tracking mode and a communications mode; an input-output interface coupled to the processor; an electro-optic controller coupled to the input-output interface; an acquisition-tracking portion coupled to the electro-optic controller; and a communication portion coupled to the electro-optic controller. Disclosed herein is a method for communicating between platforms, comprising forming a phase array antenna, wherein the phase array antenna comprises a plurality of platforms arranged in a platform community; and synchronizing a time measurement at each of the platforms, wherein each platform comprises an optical communication device. |
| US11855357B2 |
Multi-band antenna device
An antenna device includes an antenna space, a barrier, a signal processing device, and a feed space. The antenna space includes first and second antennas that transmit/receive first and second radio frequency (RF) signals in different bands. The barrier includes a penetration region, is disposed adjacent to the antenna space, and reflects the first and second RF signals. The signal processing device adjacent to the barrier, includes first and second RF circuits that process the RF signals. The feed space includes first and second feed layers and is disposed adjacent to and stacked on the signal processing device, and adjacent to the barrier. A first feed line connecting the first RF circuit to the first antenna passes through the first feed layer and the penetration region, and a second feed line connecting the second RF circuit to the second antenna passes through the second feed layer and the penetration region. |
| US11855356B2 |
Three dimensional antenna array module
An apparatus includes a plurality of antenna modules and a printed circuit board (PCB) having a plurality of holes embedded with a heat sink. Each antenna module includes an antenna substrate, a plurality of three-dimensional (3-D) antenna cells mounted on a first surface of the antenna substrate, and a plurality of packaged circuitry mounted on a second surface of the antenna substrate. The plurality of packaged circuitry are electrically connected with the plurality of 3-D antenna cells. Each of the plurality of antenna modules is mounted on a plurality of portions of the heat sink such that a corresponding packaged circuitry of the plurality of packaged circuitry is in a direct contact with the plurality of portions of the heat sink embedded within the plurality of holes. |
| US11855355B2 |
Antenna apparatus
An antenna apparatus includes a patch antenna pattern; a first feed via to feed power to the patch antenna pattern in a non-contact manner on a first side of the patch antenna pattern; and a plurality of feed patterns disposed on the first side of the patch antenna pattern on different levels and overlapping each other, and including at least one feed pattern that is electrically connected to the first feed via, and each having a width greater than a width of the first feed via and a cross-sectional area smaller than a cross-sectional area of the patch antenna pattern. |
| US11855354B2 |
Microstrip antenna and information apparatus
A microstrip antenna corresponds to a rectangular resonator. The resonator has first and second sides being parallel to a first direction and having a length corresponding to 3/2 wavelength, and has a shape notched from each of the first and second sides toward a center of the resonator. The antenna includes: a first portion constituting a periphery of the notched shape; and second and third portions facing each other across the first portion. The notched shape allows the first portion to contribute to a radiation characteristic. The first, second, and third portions each have a length corresponding to ½ wavelength in the first direction. The first portion has a width in the second direction that is narrower because of the notched shape than that of the second and third portions. The second or third portion is provided with a feeding point. |
| US11855353B2 |
Compact radio frequency (RF) communication modules with endfire and broadside antennas
The techniques described herein relate to a Radio Frequency (RF) communication module for a hand-held mobile electronic device. The Radio Frequency (RF) communication module includes a circuit board and a plurality of antennas disposed on a top side and bottom side of the circuit board. The plurality of antennas comprise a first subset of antennas comprising end-fire antennas and a second subset of antennas comprising broadside antennas. The first subset of antennas and the second subset of antennas also have a bandwidth of approximately 40 percent. The Radio Frequency (RF) communication module also includes a shielded area comprising circuitry coupled to the circuit board for controlling the antennas. |
| US11855347B2 |
Radial feed segmentation using wedge plates radial waveguide
An antenna having a wedge plate-based waveguide with feed segmentation and a method for using the same are disclosed. In one embodiment, the antenna comprises an aperture having an array of radio-frequency (RF) radiating antenna elements and a segmented wedge plate radial waveguide comprises a plurality of wedge plates that form a plurality of sub-apertures, wherein each sub-aperture includes one wedge plate and a distinct subset of RF radiating antenna elements in the array, wherein each wedge plate of the plurality of wedge plates has a feed point to provide a feed wave for propagation through said each wedge plate for interaction with its distinct subset of RF radiating antenna elements in the array. |
| US11855346B2 |
Parallel plate slot array antenna with defined beam squint
Antenna structures and assemblies for use in RADAR sensor assemblies and the like. In some embodiments, the assembly may comprise a feed waveguide comprising one or more feeding slots and a parallel plate waveguide operably coupled with the feed waveguide such that each of the one or more feeding slots of the feed waveguide is configured to inject electromagnetic energy into the parallel plate waveguide. A plurality of radiating slots may be formed in a plurality of rows and/or columns extending away from the feed waveguide to deliver electromagnetic energy out of the antenna assembly. |
| US11855343B2 |
Antenna and mobile terminal
An antenna includes a first radiator and a first capacitor structure. A first end of the first radiator is electrically connected to a signal feed end of a printed circuit board by means of the first capacitor structure, and a second end of the first radiator is electrically connected to a ground end of the printed circuit board. The first radiator, the first capacitor structure, the signal feed end, and the ground end form a first antenna configured to produce a first resonance frequency. An electrical length of the first radiator is greater than one eighth of a wavelength corresponding to the first resonance frequency, and the electrical length of the first radiator is less than a quarter of the wavelength corresponding to the first resonance frequency. |
| US11855341B2 |
Electrochemically controlled capillarity to dynamically connect portions of an electrical circuit
Embodiments herein describe a capillary containing a eutectic conductive liquid (e.g., EGaIn) and an electrolyte (e.g., NaOH) that is integrated into a printed circuit board (PCB). In one embodiment, the PCB includes a capillary, a negative electrode, a positive electrode, a plurality of insulation layers, and a conductive layer. The capillary extends through the PCB. The capillary includes a side surface forming an annular cylinder. A eutectic conductive liquid and an electrolyte are disposed within an aperture formed by the side surface. An electrode extends through the side surface and contacts at least the eutectic conductive liquid or the electrolyte. The negative electrode is disposed at a first end of the capillary. The positive electrode is disposed at a second end of the capillary. The conductive layer is disposed between two of the plurality of insulation layers. The electrode forms an electrical connection with the conductive layer. |
| US11855337B2 |
Capacitively loaded implantable loop antenna
A capacitively loaded loop antenna for an implantable medical device is disclosed comprising a feed extending from a conductive surface of an implantable housing, a radiating element having a cross section larger than the feed, and a return coupling the radiating element to a conductive surface of the implantable housing. The radiating element can have a height above the top surface of the implantable housing, creating a capacitance between the radiating element and the conductive surface of the implantable housing configured to counteract the inductance of the capacitively loaded loop antenna. |
| US11855330B2 |
Reflector for a multi-radiator antenna
A reflector for a multi-radiator antenna which comprises electrically conducting reflector parts and one or more connector device. At least two reflector parts are each provided with at least one connecting portion. At least one connector device is adapted to provide an electrical interconnection between at least two of the reflector parts. At least one connector device comprises a metallic film and one or more holding elements. The metallic film is adapted to be arranged in abutment with connecting portions of the at least two of the reflector parts to achieve the electrical interconnection. At least one of the holding elements has at least one holding portion adapted to connect to a connecting portion of a reflector part with said metallic film sandwiched therebetween. The electrical interconnection is indirect by means of a dielectric coating or layer arranged on the metallic film and/or on the connecting portions, or by means of a dielectric film arranged between the metallic film and the connecting portions. |
| US11855326B2 |
Electrical connector configured for connecting a plurality of waveguides between mating and mounting interfaces
High speed waveguide-based data communication systems are disclosed. Such systems may include separable electrical connectors, forming signal propagation paths between electronic assemblies with one or more waveguides. |
| US11855323B2 |
Heat treatment apparatus and method of membrane electrode assemblies
A heat treatment apparatus of membrane electrode assemblies includes a base, a first member extending from the base in a first direction, and a plurality of second members formed on the base in a radially outward direction of the first member and having inner surfaces facing the first member, where the first member or the second members includes a heat wire member, and membrane electrode assemblies are disposed between the first member and the second members. |
| US11855322B1 |
Fuel cell system air throttle for hybrid power control
A fuel cell power plant includes an energy storage system connected in parallel with a fuel cell system. The fuel cell system includes a controller, a fuel flow system, an air flow system, and an internal water management system. The controller is operable to receive, as inputs, the energy storage system state of charge and the power demand from an electric load. The controller is further operable to determine a power split set point and execute commands, as output, to control operation of the air flow system, wherein the air flow system actively regulates the proportion of current flow between the fuel cell system and the energy storage system to meet the power demand of the electric load. |
| US11855319B2 |
Fuel cell system
When leakage of fuel gas is detected by detection signals or disruption of the detection signals is detected, a FCECU limits a supply amount of the fuel gas from a fuel gas supply device, and shuts off the supply of the fuel gas by the fuel gas supply device when determining, after limiting the supply amount of the fuel gas, that the leakage of the fuel gas or the disruption of the detection signals has occurred. |
| US11855314B2 |
Electrochemical arrangement and electrochemical system
An electrochemical arrangement with two metallic separator plates which each define a plate plane and which are stacked in a stack direction perpendicular to the plate planes. The separator plates comprise sealing elements which are embossed into the separator plate and which are supported against one another for sealing the electrochemical cell which is arranged between the separator plates and which are reversibly deformable in the stack direction up to a distance z2. The arrangement further comprises at least one support element which is arranged between the separator plates and which is distanced to the sealing elements of the separator plates in a direction parallel to the plate planes. |
| US11855313B2 |
Separator assembly for fuel cell and fuel cell stack including same
Disclosed is a separator assembly for a fuel cell and a fuel cell stack including the same. The separator assembly includes (I) a plate-shaped first separator including a first reaction area where a flow path to which a reaction gas or a coolant flows on a center thereof and first manifolds to which the reaction gas or the coolant is introduced or discharged to opposite side areas of the first reaction area, and (ii) a plate-shaped second separator integrated with the first separator by bonding and including a second reaction area corresponding to a position where the first reaction area is formed and second manifolds communicating with the first manifolds. The first and second separators may have at least a portion of an inner edge of the respective first and second manifolds that are bent, thereby being disposed on an interface between the first and second separators. |
| US11855311B2 |
Electrolyte membrane for fuel cell having improved ion channel continuity and method of manufacturing same
Disclosed are an electrolyte membrane and a method of manufacturing the same. The electrolyte membrane, in which the continuity of a channel through which protons move is improved, may include ionomer solutions having different viscosities and a porous support having pores therein. |
| US11855309B2 |
Interconnect for a solid oxide fuel cell, its manufacturing method, and a solid oxide fuel cell
An interconnect for a solid oxide fuel cell, its manufacturing method, and a solid oxide fuel cell including the same are provided. |
| US11855302B1 |
Venting apparatus for battery ejecta for use in an electric aircraft
An apparatus for venting battery ejecta for use in an electric aircraft is presented. The apparatus includes a battery module with a plurality of electrochemical cells. The electrochemical cells of the plurality of electrochemical cells are separated by a carbon fiber barrier. Venting port of a plurality of venting ports is configured to vent an electrochemical cell of the plurality of electrochemical cells using a venting path of a plurality of venting paths, wherein the plurality of vent ports is fluidly connected to the plurality of venting paths and the plurality of venting paths are fluidly connected to at least an outlet. Venting paths direct the battery ejecta from the electrochemical cell to the outside of the electric aircraft through at least an outlet. |
| US11855301B2 |
Systems and methods for battery ventilation
An electrical storage system includes an electric storage zone, an electric storage positioned within the electric storage zone, a cooling fluid source in fluid communication with the electric storage zone via a fluid flow path, a modulating valve in the fluid flow path downstream from the cooling fluid source and upstream from the electric storage zone, and a detector in fluid communication with the electric storage zone. A method for operating an electrical storage system includes adjusting a modulating valve in a fluid flow path to reduce a cooling airflow to an electric storage zone, operating a detector in fluid communication with the electric storage zone configured and adapted to sense at least one of smoke, gas, or other particulates during a detection period with a detection system, and adjusting the modulating valve to increase the cooling airflow to the electric storage zone. |
| US11855300B2 |
Electric vehicle battery pack having external side pouch for electrical components
Electric vehicle battery packs with external side enclosures for containing electrical connectors and other components therein. Each enclosure is sized to support various connectors or other components as desired, and may have a number of openings formed to provide interfaces for connecting various electric vehicle systems to the battery pack. The enclosures may be placed at various locations along one or more sides of the battery pack, and connectors may be routed over an upper surface of a battery pack frame or through a gap formed between the pack frame and cover. Enclosures may be made of any material, including plastic for lower weight applications and metal for improved electromagnetic interference shielding. |
| US11855296B2 |
Battery cell having battery casing with receiving part and electrode lead groove
Disclosed in a battery cell including: an electrode assembly including a positive electrode, a negative electrode, and a separator interposed between the positive and negative electrodes, with electrode tabs protruding from at least one side of outside peripheral portions of the electrode assembly; and a battery casing including first and second casings provided with first and second receiving parts, respectively, the first and second receiving parts respectively accommodating the electrode assemblies and having different sizes or shapes, wherein in a state in which electrode leads connected to the electrode tabs protrude from outside peripheral portions of the first and second casings, the battery casing is sealed by thermal fusion along the outside peripheral portions of the first and second casings, wherein electrode lead grooves recessed downwardly such that the electrode leads are seated therein are provided at a portion of the outside peripheral portions of the first and second casings. |
| US11855295B2 |
Button-type lithium ion battery with metal housing
The present disclosure provides a button-type lithium ion battery with a metal housing, including: a metal housing; a cell, received in the metal housing; a terminal, disposed on an outside of the metal housing; at least one first electrode tab, arranged on the cell and electrically connected to the metal housing; at least one second electrode tab, arranged on the cell and electrically connected to the terminal; and an insulating member disposed between the metal housing and the terminal; wherein the insulating member is insulating and sealing the metal housing and the terminal; a polarity of the at least one first electrode tab is opposite to that of the at least one second electrode tab; a polarity of the metal housing is opposite to that of the terminal; the metal housing and the terminal are sealed to the insulating member by means of heat or adhesion. |
| US11855289B2 |
Negative electrode active material, process for preparing the same, and battery, battery module, battery pack and apparatus related to the same
The present application provides a negative electrode active material, a process, a battery, a battery module, a battery pack and an apparatus related to the same. The negative electrode active material comprises a core material and a polymer modified coating on at least a part of a surface of core material; wherein the core material is one or more of a silicon-based negative electrode material and a tin-based negative electrode material; the negative electrode active material has a weight loss rate satisfying 0.2%≤weight loss rate≤2% in a thermogravimetric analysis test wherein temperature is elevated from 25° C. to 800° C. under a non-oxidizing inert gas atmosphere. The present application can reduce damage to the surface structure of the negative electrode active material, reduce loss of active ions and capacity, meanwhile can well improve coulomb efficiency and cycle performance of the battery. |
| US11855288B2 |
Low-swelling graphite anode material, preparation method thereof and lithium ion battery
A low-swelling graphite anode material, a preparation method thereof, and a lithium ion battery including the graphite anode material. The preparation method of the graphite anode material includes: (1) mixing a graphite raw material with a modifier, and then performing heating modification; (2) performing heat treatment on the modified graphite under a protective atmosphere; and (3) performing post-treatment on the heat-treated graphite to obtain the graphite anode material. The graphite anode material has an extremely low swelling rate, excellent cycle performance, and outstanding rate performance, an swelling rate being 24.3% or lower, a normal temperature 10C/1C discharge capacity retention rate being greater than 90%, and a capacity retention rate after charging and discharging for 300 times being 91% or greater. |
| US11855287B2 |
Method of preparing positive electrode active material precursor for lithium secondary battery
The present invention relates to a method of preparing a positive electrode active material precursor for a lithium secondary battery in which particle size uniformity and productivity may be improved by using three reactors, a method of preparing a positive electrode active material for a lithium secondary battery by using the above-prepared positive electrode active material precursor for a lithium secondary battery, and a positive electrode for a lithium secondary battery and a lithium secondary battery which include the above-prepared positive electrode active material for a lithium secondary battery. |
| US11855286B2 |
Cathode for all-solid-state battery
Disclosed are a cathode for an all-solid-state battery including a cathode thin film for an all-solid-state battery or a cathode composite membrane for an all-solid-state battery, and an all-solid-state battery including the same. The cathode for an all-solid-state battery contains a grain that has a plane having a low surface energy and has a grain boundary arranged parallel to the electron movement direction, thus effectively lowering the interfacial resistance of the thin film while suppressing the dissolution and diffusion of the transition metal, thereby improving the cycle stability of the all-solid-state battery including the same. |
| US11855283B2 |
Method for evaluating a characteristic of a nonaqueous electrolyte secondary battery positive electrode active material
The present invention provides a method of evaluating a characteristic of a positive electrode active material for non-aqueous electrolyte secondary batteries, including a lithium-metal composite oxide powder including a secondary particle configured by aggregating primary particles containing lithium, nickel, manganese, and cobalt, or a lithium-metal composite oxide powder including both the primary particles and the secondary particle. The secondary particle has a porous internal structure. The characteristic being evaluated is a slurry pH, a soluble lithium content rate, or a porosity. |
| US11855282B2 |
Pre-lithiated electrode materials and cells employing the same
Provided are compositions, systems, and methods of making and using pre-lithiated cathodes for use in lithium ion secondary cells as the means of supplying extra lithium to the cell. The chemically or electrochemically pre-lithiated cathodes include cathode active material that is pre-lithiated prior to assembly into an electrochemical cell. The process of producing pre-lithiated cathodes includes contacting a cathode active material to an electrolyte, the electrolyte further contacting a counter electrode lithium source and applying an electric potential or current to the cathode active material and the lithium source thereby pre-lithiating the cathode active material with lithium. An electrochemical cell is also provided including the pre-lithiated cathode, an anode, a separator and an electrolyte. |
| US11855272B2 |
Cathode slurry for secondary battery
A cathode slurry comprises a cathode active material, especially a nickel-containing cathode active material, a binder, a solvent and a base having a formula of R 1R 2R 3N, with improved stability in water. Pre-treatment of nickel-containing cathode active materials may improve stability of the cathode by preventing undesirable decomposition of the material. In addition, battery cells comprising the cathode prepared by the cathode slurry exhibit impressive electrochemical performances. |
| US11855270B2 |
Cold plate heat exchanger
A heat exchanger may include a perforated plate having a plurality of openings sandwiched between a first plate and a second plate. The first plate may have a first plate central planar surface, a first plate peripheral wall extending from an internal face of the first plate central planar surface towards the second plate, and an inlet permitting fluid flow on to the internal face of the central planar surface. The second plate may have a second plate central planar surface, a second plate peripheral wall extending from an internal face of the second plate central planar surface towards the first plate, and an outlet permitting fluid to exit the heat exchanger. The first plate, the second plate and the perforated may be coupled and define a fluid passage for flow of a heat exchanger fluid from the inlet to the outlet. |
| US11855266B2 |
Cylindrical battery cell packaging and cooling configuration
Systems and methods that provide improved cooling for batteries are disclosed. A battery system according to the present disclosure may include a cooling plate, one or more battery cells coupled to one surface of the cooling plate, and one or more battery cells coupled to the opposite surface of the cooling plate. The cooling plate and corresponding batteries may be included in a battery module, and multiple battery modules electrically connected may make up a battery pack. The cooling plates may comprise channels for cooling fluid, which may be provided to the plates in parallel from a cooling fluid source. Cooling the battery cells at the ends of the cells, where they are coupled to the cooling plate, may advantageously provide one or more of improved energy density, thermal management, and safety. |
| US11855265B2 |
Acoustic signal based analysis of batteries
Systems and methods for acoustic signal based analysis, include obtaining acoustic response signal data of at least a portion of a battery cell, the acoustic response signal data comprising waveforms generated by transmitting one or more acoustic excitation signals into at least the portion of the battery cell and recording response vibration signals to the one or more acoustic excitation signals. One or more metrics are determined from at least the acoustic response signal data, the one or more metrics being determined based on correlation of the one or more metrics to one or more characteristics of battery cells and a reference model is generated from the one or more metrics. A test battery can be evaluated using the reference model. Actionable insights or recommendations can be generated based on the evaluation. The reference model can also be updated based on the evaluation. |
| US11855263B2 |
Enhanced temperature range power supply
A communication device includes a battery, a communication module, a first charging circuit between the battery and the communication module, a fast charge signal, a second charging circuit between the battery and the communication module, and a control module configured to route power from the battery to the communication module via the second charging circuit in response to the fast charge signal being enabled and to route the power via the first charging circuit in response to the fast charge signal being disabled. |
| US11855262B2 |
Electronic device
An electronic device includes a cell, a circuit board, and a cell protection unit. The circuit board is provided in the electronic device and configured to control the electronic device. The circuit board is electrically coupled to the cell, and the cell protection unit is provided on the circuit board. The cell protection unit is integrated with the circuit board, so as to facilitate heat dissipation of the cell, prolong the service life of the cell, speed up the production cycle of the cell, and reduce the production cost of the cell. |
| US11855260B2 |
Nonincendive electrolyte for lithium secondary battery, and lithium secondary battery including same
Disclosed is a nonincendive electrolyte for lithium secondary battery, the electrolyte using an organic solvent mixture including a first solvent containing fluorine and sulfur, a second solvent that is a linear carbonate-based compound containing fluorine, a third solvent that is a linear ester-based compound containing fluorine, and a fourth solvent that is a cyclic carbonate-based compound. Thus, the electrolyte is nonflammable or flame-retardant, thereby preventing a lithium secondary battery from catching on fire or exploding. That is, the electrolyte greatly improves the safety of a lithium secondary battery, allows the high voltage charge of a lithium secondary battery, and prevents the degradation of battery performance of a lithium secondary battery. In addition, a lithium secondary battery including the electrolyte is disclosed. |
| US11855259B2 |
Electrolyte for lithium secondary battery and lithium secondary battery comprising same
The present invention relates to a lithium secondary battery electrolyte and a lithium secondary battery including the same and, more specifically, to a flame retardant or nonflammable lithium secondary battery electrolyte having excellent stability even at a high voltage and a lithium secondary battery including the same. |
| US11855254B2 |
Solid electrolyte
Provided is a solid electrolyte which contains a composition expressed by 3LiOH·Li2SO4. The solid electrolyte has a lithium ion conductivity of 0.1×10−6 S/cm or more at 25° C. and an activation energy of 0.6 eV or more. |
| US11855253B2 |
Solid electrolyte and all-solid secondary battery
A solid electrolyte, in which an occupied impurity level that is formed by a part of elements contained in a mobile ion-containing material being substituted and that is occupied by electrons is included in a band gap of the mobile ion-containing material, and an amount of charge retention per composition formula of the occupied impurity level is equal to or greater than an amount of charge retention of mobile ions per composition formula of the mobile ion-containing material. |
| US11855250B2 |
Systems and methods for series battery charging
Systems and methods for charging and discharging a plurality of batteries are described herein. In some embodiments, a system includes a battery module, an energy storage system electrically coupled to the battery module, a power source, and a controller. The energy storage system is operable in a first operating state in which energy is transferred from the energy storage system to the battery module to charge the battery module, and a second operating state in which energy is transferred from the battery module to the energy storage system to discharge the battery module. The power source electrically coupled to the energy storage system and is configured to transfer energy from the power source to the energy storage system based on an amount of stored energy in the energy storage system. The controller is operably coupled to the battery module and is configured to monitor and control a charging state of the battery module. |
| US11855248B2 |
Electrode for secondary battery
An electrode for a secondary battery includes a current collector, a first electrode mixture layer disposed on at least one surface of the current collector and including carboxymethyl cellulose and styrene butadiene rubber, and a second electrode mixture layer disposed on the first electrode mixture layer and including carboxymethyl cellulose. A weight average molecular weight of the carboxymethyl cellulose included in the first electrode mixture layer is less than a weight average molecular weight of the carboxymethyl cellulose included in the second electrode mixture layer. Adhesion between the electrode current collector and the active material and cohesion between the active materials may be improved, and the resistance within the electrode may be reduced, thereby significantly increasing the capacity and lifespan characteristics of a battery. |
| US11855241B2 |
LED device having blue photoluminescent material and red/green quantum dots
A light-emitting device includes a plurality of light-emitting diodes, a first cured composition over a first subset of the light-emitting diodes, and a second cured composition over a second subset of light-emitting diodes. The first cured composition includes a first photopolymer and a blue photoluminescent material that is an organic, organometallic, or polymeric material, embedded in the first photopolymer. The second cured composition includes a second photopolymer and a nanomaterial embedded in the second photopolymer. The nanomaterial is selected to emit red or green light in response. |
| US11855239B2 |
Electrode assembly having lower electrode directly on the surface of a base substrate, a first electrode on the lower electrode, and the second electrode formed on and spaced apart from the first electrode
The present invention relates to an electrode assembly comprising nano-scale-LED elements and a method for manufacturing the same and, more specifically, to an electrode assembly comprising nano-scale-LED elements and a method for manufacturing the same, in which the number of nano-scale-LED elements included in a unit area of the electrode assembly is increased, the light extraction efficiency of individual nano-scale-LED elements is increased so as to maximize light intensity per unit area, and at the same time, nano-scale-LED elements on a nanoscale are connected to an electrode without a fault such as an electrical short circuit. |
| US11855235B2 |
Display panel and manufacturing method therefor, and display apparatus
Disclosed in embodiments of the present disclosure are a display panel and a manufacturing method therefor, and a display apparatus. The display panel includes: a base substrate; an organic functional film layer provided on the base substrate; an insulating layer provided on the organic functional film layer, a plurality of dents distributed at intervals are provided on one side of the insulating layer distant from the organic functional film layer; and an amorphous silicon solar cell film layer provided at one side of the insulating layer distant from the organic functional film layer, the amorphous silicon solar cell film layer has the same morphology as the surface of the insulating layer where the dents are provided. |
| US11855230B2 |
Metal-insulator-metal capacitor within metallization structure
A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer. |
| US11855226B2 |
Thin film transistor, semiconductor device and method of fabricating thin film transistor
A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole. |
| US11855225B2 |
Semiconductor device with epitaxial bridge feature and methods of forming the same
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers. |
| US11855224B2 |
Leakage prevention structure and method
A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material. |
| US11855223B2 |
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin. |
| US11855218B2 |
Transistor structure with metal interconnection directly connecting gate and drain/source regions
A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave. |
| US11855217B2 |
Semiconductor device having a conductive contact in direct contact with an upper surface and a sidewall of a gate metal layer
A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure. |
| US11855215B2 |
Semiconductor device structure with high contact area
A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor nanostructure and a second semiconductor nanostructure stacked over a substrate. The semiconductor device structure also includes a first epitaxial structure connecting the first semiconductor nanostructure and a second epitaxial structure connecting the second semiconductor nanostructure. The semiconductor device structure further includes a gate stack wrapped around the first semiconductor nanostructure and the second semiconductor nanostructure. In addition, the semiconductor device structure includes a conductive contact electrically connected to the epitaxial structures. The conductive contact has a portion extending towards the gate stack from terminals of the first epitaxial structure and the second epitaxial structures. The first epitaxial structure is wider than the portion of the conductive contact. |
| US11855206B2 |
Semiconductor device
A semiconductor device includes first and second metal layers, a dielectric layer, first, second, and third semiconductor regions, a first control electrode, and a first electrode. The dielectric layer is located on the first metal layer. The second metal layer is located on the dielectric layer, and electrically connected with the first metal layer. The first semiconductor region is located on the second metal layer and electrically connected with the second metal layer. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The first control electrode faces the second semiconductor region via a first insulating film. The first electrode is located on the third semiconductor region and the first control electrode, electrically connected with the third semiconductor region, and insulated from the first control electrode by a first insulating portion. |
| US11855205B2 |
Semiconductor device with negative capacitance structure
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a first negative capacitance material, and an isolation structure formed over the substrate. The semiconductor device structure includes a gate structure formed over the fin structure, and a source feature and a drain feature formed over the fin structure. An interface between the fin structure and the source feature is lower than a top surface of the isolation structure. |
| US11855203B2 |
Power semiconductor device
A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect. |
| US11855202B2 |
LDMOS transistor
A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack. The substrate has a first conductivity. The first region having the first conductivity is formed in the substrate. The second region having a second conductivity is formed in the substrate and is adjacent to the first region. The source region with the second conductivity is formed in the first region. The drain region with the second conductivity is formed in the second region. The active gate stack is disposed on the first region. The dummy gate stack is disposed on the second region, and the dummy gate stack is electrically coupled to a variable voltage. |
| US11855199B2 |
High Electron Mobility Transistor (HEMT) with a back barrier layer
Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN). |
| US11855198B2 |
Multi-gate high electron mobility transistors (HEMTs) employing tuned recess depth gates for improved device linearity
A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage. |
| US11855197B2 |
Vertical bipolar transistors
The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region. |
| US11855195B2 |
Transistor with wrap-around extrinsic base
The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base. |
| US11855192B2 |
Semiconductor device and manufacturing method thereof
A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers. |
| US11855191B2 |
Vertical FET with contact to gate above active fin
An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin. |
| US11855189B2 |
Semiconductor device and method for forming the same
A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure. |
| US11855185B2 |
Multilayer masking layer and method of forming same
A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer. |
| US11855184B2 |
Method of manufacturing a power semiconductor device having source region and body contact region formed between trench-type gate electrodes
A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region. |
| US11855179B2 |
Semiconductor devices and methods of manufacturing thereof
A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel. |
| US11855176B2 |
FinFET structure with doped region
Semiconductor structures are provided. The semiconductor structure includes a fin structure protruding from a substrate and a doped region formed in the fin structure. The semiconductor structure further includes a metal gate structure formed across the fin structure and a gate spacer formed on a sidewall of the metal gate structure. The semiconductor structure further includes a source/drain structure formed over the doped region. In addition, the doped region continuously surrounds the source/drain structure and is in direct contact with the gate spacer. |
| US11855173B2 |
Transistor with monocrystalline base structures
A semiconductor die includes a transistor with an emitter, base, and collector. The base includes an intrinsic base that is located in monocrystalline semiconductor material grown in an opening of a first semiconductor layer. A second semiconductor layer is located above the first semiconductor layer and includes a monocrystalline portion. In some embodiments, an opening was formed in the second semiconductor layer wherein a portion of the underlying first semiconductor layer was etched to form a cavity in which a monocrystalline intrinsic base was grown. |
| US11855169B2 |
Silicide structures in transistors and methods of forming
A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen. |
| US11855167B2 |
Structure and formation method of semiconductor device with nanosheet structure
A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes an isolation structure between the semiconductor fin and the source/drain epitaxial structure. |
| US11855162B2 |
Contacts for semiconductor devices and methods of forming the same
Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact. |
| US11855160B2 |
Thin film transistor structure, GOA circuit, and display device
A thin film transistor structure, a gate driver on array (GOA) circuit and a display device are provided. The thin film transistor structure defines a plurality of thin film transistors by patterning an active layer. Therefore, when a defect appears in the gate insulating layer of one of the plurality of thin film transistors and a leakage path is formed, other thin film transistors will not be affected. Therefore, a problem of functional failure of a whole thin film transistor structure can be avoided. |
| US11855156B2 |
Structure of flash memory cell and method for fabricating the same
A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure. |
| US11855155B2 |
Semiconductor device having contact feature and method of fabricating the same
A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide. |
| US11855153B2 |
Semiconductor device and method
A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material. By reducing segregation of the material, overlying conductive material can be deposited on a smoother interface. By depositing on smoother interfaces, overall losses of the deposited material may be avoided, which improves the overall yield. |
| US11855152B2 |
Ultrawide bandgap semiconductor devices including magnesium germanium oxides
Various forms of MgxGe1-xO2-x are disclosed, where the MgxGe1-xO2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of MgxGe1-xO2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of MgxGe1-xO2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices. |
| US11855151B2 |
Multi-gate device and method of fabrication thereof
A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material. |
| US11855146B2 |
Melt anneal source and drain regions
A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal. |
| US11855145B2 |
Semiconductor structure
A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line. |
| US11855144B2 |
Source/drain metal contact and formation thereof
A semiconductor device comprises a fin disposed on a substrate, a source/drain feature disposed over the fin, a silicide layer disposed over the source/drain feature, a seed metal layer disposed over the silicide layer and wrapping around the source/drain feature, and a metal layer disposed on the silicide layer, where the metal layer contacts the seed metal layer. |
| US11855141B2 |
Local epitaxy nanofilms for nanowire stack GAA device
The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer. |
| US11855138B2 |
Semiconductor device structure
Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature. |
| US11855126B2 |
Semiconductor device including metal insulator metal capacitor and method of making
A semiconductor device includes a substrate. The semiconductor device further includes a circuit layer over the substrate. The semiconductor device further includes a test line electrically connected to the circuit layer. The semiconductor device further includes a capacitor on the substrate. The capacitor includes a first conductor, wherein the first conductor is on a portion of the substrate exposed by the circuit layer. The capacitor further includes an insulator surrounding the first conductor. |
| US11855120B2 |
Substrate for a front-side-type image sensor and method for producing such a substrate
A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 μm is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate. |
| US11855116B2 |
Semiconductor apparatus and device
A first conductive portion includes a first pad surrounded by a first insulator film in a plane perpendicular to a first direction, and a first via connected to the first pad so that the first via is positioned between the first pad and a first semiconductor layer in the first direction. A second conductive portion includes a second pad surrounded by a second insulator film in a plane perpendicular to the first direction, and a second via connected to the second pad so that the second via is positioned between the second pad and a second semiconductor layer in the first direction. The first and the second conductive portions are different in dimension. |
| US11855113B2 |
Image sensor including color separating lens array and electronic device including the image sensor
Provided is an image sensor including a sensor substrate including a plurality of first pixels configured to sense first wavelength light in an infrared ray band and a plurality of second pixels configured to sense second wavelength light in a visible light band, and a color separating lens array disposed on the sensor substrate and configured to change a phase of the first wavelength light incident on the color separating lens array such that the first wavelength light is condensed to the plurality of first pixels, wherein the color separating lens array includes a plurality of light condensing regions configured to condense the first wavelength light respectively on the plurality of first pixels, and wherein an area of each of the plurality of light condensing regions is larger than an area of each of the plurality of first pixels. |
| US11855112B2 |
Sensor chip and electronic apparatus
The present disclosure relates to a sensor chip and an electronic apparatus each of which enables carriers generated through photoelectric conversion to be efficiently used. At least one or more avalanche multiplication regions multiplying carriers generated through photoelectric conversion are provided in each of a plurality of pixel regions in a semiconductor substrate, and light incident on the semiconductor substrate is condensed by an on-chip lens. Then, a plurality of on-chip lenses is arranged in one pixel region. The present technology, for example, can be applied to a back-illuminated type CMOS image sensor. |
| US11855111B2 |
MWIR lens for remote sensing
A Mid-Wave Infrared (MWIR) objective lens having an F # of 2.64 and a 33.6° angular field of view. It is deployed, with a focal plane and scanning system, on an airborne platform for remote sensing applications. Focal length is 9 inches, and the image is formed on a focal plane constituting CCD or CMOS with micro lenses. The lens has, from object to image, three optical element groups with a cold shield/aperture stop. Group 1 has a positive optical power and three optical elements; Group 2 has a positive optical power and four optical elements; Group 3 has a positive optical power and three optical elements. The objective lens is made of two Germanium and Silicon. The lens is both apochromatic and orthoscopic, and corrected for monochromatic and chromatic aberrations over 3.3 to 5.1 micrometers. |
| US11855106B2 |
Signal processing device having counter counting pulses from avalanche photodiode
A signal processing device includes a plurality of pixel signal processing units and a signal line group. The plurality of pixel signal processing units is arranged in a first direction and a second direction, each of the plurality of signal processing units acquiring a digital signal having a plurality of bits based on an output from a corresponding avalanche photodiode. The signal line group is arranged corresponding to the plurality of pixel signal processing units arranged in the first direction and including a signal line to which a plurality of signals corresponding to a plurality of bits of different digits of the digital signal held in each of the plurality of pixel signal processing units arranged in the first direction are commonly output. |
| US11855105B2 |
Solid-state imaging device and electronic device
To stably generate avalanche amplification while suppressing a reduction in resolution. A solid-state imaging device according to an embodiment includes a photoelectric conversion region in an element region defined by a trench in a semiconductor substrate, a first semiconductor region surrounding the photoelectric conversion region, a first contact that contacts the first semiconductor region at a bottom of the trench, a second semiconductor region contacting the first semiconductor region and having a first conductivity type the same as the first semiconductor region, a third semiconductor region that contacts the second semiconductor region, between the second semiconductor region and a first surface, and having a second conductivity type, and a second contact on the first surface and contacting the third semiconductor region, wherein a height of the first contact from the first surface is different from a height of the third semiconductor region from the first surface. |
| US11855100B2 |
Multilevel semiconductor device and structure with oxide bonding
A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds. |
| US11855097B2 |
Air gap formation between gate spacer and epitaxy structure
A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue. |
| US11855094B2 |
FinFET devices with dummy fins having multiple dielectric layers
A semiconductor device includes a substrate; semiconductor fins over the substrate and oriented lengthwise along a first direction; first multi-dielectric-layer (MDL) fins and second MDL fins over the substrate and oriented lengthwise along the first direction, wherein the first and the second MDL fins are intermixed with the semiconductor fins, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer and the inner dielectric layer have different dielectric materials; and gate structures oriented lengthwise along a second direction generally perpendicular to the first direction, wherein the gate structures are spaced from each other along the first direction, and are separated by the first MDL fins along the second direction, wherein the gate structures engage the semiconductor fins and the second MDL fins. |
| US11855086B2 |
Polysilicon structure including protective layer
A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer. |
| US11855083B2 |
Gate structure, fin field-effect transistor, and method of manufacturing fin-field effect transistor
A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is surrounded by the gate dielectric layer. The metal layer is disposed over the work function layer. The barrier layer is surrounded by the work function layer and surrounds the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. |
| US11855077B2 |
Semiconductor device
A semiconductor device is preferably excellent in characteristics such as a loss characteristic. Provided is a semiconductor device including a semiconductor substrate, including an upper-surface electrode provided on an upper surface of the semiconductor substrate; an lower-surface electrode provided on a lower surface of the semiconductor substrate; a transistor portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; a first diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; and a second diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode, wherein the first diode portion and the second diode portion have different resistivities in a depth direction of the semiconductor substrate. |
| US11855073B2 |
ESD structure
Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features. |
| US11855072B2 |
Integrated standard cell structure
An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region. |
| US11855070B2 |
Semiconductor device, method of and system for manufacturing semiconductor device
A semiconductor device, includes a first metal layer, a second metal layer, and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The at least one conductive via connects the first conductor and the second conductor through the third conductor. |
| US11855069B2 |
Cell structure having different poly extension lengths
A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor. |
| US11855067B2 |
Integrated circuit package and method
A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die. |
| US11855062B2 |
Method for manufacturing display array
A method for manufacturing a display array includes the following steps: providing a substrate and forming a semiconductor stacked layer on the substrate; forming an insulating layer and a plurality of electrode pads on an outer surface of the semiconductor stacked layer, the insulating layer and the electrode pads directly contacting the semiconductor stacked layer, wherein the insulating layer has a plurality of openings spaced apart from each other; and transferring the semiconductor stacked layer, the insulating layer and the electrode pads from the substrate to a driving backplane, wherein the electrode pads are respectively electrically connected to the driving backplane through the openings of the insulating layer to form a plurality of light emitting regions in the semiconductor stacked layer as the electrode pads and the semiconductor stacked layer are energized by the driving backplane. |
| US11855061B2 |
Offset-aligned three-dimensional integrated circuit
A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry. |
| US11855058B2 |
Package structure and method of forming the same
Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5. |
| US11855057B2 |
Package structure and method of forming the same
Provided are a package structure and a method of forming the same. The method includes: laterally encapsulating a device die and an interconnect die by a first encapsulant; forming a redistribution layer (RDL) structure on the device die, the interconnect die, and the first encapsulant; bonding a package substrate onto the RDL structure, so that the RDL structure is sandwiched between the package substrate and the device die, the interconnect die, and the first encapsulant; laterally encapsulating the package substrate by a second encapsulant; and bonding a memory die onto the interconnect die, wherein the memory die is electrically connected to the device die through the interconnect die and the RDL structure. |
| US11855056B1 |
Low cost solution for 2.5D and 3D packaging using USR chiplets
Systems and methods are provided for a system in a package (SiP) connectivity using one or more ultra short reach (USR) chiplets. The USR chiplet can receive/transmit data at a lower throughput and transmit/receive that data at a higher throughput over ultra short distances. The USR chiplet can be connected to a main integrated circuit (IC) using a high density interconnect or integrated with the main IC in a mold material. The USR chip can enable the main IC to transfer data over a substrate at a higher speed using a fewer number of traces. |
| US11855055B2 |
Display device
A display device according to one or more embodiments of the present disclosure includes a substrate, a first electrode and a second electrode on the substrate, a light emitting element electrically connected to the first electrode and the second electrode, and a first reflective layer on the light emitting element and including an opening overlapping the light emitting element, wherein the first reflective layer includes a material having a first reflectivity. |
| US11855050B2 |
Micro-LED displays, micro-led transferring substrates, and methods of transferring micro-LEDs using the micro-LED transferring substrates
Provided is a micro-LED display, a micro-LED transferring substrate, and a method of transferring micro-LEDs using the micro-LED transferring substrate. The micro-LED includes a backplane substrate; and a plurality of sub-pixels provided on the backplane substrate, wherein at least one sub-pixel from among the plurality of sub-pixels includes a first micro-LED; and a second micro-LED different from the first micro-LED. |
| US11855049B2 |
Semiconductor device
A semiconductor device including a semiconductor chip, an insulating circuit board having a circuit pattern formed on an insulating plate, a case including a frame part having an opening that is substantially rectangular in a plan view of the semiconductor device, inner wall surfaces of the frame part at the opening forming a storage part to store the insulating circuit board, and a printed circuit board which has a flat plate shape and which protrudes from one of the inner wall surfaces of the frame part toward the storage part. The semiconductor device further includes a sealing material filled in the storage part, to thereby seal the semiconductor chip and the printed circuit board. A front surface of the sealing material forms a sealing surface, and in a thickness direction of the semiconductor chip, the sealing surface is higher around the printed circuit board than around the semiconductor chip. |
| US11855048B2 |
Semiconductor packages with pass-through clock traces and associated systems and methods
Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts. |
| US11855047B2 |
Chip package structure with conductive shielding film
A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a curved bottom surface. |
| US11855043B1 |
Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates
A multi-chip module (MCM) includes a common substrate and first and second integrated circuit (IC) chips disposed on the common substrate. The first integrated circuit (IC) chip includes a first interface circuit disposed proximate a first edge of the first IC chip and a second interface circuit disposed proximate the first edge of the first IC chip. A first chiplet couples to the first interface circuit via a first link. A second chiplet couples to the second interface circuit via a second link. A first position of the first chiplet with respect to the first IC chip is staggered in a longitudinal dimension relative to a second position of the second chiplet with respect to the first IC chip. |
| US11855039B2 |
Chip package structure
A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure. |
| US11855038B2 |
Method for assembling components implementing a pre-treatment of the solder bumps allowing an assembly by fluxless and residue-free soldering
A method for assembling components includes assembling a first component including solder bumps with a second component including connectors. The assembly of the components is preceded by pre-treating the first and second components wherein the solder bumps are contacted with a pre-treatment liquid configured to at least partially remove an oxide layer initially present on the solder. The pre-treatment liquid is an aqueous solution containing carboxylic acids or polycarboxylic acids. The assembly of the components is carried out after the pre-treatment in the absence of liquid or gas flux. |
| US11855037B2 |
Method for producing an electrically conductive connection on a substrate, microelectronic device and method for the production thereof
The invention relates to a method (110) for producing an electrically conductive connection (112, 112′) on a substrate (114), comprising the following steps: a) providing a substrate (114), wherein the substrate (114) is configured for receiving an electrically conductive connection (112, 112′); b) providing a reservoir of an electrically conductive liquid alloy, wherein the reservoir has a surface at which the alloy has an insulating layer; c) providing a capillary (120) configured for taking up the electrically conductive liquid alloy; d) penetrating of a tip (122) of the capillary (120) under the surface of the reservoir and taking up of a portion of the alloy from the reservoir; and e) applying the portion of the alloy at least partly to the substrate (114) in such a manner that an electrically conductive connection (112, 112′) is formed from the alloy on the substrate (114), wherein the alloy remains on the substrate (114) by adhesion. The invention furthermore relates to a method for producing a microelectronic device (124) and to a microelectronic device (124), in particular a transistor (130). |
| US11855035B2 |
Stack of electrical components and method of producing the same
A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, the adhesive layer has a first portion that is located between the second and third surface and a second portion that is made of a same material as the first portion and that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface. |
| US11855034B2 |
Electronic device package and method of manufacturing the same
An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall. |
| US11855032B2 |
Semiconductor structure and manufacturing method thereof
The disclosed semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow. |
| US11855030B2 |
Package structure and method of manufacturing the same
A package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. The redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. The conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. The first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads. |
| US11855027B2 |
Integrated circuits with conductive bumps having a profile with a wave pattern
An article of manufacture comprises: an integrated circuit having a contact; a conductive bump electrically coupled to the contact, the conductive bump having a profile with a wave pattern; a lead frame electrically coupled to the conductive bump; and an integrated circuit package mold, the integrated circuit package mold covering portions of the conductive bump and the lead frame. |
| US11855023B2 |
Wafer level fan out semiconductor device and manufacturing method thereof
A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed. |
| US11855019B2 |
Method of forming a sensor device
The disclosed subject matter relates generally to methods of forming a semiconductor device, such as a moisture sensor. A plurality of electrodes and a bond pad are formed in a dielectric region. A passivation layer is formed on each electrode in the plurality of electrodes and the bond pad. A barrier layer is formed on the passivation layer. A plurality of trenches are formed to extend through the barrier layer and into the dielectric region. Formation of the trenches simultaneously exposes an upper surface of the bond pad. A moisture sensitive dielectric layer is formed on the barrier layer. Formation of the moisture sensitive dielectric layer also fills the trenches to form a plurality of projections, each projection being formed between two electrodes in the plurality of electrodes. |
| US11855016B2 |
Semiconductor device and method of manufacture
A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer. |
| US11855013B2 |
Semiconductor device
A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate. |
| US11855000B2 |
Semiconductor device having EMI shielding structure and related methods
An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package. In another embodiment, the electrical connection is made through the substrate. |
| US11854999B2 |
Patterning a transparent wafer to form an alignment mark in the transparent wafer
In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark. |
| US11854997B2 |
Method of forming semiconductor device
A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment. |
| US11854994B2 |
Redistribution structure for integrated circuit package and method of forming same
A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall. |
| US11854987B2 |
Semiconductor packages with interconnection features in a seal region and methods for forming the same
Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing. |
| US11854985B2 |
Semiconductor package and method of manufacturing the same
A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package. |
| US11854981B2 |
Electronic device and method for fabricating the same
An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction. |
| US11854979B2 |
Semiconductor device
A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring. |
| US11854976B2 |
Methods of designing and fabricating a semiconductor device based on determining a least common multiple between select layout pitches
A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5. |
| US11854972B2 |
Memory device
A memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between the extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction. |
| US11854967B2 |
Semiconductor packages
Semiconductor packages are provided. One of the semiconductor packages includes an integrated circuit, a die, an encapsulant and an inductor. The die is bonded to the integrated circuit. The encapsulant encapsulates the die over the integrated circuit. The inductor includes a plurality of first conductive patterns and a plurality of second conductive patterns. The first conductive patterns penetrate through the encapsulant. The second conductive patterns are disposed over opposite surfaces of the encapsulant. The first conductive patterns and the second conductive patterns are electrically connected to one another to form a spiral structure having two ends. |
| US11854960B2 |
Semiconductor devices including decoupling capacitors and methods of manufacturing thereof
A semiconductor device includes an active region over a substrate extending along a first lateral direction. The semiconductor device includes a number of first conductive structures operatively coupled to the active region. The first conductive structures extend along a second lateral direction. The semiconductor device includes a number of second conductive structures disposed above the plurality of first conductive structures. The second conductive structures extend along the first lateral direction. The semiconductor device includes a first capacitor having a first electrode and a second electrode. The first electrode includes one of the first conductive structures and the active region, and the second electrode includes a first one of the second conductive structures. Each of the active region and the first conductive structures is electrically coupled to a power rail structure configured to carry a supply voltage. |
| US11854956B2 |
Semiconductor die package with conductive line crack prevention design
A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction. |
| US11854954B2 |
Integrated circuit and electronic device comprising a plurality of integrated circuits electrically coupled through a synchronization signal routed through the integrated circuit
An integrated circuit includes a semiconductor substrate, electronic components integrated in the semiconductor substrate, an electric connection structure overlying the semiconductor substrate, and an conductive region, with elongated shaped, having a first and a second end. The conductive region is formed in the electric connection structure, extends over an entire length of the substrate and is not directly electrically connected to the electronic components. A first and a second synchronization connection element are electrically coupled to the first end and to the second end, respectively, of the conductive region and have each a respective synchronization connection portion facing the coupling face. |
| US11854951B2 |
Semiconductor device
Provided is a semiconductor device applicable to both types of packages regardless of whether or not double bonding of a lead frame pad is allowed. The semiconductor device includes: an operational amplifier; a feedback resistor; a reference voltage generation circuit; an output transistor; a first pad which is connected to an output terminal of the output transistor, and is to be selectively connected to a lead frame pad by a bonding wire; a second pad to be selectively connected to the lead frame pad by a bonding wire; and a connection switching element provided between the first pad and the second pad. In a case in which the second pad is connected to the lead frame pad by the bonding wire, the connection switching element interrupts connection between the first pad and the second pad. |
| US11854948B2 |
Semiconductor package
A semiconductor package includes a package substrate including a redistribution layer; a semiconductor chip disposed on the package substrate and electrically connected to the redistribution layer; a wiring structure disposed on the semiconductor chip and having an upper surface on which pads are arranged; a vertical connection structure disposed between the package substrate and the wiring structure and electrically connecting the redistribution layer and the pads; and a passivation layer disposed on the wiring structure and having openings partially exposing a region of each of the pads. The pads include a first pad adjacent to a corner of the wiring structure, and a second pad closer to a center of the wiring structure than the first pad. A first width of the first pad is greater than a second width of the second pad. A contact layer is disposed in the opening on the first pad. |
| US11854946B2 |
Semiconductor device with sealed semiconductor chip
A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires. |
| US11854939B2 |
Three-dimensional integrated system of dram chip and preparation method thereof
Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact. |
| US11854938B2 |
Electrostatic protection device and electrostatic protection circuit
The present disclosure provides an electrostatic protection device and an electrostatic protection circuit. The electrostatic protection device includes: a discharge transistor, located on a substrate for discharging electrostatic charges; and a first pad, located on a first metal layer and electrically connected to a drain region of the discharge transistor; wherein a projection of the first pad on the substrate partially overlaps a projection of the drain region on the substrate. |
| US11854935B2 |
Enhanced base die heat path using through-silicon vias
Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy. |
| US11854934B2 |
Package with heat dissipating substrate
A heat sink includes first to fifth layers. The first layer supports a frame made of ceramics, is made of copper, and has a thickness t1. The second layer is laminated to the first layer, is made of molybdenum, and has a thickness t2. The third layer is laminated to the second layer, is made of copper, and has a thickness t3. The fourth layer is laminated to the third layer, is made of molybdenum, and has a thickness t4. The fifth layer is laminated to the fourth layer, is made of copper, and has a thickness t5. A formula 3≤t1/t5≤5 is satisfied. A formula 3≤t3/t5≤5 is satisfied. |
| US11854932B2 |
Package wrap-around heat spreader
Embodiments disclosed herein include electronic packages and thermal solutions for such electronic packages. In an embodiment, an electronic package comprises, a package substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface connecting the first surface to the second surface. In an embodiment, the electronic package further comprises a heat spreader, where a first portion of the heat spreader is attached to the first surface of the package substrate and a second portion of the heat spreader is attached to the second surface of the package substrate. In an embodiment, a third portion of the heat spreader adjacent to the sidewall surface of the package substrate connects the first portion of the heat spreader to the second portion of the heat spreader. |
| US11854930B2 |
Semiconductor chip package and fabrication method thereof
A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device. |
| US11854929B2 |
Semiconductor package and method of forming the same
An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface. The second semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the second semiconductor device has a second bottom surface, a second top surface and a second side surface connecting with the second bottom surface and the second top surface, the second side surface faces toward to the first side surface, the second side surface comprises a third sub-surface and a fourth sub-surface connected with each other, the third sub-surface is connected with the second bottom surface, and a second obtuse angle is between the third sub-surface and the fourth sub-surface. The underfill layer is between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. The encapsulant encapsulates the first semiconductor device, the second semiconductor device and the underfill layer. |
| US11854928B2 |
Semiconductor package and manufacturing method thereof
A semiconductor package includes an integrated circuit (IC) structure, an insulating encapsulation laterally covering the IC structure, and a redistribution structure disposed on the insulating encapsulation and the IC structure. The redistribution structure is electrically connected to the IC structure. The IC structure includes a first die, a capacitor structure, a dielectric layer laterally covering the first die and the capacitor structure, and a second die disposed on the dielectric layer, the first die, and the capacitor structure. The second die interacts with the capacitor structure, where a bonding interface between the second die and the first die is substantially coplanar with a bonding interface between the second die and the dielectric layer. A manufacturing method of a semiconductor package is also provided. |
| US11854918B2 |
Seal ring between interconnected chips mounted on an integrated circuit
A semiconductor package includes a first die. The first die has a first side and a second side different from the first side and includes a first seal ring. The first seal ring includes a first portion at the first side and a second portion at the second side, and a width of the first portion is smaller than a width of the second portion. |
| US11854917B2 |
Radio-frequency device comprising semiconductor device and waveguide component
A radio-frequency device comprises a semiconductor device, comprising a radio-frequency chip, and a first connection element, which is configured to mechanically and electrically connect the semiconductor device to a circuit board. The radio-frequency device furthermore comprises a waveguide component arranged over the semiconductor device, comprising a waveguide embodied in the waveguide component, and a second connection element, which mechanically connects the waveguide component to the semiconductor device. At least one from the first connection element or the second connection element is embodied in an elastic fashion. |
| US11854916B2 |
Method for evaluating placement of semiconductor devices
Disclosed is a method of evaluating placement of semiconductor devices performed by a computing device according to an exemplary embodiment of the present disclosure. The method includes receiving connection information representing a connection relationship between semiconductor devices; clustering the semiconductor devices based on the connection information; and determining a reward to train a neural network model based on clustering. |
| US11854913B2 |
Method for detecting defects in semiconductor device
A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit. |
| US11854912B2 |
Semiconductor package including a chip pad having a connection portion and test portion in a first surface of the chip pad
A semiconductor package is provided. The semiconductor package includes a chip pad of a semiconductor chip, the chip pad including a connection portion and a test portion in a first surface of the chip pad; a barrier layer covering the chip pad, the barrier layer defining a first opening and a second opening that is separate from the first opening, the first opening exposing the connection portion of the chip pad, and the second opening exposing the test portion of the chip pad; and a redistribution structure. |
| US11854911B2 |
Methods, systems, and apparatus for conducting chucking operations using an adjusted chucking voltage if a process shift occurs
Methods, systems, and apparatus for conducting chucking operations are disclosed that use an adjusted chucking voltage if a process shift occurs. In one implementation, a method includes conducting a first processing operation on a substrate in a processing chamber. The first processing operation includes applying a chucking voltage to an electrostatic chuck (ESC) in the processing chamber while the substrate is supported on the ESC. The method includes determining that a process shift has occurred. The determining that the process shift has occurred includes one or more of: determining that a center of the substrate has moved by a post-processing shift relative to a pre-processing location of the center prior to the first processing operation, or determining that a defect count of a backside surface of the substrate exceeds a defect threshold. The method includes determining an adjusted chucking voltage based on the occurrence of the process shift. |
| US11854909B2 |
Semiconductor structure and method for manufacturing thereof
A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed. |
| US11854906B2 |
Gate structures for semiconductor devices
A semiconductor device with different gate structure configurations and a method of fabricating the semiconductor device are disclosed. The method includes depositing a high-K dielectric layer surrounding nanostructured channel regions, performing a first doping with a rare-earth metal (REM)-based dopant on first and second portions of the high-K dielectric layer, and performing a second doping with the REM-based dopants on the first portions of the high-K dielectric layer and third portions of the high-K dielectric layer. The first doping dopes the first and second portions of the high-K dielectric layer with a first REM-based dopant concentration. The second doping dopes the first and third portions of the high-K dielectric layer with a second REM-based dopant concentration different from the first REM-based dopant concentration. The method further includes depositing a work function metal layer on the high-K dielectric layer and depositing a metal fill layer on the work function metal layer. |
| US11854902B2 |
Integrated circuits with buried interconnect conductors
Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor. |
| US11854899B2 |
Semiconductor devices and methods of manufacturing thereof
A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer. |
| US11854896B2 |
Semiconductor device with S/D bottom isolation and methods of forming the same
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps. |
| US11854895B2 |
Transistors with channels formed of low-dimensional materials and method forming same
A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin. |
| US11854894B2 |
Integrated circuit device structures and double-sided electrical testing
Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density. |
| US11854891B2 |
Wafer manufacturing method and laminated device chip manufacturing method
A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of separating, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a through hole formed by separating the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the through hole. |
| US11854890B2 |
Capacitor and method for producing the same
In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions. |
| US11854888B2 |
Laser scribing trench opening control in wafer dicing using hybrid laser scribing and plasma etch approach
An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits. |
| US11854886B2 |
Methods of TSV formation for advanced packaging
The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power. |
| US11854883B2 |
Interconnect structure and method for forming the same
A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a first dielectric layer over a substrate, forming a first conductive feature through the first dielectric layer, etching the first conductive feature to form a recess over the first conductive feature, forming a second dielectric layer over the first dielectric layer and filling the recess, etching the second dielectric layer to form an opening exposing an upper surface of the first conductive feature, and forming a second conductive feature in the opening. |
| US11854882B2 |
Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects
Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another. |
| US11854878B2 |
Bi-layer alloy liner for interconnect metallization and methods of forming the same
A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer. |
| US11854869B2 |
Methods of forming high aspect ratio features
Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices. |
| US11854867B2 |
Semiconductor structure and method for forming the same
A method for forming a semiconductor structure includes receiving a first die having a first interconnect structure and a first bonding layer over the first interconnect structure, and a second die having a second interconnect structure and a second bonding layer over the second interconnect structure; forming a recess indenting into the first bonding layer; and forming a positioning member on the second bonding layer. The method further includes bonding the second die over the first die; and disposing the positioning member into the recess. The positioning member includes dielectric, is surrounded by the first bonding layer, and is isolated from the first interconnect structure and the second interconnect structure. |
| US11854861B2 |
System and method for performing spin dry etching
A spin dry etching process includes loading an object into a dry etching system. A dry etching process is performed to the object, and the object is spun while the dry etching process is being performed. The spin dry etching process is performed using a semiconductor fabrication system. The semiconductor fabrication system includes a dry etching chamber in which a dry etching process is performed. A holder apparatus has a horizontally-facing slot that is configured for horizontal insertion of an etchable object therein. The etchable object includes either a photomask or a wafer. A controller is communicatively coupled to the holder apparatus and configured to spin the holder apparatus in a clockwise or counterclockwise direction while the dry etching process is being performed. An insertion of the etchable object into the horizontally-facing slot of the holder apparatus restricts a movement of the object as the dry etching process is performed. |
| US11854855B2 |
Micro-transfer printing with selective component removal
An example of a method of micro-transfer printing comprises providing a micro-transfer printable component source wafer, providing a stamp comprising a body and spaced-apart posts, and providing a light source for controllably irradiating each of the posts with light through the body. Each of the posts is contacted to a component to adhere the component thereto. The stamp with the adhered components is removed from the component source wafer. The selected posts are irradiated through the body with the light to detach selected components adhered to selected posts from the selected posts, leaving non-selected components adhered to non-selected posts. In some embodiments, using the stamp, the selected components are adhered to a provided destination substrate. In some embodiments, the selected components are discarded. An example micro-transfer printing system comprises a stamp comprising a body and spaced-apart posts and a light source for selectively irradiating each of the posts with light. |
| US11854853B2 |
Wafer positioning method and apparatus
A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder. |
| US11854852B2 |
Substrate chuck for self-assembling semiconductor light-emitting diodes
Discussed is a substrate chuck including: a substrate support part for supporting a substrate having an assembly electrode; a vertical moving part which moves the substrate so that one surface of the substrate comes in contact with a fluid in a state in which the substrate is supported by the substrate support; an electrode connection part for applying power to the assembly electrode to generate an electric field so that semiconductor light-emitting diodes are placed at the predetermined positions of the substrate in a process of moving the semiconductor light-emitting diodes by a position change of at least one magnet; and a rotating part for rotating the substrate support part around a rotating shaft so that the substrate is placed in an upward or downward direction, wherein the rotating shaft is spaced apart from a center of the substrate support part at a predetermined distance. |
| US11854848B2 |
Air processing system for semiconductor container
A container includes a container body and an air processing system. The container body includes a plurality of walls defining an interior space for receiving wafers. The air processing system is attached to the container body. The air processing system includes an exchange module, an air extraction module, a first contaminant removal module, a processing module, a second contaminant removal module, a controller module and a power module. The exchange module is coupled to one of the walls of the container body. The air extraction module extracts air from the container body. The first contaminant removal module is coupled to the air extraction module and the exchange module. The processing module is coupled to the air extraction module. The second contaminant removal module is coupled to the processing module and the exchange module. The controller module is configured to turn the air extraction module on and off. |
| US11854847B2 |
Reticle pod with spoiler structure
A reticle pod with a spoiler structure includes a body and a cover. A reticle allocation area is centrally disposed at the body. The cover covers the body. A peripheral area of the cover and a peripheral area of the body are fitted together by a protruding portion and a dented portion. The dented portion and the protruding portion jointly form a spoiler structure surrounding the reticle allocation area. The spoiler structure includes a spoiler passage between the dented portion and the protruding portion. The body has at least one sidewall corresponding in position to the spoiler passage to form a particle-collecting space. Particles carried by external air current which enters the spoiler passage end up in the particle-collecting space and thus are denied entry into the reticle allocation area. |
| US11854845B2 |
System for monitoring environment
A system for monitoring an environment can be used for monitoring concentrations of airborne contaminants in a plurality of process areas in a clean room. The system includes: a sampling device, configured to collect environmental samples from process areas and including a system sampling pipeline, the environmental sample including air; an analysis device, connected to an output end of the system sampling pipeline; an air supply device, connected to the system sampling pipeline and configured to provide a purge gas to the system sampling pipeline; and a humidification device, configured to provide water mist and connected between the air supply device and the system sampling pipeline. |
| US11854843B2 |
Substrate stage, substrate processing apparatus, and temperature control method
A substrate stage includes: a base portion having a mounting surface; an annular support configured to support a substrate; an annular partition wall configured to divide the mounting surface into an outer region and an inner region in a radial direction of the substrate; a plurality of protrusions provided on the mounting surface and configured to support the substrate with a gap left between an upper end surface of the partition wall and the substrate; an outer flow path in communication with the outer region, and configured to allow a heat transfer gas supplied to a space between the substrate and the mounting surface to flow therethrough; an inner flow path in communication with the inner region, and configured to allow the heat transfer gas to flow therethrough; and an annular diffusion portion configured to diffuse the heat transfer gas along a circumferential direction of the partition wall. |
| US11854841B2 |
Space filling device for wet bench
The disclosed techniques include a space filling device to be used with a wet bench in chemical replacement procedures. The space filling device has an overall density that is higher than the chemicals used to purge the wet bench. As such, when embedded into the wet bench, or more specifically, the chemical tank of the wet bench, the space filling device will occupy a portion of the interior volume space. As a result, less purging chemicals are used to fill and bath the wet bench. |
| US11854839B2 |
Valve apparatuses and related methods for reactive process gas isolation and facilitating purge during isolation
An isolation valve assembly including a valve body having an inlet and an outlet. The isolation valve includes a seal plate disposed within an interior cavity of the valve body. The seal plate is movable between a first position allowing gas flow from the inlet to the outlet, and a second position preventing gas flow from the inlet to the outlet. The isolation valve includes a closure element disposed within the valve body. The closure element is configured to retain the seal plate stationary in the first position or the second position. The closure element includes a first sealing element positioned adjacent to a first surface of the seal plate. A working surface of the first sealing element is substantially obscured from the gas flow when the seal plate is stationary. |
| US11854837B2 |
Semiconductor devices and methods of manufacturing
Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks. |
| US11854832B2 |
Semiconductor device structure having a profile modifier
A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture. The profile modifier is disposed within the aperture to modify a profile of the aperture in a plan view. The contact feature is disposed within the aperture. |
| US11854830B2 |
Method of manufacturing circuit board
A method of manufacturing a circuit board includes preparing a substrate having electrical conductivity, removing a portion of a first surface of the substrate to form a plurality of pillars on the first surface of the substrate, locating an insulating material on the first surface of the substrate to cover a space between the plurality of pillars of the substrate, forming a pattern on a second surface, which is opposite to the first surface of the substrate, by removing a portion of the second surface of the substrate, forming a first metal layer on the first surface of the substrate, and forming a second metal layer on the second surface of the substrate. |
| US11854829B2 |
Method for structuring a substrate
A method for structuring a substrate is specified, in particular structuring by means of selective etching in the semiconductor and IC substrate industry, in which the following steps are carried out: providing a substrate, applying a titanium seed layer, full-area coating with a photoresist layer, lithographic structuring of the photoresist layer, in order to expose regions of the titanium seed layer, selectively depositing copper as conductor tracks in those areas in which the titanium seed layer is exposed, removing the structured photoresist, and etching the titanium seed layer in the areas previously covered by the structured photoresist, wherein phosphoric acid is used to etch the titanium seed layer and, in addition, exposure to UV light is carried out during the etching of the titanium. |
| US11854819B2 |
Germanium hump reduction
The present disclosure provides methods of forming semiconductor devices. A method according to the present disclosure includes receiving a workpiece that includes a stack of semiconductor layers, depositing a first pad oxide layer on a germanium-containing top layer of the stack, depositing a second pad oxide layer on the first pad oxide layer, depositing a pad nitride layer on the second pad oxide layer, and patterning the stack using the first pad oxide layer, the second pad oxide layer, and the pad nitride layer as a hard mask layer. The depositing of the first pad oxide layer includes a first oxygen plasma power and the depositing of the second pad oxide layer includes a second oxygen plasma power greater than the first oxygen plasma power. |
| US11854815B2 |
Substrate drying apparatus, substrate drying method and storage medium
A substrate drying apparatus, a substrate drying method and a storage medium are capable of sublimating a sublimable substance filled in recesses of a pattern formed on a substrate while preventing pattern collapse. A first unit includes a solution supplier which supplies a sublimable substance solution containing a sublimable substance and a solvent to a processing surface, and a first liquid remover which forms a solid film of the sublimable substance on the processing surface by removing the solvent and a processing liquid from the processing surface. A second unit includes a second liquid remover which vaporize the solvent and the processing liquid remaining in the solid film by heating the substrate, and maintaining the substrate at a temperature within a first temperature range, and a solid film remover which remove the solid film from the processing surface by heating the substrate at a temperature within a second temperature range. |
| US11854813B2 |
Low temperature deposition of pure molybenum films
Methods for depositing molybdenum films on a substrate are described. The substrate is exposed to a molybdenum halide precursor and an aluminum precursor to form the molybdenum film (e.g., elemental molybdenum) at a low temperature. The exposures can be sequential or simultaneous. |
| US11854808B2 |
Photo mask and lithography method using the same
A photo mask includes a plurality of device features, a first assist feature, and a second assist feature. The device features are in a patterning region of a device region. The first assist feature are in the patterning region and adjacent to the device features. The first assist feature is for correcting an optical proximity effect in a photolithography process. The second assist feature is in a non-patterning region of the device region. The second assist feature is a sub-resolution correction feature, and a first distance between the second assist feature and one of the device features closest to the second assist feature is greater than a second distance between adjacent two of the device features. |
| US11854805B2 |
Method for producing SiGe-based zones at different concentrations of Ge
A method for forming SiGe-based regions with different Ge concentrations is provided. After defining the regions 1, 2 on a SOI substrate, a grating of masking patterns is formed on at least one region 2. After the epitaxial growth of a Ge-based layer in each of the regions, a first vertical diffusion is carried out. A second horizontal diffusion is then carried out such that the Ge diffuses beneath the masking patterns of the region 2. Thus, the region 2 has a Ge concentration that is lower than the Ge concentration of the region 1. |
| US11854802B2 |
Super-flexible transparent semiconductor film and preparation method thereof
The present invention discloses a super-flexible transparent semiconductor film and a preparation method thereof, the method includes: providing an epitaxial substrate; growing a sacrificial layer on the epitaxial substrate; stacking and growing at least one layer of Al1-nGanN epitaxial layer on the sacrificial layer, wherein 0 |
| US11854801B2 |
Method and device for depositing a nano-object
A method for depositing an object, including: —approaching, in an enclosure, a holder in the direction of a carrier substrate, then—transferring, in the enclosure, the object from the holder to an area for depositing the carrier substrate. The transfer step is preferably carried out when the inside of the enclosure is in a vacuum at a pressure below 10−6 bar. |
| US11854800B2 |
Device and method for high pressure anneal
Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam. |
| US11854798B2 |
Semiconductor device and method
A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask. |
| US11854796B2 |
Semiconductor device structure with gate spacer
A semiconductor device structure is provided. The structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The structure also includes a sealing element extending along a sidewall of the gate stack. The sealing element has a first atomic layer and a second atomic layer, and the first atomic layer and the second atomic layer have different atomic concentrations of carbon. The structure further includes a spacer element over the sealing element. |
| US11854793B2 |
Semiconductor wafer cleaning apparatus
A semiconductor wafer cleaning apparatus is provided. The semiconductor wafer cleaning apparatus includes a spin base, a spindle, a clamping member, and a first sealing ring. The spin base has a through hole and a flange. The spindle extends through the through hole. The clamping member covers the through hole and is connected to the spindle. The clamping member includes a mounting part. The first sealing ring is disposed under the clamping member. A top surface of the first sealing ring and a top surface of the flange are in contact with a bottom surface of the mounting part. |
| US11854790B2 |
Global shutter CMOS image sensor and method for making the same
The disclosure discloses a global shutter CMOS image sensor, which adopts non-uniform storage diffusion region doping to reduce the junction leakage at storage points, so as to ensure that with the increase of the depth of photodiodes and the increase of pixels, all carriers in rows read subsequently can be transferred to storage diffusion regions, the loss of the carriers in the storage diffusion regions is not caused when a global shutter transistor is turned on, and the carriers can be completely transferred from the storage diffusion regions to floating diffusion regions through second transfer transistors even if the number of rows of pixel units increases during reading-out row by row. The disclosure further discloses a method for making the global shutter CMOS image sensor. |
| US11854789B2 |
Method for manufacturing gate structure with additional oxide layer
Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure over a substrate and forming a sealing layer surrounding the dummy gate structure. The method includes forming a spacer covering the sealing layer and removing the dummy gate structure to form a trench. The method further includes forming an interfacial layer and a gate dielectric layer. The method further includes forming a capping layer over the gate dielectric layer and partially oxidizing the capping layer to form a capping oxide layer. The method further includes forming a work function metal layer over the capping oxide layer and forming a gate electrode layer over the work function metal layer. In addition, a bottom surface of the capping oxide layer is higher than a bottom surface of the spacer. |
| US11854787B2 |
Advanced lithography and self-assembled devices
Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described. |
| US11854783B2 |
Micro device arrangement in donor substrate
This disclosure is related to arranging micro devices in the donor substrate by either patterning or population so that there is no interfering with unwanted pads and the non-interfering area in the donor substrate is maximized. This enables to transfer the devices to receiver substrate with fewer steps. |
| US11854781B2 |
Electrophoretic mass spectrometry probes and systems and uses thereof
The invention generally relates to electrophoretic mass spectrometry probes and systems and methods of uses thereof. In certain aspects, the invention provides a mass spectrometry probe having a hollow body with a distal tip, an electrically conductive hollow conduit, and an electrode. The electrically conductive hollow conduit may be operably coupled to a reservoir and a power source, and the electrically conductive hollow conduit may be configured to transport a liquid sample into the hollow body and polarize the liquid sample as it flows through the electrically conductive hollow conduit and into in the hollow body. The electrode and the electrically conductive hollow conduit are disposed within the hollow body (e.g., at different heights within the hollow body). |
| US11854780B2 |
Methods, mediums, and systems for identifying samples of interest by vector comparison
Exemplary embodiments provide methods, mediums, and systems for comparing a sample of interest to a library of known compounds to quickly determine how similar the sample is to the compounds in the library. Peaks of interest in the sample data are compared to corresponding peaks in the library compound data. These peaks may be represented as vectors, and an angle between the sample vector and the library vector may be used as a similarity metric. In some embodiments, a cosine similarity may be calculated for the vectors. If the similarity score for a given library compound/sample pair exceed a threshold, then the system determines that the library compound and the sample are similar and takes appropriate action. Various parameters associated with the comparison can be adjusted in order to improve the quality of the results and/or the efficiency of the process. |
| US11854775B2 |
Methods and apparatus for microwave plasma assisted chemical vapor deposition reactors
The disclosure relates to microwave cavity plasma reactor (MCPR) apparatus and associated optical measurement system that enable microwave plasma assisted chemical vapor deposition (MPACVD) of a component such as diamond while measuring the local surface properties of the component while being grown. Related methods include deposition of the component, measurement of the local surface properties, and/or alteration of operating conditions during deposition in response to the local surface properties. As described in more detail below, the MPCR apparatus includes one or more electrically conductive, optically transparent regions forming part of the external boundary of its microwave chamber, thus permitting external optical interrogation of internal reactor conditions during deposition while providing a desired electrical microwave chamber to maintain selected microwave excitation modes therein. |
| US11854772B2 |
Plasma processing apparatus and plasma processing method
A plasma processing apparatus according to an exemplary embodiment includes a processing container, a stage, a dielectric plate, an upper electrode, an introduction part, a driving shaft, and an actuator. The stage is provided in the processing container. The dielectric plate is provided above the stage via a space in the processing container. The upper electrode has flexibility, is provided above the dielectric plate, and provides a gap between the dielectric plate and the upper electrode. The introduction part is an introduction part of radio frequency waves that are VHF waves or UHF waves, is provided at a horizontal end portion of the space. The driving shaft is coupled to the upper electrode on a central axial line of the processing container. The actuator is configured to move the driving shaft in a vertical direction. |
| US11854771B2 |
Film stress control for plasma enhanced chemical vapor deposition
Embodiments of the present disclosure include methods and apparatus for depositing a plurality of layers on a large area substrate. In one embodiment, a processing chamber for plasma deposition is provided. The processing chamber includes a showerhead and a substrate support assembly. The showerhead is coupled to an RF power source and a ground and includes a plurality of perforated gas diffusion members. A plurality of plasma applicators is disposed within the showerhead, wherein one plasma applicator of the plurality of plasma applicators corresponds to one of the plurality of perforated gas diffusion members. Further, a DC bias power source is coupled to a substrate support assembly. |
| US11854767B2 |
Measuring method and plasma processing apparatus
A measuring method includes placing a substrate on an electrostatic chuck disposed inside a chamber, attracting the substrate onto the electrostatic chuck, generating plasma inside the chamber, detecting an amount of light reflected at the substrate by light emission of the plasma, and calculating a natural frequency of the substrate based on the amount of light. |
| US11854765B2 |
Multiple charged-particle beam apparatus and methods
Systems and methods of mitigating Coulomb effect in a multi-beam apparatus are disclosed. The multi-beam apparatus may include a charged-particle source configured to generate a primary charged-particle beam along a primary optical axis, a first aperture array comprising a first plurality of apertures having shapes and configured to generate a plurality of primary beamlets derived from the primary charged-particle beam, a condenser lens comprising a plane adjustable along the primary optical axis, and a second aperture array comprising a second plurality of apertures configured to generate probing beamlets corresponding to the plurality of beamlets, wherein each of the plurality of probing beamlets comprises a portion of charged particles of a corresponding primary beamlet based on at least a position of the plane of the condenser lens and a characteristic of the second aperture array. |
| US11854763B1 |
Backscattered electron detector, apparatus of charged-particle beam such as electron microscope comprising the same, and method thereof
The present invention provides a backscattered electron (BSE) detector comprising two or more detection components that are electrically isolated from each other. Each of the detection components includes a single continuous top metal layer configured for directly receiving incident backscattered electrons and for backscattered electron to penetrate therethrough. The thickness of one of the top metal layers is different from the thickness of another one of the top metal layers. The BSE detector can be used in an apparatus of charged-particle beam for imaging a sample material. Signals from the detection components having top metal layers of different thicknesses can be inputted into different signal amplifier circuits to get different energy bands of BSE image. |
| US11854762B1 |
MEMS sample holder, packaged product thereof, and apparatus of charged-particle beam such as electron microscope using the same
The present invention provides a MEMS sample holder comprising an observation section. The observation section includes a first layer, a second layer, and a sample compartment between the first layer and the second layer. The sample compartment is configured for filling a liquid sample and observing the liquid sample filled therewithin. The sample compartment has one, two or more windows through which an electron beam can pass. Each of the windows is formed on two cavities including a first cavity on the first layer and a second cavity on the second layer that is opposite to the first cavity across the sample compartment. |
| US11854761B2 |
Radiation anode target systems and methods
Presented systems and methods facilitate efficient and effective generation and delivery of radiation. A radiation generation system can comprise: a particle beam gun, a high energy dissipation anode target (HEDAT); and a liquid anode control component. In some embodiments, the particle beam gun generates an electron beam. The HEDAT includes a solid anode portion (HEDAT-SAP) and a liquid anode portion (HEDAT-LAP) that are configured to receive the electron beam, absorb energy from the electron beam, generate a radiation beam, and dissipate heat. The radiation beam can include photons that can have radiation characteristics (e.g., X-ray wavelength, ionizing capability, etc.). The liquid anode control component can control a liquid anode flow to the HEDAT. The HEDAT-SAP and HEDAT-LAP can cooperatively operate in radiation generation and their configuration can be selected based upon contribution of respective HEDAT-SAP and the HEDAT-LAP characteristics to radiation generation. |
| US11854759B2 |
Arrangement of conduction-cooled travelling wave tubes and method for manufacturing an arrangement
An arrangement of conduction-cooled travelling wave tubes includes multiple travelling wave tubes mounted on a common base, wherein the travelling wave tubes are thermally connected to the base so that during operation of the travelling wave tubes the base forms a heat sink for the travelling wave tubes, and the base is designed to accommodate multiple travelling wave tubes in terms of their dimensions along their beam axes so as to increase the number of travelling wave tubes per surface area unit of the base. |
| US11854756B2 |
Two-part solenoid plunger
Provided herein is an improved solenoid electrical switch. In some embodiments, a solenoid electrical switch may include a plunger at least partially disposed in a central aperture of a solenoid for rotation and axial reciprocation between at least two positions into and out of the central aperture relative to a magnetic coupling member. The plunger may include a first component including a main body and a central slot within the main body, and a second component at least partially disposed within the central slot, wherein the second component may include an engagement surface engaged with an inner surface of the central slot. |
| US11854755B2 |
Direct current electric circuit interrupting switch assembly
A direct current electric circuit interrupting switch assembly is disclosed that comprises a pyroswitch assembly, which comprises at least two pyroswitches, which are connected in parallel with each other and are each per se integrated in its respective electrically conductive branch together forming a second branch of the primary electric conductor the switch assembly, with a first, preceding pyroswitch and a second, subsequent, or last pyroswitch. Each of said pyroswitches comprises an interrupting member, by means of which each circuit with each of the pyroswitches is either connected during normal operation or is interrupted by displacing each corresponding interrupting member into another position, when a pre-determined condition is met. |
| US11854748B2 |
Thin film high polymer laminated capacitor manufacturing method
A thin film high polymer laminated capacitor includes: a laminated chip including dielectric layers, and internal electrode layers including first metal layers including a first metal vapor-deposited on the dielectric layers, and second metal layers including a second metal vapor-deposited on the first metal layers. The dielectric layers and the internal electrode layers being laminated and bonded alternately, and external electrodes formed on one end and the other end of the laminated chip. The laminated chip having a first region having the first metal layers formed on the dielectric layers, which are laminated alternately, and edge regions having the second metal layers formed on layers connected to the one end and layers connected to the other end in the first metal layers, which are laminated alternately, the first region having a capacitor function region, and the edge region having a heavy edge. |
| US11854747B2 |
Stacked capacitor, connected capacitor, inverter, and electric vehicle
A stacked capacitor includes a body having opposing faces, first side faces in a first direction, and second side faces in a second direction. The body includes a first insulation margin without a first metal film and a second insulation margin without a second metal film. The first metal film includes a metal film edge overlapping the second insulation margin. The second metal film includes a metal film edge overlapping the first insulation margin. The first and second metal films each include multiple sub-films separated by multiple first slits. A first slit includes a first portion extending from the first or second insulation margin along the first side faces and a second portion located in the metal film edge and extending at an angle with the first side faces. The second portion has a length in the first direction greater than or equal to an interval between adjacent first slits. |
| US11854743B2 |
Dielectric composition, electronic device, and multilayer electronic device
A dielectric composition includes main-phase particles each including a main component having a perovskite crystal structure represented by a general formula of ABO3. At least a part of the main-phase particles has a core-shell structure. The dielectric composition includes RA, RB, M, and Si. Each of A, B, RA, RB, and M is one or more elements selected from a specific element group. SRA/SRB>CRA/CRB is satisfied, where CRA is an RA content (mol %) to the main component in terms of RA2O3, and CRB is an RB content (mol %) to the main component in terms of RB2O3, in the dielectric composition, and SRA is an average RA content (mol %), and SRB is an average RB content (mol %), in a shell part of the core-shell structure. |
| US11854740B2 |
Capacitor block having a spacer
A capacitive block for electrical equipment includes a housing, at least one capacitive element having a first end housed in the housing and a second end, which is opposite to the first end and which extends out of the housing, an end-stop being fixed to the second end of the at least one capacitive element, and at least one spacer, which butts against the end-stop, so as to determine the distance between the second end of the at least one capacitive element and a bottom of the housing. |
| US11854736B2 |
Method of preparing a high-coercivity sintered NdFeB magnet
The present disclosure provides a method for preparing a high-coercivity sintered NdFeB magnet. The method including the steps of: S1, Providing a NdFeB powder as a main material; S2, Vacuum coating a layer of a rare earth alloy RxH(100-x) on a surface of a metal nano-powder M to obtain an auxiliary alloy material with a core-shell structure, with R being selected from one or more of Dy, Tb, Pr, Nd, La, and Ce; H being selected from one or more of Cu, Al, and Ga; the nano-powder M being selected from one or more of Mo, W, Zr, Ti, and Nb; 0≤x≤90 wt. %; S3, Adding the auxiliary alloy material obtained by step S2 to the NdFeB powder of step S1 and mixing, then orientation pressing of the mixture to obtain a compact body; and S4, Sintering and annealing treatment of the compact body to obtain the high-coercivity sintered NdFeB magnet. |
| US11854729B2 |
Direct liquid cooled inductor
A vehicle, a vehicle electronics power assembly, and a method for providing and cooling an inductor assembly are provided. The vehicle has provided with a vehicle electrical system with a variable voltage converter (VVC) and an inductor assembly with a core and a winding. A housing is provided with a first housing member and a second housing member. The first and second housing members cooperate to encapsulate the winding and at least a portion of the core of the inductor assembly. The first housing member defines a first inlet and a first outlet, and the second housing member defines a second inlet and a second outlet. A fluid system is connected to the first inlet, the second inlet, the first outlet, and the second outlet to provide pressurized fluid to the first and second inlets to circulate fluid through the housing. |
| US11854719B2 |
Wire harness
A wire harness has less differences of the amount of deflection caused by the self weight when the wire harness is constructed by arranging the plurality of the electric wire having the different cross-sectional area of the conductor. A wire harness has first and second electric wires arranged side by side in a direction intersecting an axial direction of the electric wires. Each of the first and second electric wires includes a conductor with a plurality of elemental wires, the second electric wire has a larger conductor cross-sectional area than the first electric wire has, the second electric wire has the larger outer diameter of the elemental wires composing the conductor than the first electric wire has, and the second electric wire contains a same or smaller number of elemental wires composing the conductor in comparison with the first electric wire. |
| US11854713B2 |
Cable and harness
A cable includes a plurality of electric wires including a conductor and an insulating member coating a periphery of the conductor, a tape member provided over a periphery of an aggregate configured by laying the plurality of electric wires together, and an outer sheath provided over an outer periphery of the tape member. The tape member includes a mixture of a first fiber having a melting point and a second fiber having a melting point lower than the melting point of the first fiber. The first fiber has the melting point higher than an extrusion molding temperature of the outer sheath, and the second fiber has the melting point lower than the extrusion molding temperature of the outer sheath. |
| US11854711B2 |
Productions of radioisotopes
The present disclosure generally relates to methods and structures for the production of radioisotopes from the thermal neutron irradiation of selected natural isotopes. The methods, structures and operations are applicable to the production of any radioisotope that may be produced from neutron irradiation. |
| US11854705B2 |
Method and system for supporting clinical decisions
A method is for supporting clinical decisions for a diagnosis or therapy of a patient using a medical imaging system. An embodiment of the method includes receiving a procedure order; based on the received procedure order, automatically identifying a clinical context of the ordered procedure; generating preliminary imaging data of at least a part of the patients anatomy; generating feature extraction data based on the identified clinical context and on the preliminary imaging data; extracting at least one clinical context specific feature using the generated feature extraction data; annotating the at least one extracted clinical context specific feature to obtain at least one annotated extracted feature; and selecting, for the identified clinical context, a similar case data set from a reference database of case data sets based on the at least one annotated extracted feature. |
| US11854703B2 |
Simulating abnormalities in medical images with generative adversarial networks
Systems and methods for providing a novel framework to simulate the appearance of pathology on patients who otherwise lack that pathology. The systems and methods include a “simulator” that is a generative adversarial network (GAN). Rather than generating images from scratch, the systems and methods discussed herein simulate the addition of diseases-like appearance on existing scans of healthy patients. Focusing on simulating added abnormalities, as opposed to simulating an entire image, significantly reduces the difficulty of training GANs and produces results that more closely resemble actual, unmodified images. In at least some implementations, multiple GANs are used to simulate pathological tissues on scans of healthy patients to artificially increase the amount of available scans with abnormalities to address the issue of data imbalance with rare pathologies. |
| US11854701B2 |
Time window-based platform for the rapid stratification of blunt trauma patients into distinct outcome cohorts
Provided herein are methods for segregating trauma, e.g., blunt trauma, patients into different cohorts based on risk of multiple organ dysfunction syndrome using patient data obtained within a short time window following injury. The methods are useful in providing treatment to trauma patients, and for separating trauma patients into cohorts. |
| US11854700B1 |
Method of and system for determining a highly accurate and objective maximum medical improvement status and dating assignment
A method of and system for the determination of MMI to assist in injury and exposure claim adjudication by assisting stakeholders access to a metric system analysis based on an objective claim data set. The method and system utilizes a recovery score index for determining whether the individual is medically stable and one or more recovery phase classifications for determining that available treatment has been provided to the individual. Based on these metrics, the present invention is able to determine a highly accurate and objective maximum medical improvement status and dating assignment. |
| US11854698B2 |
Remote diagnostic testing and treatment
A medical diagnostic kit are described. In one example, a medical diagnostic kit includes a container, and a plurality of medical diagnostic test kits located within the container. Each of the plurality of medical diagnostic test kits can include equipment necessary to perform a particular self-administered medical diagnostic test. The plurality of medical diagnostic test kits can include at least a first medical diagnostic kit adapted to facilitate user completion of a first medical diagnostic test and a second medical diagnostic kit adapted to facilitate user completion of a second medical diagnostic test different from the first medical diagnostic test. The container can include a machine-readable code located on an external surface of the container. |
| US11854695B2 |
Medical devices for treating medical conditions
A medical device, such as a neurostimulator, is provided that includes a housing, a power supply, a signal generator and one or more electrodes coupled to the housing. The signal generator is configured to apply one or more electrical impulses to the one or more electrodes for a period of time, the period of time being defined as a single dose. A memory is coupled to the housing and stores a first content corresponding to a time period that has elapsed and a second content corresponding to a number of single doses that have been emitted by the signal generator. The device is configured to switch from an activated mode and a deactivated mode upon a first occurrence of either a specific number of single doses have been emitted by the signal generator or a specific time period has elapsed. |
| US11854693B2 |
Method and system for updating a medical device
The present disclosure includes methods, devices and systems for establishing a connection between a medical device and a remote computing device, receiving an upgrade command at the medical device, storing a current version of persistent data and a current version of executable code in a first storage area of the medical device, transmitting at least the current version of the persistent data to the remote computing device, receiving a second format of the current version of the persistent data and an upgraded version of executable code at the medical device, storing the second format of the current version of the persistent data and the upgraded version of the executable code in a second storage area of the medical device, and executing the upgraded version of the executable code with the second format of the current version of the persistent data. |
| US11854689B2 |
Healthcare performance
Systems, methods, and storage media useful in a healthcare computing platform to provide comprehensive safety measurement scores, and the individual safety measurements that make up the comprehensive safety measurement scores, for multiple hospitals in a geographic area and/or within a healthcare system are provided. Systems, methods, and storage media provided receive changes to individual safety measurements to model how changes to individual measurements impact the comprehensive safety measurement score for a hospital. |
| US11854682B2 |
System and method for implementing physical stimulation service
The present system combines, on a host server, clinician software for accessing a case history database of past results/feedback from users seeking stimulation therapy, other users within a member network and other users outside the member network and pharmacy software for generating, in the form of a database, an expert system/artificial intelligence program and signal processing software, stimulation waveforms required by the users according to prescriptions from clinicians (completed by clinical experts/server knowledge software) and/or pain points indicated by the users, wherein an innovative open terminal data format and file format and an innovative high-efficiency frequency band waveform compression technique are used. The present method and system embed innovative software tools into an innovative stimulation controller in a wired or wireless connection and a client device of an innovative skin carrier set related thereto so as to assist users in using imaging, sensing, augmented reality and software technology to identify stimulation points, and measure skin impedance, and provide other innovative tool solutions. |
| US11854678B2 |
Systems, methods, compositions and devices for personalized nutrition formulation and delivery system
The disclosed apparatus, systems and methods relate to the delivery of personalized nutraceutical products to a subject, comprising a library of actives; a software module; and a dispensing unit. In certain aspects, the system further comprises a packaging unit and a delivery unit. According to certain aspects, the library of actives comprises a plurality of active nutraceutical ingredients formulated for precise dispensing. In further aspects, the software module is constructed and arranged to receive prescription information for the subject and to output dispensing instructions to the dispensing unit. In still further aspects, the dispensing unit is constructed and arranged to receive dispensing instructions from the software module and to dispense one or more actives from the library of actives to form a nutraceutical product, and wherein the dispensing instructions are derived from the prescription information and customized to the nutritional needs of the subject. |
| US11854677B2 |
Event tracking for advanced therapy medicinal products
There is provided a system for tracking events associated with a treatment by personalised medicine, the system comprising a plurality of nodes hosting a blockchain. The plurality of nodes include a plurality of sequence manager nodes, each associated with a respective sequence manager contract on the blockchain, and a hub node associated with a hub contract on the blockchain. A first sequence manager contract of the sequence manager contracts is arranged to receive first event data indicating a first event associated with the treatment, and store the first event data on the blockchain in association with a first event sequence. The hub contract is arranged to store an association between the first event sequence and one or more further event sequences associated with the treatment, on the blockchain. |
| US11854673B2 |
Systems and methods for managing caregiver responsibility
Methods and systems for managing patient attributions are provided. Interaction events between clinicians and the patient are identified, and using times associated with each interaction, a time series of the interactions for each clinician may be constructed. Care responsibility curves measuring a clinician's care responsibility level over time may be generated using the time series, an initial care responsibility level assigned to each interaction and a rate of decay for each interaction, which may be based on the type of action and type of clinician who interacted with the patient. A care responsibility score for each clinician may be determined from the clinician's care responsibility curve, and a patient-attribution assignment record may be created to attribute the patient to one of the clinicians based on a ranking of the clinicians' care responsibility scores. |
| US11854670B2 |
Running multiple experiments simultaneously on an array of chemical reactors
A method for executing multiple chemical experiments in parallel may be provided. The method comprises receiving a list of actions to be performed for synthesizing a chemical product. Thereby, the actions correspond to at least two chemical partial reactions and the list comprises a delimiter symbol separating two chemical partial reactions, determining identical chemical partial reactions, and building a reaction commonality tree (RCT) of the chemical reactions. Furthermore, the method comprises executing a plurality of the identical chemical partial reactions independent of a sequence of chemical partial reactions of the reaction commonality tree only once. Each of the identical chemical partial reactions is executed in a different chemical reactor and each resulting intermediate product has a quantity of the sum of the related identical chemical partial reactions. The method also comprises, storing the intermediate chemical products in a separate container, and executing remaining chemical partial reactions according to the RCT. |
| US11854669B1 |
Synthetic nucleic acids for information storage and transmission
The present invention relates to method for storing and transmitting information by employing a nucleic acid construct. The nucleic acid construct can include a lock region; a translation key region that corresponds to the identity of a key; and a message region including a nucleic sequence that corresponds to an encrypted message. |
| US11854667B2 |
System for determination of temperature cycling protocols for polymerase chain reactions:plymerase extension
In one aspect, methods are described herein for enhancing one or more nucleic acid interactions. For example, in some embodiments, methods of enhancing one or more steps of polymerase chain reaction (PCR) are described herein. In some embodiments, the optimal temperature cycling protocol for one or more PCR cycles can be determined according to methods described herein. |
| US11854661B2 |
Copy data in a memory system with artificial intelligence mode
The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation. |
| US11854660B2 |
Slew signal shaper circuit using two signal paths
To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route. |
| US11854656B2 |
Memory refresh
Performing refresh operation in a memory device is provided. A refresh operation without address rotation is performed in a cell array of the memory device. Performing the refresh operation without address rotation is repeated for a predetermined number of times. After repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array. |
| US11854652B2 |
Sense amplifier sleep state for leakage savings without bias mismatch
A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state. |
| US11854647B2 |
Voltage level shifter transition time reduction
A level shifter receives an input signal in a first power domain and generates a corresponding output signal in a second power domain. The transition time of the output signal may be longer during a low-to-high transition than during a high-to-low transition or vice versa. The level shifter may provide two outputs, wherein one of the two outputs has a shorter transition time during a high-to-low transition and the other output has a shorter transition time during a low-to-high transition. By using an inverter on the second output, two non-inverted outputs are generated with different transition times. A ramp selection circuit is used to select between the first output and the inverted second output. The ramp selection circuit selects the output with the shortest transition time. |
| US11854645B2 |
Memory system storage device with power loss protection circuit
A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source. |
| US11854642B2 |
Memory test methods and related devices
A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved. |
| US11854636B2 |
Data sampling circuit and semiconductor memory
A data sampling circuit includes a frequency dividing circuit, a sampling circuit and a selection circuit. The frequency dividing circuit is configured to receive a first data sampling signal, and perform frequency dividing processing on the first data sampling signal to obtain multiple second data sampling signals associated with respective phases; the sampling circuit is configured to receive the multiple second data sampling signals and a first data signal, and sample the first data signal according to the multiple second data sampling signals to obtain multiple second data signals associated with respective phases; and the selection circuit is configured to receive preamble information and mode register set (MRS) information, and select among the multiple second data sampling signals and the plurality of second data signals according to the preamble information and the MRS information to obtain a target data sampling signal and a target data signal respectively. |
| US11854634B2 |
Selectable trim settings on a memory device
The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells. |
| US11854633B2 |
Anti-fuse memory cell state detection circuit and memory
A state detection circuit of an anti-fuse memory cell includes a first switching element, having a first end connected to a power supply, a second end connected to a first node, and a control end connected to a controller; an anti-fuse memory cell array including a plurality of anti-fuse memory cell sub-arrays, bit lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the first node, and word lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the controller; and a comparator, having a first input end connected to the first node, and a second input end connected to a reference voltage. |
| US11854629B2 |
System and method for non-parametric optimal read threshold estimation using deep neural network
A scheme for non-parametric optimal read threshold estimation of a memory system. The memory system includes a memory device including pages and a controller including a neural network. The controller performs read operations on a selected page using a read threshold set; obtain the read threshold set, a checksum value and an asymmetric ratio of ones count and zeros count which are associated with decoding of the selected page according to each of the read operations; provide the obtained read threshold set, the checksum value and the asymmetric ratio as input information to the neural network; and estimate, by the neural network, an optimal read threshold voltage based on the input information and weights including a combination of multiple matrices and bias vectors. |
| US11854625B2 |
Device and method for operating the same
A device is disclosed herein. The device includes at least two transmit portions and at least one contact portion. Each of the at least two transmit portions is configured to receive a bit line signal. The at least one contact portion is couple to the at least two transmit portions respectively and configured to transmit the bit line signals from the least two transmit portions to a source line. |
| US11854624B2 |
Non-volatile memory device and erasing operation method thereof
A non-volatile memory device and a non-volatile memory erasing operation method is provided. The method includes the following. A first erasing operation is performed, including reducing a threshold voltage of each of a plurality of memory cells of the non-volatile memory through a first erasing pulse. A first verification operation is performed to confirm whether the threshold voltage of each of the memory cells is less than an erasing target voltage level. In response to at least one of the memory cells failing the first verification operation, a second erasing operation is performed. The second erasing operation includes selecting the at least one memory cell failing the first verification operation, and reducing the threshold voltage of the at least one memory cell to be less than the erasing target voltage level through a second erasing pulse. |
| US11854623B2 |
Memory controller, memory device and memory system having improved threshold voltage distribution characteristics and related operating methods
Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions. |
| US11854619B2 |
Memory device with content addressable memory units
In some embodiments, the present disclosure relates to a memory device, including a plurality of content addressable memory (CAM) units arranged in rows and columns and configured to store a plurality of data states, respectively. A CAM unit of the plurality of CAM units includes a first ferroelectric memory element, a plurality of word lines extending along the rows and configured to provide a search query to the plurality of CAM units for bitwise comparison between the search query and the data states of the plurality of CAM units, and a plurality of match lines extending along the columns and configured to output a plurality of match signals, respectively from respective columns of CAM units. A match signal of a column is asserted when the data states of the respective CAM units of the column match corresponding bits of the search query. |
| US11854616B2 |
Memory including metal rails with balanced loading
Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading. |
| US11854611B2 |
Aggressive quick-pass multiphase programming for voltage distribution state separation in non-volatile memory
A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events. |
| US11854609B2 |
Memory with reduced capacitance at a sense amplifier
A memory is provided that includes multiple memory banks, each one of the memory banks being associated with a read multiplexer. A first read multiplexer couples a first plurality of bit lines to a first sense node pair, and a second read multiplexer couples a second plurality of bit lines to a second sense node pair. A first sense amplifier is coupled to the first sense node pair. The second sense node pair may be coupled to the same sense amplifier or a different sense amplifier. |
| US11854606B2 |
Sense amplifier and method for controlling the same
A sense amplifier includes a first power terminal, a second power terminal, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor. When the sense amplifier works, by outputting appropriate sequential logic signals to the four switching units respectively, controlling the on and off of the four switching units. |
| US11854605B2 |
State detection circuit for anti-fuse memory cell, and memory
A state detection circuit for an anti-fuse memory cell includes: amplifier, having first input terminal connected with first reference voltage, second input terminal connected with first node and output terminal connected with second node; anti-fuse memory cell array, including anti-fuse memory cell sub-arrays, bit lines of sub-arrays are connected with first node, word lines of sub-arrays are connected with controller and each sub-array includes anti-fuse memory cells; first switch element, having first terminal connected with power supply, second terminal connected with first node and control terminal connected with second node; second switch element, having first terminal connected with power supply, second terminal connected with third node and control terminal connected with second node; third switch element, having first terminal connected with third node, grounded second terminal and control terminal connected with controller; and comparator, having first and second input terminals connected with third node and second reference voltage respectively. |
| US11854603B2 |
Logical to encoded value table in data storage device
A data storage device including, in one implementation, a memory device and a controller configured to configured to retrieve a plurality of physical memory addresses from a first lookup table in the non-volatile memory. Each physical memory address is a combination of a word line and a string number of the non-volatile memory and the each physical memory address has a first number of bits. The controller is further configured to generate a plurality of encoded values by encoding the plurality of physical memory addresses. Each of the plurality of encoded values has a second number of bits that is smaller than the first number of bits. The controller is further configured to store the plurality of encoded values in the first lookup table, generate a logical to encoded value look-up table with the plurality of encoded values, and store the logical to encoded value look-up table in the memory. |
| US11854602B2 |
Read clock start and stop for synchronous memories
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, wherein the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode. |
| US11854601B2 |
Apparatuses, systems, and methods for read clock timing alignment in stacked memory devices
Apparatuses, systems, and methods for read clock timing alignment in a stacked memory. An interface die provides a read clock to a core die. The core die includes a serializer which generates data with timing based on the read clock and an adjustable delay circuit which provides a delayed read clock back to the interface die. The interface die outputs the data with timing based on the delayed read clock received from the core die. In this way, the read clock passes along a return clock path from the interface die, through a delay circuit of the core die and back to the interface die before controlling data output timing. Each core die may adjust the timing of the delay of the read clock in order to better align the read clock with the timing of data provided from that die. |
| US11854593B2 |
Ferroelectric memory device integrated with a transition electrode
A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate. |
| US11854587B2 |
Low power wake up for memory
Disclosed herein are related to reducing power consumption of a memory device when transitioning from a sleep state to an operational state. In one aspect, the memory device includes a memory cell to store data. In one aspect, the memory device includes an output driver configured to: generate an output signal indicating the stored data, in response to a sleep tracking signal indicating that the memory cell is in the operational state, and generate the output signal having a predetermined voltage irrespective of the stored data, in response to the sleep tracking signal indicating that the memory cell is in the sleep state. In one aspect, the sleep tracking signal is delayed from a sleep control signal causing the memory cell to operate in the sleep state or the operational state. |
| US11854581B2 |
Magnetic recording devices using virtual side shields for improved areal density capability
Embodiments of the present disclosure generally relate to a magnetic media drive employing a magnetic recording device. The magnetic recording device comprises a trailing gap disposed adjacent to a first surface of a main pole, a first side gap disposed adjacent to a second surface of the main pole, a second side gap disposed adjacent to a third surface of the main pole, and a leading gap disposed adjacent to a fourth surface of the main pole. A side shield surrounds the main pole and comprises a heavy metal first layer and a magnetic second layer. The first layer surrounds the first, second, and third surfaces of the main pole, or the second, third, and fourth surfaces of the main pole. The second layer surrounds the second and third surfaces of the main pole, and may further surround the fourth surface of the main pole. |
| US11854578B2 |
Shift hub dock for incident recording systems and methods
An incident recorder records original and supplemental incident information using a simplified user interface. A lead incident recorder may request any of several support tasks be accepted by other subsystems configured to Follow. Tactical support tasks may be requested. Communication support tasks may be requested. Collection support tasks may be requested. Collection support tasks may include directives for operation of an incident recorder. |
| US11854577B2 |
Hard disk device simulator, testing system using hard disk device simulators and testing method thereof
A hard disk device simulator, a testing system using the hard disk device simulator and a testing method thereof are disclosed. The hard disk device simulator having a detection circuit is serially connected to a test port of a device under test, and a test program is executed on the device under test to read a signal link status of an insertion slot of the device under test and transmit a detection command through the test port, to drive a detection circuit of the hard disk device simulator to detect signals on a power pin, a clock pin and a system management bus, to generate a detection result, thereby verifying correctness of the device under test based on the signal link status and the detection result. As a result, the technical effect of reducing the cost of testing the device under test can be achieved. |
| US11854574B2 |
Interactive chatbot algorithm between human and companion animals through analysis of companion animal's emotions and states based on companion animal's voice and activity information
A method of operating a chatbot based on a companion animal's emotion by using a user terminal, according to an embodiment of the present disclosure includes receiving voice information and activity amount information from an TOT device when receiving a chatting value from a user; calculating a basic emotion variable, a situation variable, and a behavior pattern variable based on the voice information and the activity amount information; and searching for an answer value corresponding to the chatting value under conditions of the basic emotion variable, the situation variable, and the behavior pattern variable to output the searched answer value, wherein the TOT device includes a microphone and a behavior sensor and generates the voice information and the activity amount information by detecting a crying sound and a behavior of the companion animal wearing the TOT device. |
| US11854573B2 |
Alternate response generation
Techniques for performing conversation recovery of a system/user exchange are described. In response to determining that an action responsive to a user input cannot be performed, a system may determine a topic to recommend to a user. The topic may be unrelated to the original substance of the user input. The system may have access to various data representing a context in which a user provides an input to the system. The system may use these inputs and various data at runtime to make a determination regarding whether a user should be recommended a topic, as well as what that topic should be. The system may cause a question be output to the user, with the question asking the user about the topic, for example whether the user would like a song played, whether the user would like to hear information about a particular individual (e.g., artist), whether the user would like to know about a particular skill (e.g., a skill having a significantly high popularity among users of the system), or whether the user would like to know about some other topic. If the user responds affirmatively to the recommended topic, the system may pass the user experience off to an appropriate component of the system (e.g., one that is configured to perform an action related to the topic). If the user responds negatively, does not respond at all, or the system is unsure whether the user's response was affirmative or negative, the system may cease interaction with the user, thereby enabling the user to interact with the system as the user desires. |
| US11854570B2 |
Electronic device providing response to voice input, and method and computer readable medium thereof
An electronic apparatus, method, and computer readable medium are provided. The electronic apparatus includes a communicator, and a controller. The controller, based on a first voice input being received, controls the communicator to receive data including first response information corresponding to the first voice input from a server, and outputs the first response information on a display, and based on a second voice input being received, controls the communicator to receive data including second response information corresponding to the second voice input from the server, and outputs the second response information on the display. Based on whether the second voice input is received within a predetermined time from a time corresponding to the output of the first response information, whether a use of utterance history information is identified, and the second response information is displayed differently based on whether the second voice input is received within the predetermined time. |
| US11854566B2 |
Wearable system speech processing
A method of processing an acoustic signal is disclosed. According to one or more embodiments, a first acoustic signal is received via a first microphone. The first acoustic signal is associated with a first speech of a user of a wearable headgear unit. A first sensor input is received via a sensor, a control parameter is determined based on the sensor input. The control parameter is applied to one or more of the first acoustic signal, the wearable headgear unit, and the first microphone. Determining the control parameter comprises determining, based on the first sensor input, a relationship between the first speech and the first acoustic signal. |
| US11854564B1 |
Autonomously motile device with noise suppression
A device capable of autonomous motion may move in an environment and may receive audio data from a microphone. A model may be trained to process the audio data to suppress noise from the audio data. The model may include an encoder that includes one or more convolutional layers, one or more recurrent layers, and a decoder that includes one or more convolutional layers. |
| US11854561B2 |
Low-frequency emphasis for LPC-based coding in frequency domain
The invention provides an audio encoder including a combination of a linear predictive coding filter having a plurality of linear predictive coding coefficients and a time-frequency converter, wherein the combination is configured to filter and to convert a frame of the audio signal into a frequency domain in order to output a spectrum based on the frame and on the linear predictive coding coefficients; a low frequency emphasizer configured to calculate a processed spectrum based on the spectrum, wherein spectral lines of the processed spectrum representing a lower frequency than a reference spectral line are emphasized; and a control device configured to control the calculation of the processed spectrum by the low frequency emphasizer depending on the linear predictive coding coefficients of the linear predictive coding filter. |
| US11854559B2 |
Decoder for decoding an encoded audio signal and encoder for encoding an audio signal
A schematic block diagram of a decoder for decoding an encoded audio signal is shown. The decoder includes an adaptive spectrum-time converter and an overlap-add-processor. The adaptive spectrum-time converter converts successive blocks of spectral values into successive blocks of time values, e.g. via a frequency-to-time transform. Furthermore, the adaptive spectrum-time converter receives a control information and switches, in response to the control information, between transform kernels of a first group of transform kernels including one or more transform kernels having different symmetries at sides of a kernel, and a second group of transform kernels including one or more transform kernels having the same symmetries at sides of a transform kernel. Moreover, the overlap-add-processor overlaps and adds the successive blocks of time values to obtain decoded audio values, which may be a decoded audio signal. |
| US11854555B2 |
Audio signal processing apparatus, method of controlling audio signal processing apparatus, and program
An audio signal processing apparatus in which different pieces of predetermined parameter information regarding acoustic transfer in a head of a listener are retained as preset candidates, a parameter information list including the retained preset candidates is presented, to prompt a user to select parameter information, and an audio signal for the user is generated by using the user-selected parameter information. |
| US11854554B2 |
Method and apparatus for combined learning using feature enhancement based on deep neural network and modified loss function for speaker recognition robust to noisy environments
Presented are a combined learning method and device using a transformed loss function and feature enhancement based on a deep neural network for speaker recognition that is robust to a noisy environment. The combined learning method using the transformed loss function and the feature enhancement based on the deep neural network for speaker recognition that is robust to the noisy environment, according to an embodiment, may comprise: a preprocessing step for learning to receive, as an input, a speech signal and remove a noise or reverberation component by using at least one of a beamforming algorithm and a dereverberation algorithm using the deep neural network; a speaker embedding step for learning to classify an utterer from the speech signal, from which a noise or reverberation component has been removed, by using a speaker embedding model based on the deep neural network; and a step for, after connecting a deep neural network model included in at least one of the beamforming algorithm and the dereverberation algorithm and the speaker embedding model, for speaker embedding, based on the deep neural network, performing combined learning by using a loss function. |
| US11854550B2 |
Determining input for speech processing engine
A method of presenting a signal to a speech processing engine is disclosed. According to an example of the method, an audio signal is received via a microphone. A portion of the audio signal is identified, and a probability is determined that the portion comprises speech directed by a user of the speech processing engine as input to the speech processing engine. In accordance with a determination that the probability exceeds a threshold, the portion of the audio signal is presented as input to the speech processing engine. In accordance with a determination that the probability does not exceed the threshold, the portion of the audio signal is not presented as input to the speech processing engine. |
| US11854548B1 |
Adaptive conversation support bot
Systems and techniques for adaptive conversation support bot are described herein. An audio stream may be obtained including a conversation of a first user. An event may be identified in the conversation using the audio stream. A first keyword phrase may be extracted from the audio stream in response to identification of the event. The audio stream may be searched for a second keyword phrase based on the first keyword phrase. An action may be performed based on the first keyword phrase and the second keyword phrase. Results of the action may be out via a context appropriate output channel. The context appropriate output channel may be determined based on a context of the conversation and a privacy setting of the first user. |
| US11854545B2 |
Privacy mode based on speaker identifier
Techniques for configuring a speech processing system with a privacy mode that is associated with the identity of a user that activated the privacy mode are described. A user may speak an indication to have the speech processing system activate a privacy mode. When such an indication is detected by the speech processing system, the speech processing system determines an identity of the user, determines a unique system identifier associated with the user, and generates a privacy mode flag. The speech processing system then associates the privacy mode flag with the user's unique system identifier. The privacy mode flag indicates to components of the speech processing system that any data related to processing of the user's utterances should not be sent to long term storage, thus causing various components of the system to delete data once the respective component is finished processing with respect to an utterance of the user. |
| US11854543B2 |
Location-based responses to telephone requests
A method for receiving processed information at a remote device is described. The method includes transmitting from the remote device a verbal request to a first information provider and receiving a digital message from the first information provider in response to the transmitted verbal request. The digital message includes a symbolic representation indicator associated with a symbolic representation of the verbal request and data used to control an application. The method also includes transmitting, using the application, the symbolic representation indicator to a second information provider for generating results to be displayed on the remote device. |
| US11854541B2 |
Dynamic microphone system for autonomous vehicles
Devices, systems and processes for a dynamic microphone system that enhances the passenger experience in autonomous vehicles are described. One example method for enhancing a passenger experiences includes generating, using an artificial intelligence algorithm, a plurality of filters based on a plurality of stored waveforms previously recorded by each of one or more passengers and a plurality of recordings of one or more noise sources, capturing voice commands from at least one of the one or more passengers inside the autonomous vehicle, generating voice commands with reduced distortion based on processing the voice commands using the plurality of filters, and instructing, based on the voice commands with reduced distortion, the autonomous vehicle to perform one or more actions. |
| US11854539B2 |
Intelligent automated assistant for delivering content from user experiences
Systems and processes for operating an intelligent automated assistant are provided. In one example process, a speech input is received from a user. In response to determining that the speech input corresponds to a user intent of obtaining information associated with a user experience of the user, one or more parameters referencing a user experience of the user are identified. Metadata associated with the referenced user experience is obtained from an experiential data structure. Based on the metadata, one or more media items associated with the referenced are retrieved based on the metadata. The one or more media items associated with the referenced user experience are output together. |
| US11854538B1 |
Sentiment detection in audio data
Described herein is a system for sentiment detection in audio data. The system processes audio frame level features of input audio data using a machine learning algorithm to classify the input audio data into a particular sentiment category. The machine learning algorithm may be a neural network trained using an encoder-decoder method. The training of the machine learning algorithm may include normalization techniques to avoid potential bias in the training data that may occur when the training data is annotated for a perceived sentiment of the speaker. |
| US11854537B2 |
Systems and methods for parsing and correlating solicitation video content
Aspects relate to systems and methods for parsing and correlating solicitation video content. An exemplary system includes a computing device configured to receive a solicitation video related to a subject, where the solicitation video includes at least an image component and at least an audio component, where the audio component includes audible verbal content related to at least an attribute of the subject, transcribe at least a keyword as a function of the audio component, and associate the subject with at least a job description as a function of the at least a keyword. |
| US11854536B2 |
Keyword spotting apparatus, method, and computer-readable recording medium thereof
A keyword spotting apparatus, method, and computer-readable recording medium are disclosed. The keyword spotting method using an artificial neural network according to an embodiment of the disclosure may include obtaining an input feature map from an input voice; performing a first convolution operation on the input feature map for each of n different filters having the same channel length as the input feature map, wherein a width of each of the filters is w1 and the width w1 is less than a width of the input feature map; performing a second convolution operation on a result of the first convolution operation for each of different filters having the same channel length as the input feature map; storing a result of the second convolution operation as an output feature map; and extracting a voice keyword by applying the output feature map to a learned machine learning model. |
| US11854532B2 |
System to detect and reduce understanding bias in intelligent virtual assistants
Disclosed is a system and method for detecting and addressing bias in training data prior to building language models based on the training data. Accordingly system and method, detect bias in training data for Intelligent Virtual Assistant (IVA) understanding and highlight any found. Suggestions for reducing or eliminating them may be provided This detection may be done for each model within the Natural Language Understanding (NLU) component. For example, the language model, as well as any sentiment or other metadata models used by the NLU, can introduce understanding bias. For each model deployed, training data is automatically analyzed for bias and corrections suggested. |
| US11854529B2 |
Method and apparatus for generating hint words for automated speech recognition
Systems and methods for determining hint words that improve the accuracy of automated speech recognition (ASR) systems. Hint words are determined in the context of a user issuing voice commands in connection with a voice interface system. Terms are initially taken from most frequently occurring terms in operation of a voice interface system. For example, most frequently occurring terms that arise in electronic search queries or received commands are selected. Certain of these terms are selected as hint words, and the selected hint words are then transmitted to an ASR system to assist in translation of speech to text. |
| US11854528B2 |
Method and system for detecting unsupported utterances in natural language understanding
An apparatus for detecting unsupported utterances in natural language understanding, includes a memory storing instructions, and at least one processor configured to execute the instructions to classify a feature that is extracted from an input utterance of a user, as one of in-domain and out-of-domain (OOD) for a response to the input utterance, obtain an OOD score of the extracted feature, and identify whether the feature is classified as OOD. The at least one processor is further configured to executed the instructions to, based on the feature being identified to be classified as in-domain, identify whether the obtained OOD score is greater than a predefined threshold, and based on the OOD score being identified to be greater than the predefined threshold, re-classify the feature as OOD. |
| US11854518B2 |
Electronic musical instrument, electronic musical instrument control method, and storage medium
An electronic musical instrument includes an operation unit that receives a user performance; and at least one processor. wherein the at least one processor performs the following: in accordance with a user operation specifying a chord on the operation unit, obtaining lyric data of a lyric and obtaining a plurality of pieces of waveform data respectively corresponding to a plurality of pitches indicated by the specified chord; inputting the obtained lyric data to a trained model that has been trained and learned singing voices of a singer so as to cause the trained model to output acoustic feature data in response thereto; synthesizing each of the plurality of pieces of waveform data with the acoustic feature data so as to generate a plurality of pieces of synthesized waveform data; and outputting a polyphonic synthesized singing voice based on the generated plurality of pieces of synthesized waveform data. |
| US11854517B2 |
Soundboards and backboards for acoustic stringed instruments
Soundboards and backboards of an acoustic stringed instrument and methods of manufacturing the same are disclosed. In one embodiment, the soundboard or backboard includes a base having opposed top and bottom surfaces, a plurality of channels on the bottom surface of the base, and a plurality of braces that correspond to the plurality of channels and that are received in and attached to the plurality of channels. In one embodiment, the method includes shaping a board to a uniform nominal thickness and carving a plurality of channels on the board via a Computer Numerically Controlled (CNC) router. The method additionally includes attaching a plurality of braces that correspond to the carved plurality of channels such that the plurality of braces is received in the plurality of channels. |
| US11854516B1 |
Slip nut assembly
Musical cymbals are mounted on a tripod stand using a threaded rod which is several inches in length. A conventional nut is then threaded on the rod which has to be turned a multiple number of times until the nut abuts the cymbal thereby securing the cymbal on the rod. Using the slip nut assembly of this invention eliminates this time consuming installation procedure of the nut and similarly eliminates the time consuming uninstalling of the nut when the musician is to move to a different playing location. |
| US11854514B2 |
Drumhead with reduced volume
A reduced volume drumhead has a layer of porous material and a ring of compressible material. The ring of compressible material is fixed to the underside of the layer of porous material in a substantially centered or coaxial position with the porous material stretched across a hoop in tension. The ring may be formed of a foam or similar material with compressibility and stretchability under tension and defines an open central area of the drumhead for striking. The ring may be formed of segments and thus include one or more circumferential breaks with spacing. The drumhead provides natural tonal characteristics and has a natural feel when struck. |
| US11854512B2 |
Display device and method of image rewinding thereof
A display device is provided, which includes an image buffer, a display module, and a display controller. The display controller is used for receiving an image signal from a host, and storing the image signal in the image buffer. In response to the display controller receiving a trigger signal, the display controller controls the display device to enter an image-rewinding mode. The display controller obtains a retrospective image that corresponds to a retrospective time point according to a user command, and plays the retrospective image on the display module. |
| US11854504B2 |
Display device
A display device includes: a display panel having a display region in which pixels are arranged; scan lines each coupled to the pixels arranged in a row direction; signal lines each coupled to the pixels arranged in a column direction; a signal line drive circuit; a scan line drive circuit selecting the scan lines; and a signal processing circuit. A second half period of a selection period of a first scan line overlaps a first half period of a selection period of a second scan line. The signal processing circuit adjusts a pixel gradation value of the pixel in an m-th column coupled to the second scan line when a difference value between the pixel gradation value of the pixel in the m-th column coupled to the first scan line and an average gradation value of the pixels arranged in the m-th column is larger than a predetermined value. |
| US11854503B2 |
Wireless electronic label and system comprising the same
A wireless electronic label comprises a display module, a rectenna module and a control drive module. The display module has a display surface. The rectenna module is disposed on the display surface of the display module. The rectenna module is used to receive an electromagnetic wave signal and convert it into an electrical energy signal. The rectenna module is made of light-transmitting electronically conductive material. The control drive module is used to convert the electrical energy signal into electrical energy to power the wireless electronic label and to send a command signal to the display module. The display module is further used to display a label signal on the display surface according to the command signal. |
| US11854502B2 |
Display method, display system, and recording medium storing display program
A display method includes displaying an image on a display surface; and differentiating a brightness or a color tone of a first part of the image corresponding to a first user whose face is directed to the display surface, from a brightness or a color tone of a second part of the image that is different from the first part, based on a movement of eyelids of the first user. |
| US11854499B2 |
Controller, display device including the same, and method of driving display device using the same
A display device is disclosed that includes a display panel, a controller, and a data driver. The controller is configured to determine first luminances with respect to a reference grayscale in a second frame when the reference grayscale is displayed in the second frame after the reference grayscale is displayed in a first frame. The controller is configured to determine second luminances with respect to the reference grayscale in the second frame when the reference grayscale is displayed in the second frame after a minimum grayscale is displayed in the first frame. The controller is further configured to temporally and spatially arrange first data corresponding to the reference grayscale and second data corresponding to the minimum grayscale to generate a data signal. And, the controller is configured to drive the display panel with a digital driving method in a first grayscale section, and drive the display panel with an analog driving method in a second grayscale section. The data driver is configured to generate a data voltage based on the data signal. |
| US11854498B2 |
Display device having a plurality of sub-pixels for displaying odd or even numbered grayscale levels
According to an aspect of the present disclosure, a display device includes a display panel which includes sub pixels configured by an upper sub pixel and a lower sub pixel which share a data line and are adjacent to each other; and a data driver which converts only image data corresponding to any one of even-numbered grayscale levels and odd-numbered grayscale levels among 10-bit image data into a data voltage to supply the converted data voltage to the sub pixel, in which when the data driver converts only the even-numbered grayscale levels of image data into the data voltage and the sub pixel displays an X (X is an odd number) grayscale level, the data driver supplies an X−1 grayscale level of data voltage to the upper sub pixel and supplies an X+1 grayscale level of data voltage to the lower sub pixel. |
| US11854496B2 |
Display device and driving method thereof
The display device includes a display panel in which a first display area and a second display area adjacent to the first display area are defined, a data driving circuit which drives the plurality of data lines, a scan driving circuit which drives the plurality of scan lines, and a driving controller which receives an image signal and a control signal, and controls the data driving circuit and the scan driving circuit based on an operation mode, where the driving controller includes a luminance deviation compensation unit which compensates for luminance deviation of the first display area and the second display area when the operation mode is a multi-frequency mode in which the first display area is driven at a first frequency and the second display area is driven at a second frequency different from the first frequency. |
| US11854491B2 |
Mode switching in display device for driving a display panel
A display driver includes a GRAM, a data driver, and a control circuit. The data driver is configured to: update, in a first mode, display elements of a display panel based on a command provided to the display driver asynchronously with a display vertical sync signal; update, in a second mode, the display elements based on image data stored in the GRAM in synchronization with the display vertical sync signal; and update, in a third mode, the display elements in synchronization with an external vertical sync signal. The control circuit is configured to: switch the display drive to a second mode in response to a first command; adjust, in the second mode, the display vertical sync signal based on an external vertical sync signal; and switch the display driver to the third mode after achieving synchronization of the display vertical sync signal with the external vertical sync signal. |
| US11854489B2 |
Display substrate and manufacturing method thereof, and display device
A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, and a shift register unit, a first clock signal line and a second clock signal line which are on the peripheral region of the base substrate; the first clock signal line and the second clock signal line extend along a first direction; an active layer of the first control transistor, an active layer of the second control transistor, and an active layer of the third control transistor respectively extend along a second direction, and the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are on a side of the first clock signal line and the second clock signal line close to the display region, and are arranged side by side in the first direction. |
| US11854486B2 |
Organic light emitting diode display
An organic light emitting diode display with improved aperture ratio includes: a substrate; first and second pixels disposed in a first row of the substrate and third and fourth pixels disposed in a second row adjacent to the first row and respectively disposed in the same columns as the first and second pixels; a scan line and a previous scan line applying a scan signal and a previous scan signal, respectively, to the pixel units; a data line and a driving voltage line applying a data signal and a driving voltage, respectively, to the pixel units; and a common initialization voltage line disposed between the first and second pixels and between the third and fourth pixels, commonly connected to the pixel units, and applying an initialization voltage. One common initialization contact hole connected to all pixels units and one initialization voltage line connected to the common initialization contact hole are surrounded by the pixel units. |
| US11854483B2 |
Display device, pixel circuit, and method for driving same
The present application discloses a current-driven display device of an internal compensation type in which threshold compensation of a drive transistor is appropriately performed without causing a decrease in display quality or a decrease in yield during manufacturing, and display luminance is improved while a drive voltage is maintained. A pixel circuit 15 in the display device includes first and second drive transistors M1a, M1b, and the gate terminals thereof are connected to each other and connected to a holding capacitor Cs. During the data write period, a voltage of a corresponding data signal line Dj is written to the holding capacitor Cs via the first drive transistor M1a, having been set in a diode connection mode by a threshold compensation transistor M3, to perform data writing accompanied by threshold compensation. During the emission period, a current corresponding to the sum of currents I1, I2 flowing through the first and second drive transistors M1a, M1b in accordance with the holding voltage of the holding capacitor Cs is supplied to an organic EL element OL as a drive current Id. |
| US11854482B1 |
Pixel drive circuit and display panel
A pixel drive circuit, including a data input circuit, a switch circuit, an energy storage circuit and a light-emitting control circuit. The light-emitting control circuit has a control end connected to the data input circuit, an input connected to a first power supply, and an output connected to an anode of a light-emitting device. A cathode of the light-emitting device is connected to a second power supply. The first power supply outputs a low-potential voltage in a reset phase, and outputs a first high-potential voltage in a compensation phase, a writing phase and a light-emitting phase. The second power supply outputs a second high-potential voltage in the reset, compensation and writing phases, and output a low-potential voltage in the light-emitting phase. The switch circuit is switched on in the reset, compensation and light-emitting phases, and is switched off in the writing phase. |
| US11854481B1 |
Display panel and display device
A display panel includes a display area and a non-display area surrounding the display area. The display area includes a plurality of display lines and a plurality of display sub-pixels arranged in arrays. The non-display area further includes a dummy sub-pixel, a driver chip, a feedback line and a compensation line. The driver chip is used for acquiring a current signal of a light-emitting element in the dummy sub-pixel through the feedback line, and generating a compensation signal when the current signal fed back by the feedback line is not equal to the preset threshold value, and also for generating a display compensation signal when the current signal fed back by the feedback line is equal to the preset threshold value, and the display compensation signal is transmitted to the pixel driving circuit of the display sub-pixel through the display line. |
| US11854478B2 |
Display device and drive method for same
The present application discloses a current-driven display device that can perform accurate external compensation in consideration of a temperature distribution in a display panel while preventing the configuration from being complicated. A display portion of an organic EL display device is provided with a plurality of temperature detection circuits in addition to pixel circuits arranged in a matrix. A data-side drive circuit measures a current flowing through a transistor in each temperature detection circuit. A display control circuit obtains a temperature from the measured value based on a temperature characteristic of the transistor, estimates a temperature of each pixel circuit from the temperature, corrects a current value measured at the time of characteristic detection for a drive transistor of each pixel circuit considering the estimated temperature, and updates correction data for compensating for variations in the threshold voltage and gain of the drive transistor based on the corrected current value. |
| US11854477B2 |
Display device and pixel circuit thereof
A pixel circuit includes a capacitor, a light emitting control transistors, a driving transistor, and multiple light emitting transistors. The light emitting control transistor includes a gate electrode coupled to a light emitting control signal, a source electrode coupled to a supply voltage, and a drain electrode. The driving transistor includes a gate electrode coupled to the capacitor, a source electrode coupled to the drain electrode of the light emitting control transistor, and a drain electrode. Each light emitting transistor includes a gate electrode coupled to a respective light emitting signal, a source electrode coupled to the drain electrode of the driving transistor, and a drain electrode coupled to a respective light emitting element. Each light emitting signal turns on the respective light emitting transistor during a respective light emitting period within a frame period to cause the respective light emitting element to emit a light. The light emitting control signal turns on the light emitting control transistor during each light emitting period within the frame period. |
| US11854476B1 |
Timing controller having mechanism for frame synchronization, display panel thereof, and display system thereof
The disclosure is directed to a timing controller having a mechanism for frame synchronization, a display panel having the timing controller thereof, and a display system having the timing controller thereof. According to an aspect of the disclosure, the disclosure provides an integrated circuit which includes a timing controller to transmit a first TE signal to an application processor and receive a first image frame from the application processor after the application processor receives the first TE signal, and a control circuit to generate a first sync signal when the timing controller receives the first image frame, wherein when the application processor receives a second TE signal and the application processor is not ready to transmit a second image frame to the timing controller, the control circuit delays a first waiting period to generate a second sync signal. |
| US11854475B2 |
Display device
Disclosed herein is a display device for preventing a luminance floatation phenomenon in a low grayscale region. The display device includes a display panel, an external input interface configured to receive an image signal from an external device, and a controller configured to adjust a gamma value when an input frequency of the image signal is less than an output frequency of the display panel and a variable refresh rate (VRR) function for changing the output frequency according to the input frequency is activated and to output the image signal to the display panel based on the adjusted gamma value. |
| US11854474B2 |
Display panel, display device, and electronic device
A display device includes: a display panel including display elements each including a light emitting unit and a drive circuit for driving the light emitting unit, the display elements being arranged in a two-dimensional matrix on a substrate; and a luminance correction unit for correcting luminances of the display elements in display of an image by the display panel by correcting a gradation value of a video signal, in which a partition (60) for guiding stray light from a light emitting unit to an optical sensor (4) provided on the display panel is provided between adjacent light emitting units of the display panel, and the luminance correction unit corrects a gradation value of a video signal associated with each of the display elements on the basis of a gradation value of an uncorrected video signal and a detection result from the optical sensor. |
| US11854472B1 |
Pixel driving circuit and display panel
A pixel driving circuit and a display panel are provided. The pixel driving circuit, including a first-color subpixel, a second-color subpixel, and a third-color subpixel, is configured to drive a pixel unit. The pixel driving circuit includes a first driving unit, a second driving unit, and a third driving unit. The first driving unit is configured to drive according to a first voltage signal the first-color subpixel. The second driving unit is configured to drive according to the first voltage signal the second-color subpixel. The third driving unit is configured to drive according to the first voltage signal the third-color subpixel. The first driving unit at least includes a first capacitor, the second driving unit at least includes a second capacitor, the third driving unit at least includes a third capacitor, and at least one of the first capacitor, the second capacitor, and the third capacitor has a different capacitance. |
| US11854470B2 |
Display device
A display device includes a display panel, a data driver, a scan driver, and a light emitting driver. The display panel includes a first display area and a second display area. The display panel displays a first image on the first display area and the second display area in a first mode, and displays a second image on the first display area in a second mode. The light emitting driver activates emission control signals applied to the first display area and the second display area in the first mode. The light emitting driver activates emission control signals applied to the second display area during a first partial frame in the second mode, and maintains the emission control signals applied to the second display area in a deactivation state during a plurality of second partial frames in the second mode. |
| US11854462B1 |
Display system and operating method thereof
A display system and an operating method thereof are provided. The display system includes a display panel, a source driver, and a timing controller. The source driver is coupled to the display panel for providing a plurality of pixel voltages to the display panel. The timing controller has a transmission interface circuit and is coupled to the source driver. The timing controller detects whether an operation timing of the display system enters a vertical blanking (VBK) period. When the operation timing of the display system enters the VBK period, the timing controller turns off the transmission interface circuit and causes the source driver to enter an idle mode. When the operation timing of the display system is at a preset time before an end of the VBK period, the timing controller turns on the transmission interface circuit and wakes up the source driver. |
| US11854460B2 |
Shift register unit, driving circuit, display device and driving method
A shift register unit, a driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first input circuit, a second input circuit, an output circuit, a first control circuit, and a second control circuit. The first input circuit is electrically connected to a first node, and is configured to transmit an input signal to the first node; the second input circuit is electrically connected to the first node and a second node, and is configured to control a level of the second node; the first control circuit is electrically connected to the second node and a third node, and is configured to control a level of the third node; and the output circuit is electrically connected to the third node and an output terminal, and is configured to output an output signal to the output terminal. |
| US11854458B2 |
Driving circuit connecting first control voltage terminal and second voltage control terminal, driving method, shift register and display device
The present disclosure provides a driving circuit, a driving method, a shift register and a display device. The drive circuit includes a first control circuit, a second control circuit, a first output circuit, a second output circuit and an output terminal; the first control circuit is configured to connect or disconnect the first node and the first control voltage terminal under the control of a control signal provided by the control terminal; the second control circuit is configured to connect or disconnect the second node and the second control voltage terminal under the control of the control signal. |
| US11854456B2 |
Electro-optic displays and methods for driving the same
An electro-optic display having a plurality of pixels is driven from a first image to a second image using a first drive scheme, and then from the second image to a third image using a second drive scheme different from the first drive scheme and having at least one impulse differential gray level having an impulse potential different from the corresponding gray level in the first drive scheme. Each pixel which is in an impulse differential gray level in the second image is driven from the second image to the third image using a modified version of the second drive scheme which reduces its impulse differential The subsequent transition from the third image to a fourth image is also conducted using the modified second drive scheme but after a limited number of transitions using the modified second drive scheme, all subsequent transitions are conducted using the unmodified second drive scheme. |
| US11854446B2 |
Display device and method for measuring luminance profile thereof
A method for measuring a luminance profile of a display device including pixels divided into blocks, includes: measuring a first reference luminance profile when a partial area of each of the blocks is in a display state and a remaining area of each of the blocks is in a non-display state; measuring a first luminance profile when an entire area of a first block among the blocks is in the display state, the partial area of each of remaining blocks is in the display state, and the remaining area of each of the remaining blocks is in the non-display state; and measuring a second luminance profile when an entire area of a second block among the blocks is in the display state, the partial area of each of remaining blocks is in the display state, and the remaining area of each of the remaining blocks is in the non-display state. |
| US11854445B2 |
Method for inspecting display device and method for fabricating display device
A method for inspecting a display device includes preparing a target substrate comprising sub-pixels in which light-emitting elements are disposed, dividing each of first regions of the sub-pixels into second regions, obtaining a gray value of each of the second regions, generating a random number using the gray value, calculating a representative value of each of the first regions by reflecting variables in the random number, and summing the representative values of the first regions to calculate a number of light-emitting elements of the sub-pixels. |
| US11854443B2 |
3D holographic display device and operating method of the same
A three-dimensional holographic display device includes a light emitting diode (LED) array including a plurality of light sources controlled to sequentially output light according to a preset pattern, a lens configured to refract light incident from the LED array, a spatial light modulator (SLM) configured to modulate light incident from the lens, and a processor configured to generate a plurality of holographic signals each comprising depth information adjusted according to an arrangement location of each of the plurality of light sources, and for each of the plurality of light sources, control the SLM to modulate the light based on a holographic signal corresponding to the light source. |
| US11854435B2 |
Device for making the electrical movements of moving platforms for simulators safer
A device that makes it possible to make the movements of moving platforms safer and relates more particularly to a linear actuator that can be used in a hexapod positioner supporting a load is provided. The actuator is actuated by electric control and comprises at least one hydraulic damper positioned on the actuator such that the forces generated by damping in the event of extreme breakdown are experienced only by the load and are distributed such as to limit force and acceleration peaks. |
| US11854434B2 |
Virtual reality vehicle operation simulation
An interactive vehicle simulation system having a virtual reality engine that generates a virtual operating environment that includes a user operated vehicle having a plurality of wheel types, a vehicle position, vehicle orientation, vehicle velocity and vehicle acceleration. |
| US11854432B1 |
Developing an e-rater advisory to detect babel-generated essays
Systems and methods are provided for processing a group of essays to develop a classifier that detects nonsensical computer-generated essays. A data structure associated with a group of essays is accessed, wherein the group of essays includes nonsensical computer-generated essays and good-faith essays. Both the nonsensical computer-generated essays and the good-faith essays are assigned feature values. The distribution of feature values between the nonsensical computer-generated essays and the good-faith essays is measured. A classifier that detects whether an essay is a nonsensical computer-generated essay is developed, wherein the classifier is developed using the distribution of feature values. |
| US11854429B2 |
Portable simulated flood discharge culvert for surveying and mapping
Provided is a portable simulated flood discharge culvert for surveying and mapping, including a supporting device, where the supporting device includes a plurality of telescopic support rods, and the telescopic support rods; a tarpaulin, where the tarpaulin is cover on outer walls of the telescopic support rods; connecting devices, where each of the connecting devices is installed between any two adjacent telescopic support rods; floors, where the floors are respectively arranged between the plurality of telescopic support rods, and top surfaces of the floors are provided with a plurality of protrusions; adjusting devices, where each of the adjusting devices includes angle adjusting mechanisms and a height adjusting mechanism, and the angle adjusting mechanisms and the height adjusting mechanism are respectively fixed on a bottom surface of each of the floors; a fog generating device, a lighting part, and additional blocks. |
| US11854426B2 |
System for cosmetic and therapeutic training
Systems and methods are disclosed for an apparatus and method for practicing injection techniques through an injectable apparatus. The injectable apparatus may contain a camera that is configured to detect the intensity and color of light attenuated from a testing tool after it is injected into a simulated human or animal body parts. A training tool may be connected to a user display device to generate a display of the injection apparatus as well as the performance parameters of a trainee. |
| US11854419B2 |
System and method for monitoring food waste
The present invention relates to a system for monitoring food waste. The system includes a weight mechanism configured for weighing a waste receptacle, wherein the waste receptacle is configured for receiving food waste from a plurality of consecutive disposal events before emptying, a processor configured for measuring the difference in weight of the waste receptacle between each disposal event and calculating the weight of a disposal event based upon the difference and a user interface configured to receive at least one indication categorising the food waste in a disposal event by a user. A method for monitoring food waste is also described. |
| US11854418B2 |
Collision awareness using historical data for vehicles
This disclosure is directed to methods, computer program products, and systems for providing surface vehicle tracking data, including indications of potential collision zones, to an airport map display system onboard an aircraft. In one example, a method includes identifying historical navigation route data, aerodrome guidance features, and a predicted path of a first vehicle. The method further includes determining predicted positions along the predicted path and determining predicted positions of a second vehicle and comparing vehicle envelopes for the two vehicles to determine a predicted collision zone of the vehicles. |
| US11854417B2 |
Method and system for calculating and presenting terrain-clearance reachable regions
A method and a system are provided herein for calculating whether or not a specific aerial vehicle at a specified point of time can maneuver over a given location in the terrain while complying with terrain clearance requirements. The system may include a computer memory configured to store a 3D model representing at least a portion of a terrain located in a vicinity of an aerial vehicle; a computer processor configured to map said portion of the terrain into at least two types: a first type indicative of a potential of the aerial vehicle to maneuver over a respective terrain while complying with terrain clearance, and a second type indicative of a non-potential of said aerial vehicle to maneuver over a respective terrain, wherein the mapping is carried out based on said parameters, the 3D model and given predefined performance of the aerial vehicle. |
| US11854416B2 |
Drone station, arrangement, method of operating a drone station, and computer readable memory
According to an example aspect of the present invention, there is provided a drone station comprising a housing having a cavity, and a structure permeable to air and configured to be moved from a first position into a second position and reverse, wherein a platform for landing, storing and starting of a drone is provided by the structure within the cavity in the first position, and wherein an entry into the cavity or an exit out of the cavity through a ventral access is provided for the drone in the second position. |
| US11854409B2 |
Electronic display management device for a head-up display screen and associated display system, management method and computer program product
The invention relates to an electronic device for managing the display of a head-up display system capable of being embarked in a cockpit of an aircraft piloted by at least one pilot and comprising: a display module configured to display a plurality of symbols relative to the operation of the aircraft and its environment in at least two distinct visualization planes, the visualization planes each having a distinct depth along a line of sight from the pilot, a determination module configured to determine a reference visualization plane corresponding to an accommodation plane of the eye of the pilot and a warning module configured to generate a warning to be displayed in the reference visualization plane. |
| US11854408B2 |
Providing an open interface to a flight management system
Providing an open interface to a navigation system is provided herein. A single partition (or more than one partition) of a partitioned operating system can be utilized to provide connectivity between a navigation system and one or more user equipment devices. Thus, the navigation system and the one or more user equipment devices can be communicatively coupled via the at least one partition. Further, a Software Development Kit (SDK) can be configured to enable bi-directional communication between the navigation system and the one or more user equipment devices. In addition, the SDK can provide security for the navigation system when communicating with the one or more user equipment devices. |
| US11854405B2 |
Performing vehicle logistics in a blockchain
An example operation may include one or more of identifying one or more blockchain members of a vehicle platoon placement group, receiving a request to perform a task from the blockchain members, creating a scheduled task date associated with the task, notifying the blockchain members of the scheduled task date, receiving task progress updates corresponding to the blockchain members, and storing the task progress updates in a blockchain. |
| US11854404B2 |
Computing timing intervals for vehicles through directional route corridor
A system computes a timing interval between high-capacity vehicles (HCVs) for each of a plurality of HCV corridors within a geographic region, each respective HCV corridor of the plurality of HCV corridors including a start area. For each respective HCV corridor, the system transmits, via a network communication interface, (i) first data to a first computing device associated with a first HCV, the first data indicating the start area of the respective HCV corridor, and a first start time for the first HCV, and (ii) second data to a second computing device associated with a second HCV, the second data indicating the start area of the respective HCV corridor and a second start time for the second HCV, wherein the first start time for the first HCV and the second start time for the second HCV are based on the computed timing interval for the respective HCV corridor. |
| US11854399B2 |
System for controlling vehicle driving through roundabout and method of controlling the same
A system with control of vehicle driving through a roundabout includes: a position recognizer configured to recognize that a host vehicle is traveling around the roundabout; a front sensor disposed at a front of the host vehicle and configured to sense a vehicle that possibly enters the roundabout while the host vehicle is traveling around the roundabout; a rear sensor disposed at a rear of the host vehicle and configured to recognize a vehicle following the host vehicle while the host vehicle is traveling around the roundabout; a controller configured to calculate a possible entry time of the vehicle that possibly enters the roundabout, using information sensed by the rear sensor; and a communicator configured to provide the calculated possible entry time to the vehicle that possibly enters the roundabout. |
| US11854397B2 |
Rear lateral blind-spot warning system and method for vehicle
A rear lateral blind-spot warning system for a vehicle includes a sensor configured to sense position information and movement information on an external obstacle, a determiner configured to determine the type of the external obstacle located in a rear blind spot or a lateral blind spot of the vehicle based on the position information and the movement information sensed by the sensor, a setter configured to set a rear lateral blind-spot warning range or a rear lateral blind-spot warning time based on the type of the external obstacle determined by the determiner, and a controller configured to control rear lateral blind-spot warning operation based on the rear lateral blind-spot warning range or the rear lateral blind-spot warning time set by the setter. |
| US11854396B2 |
Methods and systems for managing parking lots in smart cities based on the internet of things
The present disclosure provides a method for managing a parking lot in a smart city based on an Internet of Things, which is executed by a management platform. The method comprises obtaining a user position of a user platform based on a service platform, determining a candidate parking lot that meets a preset condition; determining time when a vehicle to be parked arrives at the candidate parking lot based on the user position; determining free parking space information when the vehicle to be parked arrives at the candidate parking lot; determining recommendation information based on the free parking space information; and sending the recommendation information to the user platform based on the service platform. |
| US11854394B1 |
Systems and methods for curated navigational route management
Systems and methods are disclosed for the development and management of curated navigational routes are disclosed. The curated navigational route can be a particular path of travel that is specifically designed for one or more users. The curated navigational routes are carefully constructed paths of travel that are custom defined by a route manager. |
| US11854389B1 |
Systems, methods, and devices for communication between traffic controller systems and mobile transmitters and receivers
Systems, methods, and devices are disclosed for improving traffic safety and efficiency. The system includes various signal transmitters and receivers positioned throughout roadways, within automobiles, in smartphones, or supported by a cellular network backbone, for distributing traffic related information to users and traffic controller equipment. Embodiments of the present disclosure allow for vehicles and/or pedestrians to initiate a dual-transmission of cellular and RF signals for changing a traffic light state, where the first signal received at a traffic intersection controller unit is processed for changing the traffic light state (e.g., changing a light from red to green on-demand). Other embodiments of the present disclosure allow for users to receive visible and/or audible traffic related alerts on mobile devices, where the alerts are based on data shared between nearby drivers, pedestrians, and the traffic controlling equipment. |
| US11854388B2 |
Traffic estimation method and system
A method and apparatus for level of service assessment at signalized intersections is disclosed. In an exemplary embodiment, a method for estimating an average delay per vehicle at a signalized intersection with a traffic signal, including sampling vehicle arrival rates at the signalized intersection, sampling vehicle departure rates at the signalized intersection, analyzing generated shock waves at the traffic signal, wherein the traffic signal shock wave is a change in vehicle density due to changes in the traffic signal, and estimating the average delay per vehicle based on the vehicle arrival rates, the vehicle departure rates, and the traffic shock waves at the signalized intersection. |
| US11854384B2 |
Road lighting
Systems, devices, and methods are disclosed in which one or more light sources, a detector, a processor and a controller are configured such that light from the one or more light sources improves the ability of a human or automated motor vehicle driver to identify and avoid pedestrians. The one or more light sources may provide spot illumination to moving objects or pedestrians on a road surface, with the spot illumination following the moving object or pedestrians along the portion of the road surface. The one or more light sources may project images on the ground or on other surfaces. The light source may be carried by a pedestrian or on personal transport used by a pedestrian. The light sources may be stationary and provide lighting for a pedestrian street crossing. |
| US11854378B1 |
Event indicating light assembly and method
An event indicating light assembly and method for communicating a software application with a pair of lights includes a software application being programmed on an electronic device including a mobile device and a personal computer. The software application is connected with a variety of software calendars to track a plurality of events of a user. A pair of light fixtures is in wireless communication with the electronic device. Each of the light fixtures has a plurality of light emitting diodes being a variety of colors. A microprocessor is positioned within each of the light fixtures and is connected with the plurality of light emitting diodes of each light fixture. A battery is positioned within each of the light fixtures and is in electric communication with the microprocessor and with a charging port. A mounting pad of each of the light fixtures retains the light fixture to a wall. |
| US11854375B1 |
Emergency medical services (EMS) visual light guidance aiding device to guide EMS to a specific location
An emergency medical services (EMS) visual light guidance aiding device is disclosed. The EMS visual light guidance aiding device is configured to aid EMS personnel in guidance to a specific location without maps, apps, or other conventional guidance mechanisms. |
| US11854370B1 |
Security sharing systems and methods
A method may include receiving an alert and a recorded data set from a first monitoring system and receiving a first set of permissions from the first monitoring system. The method may also include determining a permission associated with sharing of the recorded data set based at least in part on the first set of permissions. The method may also include determining that sharing of at least a portion of the recorded data from the first monitoring system is permitted based at least in part on the permission and sharing the at least a portion of the recorded data set. |
| US11854365B2 |
Graphical user interface and networked system for managing dynamic geo-fencing for a personal compliance-monitoring device
A system performs compliance control. This may include a compliance-control device displaying a map, receiving a selection of a location from the map, determining an entity associated with the selection, generating a geo-fence boundary around the selection using a library of geo-fence shapes, and determining a compliance condition with the geo-fence boundary by communicating with a compliance-monitoring device. In various examples, the compliance-monitoring device may determine and transmit a compliance condition on a first time interval. In response to a breach event, the compliance-monitoring device may determine and transmit a set of subsequent compliance conditions on a second time interval that is shorter than the first time interval. The compliance-control device may display a graphical output that corresponds to the compliance condition and one or more of the subsequent compliance conditions. |
| US11854364B1 |
Emergency communication assembly
An emergency communication assembly includes a housing that is positioned in a pre-determined area such that the housing is accessible to a physically limited user in an emergency. A communication unit is integrated into the housing and the communication unit sequentially calls each of a plurality of emergency contact numbers when the communication unit is actuated until one of the emergency contact numbers answers. In this way the communication unit facilitates the physically limited user to communicate with an individual when the physically limited user is experiencing an emergency. A pull string extends outwardly from the housing and the communication unit is turned on when the pull string is pulled by the physically limited user. |
| US11854358B2 |
Monitoring system
A monitoring system for deriving a measurement of a separation distance between a monitor and one or more tags, where each tag is adapted to be attached to or contained within an object to be monitored, comprises a monitor that is operable to trigger an event if the separation distance exceeds a set separation limit. A frequency of packet exchange between a tag and monitor is dynamically altered based on a comparison of one or more. |
| US11854357B2 |
Object tracking using disparate monitoring systems
Methods, systems, apparatus, and computer programs, for tracking objects are disclosed. In one aspect, a method is disclosed that includes actions of obtaining an image, determining that a user of a first monitoring system has opted-in for object tracking by a second monitoring system that is remote from the first monitoring system, and based on a determination that the user of the first monitoring system has opted-in for object tracking: determining whether the obtained image satisfies a predetermined level of similarity to a stored tracking object image model stored on a first device of the first monitoring system, and based on a determination that the obtained image satisfies a predetermined level of similarity to the stored tracking object image model, generating a tracking update notification, and transmitting the tracking update notification to the second monitoring system that is remote from the first monitoring system. |
| US11854356B1 |
Configurable motion detection and alerts for audio/video recording and communication devices
Some embodiments provide a method for separating the motion detection zone(s) of an A/V recording and communication device from the motion alert zone(s) of the A/V recording and communication device. For example, an A/V recording and communication device may be configured to generate motion alerts, and to record audio and video footage, when an event is detected within a selected motion alert zone (e.g., within a defined radius around the A/V recording and communication device). However, the A/V recording and communication device may not generate a motion alert for an event detected outside of the selected motion alert zone, even though the device may still record audio and video footage for the detected event (e.g., when the event is within a selected motion detection zone). |
| US11854354B2 |
Mobile control unit, facility management system, mobile unit control system, facility management method and mobile unit control method
A mobile control unit adapted to move to a plurality of premises, the mobile control unit having a central monitoring system in communication with a facility system of each of the plurality of premises, such that the mobile control unit is adapted to move to one of the plurality of premises when alerted by the facility system of the one of the plurality of premises. A facility management system adapted to manage at least one of the plurality of premises, the facility management system having the mobile control unit and a facility system adapted to monitor each of the plurality of premises. A method of monitoring the plurality of premises using the mobile control unit. A facility management system having a plurality of mobile control units and a main control unit adapted to monitor the location of the plurality of mobile control units. A facility monitoring method having monitoring the location of a plurality of mobile control units from a main control unit; and communicating between the main control unit and the plurality of mobile control units. |
| US11854353B2 |
Height-adjustable kiosk apparatus
A height-adjustable kiosk apparatus includes: a kiosk unit configured to generate processed signals by recognizing and processing an image and a voice, to receive basic signals from a user, to perform output, and to process payment; and a height adjustment unit disposed under the kiosk unit, and equipped with a driving unit configured to be driven to move the kiosk unit up and down based on the processed signals; wherein the kiosk unit includes an image recognition unit, a voice recognition unit, an image processing unit, and a voice processing unit; and wherein the height adjustment unit includes a driving signal generation unit and a priority determination unit. |
| US11854352B2 |
Skill-based gaming machine and method that maintain a desired return to player
A gaming machine having an electronic display which displays a plurality of empty drinking cups. A game controller causes the display of a ball and its movement toward and into one of the empty cups. A game play mechanism allows the player to direct the movement of the ball. If the player is successful in movement of a ball into a cup, the cup and the ball is then removed from the display. During play of the game, an amount of sobriety is determined in accord with the number of cups removed by the player. In accordance with the amount of sobriety determined, the cups are displayed in wobbling movement in order to give amusement to the game as well as difficulty in the play. |
| US11854351B2 |
Systems and methods for facilitating wagering on e-sports games
A gaming system and method which is configured to, among other things, display a user created entry relating to a wager on an e-sports contest in a wager feed through the user interface of other users, and enable any of the other users to enter into the wager by selecting the entry. |
| US11854345B2 |
Systems and methods for supplementing a wagering game
An electronic gaming machine includes a display device and a game controller configured to initiate a feature game that uses a plurality of mechanical reels and the display device, identify a number of feature game symbols initially available for use during the feature game, display a plurality of symbol columns, each symbol column of the plurality of symbol columns is associated with a reel, perform a spin of the reels, in response to the player initiating the play, distribute the number of feature game symbols into the plurality of symbol columns based on an output of a random number generator, each feature game symbol being displayed in a determined symbol column of the plurality of symbol columns, evaluate an outcome of the feature game based on attributing the feature game symbols to associated reels, and award credit to the player based on the evaluating. |
| US11854343B2 |
Fraud detection system in a casino
A fraud detection system which detects fraud in a game of performing collection and redemption of chips in accordance with a win or lose result includes a camera which captures an image of chips contained in a chip tray of a dealer, an image analyzing apparatus which analyses the image captured by the camera to detect an amount of the chips contained in the chip tray, a card distribution device which determines a win or lose result of a game, and a control device which compares the win or lose result of the game and the amount of the chips contained in the chip tray before and after collection and redemption of the chips to detect fraud. |
| US11854332B2 |
Coin distribution mechanism and apparatus for discriminating and conveying coins
A coin distribution mechanism for distributing coins into their denominations during conveyance is provided, which makes it possible to distribute two desired denominations of coins using a single gate member. A first gate member movable around a first axis is provided below a coin conveyance path. The first gate member is moved by a first position switching device among a default position where a gate is closed, a first switched position that allows a coin to drop through the gate to move in a first direction, or a second switched position that allows a coin to drop through the gate to move in a second direction. When a coin has a first (or second) denomination, the first gate member is moved to the first (or second) switched position. When a coin does not have the first and second denominations, the first gate member is located at the default position. |
| US11854328B2 |
Access management system
An access management system includes a mobile device with a processor and a memory and a software platform including at least a processor and a memory. The software platform is configured to analyze data obtained from the mobile device and other devices connected to the software platform. Specifically, the software platform is operable to determine if an access key received, read, or captured by a mobile device matches an access key for an authorized account, object, device, or space for the mobile device, and to provide access to the mobile device if the access key received, read, or captured by the mobile device matches the authorized access key. |
| US11854327B1 |
Secure baggage claim system
The secure baggage claim system uses radio frequency identification (RFID) tags or the like to associate a particular item of baggage with the owner of that item of baggage. The secure baggage claim system includes a housing having a baggage entry opening, a baggage retrieval opening, and a vertically arranged carousel disposed within the housing for carrying and rotating a plurality of baggage carrying trays. A primary RFID tag reader reads a primary RFID tag secured to the item of baggage to associate the item of baggage with identification information corresponding to an individual. The item of baggage is further associated with one of the baggage carrying trays selected to carry the item of baggage. A door releasably covers and seals the baggage retrieval opening and is releasably locked by a locking mechanism. Authenticating input associated with the individual unlocks the door for retrieval of the item of baggage. |
| US11854324B2 |
Intelligent lock
A method for operating an access control comprises creating a plurality of wake-up schedules for a wireless transceiver. Each of the plurality of wake-up schedules may be configured to control how frequently the wireless transceiver wakes up to transmit or receive information. Each of the plurality of wake-up schedules for the wireless transceiver may be different from another one or the plurality of wake-up schedules for the wireless transceiver. The method may further comprise automatically switching between the plurality of wake-up schedules for the wireless transceiver such that a duration of time between wake-ups for the wireless transceiver radio is shorter during some predefined times and longer during other predefined times. The duration of time between wake-ups for the wireless transceiver may be configurable by an administrative user via an interface. |
| US11854318B1 |
User interface for vehicle monitoring
Techniques for presenting a user interface on a display for monitoring and/or controlling a vehicle. The user interface may include a digital representation of an environment in which the vehicle is operation. Additionally, the user interface may include system interface that is configured to display one or more notifications associated with systems or components of the vehicle. The system interface may additionally, or alternatively, comprise one or more control inputs for controlling systems or components of the vehicle. The user interface may also include a mission interface that includes a map interface and a mission selection interface for selecting routes the vehicle is to navigate. The user interface may additionally cause presentation of visual indicators that indicate the presence of an object that is not shown on the user interface, but that is moving in a direction such that the object will soon be visibly displayed on the user interface. |
| US11854313B2 |
Systems and methods for using on-board resources of individual vehicles in a fleet of vehicles as a distributed data center
This disclosure relates to a distributed data center that includes resources carried by a fleet of vehicles. The system includes sensors configured to generate output signals conveying information related to the vehicles. The system may detect vehicle events based on the information conveyed by the output signals. The system includes a remote computing server configured to present a user interface to a user. Through the user interface, the user may query information from one or more vehicles in the fleet. The distributed query is transmitted to individual vehicles, and results are locally processed in accordance with response constraints and subsequently transmitted back to the remote computing server for presentation to the user. |
| US11854311B2 |
Comparison of biometric identifiers in memory
Systems, apparatuses, and methods related to comparison of biometric identifiers in memory are described. An example apparatus includes an array of memory cells, a plurality of logic blocks in complementary metal-oxide-semiconductor (CMOS) under the array, and a controller coupled to the array of memory cells. The controller is configured to control a first portion of the plurality of logic blocks to receive a first subset of a set of biometric identifiers from the array and to perform a first comparison operation thereon and control a second portion of the logic blocks to receive a second subset of the set of biometric identifiers from the array and to perform a second comparison operation thereon. The first and second subsets of the biometric identifiers are different biometric identifiers and the first and second comparison operations are performed to determine a match of the first and second subsets respectively to a stored template. |
| US11854309B2 |
Systems and methods for remotely controlling locomotives with gestures
Exemplary embodiments are disclosed of systems and methods for remotely controlling locomotives with gestures. In an exemplary embodiment, a system is configured for allowing an operator(s) to remotely control operation of a locomotive with gesture(s) made by an operator(s). The system includes at least one processor configured to be operable for visually recognizing gesture(s) made by an operator(s) in one or more images captured by at least one camera. A locomotive control unit is configured to be operable for controlling the operation of the locomotive according to the visually recognized gesture(s) made by the operator(s). |
| US11854306B1 |
Fitness action recognition model, method of training model, and method of recognizing fitness action
A model including an information extraction layer that obtains image information of a training object in a depth image; a pixel point positioning layer that performs position estimation on a three-dimensional coordinate of human-body key points, defines a body part of the training object as a body component, and calibrates a three-dimensional coordinate of all human-body key points corresponding to the body component; a feature extraction layer that extracts a key-point position feature, a body moving speed feature, and a key-point moving speed feature for action recognition; a vector dimensionality reduction layer that combines the key-point position feature, the body moving speed feature, and the key-point moving speed feature as a multidimensional feature vector, and performs dimensionality reduction on the multidimensional feature vector; and a feature vector classification layer that classifies the multidimensional feature vector that is performed with dimensionality reduction, to recognize a fitness action of the training object. |
| US11854300B2 |
Fingerprint module, fingerprint recognition system, and electronic device
A fingerprint module includes: a lens, a crystal, and an optical fingerprint chip, where the crystal is an anisotropic medium, the lens is located on one side of the crystal, the optical fingerprint chip is located on the other side of the crystal, and the optical fingerprint chip is fixed in a substrate of an electronic device. Incident light including fingerprint information is incident to the crystal through the lens and is incident to the optical fingerprint chip after being refracted by the crystal; and the optical fingerprint chip is used for generating a fingerprint image, and the fingerprint image is used for fingerprint recognition. |
| US11854292B2 |
Display device having multilayered cover layer
A display device includes a display panel, a sensing layer disposed on the display panel and including a fingerprint sensor, an optical layer disposed on the display panel, and a cover layer disposed on the optical layer, wherein the cover layer is a multilayer structure. |
| US11854283B2 |
Method and apparatus for visual question answering, computer device and medium
The present disclosure provides a method for visual question answering, which relates to fields of computer vision and natural language processing. The method includes: acquiring an input image and an input question; detecting visual information and position information of each of at least one text region in the input image; determining semantic information and attribute information of each of the at least one text region based on the visual information and the position information; determining a global feature of the input image based on the visual information, the position information, the semantic information, and the attribute information; determining a question feature based on the input question; and generating a predicted answer for the input image and the input question based on the global feature and the question feature. The present disclosure further provides a device for visual question answering, a computer device and a medium. |
| US11854282B2 |
Method for correcting optical character recognition text position, storage medium and electronic device
The present disclosure provides a method for correcting an OCR text position, a storage medium and an electronic device. The method includes: determining a first slope of each text block in an OCR recognition result of a to-be-processed image; fitting a tilt field function in accordance with the first slope of each text block; determining an offset value of each text block in accordance with the tilt field function; and correcting a position of each text block in accordance with the offset value. |
| US11854279B2 |
Vehicle exterior environment recognition apparatus
A vehicle exterior environment recognition apparatus includes a monocular distance calculator, a relaxation distance calculator, and an updated distance calculator. The monocular distance calculator calculates a monocular distance of a three-dimensional object from a luminance image generated by an imaging unit. The relaxation distance calculator calculates a relaxation distance of the three-dimensional object from two luminance images generated by two imaging units based on a degree of image matching between the two luminance images determined using a threshold more lenient than another threshold used to determine the degree of image matching to generate a stereo distance of the three-dimensional object. The updated distance calculator calculates an updated distance of the three-dimensional object by mixing the monocular distance and the relaxation distance at a predetermined ratio. |
| US11854278B2 |
Information processing device and method
The present disclosure relates to an information processing device and method, and a program that enable processing, related to management of a vehicle, to be performed even in a case where no vehicle registration number is recognizable. Feature information of a vehicle is extracted from a captured image on the basis of a detection result of a number plate of the vehicle in the captured image, and the feature information of the vehicle extracted by the feature extraction unit is registered in a predetermined database. The present disclosure can be applied to, for example, an information processing device, an image processing device, a communication device, an electronic device, an information processing method, a program, and the like. |
| US11854277B1 |
Advanced number plate recognition implemented on dashcams for automated amber alert vehicle detection
An apparatus includes a camera and a processing circuit. The camera may be configured to capture images of an environment around a vehicle. The processing circuit may be configured to (i) perform automated number-plate recognition using the images, (ii) store a history of detected license plates, and (iii) search the history of detected license plates in response to receiving a request from a communication device of a vehicle user for information matching the request. |
| US11854276B2 |
Vehicle driver monitoring system for determining driver workload
A vehicular driver monitoring system includes an interior camera viewing at least a head region of a driver of a vehicle. Driver information pertaining to the driver of the vehicle is provided to an electronic control unit (ECU). Based at least in part on (i) processing at the ECU of image data captured by the interior camera and/or (ii) the received driver information, the vehicular driver monitoring system estimates a distraction workload of the driver and a driving workload of the driver. At least in part responsive to processing at the ECU of the estimated distraction workload and the estimated driving workload, the vehicular driver monitoring system determines an amount of driver attention. The amount of driver attention is determined at least in part by weighting the driving workload and the distraction workload based at least in part on driving conditions. |
| US11854267B2 |
System and method for witness report assistant
Techniques for a witness report assistant are provided. At least one camera captures at least one image of an incident scene. The incident scene is a location of an incident. A description is of the incident is received from a witness to the incident. The description of the incident includes a generic reference to an element of the incident scene. The description of the incident scene is transcribed to create a textual description. The element of the incident scene within the at least one image of the incident scene is identified. A specific identifier associated with the element of the incident scene is determined. The textual transcript of the description is supplemented with the specific identifier. |
| US11854262B1 |
Post-disaster conditions monitoring system using drones
A post-disaster conditions monitoring system. The system may include plurality of aircraft drones configured to take photographic images; a conditions monitoring center having a controller including a device processor and a non-transitory computer readable medium including instructions executable by the device processor to perform the following steps: receiving images from the plurality of aircraft drones in a geographic region; determining conditions in the geographic region based on the images received from the plurality of aircraft drones; and sending information regarding the determined conditions to one or more users of the system. |
| US11854261B2 |
Linking to social experiences in artificial reality environments
In one embodiment, a computing system may receive, from a first electronic device associated with a first user, a first request to generate a link associated with an artificial reality application and an action to be performed by the artificial reality application. The computing system may then generate a link to instructions that are executable on an artificial reality device to cause the artificial reality device to launch the artificial reality application and perform the action. The computing system may then receive, from a second electronic device associated with a second user, an indication that the second user activated the link on the second electronic device, and send the instructions associated with the link to an artificial reality device associated with the second user to cause the artificial reality device associated with the second user to launch the artificial reality application and perform the action. |
| US11854260B2 |
Situation-sensitive safety glasses
Techniques disclosed herein combine computer vision with eye tracking by identifying, via computer vision, safety hazards in a video captured by a camera mounted on a pair of safety glasses, and generating an alert if a user wearing the safety glasses has not (recently) noticed the hazard. Whether the user has noticed the hazard is determined based on eye tracking information extracted from a video captured by another camera that is mounted on the safety glasses and points toward the user. As a result, safety hazards may be automatically detected and reported to the user. In addition, only those hazards that have not been (recently) noticed by the user cause an alert to be generated, so the user is not distracted with unnecessary notifications. |
| US11854259B2 |
Holdup measurement using quantized classification and categorized local regression
Aspects of the subject technology relate to determining a holdup measurement based on a gamma spectrum through machine learning. A spectral image based on a gamma spectrum generated downhole in a wellbore can be accessed. A component of a holdup measurement for the wellbore can be classified into a specific quantized level through application of a machine learning classification model to the spectral image. A continuous value for the component of the holdup measurement for the wellbore can be quantified by applying a machine learning quantization model associated with the quantized level. |
| US11854257B2 |
Identifying canopies
Methods, apparatus and computer program for identifying canopy structures are provided. In one aspect, a method includes receiving a first calculated offset between a start point of a shadow cast by a building and a proximate first vertex of a building footprint of the building, and receiving a second calculated offset between an end point of the shadow cast by the building and a proximate second vertex of the building footprint, the shadow identified from an overhead image of the building, and wherein the building footprint comprises a shadowed side and a non-shadowed side, each running between the start point and the end point of the shadow on a different respective side of the building. The method also includes comparing the offsets to an offset threshold, and in response to both the first and second received offsets exceeding the offset threshold, determining that the building footprint represents a canopy. |
| US11854243B2 |
Gaze correction of multi-view images
Gaze is corrected by adjusting multi-view images of a head. Image patches containing the left and right eyes of the head are identified and a feature vector is derived from plural local image descriptors of the image patch in at least one image of the multi-view images. A displacement vector field representing a transformation of an image patch is derived, using the derived feature vector to look up reference data comprising reference displacement vector fields associated with possible values of the feature vector produced by machine learning. The multi-view images are adjusted by transforming the image patches containing the left and right eyes of the head in accordance with the derived displacement vector field. |
| US11854242B2 |
Systems and methods for providing personalized saliency models
Methods, systems, and computer readable media for providing personalized saliency models, e.g., for use in mixed reality environments, are disclosed herein, comprising: obtaining, from a server, a first saliency model for the characterization of captured images, wherein the first saliency model represents a global saliency model; capturing a first plurality of images by a first device; obtaining information indicative of a reaction of a first user of the first device to the capture of one or more images of the first plurality images; updating the first saliency model based, at least in part, on the obtained information to form a personalized, second saliency model; and transmitting at least a portion of the second saliency model to the server for inclusion into the global saliency model. In some embodiments, a user's personalized (i.e., updated) saliency model may be used to modify one or more characteristics of at least one subsequently captured image. |
| US11854241B2 |
Method and apparatus with dilated convolution
A neural network apparatus includes one or more processors configured to acquire an input feature map and trained weights, generate a plurality of sub-feature maps by splitting the input feature map based on a dilation rate, generate a plurality of intermediate feature maps by performing a convolution operation between the plurality of sub-feature maps and the trained weights, and generate a dilated output feature map by merging the plurality of intermediate feature maps based on the dilation rate. |
| US11854236B2 |
Fastening tool system and control method thereof
A fastening tool system for fastening a component part by using a supplied power includes: a camera portion mounted on a fastening tool to photograph a fastening portion of the component part; an image input portion for inputting an image photographed from the camera portion when a distance with the fastening portion measured through a distance measurement sensor is within a predetermined distance; a communication portion for transmitting data by wireless communication; and a fastening portion determining portion that recognizes the fastening portion through machine learning algorithm-based image classification work for an input image of the camera portion and sets a torque value matched with the recognized fastening portion. |
| US11854235B1 |
Lossless integer compression scheme
Decompressing a compressed image to obtain a decompressed image includes receiving, in a compressed stream, compressed pixel values of the compressed image; decompressing, from the compressed stream, a first compressed pixel value of the compressed pixel values using a lossy floating-point decompression scheme to obtain a floating-point pixel value; rounding the floating-point pixel value to a nearest integer to obtain a pixel value of the decompressed image; and displaying or storing the decompressed image. |
| US11854234B2 |
Calibration of mobile electronic devices connected to headsets wearable by users
A mobile electronic device is provided for use with a headset. A camera outputs digital pictures of a portion of the headset. A display device displays information for viewing by a user wearing the headset. A processor retrieves calibration parameters that characterize at least a pose of the camera relative to the display device, and processes a digital picture from the camera to identify a pose of an optically identifiable feature within the digital picture. A pose of the mobile electronic device is identified relative to the holder based on the identified pose of the optically identifiable feature within the digital picture and based on at least the pose of the camera relative to the display device as characterized by the calibration parameters. The processor controls where graphical objects are rendered on the display device based on the identified pose of the mobile electronic device relative to the holder. |
| US11854224B2 |
Three-dimensional skeleton mapping
A system includes processing hardware and a memory storing software code. When executed, the software code receives first skeleton data including a first location of each of multiple skeletal key-points from the perspective of a first camera, receives second skeleton data including a second location of each of the skeletal key-points from the perspective of a second camera, correlates first and second locations of some or all of the multiple skeletal key-points to produce correlated skeletal key-point location data for each of at least some skeletal key-points. The software code further merges the correlated skeletal key-point location data for each of those at least some skeletal key-points to provide merged location data, and generates, using the merged location data and the locations of the first, second, and third cameras, a mapping of the 3D pose of a skeleton. |
| US11854223B2 |
Mixed-reality device positioning based on shared location
Techniques and systems are provided for positioning mixed-reality devices within mixed-reality environments. The devices, which are configured to perform inside out tracking, transition between position tracking states in mixed-reality environments and utilize positional information from other inside out tracking devices that share the mixed-reality environments to identify/update positioning of the devices when they become disoriented within the environments and without requiring an extensive or full scan and comparison/matching of feature points that are detectable by the devices with mapped feature points of the maps associated with the mixed-reality environments. Such techniques can conserve processing and power consumption that would be required when performing a full or extensive scan and comparison of matching feature points. Such techniques can also enhance the accuracy and speed of positioning mixed-reality devices. |
| US11854221B2 |
Positioning system and calibration method of object location
A positioning system and a calibration method of an objection location are provided. The calibration method includes the following. Roadside location information of a roadside unit (RSU) is obtained. Object location information of one or more objects is obtained. The object location information is based on a satellite positioning system. An image identification result of the object or the RSU is determined according to images of one or more image capturing devices. The object location information of the object is calibrated according to the roadside location information and the image identification result. Accordingly, the accuracy of the location estimation may be improved. |
| US11854220B2 |
System and method for measuring the profile of a workpiece
A system and a method for measuring the profile of a part. The measurement system includes a sensor with a probe having at least one degree of freedom, and a first reference element fastened to the probe. The sensor is arranged so that the probe is able to follow the internal or external contour of the part while the first reference element is outside the part. An imaging device is adapted to capture an image representing at least a portion of the outside of the part and the first reference element. Thus, the first reference element serves as a reference element for the position of the probe relative to the reference system that is the part. |
| US11854218B2 |
Systems and methods for terrain variation detection
In one aspect, a method for detecting terrain variations within a field includes receiving one or more images depicting an imaged portion of an agricultural field. The method also includes classifying a portion of the plurality of pixels that are associated with soil within the imaged portion of the agricultural field as soil pixels with each soil pixel being associated with a respective pixel height. Additionally, the method includes identifying each soil pixel having a pixel height that exceeds a height threshold as a candidate ridge pixel and each soil pixel having a pixel height that is less than a depth threshold as a candidate valley pixel. The method further includes determining whether a ridge or a valley is present within the imaged portion of the agricultural field based at least in part on the candidate ridge pixels or the candidate valley pixels. |
| US11854212B2 |
Traffic light detection system for vehicle
A method for operating a vehicle includes detecting a traffic light located at a first spatiotemporal location based on a first digital video stream captured by a first camera and a second digital video stream captured by a second camera. It is determined that the vehicle is located at a second spatiotemporal location by validating first location data received from sensors against second location data obtained by filtering the first location data. It is determined that the traffic light is expected at the first spatiotemporal location based on a semantic map referenced by the second spatiotemporal location. Responsive to determining that the traffic light is expected at the first spatiotemporal location, a traffic signal of the traffic light is detected based on the two digital video streams. A trajectory is determined in accordance with the traffic signal. A control circuit operates the vehicle in accordance with the trajectory. |
| US11854211B2 |
Training multi-object tracking models using simulation
Training a multi-object tracking model includes: generating a plurality of training images based at least on scene generation information, each training image comprising a plurality of objects to be tracked; generating, for each training image, original simulated data based at least on the scene generation information, the original simulated data comprising tag data for a first object; locating, within the original simulated data, tag data for the first object, based on at least an anomaly alert (e.g., occlusion alert, proximity alert, motion alert) associated with the first object in the first training image; based at least on locating the tag data for the first object, modifying at least a portion of the tag data for the first object from the original simulated data, thereby generating preprocessed training data from the original simulated data; and training a multi-object tracking model with the preprocessed training data to produce a trained multi-object tracker. |
| US11854207B2 |
Point cloud segmentation method and device, and computer readable storage medium
The implementation of the present disclosure provides a point cloud partitioning method and device, and a computer-readable storage medium, including: when performing stripe division along the longest side, adjusting an initial partitioning position or determining the stripe division length according to the size of a preset block, to obtain a stripe division position, wherein, the length of the first n−1 stripes along the longest side is an integer multiple of the side length of the preset block, n is the number of divided stripes, and n is a positive integer greater than or equal to 2. |
| US11854206B2 |
Temporally distributed neural networks for video semantic segmentation
A Video Semantic Segmentation System (VSSS) is disclosed that performs accurate and fast semantic segmentation of videos using a set of temporally distributed neural networks. The VSSS receives as input a video signal comprising a contiguous sequence of temporally-related video frames. The VSSS extracts features from the video frames in the contiguous sequence and based upon the extracted features, selects, from a set of labels, a label to be associated with each pixel of each video frame in the video signal. In certain embodiments, a set of multiple neural networks are used to extract the features to be used for video segmentation and the extraction of features is distributed among the multiple neural networks in the set. A strong feature representation representing the entirety of the features is produced for each video frame in the sequence of video frames by aggregating the output features extracted by the multiple neural networks. |
| US11854196B2 |
System and method for real time assay monitoring
A real time assay monitoring system and method can be used to monitor reagent volume in assays for fluid replenishment control, monitor assays in real-time to obtain quality control information, monitor assays in real-time during development to detect saturation levels that can be used to shorten assay time, and provide assay results before the assay is complete, enabling reflex testing to begin automatically. The monitoring system can include a real time imaging system with a camera and lights to capture images of the assay. The captured images can then be used to monitor and control the quality of the staining process in an assay, provide early assay results, and/or to measure the on-site reagent volume within the assay. |
| US11854193B2 |
Validity evaluation device for cancer region detection
An apparatus for evaluating validity of detection of a cancer region may be provided. The apparatus comprises a parametric magnetic resonance imaging (MRI) provider configured to provide at least one MRI constructed based on different parameters, a first cancer region input unit configured to receive a first cancer region based on the at least one parametric MRI, a cancer region processor including a cancer region detection model for receiving the at least one parametric MRI as input and outputting cancer region information and configured to generate and provide guide information corresponding to an image to be analyzed through the cancer region detection model, a second cancer region input unit configured to receive a second cancer region based on the guide information, and a validity evaluator configured to generate validity evaluation information of the second cancer region, by comparing the first cancer region with the second cancer region based on a pathology image obtained by mapping a region, in which cancer is present, of an extracted body portion. |
| US11854192B2 |
Multi-phase object contour refinement
A method and system perform single phase and multi-phase contour refinement of lesions. The method includes receiving a three dimensional input mask; receiving input slices from the medical images including a lesion; cropping the input slices with the input mask; performing lesion contour refinement for the cropped input slices and the input mask to obtain a predicted mask; and storing the predicted mask that includes 3D lesion contour refinement. A multiphase method includes deforming the 3D input mask from the reference phase to a target phase or warping the input slices from the target phase to the reference phase before contour refinement. The warped images generate an output mask in the reference phase coordinate system that is then deformed to the target phase coordinate system for display. |
| US11854186B2 |
Comparison method and modeling method for chip product, device and storage medium
The present application provides a comparison method and a modeling method for a chip product, a device and a storage medium. According to the method, the chip product is modeled by using a neural network based on a slice sequence of the chip product in advance to obtain a three-dimensional stereoscopic model. When the chip products are compared, a comparison feature is acquired responsive to an operation of a user. For each chip product, a comparison result corresponding to the comparison feature is acquired from the three-dimensional stereoscopic model corresponding to each chip product. Then, the comparison result corresponding to each chip product is displayed. |
| US11854182B2 |
Dimensional measurement method based on deep learning
The present disclosure provides a dimensional measurement method and device based on deep learning. The method includes capturing a target image of a target object, obtaining measurement data for the target image, and determining whether or not the target object is within a preset tolerance. |
| US11854178B2 |
Photography session assistant
Devices and methods for evaluating at least one photograph during a photography session are described. In some instances, a camera may be used to capture images during a photography session and a computing device may be used to identify a portrait order specification for the photography session including a set of required photographs, each having associated required criteria. The computing device may evaluate the images and determine whether the images can be associated with any of the required photographs based on features included in the images being associated with the required criteria of the required photographs. The images associated with required photographs may be displayed, and a determination of whether the images qualify as a required photograph may be made using a graphical user interface, or may be made automatically. |
| US11854177B2 |
Image splicing method
Provided is an image splicing method, including the following. A to-be-predicted image is divided into first and second cropped images. An overlap region exists between the first and second cropped images. The overlap region is divided into first and second sub-overlap regions. A first image region that does not include the second sub-overlap region is found in the first cropped image, and a second image region that does not include the first sub-overlap region is found in the second cropped image. First and second prediction result images respectively corresponding to the first and second cropped images are generated. A first prediction image region corresponding to the first image region is found in the first prediction result image, and a second prediction image region corresponding to the second image region is found in the second prediction result image. The first and second prediction image regions are spliced into a spliced image. |
| US11854169B2 |
Image correction device, image generation device, camera system, and vehicle
An image correction device including: an image data acquisition part for acquiring the image data obtained by a camera; and a correction part for correcting the image data on the basis of a first difference that is a difference between a first image height obtained by light having entered the camera at a first incident angle and a first reference image height obtained by light having entered the camera at the first incident angle when the camera is free of manufacturing errors. |
| US11854167B2 |
Photographic underexposure correction using a neural network
A method for image capture includes determining an exposure range and setting at least one camera parameter to capture an underexposed image outside the exposure range. The underexposed image is processed using a neural network to recover image details. Image defects due to camera or object motion blur can be reduced. |
| US11854166B2 |
Apparatus and method using baseline estimation and half-quadratic minimization for the deblurring of signal data
A method for estimating baseline in a signal, the signal being represented by input signal data (I(xi)), includes estimating a baseline contribution (I2(xi)) in the signal to obtain baseline estimation data (f(xi)), wherein the baseline estimation data (f(xi)) are computed as a fit to at least a subset of the input signal data (I(xi)) by minimizing a least-square minimization criterion (M(f(xi))). Deblurred output signal data (O(xi)) are obtained based on the baseline estimation data (f(xi)) and the input signal data (I(xi)). The least-square minimization criterion (M(f(xi))) comprises a penalty term (P(f(xi))). |
| US11854155B2 |
Data processing program, data processing method and data processing device for displaying external information in virtual space
A processing device that causes a virtual-space image to be displayed on a display device mounted on a player's head is provided with a first display processor and a second display processor. The first display processor causes first external information input from outside to be displayed on a specified object included in the virtual-space image when the virtual-space image is being caused to be displayed by the HMD. The second display processor causes second external information that is second external information input from outside and includes a real-space image to be displayed along with the virtual-space image when the virtual-space image is caused to be displayed by the HMD. The virtual-space image is, for example, the virtual-space image of a game, and the real-space image is, for example, an image imaged by an imaging device installed in the surroundings of the player. |
| US11854154B1 |
Systems and methods for synchronizing the scanning of a scene with the viewing of the scan results relative to a live view of the scene
Disclosed is a three-dimensional (“3D”) scanning system that synchronizes the scanning of a scene with the viewing of the scan results relative to a live view of the scene. The system includes a first device that scans a first set of surfaces that are exposed to the first device from a first position. The system further includes a second device that receives the scan data as it is generated for each scanned surface of the first set of surfaces. The second device augments a visualization of a second set of surfaces, within a field-of-view of the second device from a second position, with the scan data that is generated for a subset of scanned surfaces from the first position corresponding to one or more surfaces of the second set of surfaces visualized from the second position. |
| US11854153B2 |
Interference based augmented reality hosting platforms
Interference-based augmented reality hosting platforms are presented. Hosting platforms can include networking nodes capable of analyzing a digital representation of scene to derive interference among elements of the scene. The hosting platform utilizes the interference to adjust the presence of augmented reality objects within an augmented reality experience. Elements of a scene can constructively interfere, enhancing presence of augmented reality objects; or destructively interfere, suppressing presence of augmented reality objects. |
| US11854147B2 |
Augmented reality guidance that generates guidance markers
Augmented reality guidance for guiding a user through an environment using an eyewear device. The eyewear device includes a display system and a position detection system. A user is guided though an environment by monitoring a current position of the eyewear device within the environment, identifying marker positions within a threshold of the current position, the marker positions defined with respect to the environment and associated with guidance markers, registering the marker positions, generating overlay image including the guidance markers, and presenting the overlay image on a display of the eyewear device. |
| US11854145B2 |
Octree-based three-dimensional building model LOD method
The present invention provides an octree-based three-dimensional building model LOD method, specifically comprising the following steps: S1, reading three-dimensional building model data; S2, setting a tree depth Depth parameter of the octree; S3, respectively merging leaf node bounding boxes of the octree according to layers, and establishing coarse grid blocks; S4, merging the coarse grid blocks of the components of each layer; S5, performing triangularization; S6, calculating a normal vector of the coarse grid block; S7, merging the simplified components to form a building model of a coarse grid block; S8, deleting internal vertexes; S9, setting materials or textures; and S10, outputting the three-dimensional building LOD model. |
| US11854144B2 |
Subsurface scattering calculation method for translucent material rendering
The embodiments of the present disclosure disclose subsurface scattering calculation method for translucent material rendering, which relates to the clipping and polynomial fitting of brute-force Monte Carlo photon tracking experimental results to accurately represent the energy attenuation of subsurface scattering in distance. On this basis, an average free path and a single scattering rate are used to determine the relationship of each term in the multinomial fitting formula so as to facilitate the calculation and adjustment of the reflection profile. In the end, through a new real-time importance sampling solution, the outgoing radiation from any point on the object surface is calculated by the Monte Carlo method. This importance sampling solution is also applicable to any other subsurface scattering calculation model. By combining this subsurface scattering calculation result with other results, such as highlight reflection, any translucent material object can be rendered accurately and efficiently. |
| US11854143B2 |
Light probe generation method and apparatus, storage medium, and computer device
A light probe generation method and apparatus, a storage medium, and a computer device are provided. The method includes: selecting shadow points of a target object in a virtual scene; converting the selected shadow points into a voxelized shadow voxel object; reducing a quantity of vertexes in the shadow voxel object to obtain a shadow voxel object after the reduction; and generating a light probe at a vertex position of the shadow voxel object after the vertex reduction. |
| US11854142B2 |
Computing device for algorithm to reconstruct three-dimensional tomogram by considering multiple scattering, and method of the same
Various example embodiments provide a computing device of an algorithm for reconstructing a three-dimensional (3D) image in consideration of multiple scattering and a method of the same. According to various example embodiments, the computing device may be configured to set a 3D refractive index based on a plurality of 2D images for a specimen and to reconstruct a 3D image for the specimen from the set refractive index using a modified Born expansion considering multiple scattering to converge a calculation result. |
| US11854141B2 |
Early release of resources in ray tracing hardware
Techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. Throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. The allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. When reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. The compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. One or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query. |
| US11854135B2 |
Systems and methods for authoring cross-browser HTML 5 motion path animation
The present disclosure provides systems and methods for implementations of motion paths via pure CSS3 and HTML5, working in all major browsers and requiring no JavaScript. For each motion path degree of freedom (e.g., x translation), the system may insert an additional element into the document object model (DOM) to host its animation. In some implementations, the system may apply an optimization process to fit CSS3 keyframes rules that approximate the ideal motion path trajectory to a predetermined tolerance while minimizing the storage footprint. In addition to supporting CSS3 motion paths, this authoring model retains the ability to supply arbitrary standard CSS3 animations to transform channels, which allows users to, e.g., animate the scale and rotation of an element independent of its progress along a motion path. |
| US11854134B2 |
Information display using electronic diffusers
Embodiments of systems and methods for using electronic diffusers to implement message indicators are described. A segment of a diffuser attached to an electronic device is configured to indicate an informational message in response to signals that result in a change to an optical property. A set of information to be displayed using the segment is determined, and a signal is transmitted to the segment to display the information. |
| US11854130B2 |
Methods, apparatus, systems, devices, and computer program products for augmenting reality in connection with real world places
Methods, apparatus, systems, devices, and computer program products directed to augmenting reality with respect to real-world places, and/or real-world scenes that may include real-world places may be provided. Among the methods, apparatus, systems, devices, and computer program products is a method directed to augmenting reality via a device. The method may include capturing a real-world view that includes a real-world place, identifying the real-world place, determining an image associated with the real-world place familiar to a user of the device viewing the real-world view, and/or augmenting the real-world view that includes the real-world place with the image of the real-world place familiar to a user viewing the real-world view. |
| US11854129B2 |
Generating visual content consistent with aspects of a visual language
Systems, methods and non-transitory computer readable media for generating visual content consistent with aspects of a visual brand language are provided. An indication of at least one aspect of a visual brand language may be received. Further, an indication of a desired visual content may be received. A new visual content consistent with the visual brand language and corresponding to the desired visual content may be generated based on the indication of the at least one aspect of the visual brand language and the indication of the desired visual content. The new visual content may be provided in a format ready for presentation. |
| US11854128B2 |
Automated digital tool identification from a rasterized image
A visual lens system is described that identifies, automatically and without user intervention, digital tool parameters for achieving a visual appearance of an image region in raster image data. To do so, the visual lens system processes raster image data using a tool region detection network trained to output a mask indicating whether the digital tool is useable to achieve a visual appearance of each pixel in the raster image data. The mask is then processed by a tool parameter estimation network trained to generate a probability distribution indicating an estimation of discrete parameter configurations applicable to the digital tool to achieve the visual appearance. The visual lens system generates an image tool description for the parameter configuration and incorporates the image tool description into an interactive image for the raster image data. The image tool description enables transfer of the digital tool parameter configuration to different image data. |
| US11854125B2 |
Method and apparatus for providing an artifact-reduced x-ray image dataset
A method is for providing a second artifact-reduced x-ray image dataset based on an artifact-affected x-ray image dataset of an examination object, the artifact being caused by an object at least one of on, outside of and within the examination object. In an embodiment, the method includes creating a first artifact-reduced x-ray image dataset based on the artifact-affected x-ray image dataset, based on which a second projection dataset is created; identifying an object area which maps the object in the at least one projection; creating a third projection dataset based on the first projection dataset; and crating the second artifact-reduced x-ray image dataset based on the third projection dataset, through which the second artifact-reduced x-ray image dataset is provided. |
| US11854123B2 |
Sparse background measurement and correction for improving imaging
Disclosed herein is an imaging system including a first x-ray source configured to produce first x-ray photons in a first energy range suitable for imaging, project the first x-ray photons onto an area designated for imaging, a rotatable gantry configured to rotate the first x-ray source such that the first x-ray source traverses an angular path, and a data processor having an analytical portion. The analytical portion is configured to collect first data relating to the transmission of the first x-ray photons through the area designated for imaging at a set of image-collection angles along the angular path, collect background data at a set of background-collection angles along the angular path, wherein the system acquires more than one image of the designated area for imaging between background angles. The analytical portion is also configured to remove errors in the first data using the background data, and generate a corrected image based on the removal of errors in the first data. |
| US11854114B2 |
Apparatus and method for seamless container migration for graphics processors and associated devices
Apparatus and method for migrating a container including graphics processor state. One embodiment of an apparatus comprises: a first graphics processor coupled to a first system memory; execution circuitry of the graphics processor to execute graphics operations of processes grouped into a plurality of containers, the execution circuitry to be shared by the plurality of containers; and a first container migration engine to migrate a first container of the plurality of containers to a second graphics processor coupled to a second system memory, the first container migration engine to freeze operation of the first container at a specified execution point defined by a first container state including process-visible state data and driver-visible state data, the first container migration engine to transmit the first container state to a second container migration engine associated with the second graphics processor and second system memory, the second container migration engine to restore the first container to the specified execution point using the process-visible state data and the driver-visible state data. |
| US11854113B2 |
Deep learning methods for event verification and image re-purposing detection
Systems and methods herein describe accessing an image, generating a resized image, generating an image feature vector by applying an image classification neural network to the resized image, generating analysis of the image by processing the image feature vector using a machine-learning classifier trained to analyze the image feature vector, and based on the analysis, determining an event that is attributed to the image. |
| US11854110B2 |
System and method for determining geographic information of airport terminal chart and converting graphical image file to hardware directives for display unit
A system may include a processor configured to: obtain an image of an airport terminal chart; based on a latitudinal set of characters, determine a latitude for each line of latitude; based on the latitude for each line of latitude and a first image distance between the lines of latitude, determine a first ratio of latitudinal degrees between the lines of latitude to the first image distance; based on a longitudinal set of characters, determine a longitude for each line of longitude; based on the longitude for each line of longitude and a second image distance between the lines of longitude, determine a second ratio of longitudinal degrees between the lines of longitude to the second image distance; and output information associated with the first ratio, the second ratio, the determined latitude for each line of latitude, and the determined longitude for each line of longitude. |
| US11854108B2 |
System and method for controlling drone delivery or pick up during a delivery or pick up phase of drone operation
A system including a landing location where a drone at least one of delivers and acquires a parcel, and a homing device to interact with the drone to guide the drone to the landing location independent of interaction from another source. The homing device guides the drone during the landing phase of a flight plan. A method is also disclosed. |
| US11854105B2 |
System and method for visitation management in a controlled environment
A system is described herein that facilitates the easy scheduling and conducting of prison visitations. The system provides a remotely-accessible means for visitors to authenticate themselves, check the availability of those they wish to visit, and schedule a visit with that individual. As part of this process, the system tracks the availability of prison inmates as well as the devices and visit sites that are available to those inmates. In this manner, the system can quickly identify the availability of different inmates in order to provide on-demand scheduling capabilities to potential visitors. The system is connected to multiple facilities as well as public networks, and therefore can be remotely accessed. Additionally, the system also functions to monitor visits while they are in progress, as well as to store visit recordings for future review. Because the system is networked, remote monitors can access the review system in order to monitor visits or review recordings. The system also employs rigorous authentication and other security measures to ensure the safety and security of the visitors, the inmates, the staff, as well as others within the prison facility. |
| US11854103B2 |
Systems and methods for state-based risk analysis and mitigation for exam registration and delivery processes
Systems and methods may involve processing of entity data by machine learning models to produce one or more aggregate risk scores, which may be compared to one or more thresholds to determine when one or more predefined actions should be taken. The entity data may be collected for various entities related to an exam registration and delivery process, which may include a candidate, an exam, a test center, an exam registration event, a proctor, and an exam delivery event. The exam registration and delivery process may include multiple states—each being associated with a different set of entities. Aggregate risk scores for a given state may be calculated using only entity data for the set of entities associated with that state. The predetermined actions taken may also be dependent on the current state. |
| US11854100B2 |
Property inspection system and method
A computer system and method for performing property inspections. Digital media is received in a computer vision image analysis system from one or more user devices via a network and a determination is made regarding an environment type associated with the received digital media. One or more objects are determined that are located in the determined environment and which are present in the received digital media. A determination is made regarding an absence of objects in the received digital media contingent upon the determined environment type based upon a set of rules. |
| US11854096B2 |
Methods and systems for meeting rapidly fluctuating power demands using interruptible load and stable power production
An automated control method for meeting rapidly fluctuating power demands with stable power production is disclosed. The method includes determining a market value of a unit of electricity sold on the grid, a fuel cost required to produce the unit of electricity, and a market value of a processing task requiring the unit of electricity. The method also includes calculating which of the electricity, processing, or fuel is most valuable; shutting off a running process when the value of the electricity is highest or the value of the fuel is highest; and starting a pending process when the net market value of the processing task is highest. The method may also include reducing electricity generation at a power plant when the value of electricity is negative, or exercising a futures contract to supply electricity. |
| US11854089B2 |
Virtual simulation for insurance
A driving accident simulation, having a head-wearable user interface (e.g., a head-worn virtual-reality display), may be used to inform a driver of the driver's potential liability under different insurance options. The simulation may determine damages caused by the simulated accident, and identify multiple insurance options and the resulting user liability under each option. The simulation may also be used to assess an insurance adjuster's ability to estimate damages from an accident, by receiving the adjuster's estimate and comparing it to the simulation's own estimate of damages. In some embodiments, the simulation may present a driver with a simulated view from a point of view of another party to the simulated accident. |
| US11854087B1 |
Systems and methods for water loss mitigation messaging
A computer-implemented method, includes identifying, a set of insurance policyholders that have experienced water loss and a second set of insurance policyholders that have not experienced water loss. The method also includes determining an attribute indicative of increased likelihood of future water loss using a predictive model using a percentage of the first set of insurance policyholders defining a first sample size of the first set of insurance policyholders that is smaller relative to a percentage of the second set of insurance policyholders defining the second sample size of the second set of insurance policyholders. Further, the method includes identifying at least one targeted insurance policyholder having an increased likelihood of water loss, based upon the attribute and providing a water loss mitigation strategy to the at least one targeted insurance policyholder. |
| US11854084B2 |
System and method for delaying an executable instruction that would otherwise be executable immediately upon arrival at an executing system
A system and method are provided for intentionally delaying an execution of an executable instruction by determining if a current executable instruction is received from a predefined source for which all executable instructions are to be intentionally delayed. When so, the system sets a sequence time associated with the instruction equal to a receipt time plus a delay time. The system saves the instruction in an intentional delay queue for future execution. When the current executable instruction is received from a source that is not the predefined source, the system determines if a condition for immediate processing of the current executable instruction is present. When so, the system executes the instruction immediately. Otherwise, it performs an intentional delay determination that determines whether the current executable instruction has been intentionally delayed. When the current executable instruction has been intentionally delayed, the system executes the instruction immediately. |
| US11854082B1 |
Blockchain instrument for transferable equity
Systems and methods for offering and purchasing tokenized securities on a blockchain platform meeting current and future federal, state, and offering and holding entity rules and regulations. Tokenized securities purchased during or after the tokenized securities offering are tradable on a secondary market. The server computer of the tokenized securities provides an automated transfer capability for tokenized securities holders. |
| US11854074B1 |
Geolocation-based mesh automatic lending network
A distributed computing system facilitates automatic loan agreements between syndicate participants. The system includes a blockchain comprising circuitry embodying a plurality of blockchain services. A membership service registers participants to the syndicate, generates a unique identifier for each of the participants, and verifies that a respective entity is a node on the blockchain. An oracle service retrievably stores loan terms templates provided by the participants via a centrally managed entity. A smart contracts service receives financial and/or geo-location data associated with the plurality of syndicate participants. A predictive analytics service uses the data to determine whether a first syndicate participant has an excess of funds and whether a second syndicate participant has a lack of funds. A loan service automatically facilitates a loan agreement between the first participant and the second participant. The loan agreement is based on the data and/or a loan terms template provided by the oracle. |
| US11854070B2 |
Generating virtual makeup products
Techniques are described for generating virtual makeup products. Virtual makeup products, in this context, may include a predefined effect and a configuration for the effect, wherein the predefined effect includes one or more layered visual filters. In an embodiment, a system in accordance with the present disclosure may acquire makeup product definition data based on characteristics of a real-world makeup product from an entity associated with the real-world product such as a designer, manufacturer, or vendor. Using the makeup product definition data, the system may generate a virtual makeup product includes a configuration of a predefined effect based on the acquired product definition data. The generated virtual makeup product is then passed through a process of internal calibration, internal review, and external review to improve the accuracy of the simulation of the real-world makeup product. In some embodiments, external review is performed by an external reviewing entity (e.g., a designer, manufacturer, or vendor) by using a validation application. |
| US11854064B2 |
System and method for adding items to an electronic order
A system includes one or more processors and one or more non-transitory computer-readable media storing computing instructions configured to run on the one or more processors to perform: receiving, from a customer device, an online order for a customer, wherein the online order comprises a customer identification for the customer; receiving, from the customer device, a selection of a pick-up time for retrieval at a store; receiving an additional order for the customer; linking the additional order to the online order based on the customer identification; sending instructions to an assembler configured to (1) read identifiers of the online order and the additional order, (2) retrieve the plurality of items and the one or more additional items from a facility, and (3) place the plurality of items and the one or more additional items in a designated location. Other embodiments are disclosed. |
| US11854055B2 |
Methods and apparatus for anomaly detections
This application relates to apparatus and methods for identifying anomalies within a time series. In some examples, a computing device receives sales data identifying a sale of at least one item, and aggregates the received data in a database. The computing device may generate a plurality of time series based on the aggregated sales data. The computing device may extract features from the plurality of time series, and generate an alerting algorithm that is based on clusters of the extracted features. The computing device may apply the alerting algorithm to a time series generated from received sales data to determine whether the time series is an anomaly. Based on the determination, the computing device may generate and transmit anomaly data identifying whether the time series is an anomaly, such as to another computing device. |
| US11854054B2 |
Adaptive energy storage operating system for multiple economic services
The present disclosure provides an adaptive energy storage operating system that is programmed or otherwise configured to operate and optimize various types of energy storage devices. |
| US11854043B2 |
Online marketplace cooperative promotional platform
An on-line marketplace provides systems and methods for a mutually beneficial messaging campaign with one or more merchants, in order to promote the merchants' products. One aspect of the messaging campaign includes augmenting the merchants' budgets across multiple commercial channels. The channels may include merchant-operated channels, marketplace-operated channels, and/or third party channels. The marketplace selects when and how to augment the merchants' budgets. The augmented budget comprises an overall content budget for the messaging campaign, including a first budget portion provided by the merchant(s) and a second budget portion provided by the on-line marketplace. The augmented budget may be determined based on a weighted combination of goals of the marketplace and one or more merchants. The augmented budget may be segmented into static and dynamic portions, in which the dynamic portion is varied between channels to determine variables to optimize budget allocation and message performance. |
| US11854041B2 |
Methods and apparatus to determine impressions corresponding to market segments
An example apparatus includes processor circuitry to access demographics from a database proprietor corresponding to impression requests from computing devices indicative of media impressions, determine a first media impression count corresponding to a sum of first media impressions that occurred on first computing devices satisfying a device type criterion and that are attributable to a demographic group corresponding to a) the demographics from the database proprietor, b) panel-based demographics corresponding to a market segment, determine a second media impression count corresponding to second media impressions that occurred on second computing devices not satisfying the device type criterion and that are attributable to the demographic group corresponding to a) the demographics from the database proprietor, b) the panel-based demographics corresponding to the market segment, and determine a total media impression count by adding the first media impression count to the second media impression count that are attributable to the demographic group. |
| US11854040B1 |
Responding with unresponsive content
This disclosure describes systems and techniques receiving a request for information from a user and, in response, outputting the requested information along with unsolicited, interesting content that is related to, yet nonresponsive to, the requested information. In some instances, if the requested information is unknown, the techniques may output an indication that the information is unknown, followed by the additional, unsolicited, interesting content. |
| US11854037B2 |
Computer system for identifying aberrant activity on a reward card platform
A reward card platform includes a database storing funding accounts, reward card purchase transactions, and aberrant activity rules. A first user interface enables purchasing reward cards, including controls to specify reward card parameters. A second user interface enables specifying rules to detect aberrant activity. The second user interface includes user interface controls to specify the rule parameters, including: specifying a moving window of time; specifying an aggregation type; specifying filtering; specifying aggregation grouping; and specifying a threshold value for triggering an alert. The platform includes a rules execution engine that runs periodically to evaluate each of the rules. For each rule, the engine identifies transactions whose timestamps fall within the moving window of time relative to a current time and satisfies the filters, then computes an aggregation of the transactions according to the aggregation type and aggregation grouping. When the aggregation exceeds the threshold value, the platform raises an alert. |
| US11854035B2 |
Methods, systems, and non-transitory computer- readable record media for providing reward through reward account associated with player
A method, system, and non-transitory computer-readable record medium for providing a reward through a reward account connected to a player. A reward providing method includes connecting, by processing circuitry, a plurality of reward accounts registered by a user on a player, the player being installed on an electronic device, determining, by the processing circuitry, an analysis result based on content playback information, the content playback information corresponding to content output through the player, and providing, by the processing circuitry, a reward through a first reward account among the plurality of reward accounts based on the analysis result, the reward corresponding to the content output through the player. |
| US11854032B1 |
Merchant services statements and pricing
A method for obtaining credit card pricing for a merchant includes obtaining a merchant category classification (MCC) code. A sales volume, a number of credit card transactions, an average dollar amount of the credit card transactions and a percentage of credit card transactions that are keyed are obtained. The MCC code, the average dollar amount of the of credit card transactions processed and the percentage of credit card transactions that are keyed are compared with corresponding data from a database of merchant credit card transactions. A matched merchant is identified whose transaction profile closely matches a combination of the MCC code, the average dollar amount of the credit card transactions processed and the percentage of credit card transactions that are keyed. Credit card processing pricing information for the matched merchant is obtained from the database. The credit card processing pricing information is used to calculate credit card processing pricing for the matched merchant. |
| US11854018B2 |
Labeling optimization through image clustering
A method, computer system, and a computer program product for labeling optimization is provided. The present invention may include receiving a plurality of labeled historical transaction timeline image clusters based on a plurality of historical transaction timeline images clustered using unsupervised machine learning. The present invention may further include training an image recognition model using supervised machine learning based on the received plurality of labeled historical transaction timeline image clusters. The present invention may also include receiving, by the trained image recognition model, a current transaction timeline image. The present invention may further include assigning a corresponding label to the received current transaction timeline image based on matching the received current transaction timeline image to one of the received plurality of labeled historical transaction timeline image clusters. |
| US11854010B2 |
Authorization of cardless payment transactions
A method of processing a transaction between a customer and a merchant includes receiving from a mobile device of the customer or from another device of the customer an indication of consent to perform a cardless payment transaction with the merchant, receiving from the mobile device an indication that the customer is within a predetermined distance of the merchant, after receiving both the indication of consent and the indication that the customer is within the predetermined distance, sending to a computer system of the merchant an indication of the presence of the customer and personal identifying information for the customer, receiving data indicating a transaction between the customer and the merchant, and submitting the transaction to a financial service for authorization. |
| US11854009B2 |
Method for pooling in a proof-of-space-based blockchain via singletons
A method for pooling and retrieving block rewards in a reward pool including an operator node and a set of member nodes in a distributed network extending a proof-of-space-based blockchain includes: submitting a transaction configured to generate a singleton in a set of singletons, the singleton including: an outer puzzle hash linking the singleton to a singleton puzzle hash; and an inner puzzle hash defining a pool address associated with the reward pool; generating a block including a proof-of-space and a block reward allocated to the singleton puzzle hash; detecting the block reward allocated to the singleton puzzle hash; identifying the singleton linked to the singleton puzzle hash; and submitting a transaction configured to: remove the singleton from the set of singletons; and transfer the block reward from the singleton puzzle hash to the pool address. |
| US11854005B2 |
Embedded data transaction exchange platform
Aspects of the present disclosure are presented for an Embedded Data Transaction Exchange Platform (EDT-X) that generates marker data about relevant data of a transaction, and reliably stores the marker data in a permanent data storage, such as a block chain distributed ledger. The EDT-X platform does not generate the actual information that explains who was involved in the transaction or what the contents of the transaction were, but rather generates marker data that can reliably lead to tracing back to that information. The marker data may be permanently stored in a permanent data storage entity, such as a block chain distributed ledger. The data about the content of the transaction may be anonymously stored in a secure database, and the marker data pointing to the content of the transaction may be retrieved from the block chain distributed ledger to look up where the content data is stored in the secure database. |
| US11854003B2 |
Signature verification method, apparatus, and system
Described are a signature verification method, apparatus, and system. The method includes: encrypting a third-party payment identifier and payment information according to a first key to obtain a first signature; encrypting a third-party client identifier and first signature information according to a second key to obtain a second signature; and providing the third-party client identifier, the first signature information, and the second signature to a client server for verification. |
| US11853996B2 |
Card dispenser
A card dispenser for dispensing a rewritable card is disclosed herein. The card dispenser may include a card feeder for receiving or dispensing a rewritable card. In addition, the card dispenser includes a roller assembly for moving the card from the card feeder to components within the card dispenser; a processor for receiving card data via a short-range wireless connection with a mobile device of a user, the card data including (i) a card identifier of a plurality of card identifiers associated with an account of the user and (ii) a unique derivation key for encrypting the card identifier; and a card writer for powering an electrophoretic display of the card, causing at least a portion of the card data to be rendered on the display, and stopping the powering of the display. |
| US11853994B2 |
System, method, and computer program product for partitioning mobile device transactions
A computer-implemented method for partitioning mobile device transactions may include generating a machine-readable indicia encoded with transaction data for a transaction between a merchant and at least one user; receiving a transaction request message including the transaction value and a split payment identifier; initiating a programmatic timer for a time interval in response to receiving the transaction request message from the first mobile device; receiving at least one additional transaction request message prior to expiration of the time interval; partitioning the transaction value between each of the first user account and the at least one other user account based at least partially on the transaction request message; and generating a separate authorization request message for each of the first user account and the at least one other user account, each authorization request message including a partial transaction value representing a portion of the transaction value. |
| US11853992B2 |
Settlement device
A settlement device includes a packing unit located near a reading unit to pack a commodity, a symbol of which is read by a reading unit, a measuring unit to measure the packed commodity, a light emitting unit, determining means for determining, using data of weight measured, whether the commodity, the symbol of which is read, is packed, and light-emission controller for, if determining that the commodity, the symbol of which is read, is packed, causing the light emitting unit to emit light in a first form and, if determining that the commodity, the symbol of which is read, is not packed, causing the light emitting unit to emit light in a second form. |
| US11853990B2 |
Systems and methods for providing a point of sale platform
This disclosure describes systems, methods, and computer-readable media related to providing a point of sale platform. In some embodiment, a point of sale (POS) device may receive information associated with an order and payment information associated with the order. The POS device may generate a first object based at least in part on the information associated with the order and a second object based at least in part on the payment information. The POS device may store the first object and the second object in a queue. The POS device may transmit the first object and the second object to a remote server. |
| US11853983B1 |
Video revenue sharing program
Videos to be hosted at an asset hosting platform and submitted by an owner of the videos are received. The videos are provided for consumption by users of the asset hosting platform. The historical data identifies a historical popularity of one or more of the videos. Whether the historical data associated with the one or more of the videos satisfies a viewership rate specifying a rate of viewership over a predetermined period of time for the one or more of the videos is determined. Responsive to determining that the historical data associated with the one or more of the videos satisfies the viewership rate, the owner is determined as eligible to participate in a video performance sharing program. A communication for a client device associated with the owner of the videos to invite the owner to participate in the video performance sharing program is generated. |
| US11853982B1 |
User dashboard for enabling user participation with account management services
A network computing system to provide an account management service for guiding user actions and providing users with information to facilitate decision making. In providing the account management services, the network computer system makes predictive determinations about the actions of service providers, in connection with specific actions of individual users. |
| US11853979B1 |
Math based currency credit card
Systems, methods, and computer-readable storage media utilized in remote math based currency (MBC) transactions. One method includes receiving, from a customer computer system, a token generation request associated with a remote MBC transaction including an amount of MBC funds to transfer, wherein the token generation request includes an identifier of a recipient computer system, and generating and transmitting, to the customer computer system, a token embedded with at least an MBC account number of the customer computer system. The method further includes receiving, from the recipient computer system, the token, wherein the recipient computer system is associated with a recipient MBC account, and creating a first and second public and private key pair. The method further includes transmitting the first public and private key pair to a recipient account destination of the recipient MBC account, and updating a pooled MBC account database with the second public and private key pair. |
| US11853978B2 |
Virtual currency management method
Provided is a virtual currency remittance method that causes a second computer connected to a first computer including a state DB that manages account discrimination information and balance information related to virtual currency relevant to an account discriminated by the account discrimination information, and remittable account discrimination information, and a blockchain that manages transaction information including first account discrimination information, second account discrimination information, and a sum of virtual currency to be remitted from an account discriminated by the first account discrimination information to an account discriminated by the second account discrimination information. |
| US11853976B2 |
System and method for management of healthcare practice
A system to manage records in a healthcare practice includes a server and a memory that stores patient data records and inventory equipment records. A check-in client computing device and first and second HCP client computing devices run apps that program respective devices to check-in patients for appointments, retrieve, and store patient healthcare data at the server. Display screens show approved appointments and the apps sort appointments as selected. The patient check-in app verifies that patients meet check-in requirements and locks the appointments of patients who do not. Apps retrieve patient data for the approved appointments and sort them. The server stores examination, treatment, and prescription data. Equipment inventory delivery data and returns data are stored. The server is programmed to communicate with all apps in their form and format of data and to translate all disparate data types into that form and format. |
| US11853974B2 |
Apparatuses and methods for assorter quantification
An apparatus and method for assorter quantification. The apparatus includes a processor that is configured to track a candidate through the recruiting process such that an assorter may be compensated for their recruiting efforts. The apparatus includes receiving data sets from the assorter and the employer and determining a quantification amount for assortment activities by the assorter. |
| US11853973B1 |
Method of and system for executing an impairment repair process
A method and system enhances the execution of the telemedicine impairment repair process (IRP) to claim closure by assisting all stakeholders by monitoring the process and reminding the stakeholders of the stakeholder roles and responsibilities to maintain a prudent time frame for the reported injury and/or illness. The method of and system for executing an impairment repair process addresses flaws in the current process by implementing timing guided by legislation and best medical practice. Key aspects of the impairment repair process are addressed to ensure prudent timing by assuring accuracy of claim development, monitoring, and initiating communication to closure. The process is implemented in multiple stages including, assessment, documentation, prescribed treatment, and analysis of outcome. |
| US11853970B2 |
Trading partner relationship graph for information exchange platform
An information exchange platform referred to as a Trading Grid (TG) may perform relationship-based data processing utilizing a trading partner (TP) graph that describes relationships amongst operating units (OUs) on the TG. When the TG receives a request from an OU to exchange data with a TP, the TG accesses the TP graph and determines a relationship between the OU and their TP as reflected in the TP graph. The TP graph is maintained and controlled by the system independently of the OU and the TP. The TG may route the data based on instructions associated with the relationship that is reflected in the TP graph. The instructions associated with the relationship may specify network based services provided by the TG. An orchestration component may operate to orchestrate the performance of the network based services. The TG then communicates the processed and/or produced data to the TP. |
| US11853969B2 |
Managing artifact information, especially comparing and merging artifact information, method and system
Systems and methods for improved management of artifact information of at least one first artifact document comprising a plurality of first fragments of artifact information and of at least one second artifact document comprising a plurality of second fragments of artifact information, especially comprising comparing and merging artifact information. |
| US11853967B2 |
Rental property management technology
Rental property management technology, in which electronic entry data for rental properties, energy related data for the rental properties, reservation data for the rental properties, and settings for energy management of the rental properties is accessed. Integrated data that includes the accessed electronic entry data, the accessed energy related data, and the accessed reservation data integrated with the accessed settings for energy management of the rental properties is stored in electronic storage. The integrated data is analyzed to determine whether energy management of the rental properties aligns with the accessed settings and accords with one or more efficiency rules. Based on the analysis, an energy management operation is performed for at least one of the rental properties. |
| US11853964B1 |
System and method for smart inventory capture
A smart inventory service provider system is provided. The system comprises a network interface configured to communicate data over a network and a processing circuit. The processing circuit comprises one or more processors coupled to non-transitory memory. The processing circuit is configured to receive inventory item data associated with an inventory item from a user mobile device and to associate the inventory item data with a user account in a user inventory database. The processing circuit is further configured to monitor a frequency of usage of the inventory item and to transmit a message to an external computing system soliciting a transaction offer related to the inventory item based on the frequency of usage of the inventory item. The processing circuit is further configured to, upon receiving the transaction offer from the external computing system, transmit the transaction offer to the user mobile device. |