| Document | Document Title |
|---|---|
| US11509437B2 |
Signal processing method and device
Embodiments of this disclosure provide a signal processing method and device. The method includes: transmitting first information via RMSI, and/or transmitting second information via RRC signaling; wherein SSB related information indicated by the first indication information is at least partially same as SSB related information indicated by the second indication information. |
| US11509436B2 |
Facilitation of enhanced channel state information estimation for 5G or other next generation network
A delay doppler domain transformation can be used to estimate characteristics of a channel between a base station and a user equipment or alternatively, between the user equipment and another user equipment. Thus, the velocity and the distance position of the user equipment can be calculated. For example, a signal received in the time-frequency domain, can be converted to the delay doppler domain by the base station. In response to the conversion, the base station can estimate the velocity of the user equipment. The velocity can be utilized by various applications. For example, the velocity can be utilized to alert the other user equipment to the location or an anticipated location of the user equipment. |
| US11509435B2 |
Generating downlink sector beams based on uplink channel estimates utilizing a base band unit pool for modular massive multiple-input multiple-output arrays
A system includes a base band unit pooling component that determines, via a base band unit pool of base station devices, respective uplink channel estimates of an uplink channel wirelessly coupling, using frequency division duplexing via respective modular antenna elements, a user equipment to the base band unit pool. A downlink channel estimation component of the system derives, based on the respective uplink channel estimates, a downlink channel estimate of a downlink channel wirelessly coupling, using the frequency division duplexing via a portion of the respective modular antenna elements corresponding to a base station device of the base band unit pool, the base station device to the user equipment. In turn, the system generates, using the downlink channel estimate, a group of downlink sector beams to be transmitted to the user equipment using the downlink channel via the portion of the respective modular antenna elements. |
| US11509424B2 |
Method and apparatus for grant free based data transmission in wireless communication system
A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) is provided. The communication method includes intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. This disclosure provides a grant-free-based data transmission method and apparatus. |
| US11509423B2 |
Dynamic redundancy for multimedia content
A device implementing dynamic redundancy may include at least one processor configured to receive, from another device, packet reception data corresponding to video data previously provided for transmission from the device to the other device and determine, based at least in part on the packet reception data, an amount of redundancy to apply to video data provided for transmission to the other device. The at least one processor may be further configured to determine, based at least in part on the amount of redundancy, an encoding scheme for applying the redundancy to the video data. The at least one processor may be further configured to apply the amount of redundancy to the video data based at least in part on the encoding scheme to generate redundant data items and provide the video data and the redundant data items for transmission to the other device. |
| US11509419B2 |
Acknowledgement and retransmission techniques utilizing secondary wireless channel
This disclosure provides methods, devices and systems for acknowledgement and retransmission, and more specifically, to methods, devices and systems that enable a secondary wireless channel to provide acknowledgements of data transmitted on a primary wireless channel concurrently with the reception of additional data on the primary wireless channel. In some implementations, a transmitting device may transmit wireless packets including multiple codewords to a receiving device via a first wireless channel. The receiving device may attempt to decode the received codewords based on primary information in the codewords. The receiving device may then transmit to the transmitting device, via a second wireless channel, a codeword acknowledgement that identifies codewords that the receiving device did not successfully decode. The transmitting device may then transmit parity information to the receiving device via the first wireless channel that aids the receiving device in decoding the identified codewords. |
| US11509417B2 |
Systems and methods to generate copies of data for transmission over multiple communication channels
Systems and methods to transmit data over multiple communication channels in parallel with forward error correction. Original packets are evenly distributed to the channels as the initial systematically channel-encoded packets. Subsequent channel-encoded packets are configured to be linearly independent of their base sets of channel-encoded packets, where a base set for a subsequent channel-encoded packet includes those scheduled to be transmitted before the subsequent packet in the same channel as the subsequent packet, and optionally one or more initial packets from other channels. The compositions of the sequences of the encoded packets can be predetermined without the content of the packets; and the channel-encoded packets can be generated from the original packets on-the-fly by the transmitters of the channels during transmission. When a sufficient number of packets have been received via the channels, a recipient may terminate their transmissions. |
| US11509414B2 |
Method and apparatus for encoding data using a polar code
Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter. |
| US11509413B2 |
Apparatus, system and method of an orthogonal frequency-division multiplexing (OFDM) transmission over a wide bandwidth
For example, an apparatus may include a segment parser to parse scrambled data bits of a PPDU into a first plurality of data bits and a second plurality of data bits, the PPDU to be transmitted in an OFDM transmission over an aggregated bandwidth comprising a first channel in a first frequency band and a second channel in a second frequency band; a first baseband processing block to encode and modulate the first plurality of data bits according to a first OFDM MCS for transmission over the first channel in the first frequency band; and a second baseband block to encode and modulate the second plurality of data bits according to a second OFDM MCS for transmission over the second channel in the second frequency band. |
| US11509408B1 |
System and method for large data transmission in digital radio broadcasting
Large data transmission in digital radio broadcasting system and method are disclosed. A first channel information of tuned frequency indicates the availability of the data distribution table. Second channel information contains the data distribution info table (list of frequencies mapped to data chunk identifiers). Data chunks have a unique id. Digital broadcast radio receiver receives data distribution tables and parses through the currently tuned frequencies data distribution table. The receiver has information on how to collect the distributed data. Receiver uses its primary tuner to receive the data chunks in the current tuned frequency. Rest of the data chunks are collected by the background tuners in a parallel fashion by tuning to required frequencies. Once all chunks are collected, data file is reconstructed and available for presentation to the user. |
| US11509406B2 |
Antenna assembly detection based on oscillator and variable reactance tank circuit
A device, a method, and a non-transitory storage medium are described in which an antenna assembly detection service is provided. A device may include an oscillator circuit whose frequency of operation is determined by a resonant frequency of a tank circuit and reactance of a load associated with the antenna terminal configured to receive an external antenna. A controller may be configured to measure an output signal of the oscillator circuit when the oscillator circuit is connected to the antenna terminal, and determine whether or not the external antenna is connected to the antenna terminal based on the measurement and comparison data. |
| US11509401B2 |
Optical connector and power sourcing equipment of power over fiber system, and power over fiber system
An optical connector of a power over fiber system includes a shutter. The shutter opens in conjunction with a connection operation to enable the connection and closes in conjunction with a disconnection operation to block feed light from exiting. A light receiving surface of the shutter is made of a wavelength conversion material. The light receiving surface receives the feed light when the shutter is closed. The optical connector is disposed at a feed-light output end in the power over fiber system. |
| US11509398B2 |
Control apparatus and control method
A control apparatus includes an optical wavelength change control unit that specifies, in response to a request to change a wavelength band of a first optical wavelength path used by a first transmission apparatus and a second transmission apparatus to a wavelength band of a second optical wavelength path, a first route between routers which is affected by the request and a service which uses the first route and that specifies a second route between the routers which detours the specified service; a router control unit that transmits a request to detour the specified service to the second route, to a start-point router and an end-point router on the first route; and a transmission apparatus control unit that transmits a request to change the wavelength band of the first optical wavelength path to the wavelength band of the second optical wavelength path, to the first transmission apparatus and the second transmission apparatus. |
| US11509396B2 |
Polarization multi/demultiplexed optical transceiver circuit
Provided is a polarization multiplexing optical transmitting and receiving circuit that compensates for transmission side PDL so as to suppress a reduction in transmission power and makes a branching ratio of light from a light source variable between a transmission side and a receiving side according to a system to be used. The polarization multiplexing optical transmitting and receiving circuit includes an optical variable branching circuit that branches the light output from the light source, a light fixing symmetric branching circuit connected to one of outputs of the optical variable branching circuit and a light fixing asymmetric branching circuit connected to the other, optical receivers connected to two outputs of the light fixing symmetric branching circuit, respectively, optical transmitters connected to two outputs of the light fixing asymmetric branching circuit, a polarized wave rotator connected to one of the optical transmitters, and a polarized wave multiplexer that polarization-multiplexes the outputs of the optical transmitters. |
| US11509393B2 |
Optical wireless transmission system
An optical wireless transmission system 10 includes a transmission device including at least one memory storing instructions, and at least one processor configured to execute the instructions to; generate a plurality of digital outphasing signals; orthogonally modulate the digital outphasing signals at an intermediate frequency; and set an intermediate frequency for satisfying a specified signal-to-distortion power ratio based on a sampling frequency, wherein the digital outphasing signals are orthogonally modulated at the intermediate frequency; a hardware optical fiber module configured to convert orthogonally modulated digital electrical signals into optical signals, transmit the optical signals through an optical fiber, and convert the optical signals into digital electrical signals; and a remote unit configured to combine the digital electrical signals transmitted by the hardware optical fiber module, and transmit a combined signal as a radio signal. |
| US11509392B2 |
Signal quality information notification method and relay communication apparatus
A communication system transmits relay data through a communication path including a plurality of sections in which different communication schemes are used. A relay communication device is provided between a first section and a second section which are adjacent sections. The relay communication device includes a receiving unit receiving the relay data from the first section through a frame of a first communication scheme, and a relaying unit configuring, in a frame of a second communication scheme used to transmit the relay data to a relay destination, signal quality information representing signal quality calculated for a physical link in each of the sections through which the relay data is transmitted before arriving at the relay communication device, and outputting the frame of the second communication scheme to the second section. |
| US11509389B1 |
Interference reduction in heterogenous terrestrial/aerial, networks
Aspects of the subject disclosure may include, for example, an aerial base station determining operating frequencies of terrestrial base stations, and taking one or more actions to reduce the potential for interference between the aerial base station and the terrestrial base stations. Actions taken by the aerial base station may include changing frequency, changing altitude, changing location, and changing transmit power. Other embodiments are disclosed. |
| US11509385B1 |
Angle diversity multiple input multiple output radar
A radar system includes an antenna array including a plurality of antenna elements; and a transmitter portion coupled to the antenna array, the transmitter portion being configured to sequentially transmit a first transmit beam and a second transmit beam from a single pulse, the first transmit beam and second transmit beam being formed using the same aperture of the antenna array, wherein a skew angle of the first transmit beam is distinct from a skew angle of the second beam. Such radar system alternatively transmitting through subarrays and receiving each via the entire array and combining the signals such that the transmit and receive parts of one of two 2-way beams point in the same direction and the transmit and receive parts of the second 2-way beam point in the same direction and these directions are within a standard beamwidth of each other. |
| US11509384B2 |
Beam selection in idle mode to avoid monitoring occasion collision
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may measure a plurality of beams, from a base station, wherein the plurality of beams are associated with a corresponding plurality of monitoring occasions for a first subscription of the UE. The UE may determine whether a monitoring occasion for a second subscription of the UE collides with one or more of the plurality of monitoring occasions, for the first subscription of the UE, corresponding with the plurality of beams. The UE may transmit, to the base station, an indication of a selected beam, from the plurality of beams, based at least in part on the measuring and the determining. Numerous other aspects are provided. |
| US11509381B2 |
Resource-efficient beam selection in 5G and 6G
Communications in 5G and 6G can use “beams” to focus electromagnetic energy on the recipient, and the recipient can likewise arrange a focused reception “beam” toward the transmitter, thereby saving energy and avoiding interference. However, aligning the transmission and reception beams remains an arduous process. Herein, procedures are disclosed for rapid and efficient beam alignment at both transmission and reception devices, using very brief response signals to select an optimal beam direction for best signal quality. By encoding the selected beam index in the time, frequency, and optionally modulation of the brief signal, the transmitter and receiver can cooperate to optimize communication and save energy. |
| US11509378B2 |
Apparatus search for optimal directional beams
A wireless communication system which includes first and second wireless station apparatuses having a plurality of antenna elements and performs directivity forming. For T1 and T2 such that T2=N2×T0 and T1=N1×T2 with a predetermined period T0, the wireless communication system performs the steps of sequentially switching N1 types of directional beams at intervals of period T2 and transmitting signals while performing switching with an identical directional beam switching pattern maintained over period T1, sequentially switching N2 types of directional beams at intervals of period T0 and receiving signals over the period T1 or more while performing switching with an identical directional beam switching pattern maintained over the period T2, searching for a directional beam having a highest reception level among those acquired over a predetermined period, and setting the searched directional beam as a directional beam to be used. |
| US11509374B2 |
Method for determining index of orthogonal basis vector and device
Some embodiments of this disclosure provide a method for determining an index of an orthogonal basis vector and a device. The method includes: receiving position information, where the position information is associated with an orthogonal basis vector; and determining at least one first index set based on the position information, where the first index set represents a set of column indices of a plurality of orthogonal basis vectors in an orthogonal basis matrix. |
| US11509369B2 |
Transmission and reception method for multi-modal apparatus in millimeter band
A communication technique and a system thereof for are provided fusing a 5G communication system to support higher data rates, which is subsequent to the 4G system, with IoT technology. The disclosure may be applied to intelligent services (e.g., smart homes, smart buildings, smart cities, smart cars or connected cars, healthcare, digital education, retail business, security and safe-related services, etc.) based on 5G communication technology and IoT-related technology. A method of operating a base station in a wireless communication system includes transmitting channel feedback configuration information to a terminal; receiving channel feedback information from the terminal; and performing transmission/reception of data, based on the channel feedback information. The channel feedback information may include information indicating a state of an antenna panel of the terminal. |
| US11509367B2 |
Coefficient determination for measurement report feedback in multi-layer beamformed communications
Methods, systems, and devices for wireless communications are described that provide for channel state information (CSI) feedback for multiple discrete Fourier transform (DFT) beams on multiple transmission layers. A user equipment (UE) may report a total number of non-zero power DFT beams across all of the transmission layers. The UE may be configured with a total number of leading beams (Ktotal) across all of the transmission layers for which to provide high quantization feedback. When the total number of non-zero DFT beams across all the transmission layers exceeds the configured total number of leading beams across all the transmission layers, the UE may report high-resolution quantization feedback for Ktotal non-zero power precoding coefficients having the highest amplitude coefficients, and may report low-resolution quantization feedback for the remaining non-zero power precoding coefficients. A base station may receive the CSI feedback to determine a precoding matrix. |
| US11509362B2 |
Wireless signal transmitting method and wireless apparatus
Interference in preamble signals and pilot signals in cooperative transmission using interference suppressing technology is avoided. A wireless apparatus for transmitting a wireless signal on which directivity control has been performed to stations in a wireless system including at least one wireless apparatus is provided with a known signal generating unit which generates a known signal to be added to the wireless signal, a weighting processing unit which performs weighting on the known signal generated by the known signal generating unit, and a wireless processing unit which transmits the known signal on which the weighting has been performed by the weighting processing unit. |
| US11509360B2 |
Terminal device capability transmission method, apparatus, and system
Embodiments of this application disclose a terminal device capability transmission method, apparatus, and system. A terminal device reports, to a network device, capability information used to indicate a channel state information CSI reporting capability of the terminal device. The capability information is associated with a quantity, supported by the terminal device in a time-domain unit, of ports of pilots used for CSI measurement, and is used to enable the network device receiving the capability information to learn the CSI reporting capability of the terminal device, thereby determining a CSI measurement configuration of the terminal device. |
| US11509358B2 |
Method for receiving reference signal in wireless communication system and apparatus therefor
Disclosed is a method for receiving a channel state information (CSI)-reference signal (RS) by a user equipment (UE) in a wireless communication system, which includes: receiving a CSI-RS associated with the SSB, in which the CSI-RS may be assumed to be quasi co-located (QCL) with the SSB. |
| US11509353B2 |
Communication systems and methods over direct current (DC) power conductors to remote subunits
Communication systems and methods over direct current (DC) power conductors to remote subunits may include interrupt windows in a power signal on a DC power conductor for safety reasons. The timing of rising and falling edges of the interrupt window may be modified, thereby changing the duration, period, or position within a period of the interrupt window. In effect, interrupt windows within the DC power signal may be pulse width modulated to send data between a power source and one or more subunits. Pulse width modulation (PWM) of the DC power signal preserves the safety features, but allows data and/or commands to be transferred between the power source and any subunits. |
| US11509346B2 |
Systems and methods for die-to-die communication
A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency. |
| US11509341B2 |
Systems and methods for reconfiguring buttons of a remote control device
Aspects of the disclosure relate to a remote control which may include one or more buttons configured to provide input to the remote control upon being activated, a transmitter for transmitting data, a receiver for receiving data, a processor and memory storing computer executable instructions that, when executed, cause the two-way remote control to perform a method for configuring repeat transmission behavior of one or more of the buttons of the two-way remote control. Further, the receiver may be configured to receive data from a device configured to be controlled by the remote control and the data may include instructions for configuring the repeat transmission behavior of the one or more buttons of the two-way remote control. Additionally, the two-way remote control may configure the repeat transmission behavior of the one or more buttons of the two-way remote control based on the data received from the device. |
| US11509336B2 |
Radio-frequency circuit, communication device, and antenna module
A radio-frequency circuit includes a first power amplifier that outputs a first transmission signal and a second power amplifier that outputs a second transmission signal having a frequency different from a frequency of the first transmission signal. In a period in which the first transmission signal the second transmission signal are simultaneously outputted, at least one of the first power amplifier or the second power amplifier reduces transmission power of the at least one of the first power amplifier or the second power amplifier to cause a power component of intermodulation distortion superimposed on a transmission signal output from the first power amplifier and the second power amplifier to be less than or equal to a threshold value. |
| US11509329B2 |
Compression of power system signals
The present disclosure pertains to systems and methods to compress an input signal representing a parameter in an electric power system. In one embodiment, a system includes a data acquisition subsystem to receive an input signal comprising a plurality of high-speed representations of electrical conditions. A linear prediction subsystem generates an excitation signal estimate based on the input signal, a plurality of linear prediction coefficients based on the input signal, and an estimated signal based on the excitation signal estimate and the plurality of linear prediction coefficients. An error encoding subsystem may generate an encoding of an error signal based on a difference between the input signal and the estimated signal. A non-transitory computer-readable storage medium may store an encoded and compressed representation of the input signal comprising the excitation signal estimate, the plurality of linear prediction coefficients, and the encoding of the error signal. |
| US11509326B2 |
Sigma-delta analogue to digital converter
A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source. |
| US11509324B2 |
Analog-to-digital conversion system for stabilizing supply voltage and method of the same
An analog-to-digital conversion system includes an analog-to-digital converter and a power supply. The analog-to-digital converter is configured to convert an analog input signal to generate a digital output signal, and configured to generate a control signal according to a state of converting the analog input signal. The power supply is configured to provide a supply voltage to the analog-to-digital converter, and change the ability to provide the supply current of the power supply according to the control signal to stabilize the supply voltage. |
| US11509323B2 |
Adaptive low power common mode buffer
A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation. |
| US11509317B2 |
Systems and methods for integration of injection-locked oscillators into transceiver arrays
Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal. |
| US11509314B2 |
All-digital phase-locked loop
The present disclosure discloses an all-digital phase-locked loop. The all-digital phase-locked loop may include a time-to-digital conversion circuit configured to convert phase differences between a reference signal and a feedback signal into respective digital values and to output a first data signal and a second data signal corresponding to the respective digital values, a digital loop filter configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating the valid data and a first register signal, a digitally controlled oscillator configured to generate an oscillation signal and control a frequency of the oscillation signal in response to the control signal, and a divider configured to divide the oscillation signal and output the feedback signal to the time-to-digital conversion circuit. |
| US11509312B1 |
Apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops
An apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops (PLLs). The apparatus coupled within each PLL comprises: a local counter configured to provide a count when receiving a reference clock signal; a comparator configured to compare the count from the local counter with a predetermined or preconfigured value; wherein a multiplexor connected to the local counter and counters of adjacent PLLs, configured to select the count from the local counter or a count from the counters of the adjacent PLLs; wherein the selected count from the multiplexor is incremented and directed to the local counter; wherein an output clock divider enable is asserted to the PLL to start an output clock divider to generate the output clock signal when the count from the local counter reaches the predetermined or preconfigured value. |
| US11509310B2 |
Charge locking circuits and control system for qubits
Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate. |
| US11509306B2 |
Flip-flop device and method of operating flip-flop device
An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal. |
| US11509300B2 |
Switch module for an electronic switch
An electronic switch includes switching modules to change a forward resistance of a semiconductor switch via a drive circuit depending on data exchanged via a data interface and depending on measurement values of a current sensor. The semiconductor switches of the switching modules are arranged electrically in parallel and a current through the electronic switch is divided among the semiconductor switches. The electronic switch controls a division of the current through the electronic switch among the semiconductor switches via the drive circuits by changing a forward resistance of the semiconductor switches, synchronously switches the semiconductor switches via the drive circuit and operates the semiconductor switches in a linear region in a time range of 1 μs to 10 μs upon a change between ON and OFF and a change between OFF and ON in such a way that the current through the switching modules is reduced in a controlled manner. |
| US11509298B2 |
Comparator providing offset calibration and integrated circuit including comparator
A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal. |
| US11509297B2 |
Duty cycle correction circuit including a reference clock generator
A duty cycle correction circuit includes a first duty cycle detecting circuit configured to detect a duty cycle of a clock signal with a first resolution; a reference clock generating circuit configured to generate a reference clock signal by adjusting a phase of the clock signal; a second duty cycle detecting circuit configured to detect a duty cycle of the clock signal with a second resolution according to the reference clock signal and the clock signal, the second resolution being finer than the first resolution; a first duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more first control signals output from the first duty cycle detecting circuit; and a second duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more second control signals output from the second duty cycle detecting circuit. |
| US11509295B2 |
High-speed flip flop circuit including delay circuit
A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level. |
| US11509294B2 |
Reduced area, reduced power flip-flop
A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter. |
| US11509293B2 |
Footprint for multi-bit flip flop
An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals. |
| US11509290B2 |
Filter and multiplexer
A filter includes a series arm resonator that defines at least a portion of a signal path connected between first and second terminals, a parallel arm resonator including one end that is grounded, a first inductor including one end that is connected to one end of the series arm resonator and another end that is connected to another end of the parallel arm resonator, and a second inductor including one end that is connected to another end of the series arm resonator and another end that is connected to the other end of the parallel arm resonator. A relative band width of the parallel arm resonator is smaller than a relative band width of the series arm resonator. |
| US11509286B2 |
BAW resonator with increased quality factor
A BAW resonator comprises a center area (CA), an underlap region (UL) surrounding the center area having a thickness smaller than the thickness dC of the center region and a frame region (FR), surrounding the underlap region having thickness dF greater than dC. |
| US11509285B2 |
Wireless sensor system for harsh environment
A sensor system that combines the sensing application of surface acoustic wave (SAW) sensor and sensor signal transfer though the enclosure wall via acoustic means. The sensor system includes SAW sensor placed inside the enclosure and at least one pair of bulk acoustic wave (BAW) transducers, one mounted inside and second outside the enclosure wall, allowing the interrogation of SAW sensor from outside the enclosure. The external BAW transducer converts interrogation electrical pulse into acoustic pulse which travels though the enclosure wall to the internal BAW transducer. The internal BAW transducer converts the interrogation electrical pulse to electrical pulse and transfers it to SAW sensor. The response of the SAW transducer containing series of electric pulses is converted to the series of acoustic pulses by internal BAW transducer which propagates though enclosure wall. The external BAW transducer converts the series of acoustic pulses into series of electrical pulses and is received by the interrogation circuit for processing. |
| US11509284B2 |
Acoustic wave device and radio-frequency front-end circuit
An acoustic wave device includes a piezoelectric layer, an IDT electrode, a high-acoustic-velocity support substrate, and a low-acoustic-velocity film. The high-acoustic-velocity support substrate is located on an opposite side of the piezoelectric layer from the IDT electrode in the thickness direction of the piezoelectric layer. The low-acoustic-velocity film is disposed between the high-acoustic-velocity support substrate and the piezoelectric layer in the thickness direction. The high-acoustic-velocity support substrate includes a base region and a surface region disposed nearer to the low-acoustic-velocity film than the base region in the thickness direction and whose crystal quality is worse than that of the base region. The surface region includes first and second layers disposed nearer to the base region than the first layer in the thickness direction and whose crystal quality is better than that of the first layer. |
| US11509282B2 |
Acoustic wave device
An acoustic wave device includes a support substrate including silicon, a piezoelectric layer provided directly or indirectly on the support substrate, and an interdigital transducer (IDT) electrode provided on the piezoelectric layer. When a wavelength defined by an electrode finger pitch of the IDT electrode is λ, a thickness of the piezoelectric layer is about 1λ or less. VL, which is an acoustic velocity of a longitudinal wave component of a bulk wave propagating through the piezoelectric layer, satisfies Unequal Equation (2) below in relation to an acoustic velocity VSi-1 determined by Equation (1) below: VSi-1=(V2)1/2 (m/sec) Equation (1), VSi-1≤VL Unequal Equation (2), V2 in Equation (1) is a solution of Equation (3), and Ax3+Bx2+Cx+D=0 Equation (3). |
| US11509281B2 |
Acoustic wave device
An acoustic wave device includes first and second IDT electrodes electrically connected in series with each other by a common busbar common to the first and second IDT electrodes. In each of a first acoustic impedance layer and a second acoustic impedance layer, at least one of at least one high acoustic impedance layer and at least one low acoustic impedance layer is a conductive layer. At least a portion of the conductive layer in the first acoustic impedance layer and at least a portion of the conductive layer in the second acoustic impedance layer do not overlap with the common busbar when viewed in plan from a thickness direction of a piezoelectric layer. The conductive layer in the first acoustic impedance layer and the conductive layer in the second acoustic impedance layer are electrically insulated from each other. |
| US11509280B2 |
Elastic wave device and method for manufacturing the same
An elastic wave device includes a supporting substrate, a high-acoustic-velocity film stacked on the supporting substrate and in which an acoustic velocity of a bulk wave propagating therein is higher than an acoustic velocity of an elastic wave propagating in a piezoelectric film, a low-acoustic-velocity film stacked on the high-acoustic-velocity film and in which an acoustic velocity of a bulk wave propagating therein is lower than an acoustic velocity of a bulk wave propagating in the piezoelectric film, the piezoelectric film is stacked on the low-acoustic-velocity film, and an IDT electrode stacked on a surface of the piezoelectric film. |
| US11509279B2 |
Acoustic resonators and filters with reduced temperature coefficient of frequency
Acoustic resonator devices and filters. An acoustic resonator includes a substrate having a surface and a lithium niobate plate. A back surface of the lithium niobate plate is attached the substrate except for a portion of the lithium niobate plate forming a diaphragm that spans a cavity in the substrate. An interdigital transducer (IDT) is formed on a front surface of the lithium niobate plate such that interleaved fingers of the IDT are disposed on the diaphragm. The IDT and the lithium niobate plate configured such that a radio frequency signal applied to the IDT excites a shear primary acoustic mode within the diaphragm. Euler angles of the lithium niobate plate are [0°, β, 0°], where β is greater than or equal to 40° and less than or equal to 70°. |
| US11509277B2 |
Piezoelectric single crystal silicon carbide microelectromechanical resonators
A resonator has a resonator body and a frame at least partially surrounding the resonator body, the resonator body being coupled to the frame by at least one tether. The resonator body, frame and at least one tether comprise silicon carbide. A plurality of interdigitated electrodes are disposed on the silicon carbide resonator body. The resonator body preferably comprises 6H silicon carbide and preferably has a crystalline c-axis oriented generally parallel to a thickness direction of the resonator body. |
| US11509270B2 |
Device stack with novel gate capacitor topology
Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution. |
| US11509269B2 |
Radio frequency (RF) amplifier bias circuit
An amplifier circuit includes an amplifier configured to receive a radio frequency (RF) input signal from an input node, a bias circuit comprising a reference transistor coupled between a reference current source and ground, and a bias transistor coupled to the reference transistor and configured to generate a main bias current to bias the amplifier, an input power sense circuit coupled to the input node, and an additional transistor coupled to the input power sense circuit and to the bias transistor, the additional transistor configured to generate an additional bias current to bias the amplifier, the additional bias current responsive to a power level of the RF input signal. |
| US11509265B2 |
Integrated circuit, oscillator, electronic apparatus, and vehicle
An integrated circuit includes a first coupling terminal and a second coupling terminal disposed along a first side, an oscillation circuit which is electrically coupled to a resonator element via the first coupling terminal and the second coupling terminal, a temperature sensor, a temperature compensation circuit configured to compensate a temperature characteristic of the resonator element based on an output signal of the temperature sensor, and an output circuit to which a signal output from the oscillation circuit is input, and which is configured to output an oscillation signal, wherein d1 |
| US11509261B2 |
Verta solar sun panel
Systems for generating solar power are provided. One such system includes a solar radiation collector and one or more side-emitting fiber-optic cables, coupled to the solar radiation collector. The system further includes one or more photovoltaic cell enclosures, including an outer housing and one or more photovoltaic cells, wherein the one or more side-emitting fiber-optic cables is positioned within the outer housing and configured to emit, to the one or more photovoltaic cells, solar radiation collected from the solar radiation collector. |
| US11509260B1 |
Reclamation of energy leaking from waveguides
Techniques related to reclamation of energy leaking from waveguides are disclosed. One or more photovoltaic cells may receive light leaking from a waveguide at a first surface of the wave guide. The first surface may be opposite to a second surface at which an in-coupling element is located. The light leaking from the waveguide results from inefficiency in redirecting incoming light for propagation within the waveguide. The one or more photovoltaic cells may generate electric power from the light leaking from the waveguide. |
| US11509258B2 |
Solar tracking installation
Solar tracking installation includes first movement assembly which functionally engages with the primary axis shaft to cause rotation of the primary axis shaft around the primary axis for moving the plurality of planar modules of solar collector elements in a first rotational direction around the primary axis. The installation further includes a second movement assembly which functionally engages with the secondary movement member to cause tilting of each of the plurality of planar modules of solar collector elements around each respective pivotal mount. In this way the movement of the multitude of solar collection elements is a combination of the rotation of first movement assembly and the tilting motion caused by the second movement assembly. |
| US11509256B2 |
Method and system for an engine
A system includes a generator coupled to an engine and configured to generate electricity from rotational movement of a shaft of the engine, a motor configured to be driven by the generator through one or more power conversion components, the motor configured to drive a load, a sensor configured to measure generator output, and a controller configured to detect engine imbalance based on a frequency content of a signal output from the sensor in response to a contribution to the frequency content from the one or more power conversion components and/or the load of the motor being less than a threshold value. |
| US11509255B2 |
Electric machine fault detection scheme
A short circuit detection system and method that identifies a short circuit between turns of a winding of a permanent magnet machine having a three-phase winding in response to detection of imbalances between the three motor phases at an instant in time. The imbalances are identified by monitoring motor terminal voltages and currents. |
| US11509252B2 |
Management of the number of active power cells of a variable speed drive
A method for controlling a variable speed drive supplying power to an electric motor, the variable speed drive comprising a plurality of at least Ni low-voltage power cells connected in series, comprising: upon reception of a speed command, determining a number Mi of cells sufficient to supply power to the motor at a target voltage V that is determined based on the speed command; and activating the Mi power cells from among the Ni power cells, and deactivating the Ni-Mi other power cells in order to supply power to the motor in accordance with the speed command. |
| US11509248B2 |
Position estimation device and position estimation method
A position estimation device acquires detection values of magnetic field strength at three or more locations of a rotor in a range where a rotor angle is less than one rotation. A section is selected based on a detection value of the magnetic field strength from predetermined sections for a pole pair number of the rotor. A feature amount calculator is provided to calculate feature amounts of a waveform of the magnetic field strength based on a combination of the detection values of the magnetic field strength according to the section selected. An estimator is provided to determine, for each segment associated with the section selected, whether or not a magnitude relationship of the feature amounts learned in advance coincides with a magnitude relationship of the feature amounts calculated, and estimating, as a rotation position of the rotor, the pole pair number associated with the segment having the same magnitude relationship. |
| US11509247B2 |
Device and method to reduce clutch engagement speed
A safety device includes a safety module and a safety control module in order to reduce a speed of an unwanted clutch engagement when a malfunction of a motor for a clutch control actuator occurs, such as by the power supply for the motor being interrupted, so that a driver can have more time to react in such situation. |
| US11509245B2 |
Electrical architecture for an aircraft, aircraft comprising the architecture and method for operating the architecture
An architecture for an aircraft comprises two air-conditioning systems, two converters, each intended to supply one of the air-conditioning systems, and at least one first electric machine which starts up a first main engine of the aircraft. The electrical architecture is configured such that the two converters can together supply the first electric machine. A method of operating the architecture is also provided. |
| US11509234B2 |
Power conversion apparatus
A power conversion apparatus has a positive electrode bus bar and a negative electrode bus bar. The power conversion apparatus has a first semiconductor module incorporating an upper-arm switching element and including a positive electrode terminal and a second semiconductor module incorporating a lower-arm switching element and including a negative electrode terminal. The first semiconductor module and the second semiconductor module are placed such that the positive electrode terminal and the negative electrode terminal face each other in a direction orthogonal to a protruding direction. The positive electrode bus bar and the negative electrode bus bar respectively have coexisting parts placed together between the positive electrode terminal and the negative electrode terminal as seen in the protruding direction of power terminals. The coexisting parts are at least partially placed in a space between the positive electrode terminal and the negative electrode terminal. |
| US11509231B2 |
Matrix converter control using predicted output current
There is provided a method of generating a control strategy based on at least three switching states of a matrix converter. The at least three switching states are selected based on at least a predicted output current, associated with each switching state, and a desired output current. In particular, mathematical transformations of a desired output current as well as output currents associated with each of a plurality of switching states are used to identify appropriate switching states. |
| US11509230B2 |
Power stage controller for switching converter with clamp
A power stage controller includes: a reference circuit having a first reference input and a reference output, the first reference input adapted to be coupled to an input terminal of a power stage, and the reference circuit configured to adjust a reference voltage at the reference output responsive to whether a voltage at the first reference input is below a threshold; and a comparator having a current sense input, a second reference input, and a comparator output, the current sense input adapted to be coupled to a current terminal of the power stage, the second reference input coupled to the reference output, and the comparator output coupled to a driver input of a driver circuit configured to configured to control a driver output adapted to be coupled to a gate of a transistor of the power stage and responsive to the driver input. |
| US11509226B2 |
Power converter and image processing apparatus
A power converter includes a first circuit including an inductor and configured to convert an input voltage into a first voltage, a second circuit including a transformer and configured to convert the first voltage input to the insulating transformer to a second voltage, a control circuit configured to control the first circuit, a first power supply circuit including a first winding magnetically coupled to the inductor and configured to output a third voltage generated by the first winding to the first control circuit, and a second power supply circuit including a second winding magnetically coupled to the transformer and configured to output a fourth voltage generated by the second winding to the first control circuit. When the second voltage is not output the third voltage is output to the control circuit, and when the second voltage is output the fourth voltage is output to the control circuit. |
| US11509225B2 |
Power IC including a feedback resistor, and a switching power supply and electronic appliance including the power IC
This power supply IC is a semiconductor integrated circuit device serving as a main part for controlling a switching power supply and is formed by integrating a feedback resistor and an output feedback control unit on a single semiconductor substrate, said feedback resistor generating a feedback voltage by dividing the output voltage of the switching power supply (or the induced voltage appearing across an auxiliary winding provided on the primary side of a transformer included in an insulation-type switching power supply), said output feedback control unit performing output feedback control of the switching power supply in accordance with the feedback voltage. The feedback resistor is a polysilicon resistor having a withstand voltage of 100 V or more. A high-voltage region having higher withstand voltage in the substrate thickness direction than the other region is formed in the semiconductor substrate, and the feedback resistor is formed on the high-voltage region. |
| US11509223B2 |
Switched-mode power supply with bypass mode
In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%. |
| US11509222B2 |
Voltage converter with loop control
A voltage converter system includes a switch configured to switch between first and second states responsive to a first control signal. Timer circuitry is configured to generate a timing signal representing a duration of the first state based on input and output voltages of the voltage converter system. Control logic is coupled to the switch and the timer circuitry, and configured to generate the first control signal based on a second control signal. The second control signal is based on a feedback voltage and a reference voltage. Timer control circuitry is coupled to the control logic and the timer circuitry, and configured to: detect a phase difference between the first control signal and the second control signal; and adjust the timer circuitry to change the duration based on the phase difference. |
| US11509213B2 |
LLC resonant converter, control unit, and method of controlling the same
An LLC resonant converter includes a square wave generator having a first switch and a second switch, a resonant tank, a transformer, a synchronous rectifying (SR) unit having a first SR switch and a second SR switch, and a control unit. The control unit provides a first control signal controls the first switch, a second control signal controls the second switch, a first rectifying control signal controls the first SR switch, a second rectifying control signal controls the second SR switch. When a frequency control command is lower than a phase-shift frequency, the first control signal and the first rectifying control signal are frequency-variable and phase-shifted, and the second control signal and the second rectifying control signal are frequency-variable and phase-shifted. |
| US11509206B2 |
Linear-motor type transport device for transporting material for absorbent article and method for manufacturing absorbent article
A linear-motor type transport device for transporting material for an absorbent article includes: a shaft portion that has an axial direction, a radial direction, and a circumferential direction; a pair of guide portions that is disposed on the shaft portion with a predetermined axial-direction space between the guide portions and that forms an orbital transport path that extends along the circumferential direction; a mobile unit that moves on the transport path along the guide portions while supporting a transport head rotatably about a rotation axis; a cam mechanism that rotates the transport head about the rotation axis through a predetermined angle when the mobile unit is moved on the transport path; and a controller that moves the mobile unit by supplying currents to conductors and generating a propulsive force between one of the conductors and a magnet that is disposed on the mobile unit. |
| US11509203B2 |
Claw-pole motor with rotor flux concentrators and poles and stator with solenoid coil and alternating stator teeth
A claw-pole motor comprising a non-magnetic rotary shaft having a longitudinal axis, a plurality of flux concentrators extending along the longitudinal axis of the rotary shaft, and a plurality of magnetic claw poles extending along the longitudinal axis of the rotary shaft, each of the plurality of flux concentrators alternating with each of the magnetic claw poles about the rotary shaft, and a stator having a plurality of coil assemblies, each coil assembly including a solenoid coil and an enclosure having a upper portion and lower portion, the upper portion and the lower portion of the enclosure having alternating stator teeth about the longitudinal axis. |
| US11509201B2 |
Electric fan
An electric fan for producing thrust to propel an aircraft is disclosed. The electric fan comprises a stator, a fan rotor rotatably mounted relative to the stator and an electric motor mounted to the stator and drivingly engaged with the fan rotor to cause rotation of the fan rotor relative to the stator. The fan rotor comprises an annular body defining a flow passage therethrough and a plurality of fan blades disposed in the flow passage and mounted for common rotation with the annular body about a fan rotation axis. The electric motor has a motor rotation axis that differs from the fan rotation axis. |
| US11509198B2 |
Electromagnetic interference suppression
A power tool comprising: a conductive tube; a rear unit located at a rear end of the tube; a front unit located at a front end of the tube; a battery interface comprising a plurality of terminals, wherein the battery interface is located in the rear unit; a motor located in the front unit; at least one power line for supplying power from the rear unit to the front unit, wherein at least a portion of the power line is located within the tube; and an electromagnetic interference (EMI) suppressor for suppressing EMI from the at least one power line, the EMI suppressor comprising an electrical component electrically connecting the tube to a first terminal of the plurality of terminals. |
| US11509189B2 |
Rotary actuator
A rotary actuator is used in a shift-by-wire system for a vehicle. The actuator includes a motor, a controller, a housing, and a bus bar. The controller controls the motor. The housing holds a stator of the motor and the controller. The bus bar includes a terminal and a holder. The terminal electrically connects a coil of the stator to a control board of the controller. The holder is molded with a part of the terminal. The terminal includes a board-side arm that extends from the holder and a connecting pin that protrudes from the board-side arm toward the control board and that is connected to the control board. The board-side arm includes a stress releasing member that extends along an imaginary plane in parallel with the control board. The stress releasing member includes at least one curved portion at which the stress releasing member is curved or bent. |
| US11509188B2 |
End plate for motor casing
An end plate for a motor with a motor casing. The end plate includes a body adapted to be coupled to the motor casing and cover an opening of the motor casing. The body defines a ribbed structure to shield a power terminal assembly disposed laterally outwardly with respect to the motor casing. The ribbed structure includes a first rib and a second rib spaced apart from the first rib, and the power terminal assembly is adapted to be coupled to and be captured in between the first rib and the second rib. |
| US11509178B2 |
Electric machine distributed cooling system and method
An electric machine including a distributed cooling system is disclosed. The electric machine includes a housing, a stator assembly, a rotor assembly, and a distributed cooling system. The distributed cooling system comprising at least one inlet, a first passage, a second passage, and a third passage. The first passage extending axially in a first direction through at least a portion of the rotor shaft to direct a flow of coolant in the first direction. A second passage fluidly coupled to the first passage extending in a second direction through at least a portion of the rotor shaft between a receiving end and a distributing end. At least one third passage fluidly coupled to the second passage extending between a first end and a second end and distributes coolant received from the second passage to at least one of the first end or the second end into the stator assembly. |
| US11509176B2 |
Rotating electrical machine and production method thereof
A rotating electrical machine is equipped with a rotor and a stator. The rotor includes a magnet unit and a rotor core retaining the magnet unit. The rotor core is made of a stack of annular core plates and an annular end plate mounted on an end of the stack of the core plates. The end plate has a deformable wave shape. The stack of the core plates and the end plate has formed therein through-holes extending through a length thereof. Bar-shaped fastening members, such as rivets, which have flanges on ends thereof are inserted into the through-holes with the flanges pressing the end plate to elastically deform the wave shape of the end plate, thereby tightly gripping the stack of the core plates in the lengthwise direction. This minimizes concentration of stress on the core plates to eliminate a risk of damage or breakage of the rotor. |
| US11509173B2 |
Method of wireless charging and electronic device supporting wireless charging
A method for wireless charging an electronic device and a method therefor are provided. The electronic device includes a near field communication device, a wireless charging device including a conductive coil, and at least one processor operatively connected to the near field communication device and the wireless charging device. The at least one processor is configured to transmit a first ping, using the near field communication device, receive first acknowledgement (ACK) information responsive to the first ping from an external electronic device, transmit a second ping, using the wireless charging device, based on that the first ACK information is received, and control the wireless charging device such that a charging current flows through the conductive coil based on second ACK information responsive to the second ping being received from the external electronic device within a specified time from the transmission of the second ping. |
| US11509170B2 |
Wireless power transmission system comprising reception coil having constant pitch
A wireless power receiving apparatus, according to an example embodiment, may include a receiving coil in which a first wire including a copper core and a second wire not including a copper core are wound around a same axis. The second wire may be located at a pitch of the first wire, and a diameter of the second wire may correspond to the pitch of the first wire. |
| US11509166B2 |
Microgrid control system and microgrid
Provided in the present invention are a microgrid control system and a microgrid, the microgrid control system comprising: a grid-connected switch, an energy router, a first controller and a second controller; the first controller controls the grid-connected switch and sends a first control instruction; the second controller receives the first control instruction and responds to the first control instruction for controlling the energy router. |
| US11509164B2 |
Systems and methods for solar energy management
Systems and methods are provided for solar energy management that can charge a battery from a solar panel as well as operate without a battery, using the same equipment. This multi-modal functionality provides the ability to incrementally increase capacity and extend the availability of electricity from daytime-only to a continuous supply irrespective of solar conditions. |
| US11509153B2 |
Charge/discharge control method for storage system and charge/discharge control device
In a storage system including a plurality of battery units, the charge/discharge amounts of the battery units are determined by predetermined computation using the state of charge (SOC). The predetermined computation includes allocating a larger discharge amount to a battery unit higher in SOC, out of the battery units, in the discharge mode, and allocating a larger charge amount to a battery unit lower in SOC, out of the battery units, in the charge mode. |
| US11509146B1 |
Dual-battery charging apparatus and control method
A battery charging apparatus includes a first converter having an input coupled to an input voltage bus and an output coupled to a first battery, and a second converter having an input coupled to the input voltage bus and an output coupled to the first battery and a second battery through a first bidirectional current blocking switch and a second bidirectional current blocking switch, respectively. |
| US11509145B2 |
In-situ on-line and embedded battery impedance measurement device using active balancing circuits
The present disclosure relates to methods and systems for management and control of interconnected energy storage modules, such as battery packs, that can form a larger energy storage system. The disclosure also relates to methods and system for the measurement of cell impedances in a battery pack in-situ and on-line and using active balancing circuits that may already be present in the battery pack. The methods and systems can inject disturbances of different frequencies and measure impedance by using the active balancing circuits present in the battery pack, which can transform an active balancer into a dual active balancer and impedance measurement system. The speed up of impedance measurement energy storage modules can be accomplished by using multi-tone, orthogonal or spread spectrum waveforms applied simultaneously on all or a sub-set of the active balancer circuits in an active balancer. |
| US11509144B2 |
Large-format battery management system with in-rush current protection for master-slave battery packs
A system for suppressing inrush currents is described. The system may include a negative temperature coefficient (NTC) thermistor and a positive temperature coefficient (PTC) thermistor arranged in series between a power source and a battery system to be charged. At a low temperature, while the PTC thermistor provides only minimal resistance to minimize an inrush current, the NTC thermistor provides increased resistance. As the temperature increases, the resistance provided by the PTC thermistor increases as the resistance from the NTC thermistor decreases. The system may be used in conjunction with a battery charging system has at least one current pathway from the power source to the battery system. |
| US11509139B2 |
Load re-balancing on a multi-phase power system
A system for load balancing on a multi-phase power line connected to a single phase lateral power line, includes a contactor configured to selectively connect each phase of the multi-phase power line to the single phase lateral power line. There is a phase change device connected in parallel with the contactor and a controller. During the phase change state, the controller connects the input of the phase change device to the multi-phase power line and connects the output of the phase change device the single phase lateral power line. The controller causes the phase change device to output a voltage to the single phase lateral line initially aligned with the first phase and then rotated to align with the second phase and causes the contactor changes connection to the second phase of the multi-phase power line and disconnect the phase change device from the power lines. |
| US11509138B1 |
System and method for improving transient stability of grid-connected wind generator system
A power electronic control-based capacitor to be used at the terminal of a grid-connected wind generator system for improving the transient stability of the generator following a fault in the network. This eliminates the need of adding auxiliary control devices at the grid side. The wind generator terminal capacitor is controlled through power electronics in such a way as to function both at the steady state and transient conditions maintaining the stability of the wind generator. A power electronic control-based terminal capacitor (“C”) is connected through two back-to-back thyristor switching devices, T1 and T2. The function of the capacitor depends on the triggering or firing-angle of the thyristor switches, which varies from 0 degrees to 180 degrees. |
| US11509134B2 |
Communication interface protection circuit having transient voltage suppression
An interface protection circuit and a device interface are disclosed. The interface protection circuit includes a capacitor and a transient voltage suppressor (TVS) transistor. A first end of the capacitor is connected to a connection port, a second end of the capacitor is connected to a first end of the TVS transistor and an interface chip, and a second end of the TVS transistor is grounded. |
| US11509132B2 |
Intelligent window heat control system
A system for monitoring performance of an aircraft windshield includes a sensor comprising a sensory contact and an evaluation unit. The sensory contact is in physical contact with one or more components of the windshield, and generates a signal representative of the performance of the component(s) of the windshield. An electrical connector is secured to the surface of the windshield facing the interior of the aircraft. The signal from the sensory contact passes through the connector to the evaluation unit. The evaluation unit acts on the signal to determine the performance of the component(s) of the windshield, wherein the evaluation unit is spaced from and out of physical contact with the windshield and the electrical connector, and is in electrical contact with the electrical connector. |
| US11509131B2 |
Wireless power system and method with protection from overvoltage conditions
A wireless power system and method performs wireless power transmission with sensing to detect a distance and/or misalignment of a power receiver from the power transmitter. Power transmission is adjusted in response to the sensing detecting the distance and/or misalignment exceeding a determined threshold, or in response to instructions sent by the receiver based, at least in part, on a duration of the overvoltage condition exceeding a determined time period. |
| US11509130B2 |
Disconnection arc prevention in cable-supplied power connection
Power delivery may be controlled to help prevent arcing when a data cable supplying power from a power source device to a power sink device is disconnected. The presence of a user in proximity to a connection between a cable plug and a cable receptacle may be detected. The level of a power signal being conveyed from the power source to the power sink may be reduced in response to the detection. |
| US11509129B2 |
Electric working machine and method for smoothing AC power supplied thereto
An electric working machine according to one aspect of the present disclosure comprises a motor, a rectifier circuit, a capacitor, a series switching element, a resistive element, a drive circuit, a peak voltage value acquirer, and a controller. The capacitor smooths power rectified by the rectifier circuit. The series switching element is coupled in series with the capacitor. The resistive element is coupled in parallel with the series switching element. The controller brings the series switching element into conduction in a case where AC power is inputted to the rectifier circuit and where a specified conducting condition based on a peak voltage value acquired by the peak voltage value acquirer is satisfied. |
| US11509125B1 |
Adjustable in-ground utilities box assembly
An adjustable in-ground box assembly is configured to form a protective enclosure for an in-ground utilities device. The adjustable in-ground box assembly includes an outer box and an inner box. A reinforced vertical interior fastener panel is formed with a wall of the outer box, and includes a number of pre-formed outer box fastener holes arranged in spaced apart vertical columns. The inner box includes a number of inner box fastener holes arranged in a horizontal row. The height of the in-ground box assembly is vertically adjusted by aligning the inner box fastener holes with horizontally-situated outer box fastener holes at a selected height on the vertical fastener panel. The tilt of the in-ground box assembly is adjusted by aligning the inner box fastener holes with selected diagonally-situated outer box fastener holes. |
| US11509123B2 |
Wiring sheet, sheet-shaped system, and structure operation support system
A wiring sheet includes one or more carbon wires each of which is one of a signal line and a power supply line, and which are conductors including carbon as a main material and have flexibility; and an insulation sheet that encloses substantially an entirety of the one or more carbon wires, includes an electrical insulator as a main material, and has flexibility. |
| US11509117B2 |
Light emitting element
A light emitting element (semiconductor laser element) includes a multilayer structure in which a substrate, semiconductor layers to, an insulating layer, and a metal layer are stacked in order. The light emitting element includes a plurality of light emitting portions each of which emits a laser beam. The plurality of light emitting portions each include a ridge (ridge waveguide). The distance from a specific position in an active region in at least one of the light emitting portions to an inner surface of the metal layer is different from that in another of the light emitting portions. |
| US11509114B2 |
Quantum cascade laser system with angled active region
A QCL may include a substrate, an emitting facet, and semiconductor layers adjacent the substrate and defining an active region. The active region may have a longitudinal axis canted at an oblique angle to the emitting facet of the substrate. The QCL may include an optical grating being adjacent the active region and configured to emit one of a CW laser output or a pulsed laser output through the emitting facet of substrate. |
| US11509113B2 |
Method for producing a plurality of transferable components and composite component of components
A method for producing a composite component (100) and a composite component (100) comprising a plurality of components (10), a removable sacrificial layer (4), an anchoring structure (3) and a common intermediate carrier (90) are specified. The components each have a semiconductor body (2) comprising an active zone (23), are configured to generate coherent electromagnetic radiation and are arranged on the common intermediate carrier. The sacrificial layer is arranged in a vertical direction between the intermediate carrier and the components. The anchoring structure comprises a plurality of anchoring elements (3A, 3B), wherein the anchoring structure and the sacrificial layer provide a mechanical connection between the intermediate carrier and the components. Without the sacrificial layer, the components are mechanically connected to the intermediate carrier solely via the anchoring elements, wherein the anchoring elements are formed in such a way that under mechanical load they release the components so that the components are detachable from the intermediate carrier and are thus formed to be transferable. |
| US11509112B2 |
Mixed-signal frequency control loop for tunable laser
A Lidar system includes a tunable laser configured to generate an output light signal and a photodiode array for receiving light from the tunable laser reflected from a target object. The tunable laser includes a feedback loop including a Mach-Zender interferometer, MZI, receiving the output light signal from the tunable laser, in which the MZI includes two optical paths receiving the output light signal. A phase shifter is provided in one optical path that is operable to produce a pre-determined shift in the phase angle of the light signal passing through the one optical path relative to the phase angle of the light signal passing through the other optical path. A photodiode configured to detect the interference signal generated by the MZI is operable to generate a photodiode current in response thereto. Circuitry converts the photodiode current to a control signal for controlling the tunable laser. |
| US11509110B2 |
Broadband Ho-doped optical fiber amplifier
A broadband optical amplifier for operation in the 2 μm visible wavelength band is based upon a single-clad Ho-doped fiber amplifier (HDFA). A compact pump source uses a combination of discrete laser diode with a fiber laser (which may be a dual-stage fiber laser) to create a pump output beam at a wavelength associated with creating gain in the presence of Ho ions (an exemplary pump wavelength being 1940 nm). The broadband optical amplifier may take the form of a single stage amplifier or a multi-stage amplifier, and may utilize a co-propagating pump and/or a counter-propagating pump arrangement. |
| US11509108B2 |
Tm-doped fiber amplifier utilizing wavelength conditioning for broadband performance
A multi-stage thulium-doped (Tm-doped) fiber amplifiers (TDFA) is based on the use of single-clad Tm-doped optical fiber and includes a wavelength conditioning element to compensate for the nonuniform spectral response of the initial stage(s) prior to providing power boosting in the output stage. The wavelength conditioning element, which may comprise a gain shaping filter, exhibits a wavelength-dependent response that flattens the gain profile and output power distribution of the amplified signal prior to reaching the output stage of the multi-stage TDFA. The inclusion of the wavelength conditioning element allows the operating bandwidth of the amplifier to be extended so as to encompass a large portion of the eye-safe 2 μm wavelength region. |
| US11509107B2 |
Method for producing a multi-core cable and correspondingly produced cable
A method for producing a multi-core cable includes arranging first and second contact elements in a contact carrier having first and second longitudinal channels connecting a contacting side to a cable side, and first and second through-openings respectively crossing the first and second longitudinal channels, and a second through-opening crossing the second longitudinal channel. The first and second longitudinal channels and the first and second through-openings are sealed in a fluid-tight manner by inserting two first sealing pieces into the first through-opening and two second sealing pieces into the second through-opening. In an injection-molding method, a connecting piece is formed connecting the contact carrier to the outer sheath of the cable by overmolding at least a rear section of the contact carrier comprising the first and second through-openings and a section of the cable protruding on the cable side. |
| US11509106B2 |
Punchdown tool
A punchdown tool for fitting wires into connectors including a housing with a front side, a back side, a front end, a rear end opposite the front end, a leading surface on the front end, and an interior defined between the front and back sides. The punchdown tool also includes a drive mechanism with a hammer, an anvil, and a drive spring. The drive mechanism is positioned in the interior of the housing adjacent the front end. The punchdown tool further includes a circuit board positioned in the interior of the housing adjacent the rear end with a controller. The punchdown tool also includes a light positioned on the leading surface of the housing that is electrically coupled to the controller and at least one battery positioned in the interior of the housing for supplying power to the light and the circuit board. |
| US11509103B2 |
Electrical junction box and method for manufacturing electrical junction box
Provided are an electrical junction box for which the time required for production is short, and a method for manufacturing the electrical junction box. An electrical junction box houses an electric device. A plurality of external devices are connected to each other via the electric device housed in the electrical junction box. The electrical junction box includes a housing box and a connector. The housing box is provided with an insertion port 40 into which the connector is inserted, and an opposite opening that is opposite to the insertion port. The insertion port and the opposite opening have the same axial direction. Inside the housing box, a component can be attached to the connector. |
| US11509100B2 |
High density receptacle
A connector assembly includes an insulative housing, first and second conductive ground wafers (see e.g., 661 and 663) and a plurality of grounding links. The insulative housing has a plurality of conductive signal terminals disposed therein (see e.g., 662). The insulative housing has opposite side surfaces and a plurality of openings therein extending between the side surfaces. The second ground wafer is spaced from and parallel to the first ground wafer. The grounding links are electrically connected to one of the ground wafers and extend towards another of the ground wafers and extend through the openings in the housing. |
| US11509099B1 |
Electric connector structure
An electric connector includes an insulative body, multiple conductive terminals, a shielding sheet, and a shielding shell. The insulative body includes a base and a tongue. The conductive terminals include an upper row of terminals and a lower row of terminals, which are disposed on an upper side and a lower side of the tongue, respectively. The shielding sheet is embedded in the insulative body and located between the upper row of terminals and the lower row of terminals. Two sides of the shielding sheet are extended with an extending section respectively. A distal end of each extending section is folded back to form an engaging portion. The shielding shell is adapted to sheathes the insulative body. Two sides of the shielding shell are respectively provided with an engaging trough engaged with one of the engaging portions to make the shielding shell contact with the shielding sheet. |
| US11509093B2 |
Connector assembly device having a connector position assurance device
A connector assembly device includes a connector element and a connector position assurance (CPA) device mounted to move relative to the connector element between a delivery position and a locking position. The connector element includes a first locking device and a second locking device. The CPA device includes a locking lance that has an associated first locking device configured to implement a first form-fitting connection with the first locking device of the connector element and an associated second locking device configured to implement a second form-fitting connection with the second locking device of the connector element in the locking position. The form-fitting connections prevent any movement of the CPA device in a direction from the locking position towards the delivery position and take place in different planes. |
| US11509091B2 |
Cable securing clamp and data transmission device
Provided are a cable securing clamp and a data transmission device. The cable securing clamp includes a clamp body and a snap member. The clamp body is provided with a first through hole, a side wall of the clamp body is provided with a second through hole communicating with the first through hole, and the first through hole is configured to allow a cable to pass through. A first end of the snap member is pivotally connected to the clamp body, a second end of the snap member is in interference fit with the second through hole, a surface of the second end of the snap member is provided with a tooth structure, and the tooth structure is configured to snap the cable in the first through hole such that the cable is secured in an extending direction of the first through hole. |
| US11509089B1 |
Connector assembly with an adaptor
A connector assembly is configured to mate a first connector housing. The connector assembly includes a second connector, a second terminal, a second connector housing, an adaptor and a cover. The second connector housing accommodates the second terminal and includes an opening for providing access to the second terminal. The adaptor is coupled to the second connector housing. The cover is detachably mounted to the adaptor, wherein the adaptor is movable between a first position and a second position. In the first position the cover is separated from the opening of the second connector housing so as to provide access to the first terminal and the second terminal. In the second position the cover is closes the opening of the second connector housing. |
| US11509088B2 |
Dual row low profile high voltage connector and method for assemblying thereof
A dual row low profile high voltage connector, having a minimal height and meeting high voltage requirements and a method of assembling thereof, includes a male housing and a female housing, and further includes a terminal position assurance (TPA) device and a connector position assurance (CPA) device, the TPA device ensuring that a terminal, housed within the female housing, provides a secondary lock, so as to ensure that the terminal is secured or locked within the female housing. The CPA device assures that the male and female housings remain locked. The terminal is housed within the female housing to meet a minimal height requirement and having dual rows of terminals inserted therein the female. The TPA device and the CPA device function in pre-lock or full-lock positions. A method also improves clearance and creepage by allowing a clearance or electrical path to extend around an inserted TPA between terminals. |
| US11509086B2 |
Electrical connector
An electrical connector includes a main body portion having a receiving passage adapted to receive a plate-type plug inserted in an insertion direction, and a locking protrusion formed on the main body portion and protruding toward the receiving passage. The locking protrusion has a connection portion adapted to connect a top portion of the locking protrusion with the main body portion downstream in the insertion direction. |
| US11509084B2 |
Electrical connector assembly having hybrid conductive polymer contacts
An electrical connector assembly is provided and includes a carrier having an upper surface and a lower surface. The lower surface is configured to face a host circuit board. The upper surface is configured to face a component circuit board of an electrical component. The carrier includes a plurality of contact openings therethrough. The electrical connector assembly includes contacts coupled to the carrier and passing through the corresponding contact openings. Each contact has a conductive polymer column extending between an upper mating interface and a lower mating interface. The conductive polymer column is compressible between the upper mating interface and the lower mating interface. The conductive polymer column includes an inner core and an outer support body. The inner core is manufactured from a first material. The outer support body is manufactured from a second material. The second material has a lower compression set than the first material. The first material has a higher electrical conductivity than the second material. |
| US11509080B2 |
Electrical connector assembly having hybrid conductive polymer contacts
An electrical connector assembly includes a carrier having an upper surface and a lower surface. The carrier includes a plurality of contact openings therethrough. The electrical connector assembly includes contacts coupled to the carrier and passing through the corresponding contact openings. Each contact has a conductive polymer column extending between an upper mating interface and a lower mating interface. The conductive polymer column includes an inner core manufactured from a first material and an outer shell manufactured from a second material. The second material has a higher electrical conductivity than the first material. The first material has a lower compression set than the second material. |
| US11509079B2 |
Blind mate connections with different sets of datums
Blind mate connection techniques and associated connectors are disclosed. Blind mate connectors provide connections where visual inspection at time of connection may not be available. Stacking tolerance increases when connectors have a different set of datums (e.g., a different relative orientation) relative to adjacent connectors. Different datums permit twinning two printed circuit boards (“PCBs”) prior to insertion into a slot of a chassis. Each connector may be attached to a respective PCB utilizing a spring and offset feature to provide a standoff on a respective PCB. Control of standoff and rotational movement (e.g., via brackets) allows each individual connector to have a “float” for improved insertion tolerance. Connector pairs may connect through an opening in a midplane while simultaneously connecting to the midplane. Switch trays and node trays may be inserted through opposing sides of a chassis and be connected through the midplane of that chassis. |
| US11509077B2 |
Cover
A cover includes a top wall, a first side wall, a second side wall facing the first side wall, and a lock releasing portion. The first side wall includes a locking portion engageable with a locked portion of a covered body. The second side wall includes an opposed locking portion engageable with an opposed locked portion of the covered body. The lock releasing portion includes: a release operation portion inclined and projecting from the top wall in a cover mounting direction; and a connecting portion connecting the release operation portion with the first side wall around the locking portion or the release operation portion with the locking portion. |
| US11509075B2 |
High frequency electrical connector
An electrical connector that has a conductive shell supporting at least one signal contact therein and that has a front end for mating with a mating connector and a back end opposite the front end for electrically connecting to a coaxial cable. A ground connection is located inside of the conductive shell. A coupling member is rotatably coupled to the conductive shell and has an engagement feature for mechanically engaging a support panel associated with the mating connector. A sealing member is disposed on the conductive shell that is configured to provide an environmental seal between the conductive shell and the support panel when the conductive shell is mated with the mating connector. |
| US11509072B1 |
Radio frequency (RF) polarization rotation devices and systems for interference mitigation
Aspects of the subject disclosure may include, for example, receiving, by a radio frequency (RF) mechanical device, signals relating to one or more crossed-dipole radiating elements of an antenna system, performing, by the RF mechanical device, polarization rotation of the signals to derive output signals having polarizations that are rotated in a manner that mimics physical rotation of the one or more crossed-dipole radiating elements, and providing, by the RF mechanical device, the output signals to enable avoidance of interference. Other embodiments are disclosed. |
| US11509068B2 |
Structure, antenna, wireless communication module, and wireless communication device
A structure includes first to a first conductor, a second conductor, a third conductor, and a fourth conductor. The first conductor extends along a second plane including a second direction and a third direction intersecting with the second direction. The second conductor faces the first conductor along a first direction intersecting with the second plane and extends along the second plane. The third conductor capacitively connects the first conductor and the second conductor. The fourth conductor is electrically connected to the first conductor and the second conductor, and extends along a first plane including the first direction and the third direction. The third conductor faces the fourth conductor via a base. The base includes a plurality of first fiber components and a first resin component that holds the first fiber components. Part of the first fiber components extends along the first direction. |
| US11509065B2 |
Millimeter wave antenna array
An antenna array may include a plurality of printed circuit boards (PCBs) oriented in a stacked arrangement, parallel to and spaced apart from one another. Each of the PCBs may include a linear array of antenna elements, which cooperate with the linear arrays of antenna elements on other PCBs to form a two-dimensional array of antenna elements. The PCBs may be supported at one end by a common backplate in a cantilevered manner, with the linear arrays of antenna elements located near the free end of the PCBs. The PCBs may include a thicker portion and a thinner portion, and the thinner portion may include a heat sink or other thermal dissipation structure. |
| US11509063B2 |
Structure, antenna, wireless communication module, and wireless communication device
There is provided a new type of structure that resonates at a predetermined frequency, an antenna, a wireless communication module, and a wireless communication device. The structure includes a first conductor that extends in a second direction, a second conductor, a third conductor, a fourth conductor. The second conductor faces the first conductor in a first direction and that extends along the second direction. The third conductor is configured to capacitively connect the first conductor and the second conductor. The fourth conductor is configured to be electrically connected to the first conductor and the second conductor and extends along a first plane. Each of the first conductor and the second conductor includes a portion that extends along the second direction and that is exposed to an exterior space. |
| US11509062B2 |
Broadband wire antenna with resistive patterns having variable resistance
The invention relates to a wire antenna adapted to operate in at least one predetermined frequency band, comprising a plurality of superimposed layers, comprising at least one radiating element placed on a support layer, wherein the support layer is placed on a spacer substrate, and wherein the spacer substrate is placed on a reflector plane comprising at least one resistive layer between the support layer of the radiating element(s) and the substrate spacer, while the resistive layer comprises at least two sets of nested resistive patterns. This antenna is such that the sets of resistive patterns have resistance values gradually varying between a central antenna point and an outer edge of the antenna, in order to achieve a resistance gradient. |
| US11509061B2 |
Milliwave band radio wave absorption sheet and milliwave radio wave absorption method
Provided is a light weight and remarkably flexible sheet-shaped radio wave absorber having excellent radio wave absorbing capacity in milliwave band frequencies. The invention is a milliwave band radio wave absorption sheet comprising a radio wave reflection layer (A), a radio wave absorption layer (B) disposed above the layer (A) so as to be parallel thereto, and a protective layer (C) disposed above the layer (B) so as to be parallel thereto. The layer (B) has, at a frequency of 79 GHz, a dielectric constant, wherein the real part is 10 to 20 and the absolute value of the imaginary part is 4 to 10. The layer (B) has a film thickness of 200 to 400 μm. The absolute value of the imaginary part/real part from the dielectric constant is within a range of 0.30 to 0.60. The layer (C) has, at a frequency of 79 GHz, a dielectric constant, wherein the real part is 1.5 to 8.0 and the absolute value of the imaginary part is less than 1.0, and has a film thickness of 50 to 200 μm. In the milliwave band radio wave absorption sheet, the optical reflectance at an incident angle of 60° is 50% or greater, and the optical reflectance at an incident angle of 20° is 25% or greater. In addition, the invention provides a milliwave band radio wave absorption method using the radio wave absorption sheet, and a radio wave damage prevention method involving the installation of the radio wave absorption sheet. |
| US11509055B2 |
Wireless communication device, automatic door, and automatic door system
A wireless communication device includes an antenna and is used for storage as an electrical conductive body. The antenna includes a first conductor and a second conductor, one or more third conductors, a fourth conductor, and a feeding line. The first conductor and the second conductor face each other in a first axis. The one or more third conductors are located between the first conductor and the second conductor and extend in the first axis. The fourth conductor is connected to the first conductor and the second conductor and extends in the first axis. The feeding line is connected to any one of the third conductors. The first conductor and the second conductor are capacitively coupled to each other via the third conductor. The fourth conductor faces a conductor part of the storage. |
| US11509052B2 |
Smart antenna controller system
An information handling system (IHS) includes an antenna system. The antenna system includes a smart antenna and a smart antenna control system, the smart antenna control system controlling configuration of a configurable aspect of the smart antenna based upon information regarding the configurable aspect of the smart antenna. |
| US11509046B2 |
Antenna module and electronic device including the same
Disclosed is an antenna module including a first printed circuit board (PCB) including a first surface facing a first direction and a second surface facing a second direction opposite the first direction, a second PCB including a third surface facing the first direction spaced from the first PCB and a fourth surface facing the second direction spaced from the first surface, a radio frequency integrated circuit (RFIC) disposed on the first surface, and a connection member comprising a conductive material connecting the first surface to the fourth surface. The at least one first conductive pattern is connected to the RFIC. The at least one third conductive pattern is connected to the RFIC via the connection member. The at least one first conductive pattern and the at least one third conductive pattern at least partially overlap with each other at least partly, when viewed from above the second surface. |
| US11509041B2 |
Antenna of mobile terminal, and mobile terminal
Provided are an antenna of a mobile terminal, and a mobile terminal. The antenna includes a dielectric substrate, a ground plate located on one side of the dielectric substrate, and a near-feed unit, a near-ground unit and a coupling unit that are arranged on the other side of the dielectric substrate; the near-ground unit has one end connected to the coupling unit and the other end connected to the ground plate; the coupling unit and the near-ground unit are equivalent to a Left-Handed (LH) inductor; the near-feed unit is equivalent to a Right-Handed (RH) inductor; the coupling unit is coupled to the near-feed unit and is equivalent to an LH capacitor; the coupling unit is coupled to the ground plate and is equivalent to an RH capacitor; and the near-feed unit, the near-ground unit, the coupling unit and the ground plate form a Composite Right-Left-Handed Transmission Line (CRLH-TL) structure. |
| US11509040B2 |
Mobile terminal
The present invention relates to a mobile terminal comprising: a terminal body; a ground provided in the interior of the terminal body; a first conductive member distanced from the ground, electrically supplied from a first supply unit, and surrounding one side of the ground; a second conductive member disposed on one side of the first conductive member, electrically supplied from a second supply unit, and surrounding the other side of the ground; and a junction portion, disposed at one point on the first conductive member, for grounding same to the ground, wherein one end of the first conductive member is distanced from the ground to form a first open slot, one end of the second conductive member is distanced from one end of the first conductive member to form a second open slot, the other ends are connected to the ground, and the first and second conductive members are oriented so as to cross each other. |
| US11509038B2 |
Semiconductor package having discrete antenna device
A semiconductor package includes a bottom chip package having a first side and a second side opposing the first side. The bottom chip package comprises a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. A top antenna package is mounted on the first side of the bottom chip package. The top antenna package comprises a radiative antenna element. A connector is disposed on the second side. |
| US11509034B2 |
Directional coupler
A directional coupler includes a main line through which a signal is transmitted, first and second sub-lines that are selectively coupled to the main line, and a common output port that outputs a detection signal generated by the signal transmitted through the main line, wherein a first degree of coupling between the main line and the first sub-line is different than a second degree of coupling between the main line and the second sub-line. |
| US11509030B2 |
Dielectric filter and communications device
This application provides an example dielectric filter and an example communications device. The dielectric filter includes a dielectric block. At least two resonant through holes that are parallel to each other are provided in the dielectric block. The resonant through hole is a stepped hole. The stepped hole includes a large stepped hole and a small stepped hole that are arranged coaxially and that are in communication. The small stepped hole passes through a first surface of the dielectric block. The large stepped hole passes through a second surface of the dielectric block. A stepped surface is formed between the large stepped hole and the small stepped hole. The surfaces of the dielectric block are covered with conductor layers. The conductor layers cover the surfaces of the dielectric block and inner walls of the large stepped hole and the small stepped hole. A conductor layer of the inner wall of the large stepped hole is short-circuited with a conductor layer of the second surface. A conductor layer of the inner wall of the small stepped hole is short-circuited with a conductor layer of the first surface. A loop gap that does not cover the conductor layers is provided on the stepped surface. The loop gap is arranged around the small stepped hole. |
| US11509025B2 |
Secondary battery and method of manufacturing the same
A negative-electrode terminal that is secured to a sealing plate is connected to a first negative-electrode current collector. A negative-electrode tab that is connected to the negative-electrode sheet is connected to a second negative-electrode current collector. The first negative-electrode current collector and the second negative-electrode current collector are disposed along the sealing plate. The second negative-electrode current collector has an opening. The second negative-electrode current collector is disposed on the first negative-electrode current collector such that the opening faces the first negative-electrode current collector. The second negative-electrode current collector is welded to the first negative-electrode current collector around the opening. |
| US11509019B2 |
Electrochemical device
The present application relates to an electrochemical device. The electrochemical device includes: at least one electrode, the at least one electrode having a first surface; and a fiber coating layer, the fiber coating layer including a fiber and being disposed on the first surface. The electrochemical device has the advantages of high energy density, strong liquid retention ability, good drop resistance, good chemical stability and the like since its fiber coating layer has small thickness, high porosity and stronger interfacial adhesion to the electrode. |
| US11509016B2 |
Papers useful as thermal insulation and flame barriers for battery cells
A paper suitable for use as a cell-to-cell flame barrier in a battery, and a battery comprising the paper, the paper comprising 40 to 70 weight percent fibrids and 30 to 60 weight percent mica, based on the total weight of the fibrids and mica in the paper; wherein the fibrids comprise a blend of 80 to 20 weight percent polymer and 20 to 80 weight percent aerogel powder, based on the total weight of the polymer and aerogel powder in the fibrids; the paper having a thickness of 100 to 4000 micrometers. |
| US11509015B2 |
Energy storage module and energy storage device
An energy storage module according to an aspect of the present invention includes: a plurality of energy storage devices each including a case; a glass paper sheet provided between the energy storage devices, brought into contact with the case, and mainly composed of a glass fiber; and a holding member holding the plurality of energy storage devices and the glass paper sheet, wherein the glass paper sheet is compressed between the energy storage devices. |
| US11509013B2 |
Storage battery module
A storage battery module includes battery cells, a first member and a second member opposing the first member across a substrate. The first member closes the space between adjacent terminals, and covers an open surface of a housing in a state where the terminals of the battery cells are exposed. The first member is formed of a material having a thermal resistance greater than or equal to a first threshold. The substrate opposing the battery cells across the first member has holes through which the terminals are inserted and a conductor formed therein so as to electrically connect the terminals. The second member opposing the first member across the substrate surrounds the terminals projecting from the holes and covers the substrate with the terminals exposed from the holes. The second member is formed of a material having a thermal resistance greater than or equal to a second threshold. |
| US11509007B2 |
Refrigeration cycle device for cooling battery
A refrigeration cycle cools a battery. A controller controls a refrigerant flow rate flowing through a battery cooling system so as to adjust a temperature of the battery. The controller adjusts the refrigerant flow rate flowing in the battery cooling system so that the oil retained in the battery cooling system is flushed toward the compressor. The battery cooling system has a plurality of parallel systems. Electric expansion valves as flow adjusting valves are controlled so as to intermittently provide an oil-back operation. In the oil-back operation, the flow rate of the refrigerant flowing through a part among the plurality of parallel systems is increased more than a flow rate of the refrigerant flowed by a temperature control unit. |
| US11509005B2 |
Battery pack including separator between secondary batteries
A battery includes a plurality of secondary batteries, a casing including a lower case and an upper case, and a plurality of separators interposed between corresponding secondary batteries. Each separator includes a first stopper in a lower part, a second stopper in an upper part, and a cooling passage between the secondary batteries and between the first stopper and the second stopper. The casing includes a face opposing the lateral faces of the secondary battery and including an opening opposing the cooling passage. |
| US11509003B2 |
Cooling structure for power storage stack and cooling system for power storage stack
A cooling structure includes a power storage stack including power storage cells, first and second end plates, a refrigerant supply path for supplying refrigerant, and first paths each provided in a clearance between two of the adjacent power storage cells. The first end plate is configured to form a second path communicating with the refrigerant supply path in a clearance between a first end of the power storage stack and the first end plate. The second end plate is configured to form a third path communicating with the refrigerant supply path in a clearance between a second end of the power storage stack and the second end plate. The power storage stack is cooled to have a temperature distribution in which the power storage cells disposed on the second end side have temperatures higher than the temperatures of the power storage cells disposed on the first end side. |
| US11509002B2 |
Battery pack
A battery pack includes a plurality of battery cells, wherein each of the battery cells is provided with first and second terminals connected to first and second cell electrodes, respectively; a first conductor electrically connecting at least a first and a second battery cell via one of the terminals of each of the first and second battery cells; and an electric heating element arranged to allow heating of at least the first and second battery cells via heating of the first or second terminal thereof. The battery pack includes at least a first metal plate capable of conducting both electric current and heat, wherein the first metal plate forms the first conductor and wherein the electric heating element is arranged onto the first metal plate so as to allow heating of at least the first and second battery cells via the first metal plate and further via the terminals connected to the first metal plate. |
| US11509001B2 |
Thermal management power battery assembly and battery pack
A thermal management power battery assembly and a battery pack having a plurality of the thermal management power battery assemblies connected in series. The battery assembly includes a plurality of staggered battery cells, a thermal conduction module, a liquid cooling module, and a battery cell fixing module for fixing the battery cells. The battery cell fixing module includes a battery cell position limiting device, and assembly supporting device located at two sides of the battery cell position limiting device; the liquid cooling module is integrated in the assembly supporting device; the thermal conduction module is simultaneously in contact with the battery cells and the assembly supporting device. The liquid cooling module is integrated with the assembly supporting device. The liquid cooling module is intergrated with the assembly supporting device. |
| US11508999B2 |
Lithium-ion batteries recycling process
It is provided a process for recycling lithium ion batteries comprising shredding the lithium-ion batteries and immersing residues in an organic solvent; feeding the shredded batteries residues in a dryer producing a gaseous organic phase and dried batteries residues; feeding the dried batteries residues to a magnetic separator removing magnetic particles; grinding the non-magnetic batteries residues; mixing the fine particles and an acid producing a metal oxides slurry and leaching said metal oxides slurry; filtering the leachate removing the non-leachable metals; feeding the leachate into a sulfide precipitation tank; neutralizing the leachate; mixing the leachate with an organic extraction solvent; separating cobalt and manganese from the leachate using solvent extraction and electrolysis; crystallizing sodium sulfate from the aqueous phase; adding sodium carbonate to the liquor and heating up the sodium carbonate and the liquor producing a precipitate of lithium carbonate; and drying and recuperating the lithium carbonate. |
| US11508993B2 |
Electrode assembly having an electrode subassembly, and battery including the electrode assembly
An electrode assembly includes an electrode subassembly forming by winding a first electrode plate and a second electrode plate. The first electrode plate includes a first electrode plate unit. The first electrode plate unit includes a bipolar current collector, a first active layer, and a second active layer. The bipolar current collector is disposed between the first active layer and the second active layer. The first active layer is electrically connected to the second active layer. The second electrode plate includes a composite current collector, a third active layer, and a fourth active layer. The composite current collector is disposed between the third active layer and the fourth active layer. The third active layer is electrically insulated from the fourth active layer. The disclosure further provides a battery including the electrode assembly. |
| US11508983B2 |
Automated batch sample preparation method for button battery
The invention provides an automated batch sample preparation method for button battery, comprising the following steps: preparing an electrolyte and elements of different specifications, presetting an injection amount of a liquid injection component, scanning and recording the identification information of the elements by a scanning component, grabbing the elements onto a sealing component, injecting the electrolyte into the elements on the sealing component, sealing the elements as a button battery by the sealing component, removing the button battery, then repeat the above steps. The automated batch sample preparation method for button battery provided by the invention has the advantages of high automation degree, simple operation, high-precision assembly and high efficiency. The injection amount can be adjusted and controlled, and button batteries with different specifications can be produced in batch. The information recorded by the scanning component can facilitate the optimization of the process. |
| US11508982B2 |
Fuel cell stack
A fuel cell stack comprising stacked unit cells, each comprising a membrane electrode assembly comprising an electrolyte membrane and a pair of electrodes disposed on both surfaces thereof, two separators sandwiching the membrane electrode assembly, and a frame-shaped resin sheet disposed between the two separators and around the membrane electrode assembly to attach the separators, wherein the resin sheet comprises a first protrusion protruding in the planar direction of the resin sheet and occupying a part of a first region occupied by a reaction gas inlet manifold, and a second protrusion protruding in the planar direction of the resin sheet and occupying a part of a second region occupied by a reaction gas outlet manifold; and wherein the resin sheet comprises at least one water discharge hole at a predetermined position of at least one protrusion selected from the group consisting of the first protrusion and the second protrusion. |
| US11508980B2 |
Systems and methods for distributed fault management in fuel cell systems
A distributed fault management system includes at least one sensor associated with a fuel cell system and at least one first fault management computing device coupled to the at least one sensor. The at least one first fault management computing device is configured to receive data associated with a first fault condition. The at least one first fault management computing device is further configured to generate a resolution to the first fault condition and transmit at least one resolution command signal to at least one second fault management computing device. The at least one resolution command signal configures the at least one second fault management computing device to use the resolution to resolve a second fault condition in a similar manner. |
| US11508976B2 |
Fuel cell system
A fuel cell system includes a fuel cell, an anode gas supply system, an anode gas circulatory system, a cathode gas supply-discharge system, a gas-liquid discharge passage, a gas-liquid discharge valve configured to open and close the gas-liquid discharge passage, a flow-rate acquisition portion, and a controlling portion. After the controlling portion instructs the gas-liquid discharge valve to be opened, the controlling portion executes a normal-abnormality determination such that, when a discharge-gas flow rate of anode gas is a predetermined normal reference value or more, the controlling portion determines that the gas-liquid discharge valve is opened normally, and when the discharge-gas flow rate is lower than the normal reference value, the controlling portion determines that the gas-liquid discharge valve is not opened normally. |
| US11508974B2 |
Pressure vessel mounting structure
A pressure vessel mounting structure includes: a manifold including a discharge gas passage branching from a general passage via which a container body communicates with a valve; a fusible plug valve configured to close the discharge gas passage and to, when the fusible plug valve is melted, open the discharge gas passage such that the high-pressure gas is discharged; a case including a bottom face portion covering the container body and the manifold from below in the vehicle up-down direction, the case including a bead placed near the fusible plug valve, the bead being formed by protruding a part of the bottom face portion upward in the vehicle up-down direction; and a communicating opening via which a space under a floor of a vehicle communicates with the fusible plug valve, the communicating opening being formed in a part of the bead, the part facing the fusible plug valve. |
| US11508971B2 |
Catalyst layer for fuel cell
There is provided a catalyst layer for a fuel cell that can inhibit reduction in water electrolysis function. The catalyst layer for a fuel cell according to this disclosure comprises carbon supports on which Pt particles are supported, and Ir oxide particles, wherein the ratio of the mean primary particle size of the Ir oxide particles with respect to the mean primary particle size of the Pt particles is 20 or greater. The mean primary particle size of the Pt particles may be 20.0 nm or smaller and the mean primary particle size of the Ir oxide particles may be 100.0 nm to 500.0 nm. |
| US11508970B2 |
Battery and battery manufacturing method
A battery includes a first current collector, a first electrode layer, and a first counter electrode layer. The first counter electrode layer is a counter electrode of the first electrode layer, and the first current collector includes a first electroconductive portion, a second electroconductive portion, and a first insulating portion. The first electrode layer is disposed in contact with the first electroconductive portion, and the first counter electrode layer is disposed in contact with the second electroconductive portion. The first insulating portion links the first electroconductive portion and the second electroconductive portion, and the first current collector is folded at the first insulating portion, whereby the first electrode layer and the first counter electrode layer are positioned facing each other. |
| US11508964B2 |
Lithium complex oxide for lithium secondary battery positive active material and method of preparing the same
Disclosed is a lithium complex oxide and method of manufacturing the same, more particularly, a lithium complex oxide effective in improving the characteristics of capacity, resistance, and lifetime with reduced residual lithium and with different interplanar distances of crystalline structure between a primary particle locating in an internal part of secondary particle and a primary particle locating on the surface part of the secondary particle, and a method of preparing the same. |
| US11508953B2 |
Negative electrode for lithium secondary battery, lithium secondary battery comprising the same, and method of preparing the negative electrode
A negative electrode for a lithium secondary battery, which includes a negative electrode active material layer formed on a negative electrode collector, and a coating layer formed on the negative electrode active material layer and which includes lithium metal and metal oxide, a lithium secondary battery including the same, and a method of preparing the negative electrode. |
| US11508952B2 |
Secondary battery, battery pack, and vehicle
According to one embodiment, provided is a secondary battery including a positive electrode, a negative electrode, and an electrolyte. The negative electrode includes a niobium-titanium composite oxide having fluorine atoms on at least part of a surface the niobium-titanium composite oxide. An abundance ratio AF of fluorine atoms, an abundance ratio ATi of titanium atoms, and an abundance ratio ANb of niobium atoms on a surface of the negative electrode according to X-ray photoelectron spectroscopy satisfy a relationship of 3.5≤AF/(ATi+ANb)≤50. |
| US11508943B2 |
Pixel circuit, display panel, and temperature compensation method for display panel
The present application provides a pixel circuit, a display panel, and a temperature compensation method for a display panel. The display panel includes a plurality of pixel units. At least one of the plurality of pixel units includes: a display layer comprising a light emitting element; and a thermoelectric conversion layer comprising a thermoelectric element having a first terminal and a second terminal, wherein the first terminal is disposed adjacent to the light emitting element and in thermal contact with the light emitting element, and the second terminal is disposed away from the light emitting element. The thermoelectric element has a first signal terminal and a second signal terminal, and is configured to generate a temperature difference voltage signal between the first signal terminal and the second signal terminal according to a temperature difference between the first terminal and the second terminal. |
| US11508940B2 |
Display device with optical pattern layer
A display device includes a light emitting element layer, and an optical pattern layer disposed on the light emitting element layer. The optical pattern layer includes a first pattern layer having a base part and protruding parts, and a second pattern layer having a refractive index less than a refractive index of the first pattern layer to scatter light incident to the optical pattern layer and minimize reduction in front efficiency, thereby providing an improved display quality of a side viewing angle. |
| US11508938B2 |
Display device
The disclosure relates to a display device including a display panel, an inorganic layer directly contacting the display panel, and a carbon layer directly contacting the inorganic layer. A thickness of the carbon layer is about 1 nm to about 10 nm. |
| US11508937B2 |
Light-diffusing barrier film
Provided is a light-diffusing barrier film. The film is an integral film comprising a barrier layer, a base layer and a light-diffusing layer, sequentially. The film can prevent moisture penetration into a device such as an organic light emitting device, and also imparts a light-diffusing function to the device. In particular, the film can have excellent moisture blocking properties even after a roll-to-roll process. |
| US11508934B2 |
Display device
A display device includes, a display region, and a peripheral region arranged outside of the display region, the peripheral region includes, a first inorganic insulating layer, a first organic insulating layer arranged on the first inorganic insulating layer, and a second inorganic insulating layer arranged on the first organic insulating layer, wherein a part of the first inorganic insulating layer in the display region side from a slope of the first inorganic insulating layer is in contact with the second inorganic insulating layer, the slope of the first inorganic insulating layer is exposed at the end part of the periphery region, and includes a bottomed hole with a concave and convex part, and the density of a fluorine ions in the concave and convex part is more than 100 times greater than the density of the fluorine ions in the first inorganic insulating layer arranged in the display region. |
| US11508932B2 |
Package structure, display panel, display device, and method for detecting package structure
The present disclosure relates to a package structure, a display panel, a display device, and a method for detecting a package structure. The package structure includes a first package layer and a second package layer disposed opposite to each other, and a sealing element between the first package layer and the second package layer for forming a sealed space between the first package layer and the second package layer. The package structure further includes a detecting element located in the sealed space, the detecting element including an oxygen sensitive material, the oxygen sensitive material including a material whose light emission characteristics are changed after exposure to oxygen. |
| US11508928B2 |
Self-luminous element and self-luminous display panel
A self-luminous element includes: a pixel electrode; a light-emitting layer that is disposed above the pixel electrode and includes a light-emitting material; a first functional layer that is disposed on the light-emitting layer and includes a metal fluoride; a second functional layer that is disposed on the first functional layer and includes a first organic material having at least one of electron transport properties and electron injection properties; and a counter electrode that is disposed above the second functional layer. The second functional layer does not include at least one metallic element selected from the group consisting of alkali metals, alkaline earth metals, and rare earth metals that reduce the metal fluoride. |
| US11508925B2 |
Photovoltaic device
A photovoltaic device (10) comprising a photoactive body between two electrodes (contact 1, contact 2). The body comprises semiconductor particles (24) embedded in a semiconductor matrix (22). The particles and matrix are electronically or optically coupled so that charge carriers generated in the particles are transferred directly or indirectly to the matrix. The matrix transports positive charge carriers to one of the electrodes and negative charge carriers to the other electrode. The particles are configured so that they do not form a charge carrier transport network to either of the electrodes and so perform the function of charge carrier generation but not charge carrier transport. |
| US11508924B2 |
Method of formulating perovskite solar cell materials
A method for preparing photoactive perovskite materials. The method comprises the step of preparing a germanium halide precursor ink. Preparing a germanium halide precursor ink comprises the steps of: introducing a germanium halide into a vessel, introducing a first solvent to the vessel, and contacting the germanium halide with the first solvent to dissolve the germanium halide. The method further comprises depositing the germanium halide precursor ink onto a substrate, drying the germanium halide precursor ink to form a thin film, annealing the thin film, and rinsing the thin film with a second solvent and a salt. |
| US11508914B2 |
Condensed cyclic compound and organic light-emitting device including the same
A condensed cyclic compound represented by Formula 1: wherein in Formula 1, Ar1 and R1 to R8 are the same as described in the specification. |
| US11508911B2 |
Record photocatalytic hydrogen evolution from organic semiconductor heterojunction nanoparticles
A nanoparticle comprises an internal D/A heterojunction, wherein the nanoparticle comprises a HER rate of 64,426±7022 μmolh−1g−1 under broadband visible light illumination. Measured EQEs of the nanoparticle throughout a visible spectrum exceed 5% at 660 to 700 nm. Methods may include fabricating a nanoparticle comprising: preparing individual stock solutions of PTB7-TH and EH-IDTBR in chloroform; heating the individual stock solutions to a complete dissolution; filtering the individual stock solutions; preparing a nanoparticle precursor solution from the filtered individual stock solutions by mixing the individual stock solutions in a ratio of 0-100% EH-IDTBR adding a portion of the nanoparticle precursor solution to a solution of surfactant (SDS or TEBS) in water and mixing to form a pre-emulsion; sonicating the pre-emulsion to form a mini-emulsion; heating the mini-emulsion to remove the chloroform to thereby form a surfactant stabilized nanoparticle dispersion; and filtering the nanoparticle. |
| US11508909B2 |
Organic electronic material and use of same
An organic electronic material containing a charge transport compound having at least one of the structural regions represented by formulas (1), (2) and (3) shown below. In the formulas, Ar represents an arylene group or heteroarylene group of 2 to 30 carbon atoms, a represents an integer of 1 to 6, b represents an integer of 2 to 6, c represents an integer of 2 to 6, and X represents a substituted or unsubstituted polymerizable functional group. —Ar—O—(CH2)a—O—CH2—X (1) —Ar—(CH2)b—O—CH2—X (2) —Ar—O—(CH2)c—X (3) |
| US11508908B2 |
Substrate etching method for manufacturing mask
A method for manufacturing a mask may include the following steps: preparing a substrate; providing a first coating, which may be optically transparent, may cover a covered portion of the substrate, and may expose exposed portions of the substrate; forming a scattering layer between the first coating layer and the covered portion of the substrate; and removing the exposed portions of the substrate to form mask holes. |
| US11508905B2 |
Resistive memory device having an oxide barrier layer
A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode, and a first barrier layer, including a first oxide material and a second oxide material, where the first oxide material is different from the second oxide material, and where the first barrier layer is between one of A) the memory layer and the bottom contact, and B) the top electrode and the top contact, where the first barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough. |
| US11508896B1 |
Materials and methods for fabricating superconducting quantum integrated circuits
Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions. |
| US11508888B2 |
Light-emitting device assembly with emitter array, micro- or nano-structured lens, and angular filter
A light-emitting device assembly includes an emitter array of light-emitting elements, a transparent substrate, a structured lens, and an angular filter. The emitter array emits from its emission surface output light that is transmitted through the substrate, and enables selective activation of and emission from individual elements or subsets of elements of the array. The structured lens is formed on or in the substrate, and comprises micro- or nano-structured elements resulting in an effective focal length less than an effective distance between the structured lens and the emission surface. The angular filter is positioned on or in the substrate or on the emission surface and exhibits decreasing transmission or a cutoff angle with increasing angle of incidence. |
| US11508884B2 |
Method for producing optoelectronic semiconductor devices and optoelectronic semiconductor device
The invention relates to a method for producing a plurality of optoelectronic semiconductor components, including the following steps: preparing a plurality of semiconductor chips spaced in a lateral direction to one another; forming a housing body assembly, at least one region of which is arranged between the semiconductor chips; forming a plurality of fillets, each adjoining a semiconductor chip and being bordered in a lateral direction by a side surface of each semiconductor chip and the housing body assembly; and separating the housing body assembly into a plurality of optoelectronic components, each component having at least one semiconductor chip and a portion of the housing body assembly as a housing body, and each semiconductor chip not being covered by material of the housing body on a radiation emission surface of the semiconductor component, which surface is located opposite a mounting surface. The invention also relates to a semiconductor component. |
| US11508880B2 |
Structure, methods for producing a structure and optoelectronic device
A structure and a method for producing a structure are disclosed. In an embodiment a structure includes at least one semiconductor structure comprising at least one semiconductor nanocrystal and a high-density element for increasing a density of the structure, wherein a density of the high-density element is greater than a density of silica, and wherein the structure is configured to emit light. |
| US11508878B2 |
Method of producing a layer stack and layer stack
A method of producing a layer stack includes a) forming a first layer having a first material composition on a substrate, b) performing intermediate processing of the substrate with the first layer, c) forming an additional layer having a second material composition, the first material composition and the second material composition differing from each other by at most 10% by weight, at least locally directly on the first layer and d) applying a second layer at least in places directly onto the additional layer. |
| US11508876B2 |
Light emitting device package and display device having the same
A light emitting device package including a substrate, a light emitting structure including a plurality of epitaxial stacks sequentially stacked on the substrate configured to emit light having different wavelength bands from each other, the light emitting structure having a light emitting area defined by the epitaxial stacks, a plurality of bump electrodes disposed on the light emitting structure, at least a portion of each bump electrode overlapping with the light emitting area, a molding layer covering a side surface and an upper surface of the light emitting structure, a plurality of fan-out lines disposed on the molding layer and connected to the light emitting structure through the bump electrodes, and an insulating layer disposed on the fan-out lines and exposing a portion of the fan-out lines, in which the exposed portion of the fan-out lines does not overlap with the light emitting area. |
| US11508868B2 |
Avalanche photodiode structure
A germanium based avalanche photo-diode device and method of manufacture thereof. The device including: a silicon substrate; a lower doped silicon region, positioned above the substrate; a silicon multiplication region, positioned above the lower doped silicon region; an intermediate doped silicon region, positioned above the silicon multiplication region; an un-doped germanium absorption region, position above the intermediate doped silicon region; an upper doped germanium region, positioned above the un-doped germanium absorption region; and an input silicon waveguide; wherein: the un-doped germanium absorption region and the upper doped germanium region form a germanium waveguide which is coupled to the input waveguide, and the device also includes a first electrode and a second electrode, and the first electrode extends laterally to contact the lower doped silicon region and the second electrode extends laterally to contact the upper doped germanium region. |
| US11508865B2 |
Copper halide chalcogenide semiconductor compounds for photonic devices
A semiconductor material having the molecular formula Cu2l2Se6 is provided. Also provided are solid solutions of semiconductor materials having the formulas Cu2lxBr2-xSeyTe6-y and Cu2lxBr2-xSeyS6-y, where 0≤x≤1 and 0≤y≤3. Methods and devices that use the semiconductor materials to convert incident radiation into an electric signal are also provided. The devices include optoelectronic and photonic devices, such as photodetectors, photodiodes, and photovoltaic cells. |
| US11508864B2 |
Tandem module unit
Presented herein are embodiments of a tandem solar panel subunit with 2-terminals, made from two 3-terminal cell tandems, whose top-cells are strongly current-mismatched to the Si 3-terminal bottom cell. |
| US11508863B2 |
Semiconductor component and method for singulating a semiconductor component having a pn junction
A a semiconductor component (1a, 1b) having a front side and an opposite rear side and also side surfaces, and also at least one emitter (2a, 2b) and at least one base (3a, 3b), wherein a pn junction (4a, 4b) is formed between emitter (2a, 2b) and base (3a, 3b) and the emitter (2a, 2b) extends parallel to the front and/or rear side. At least one side surface is a passivated separating surface (T), at which a separating surface passivation layer (6a, 6b) is arranged, which has stationary charges having a surface charge density at the separating surface (T) with a magnitude of greater than or equal to 1012 cm-2. A method for singulating a semiconductor component (1a, 1b) having a pn junction is also provided. |
| US11508860B2 |
In-cell bypass diode
A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode. |
| US11508858B2 |
Multi-well selenium device and method for fabrication thereof
Provided is a field shaping multi-well detector and method of fabrication thereof. The detector is configured by depositing a pixel electrode on a substrate, depositing a first dielectric layer, depositing a first conductive grid electrode layer on the first dielectric layer, depositing a second dielectric layer on the first conductive grid electrode layer, depositing a second conductive grid electrode layer on the second dielectric layer, depositing a third dielectric layer on the second conductive grid electrode layer, depositing an etch mask on the third dielectric layer. Two pillars are formed by etching the third dielectric layer, the second conductive grid electrode layer, the second dielectric layer, the first conductive grid electrode layer, and the first dielectric layer. A well between the two pillars is formed by etching to the pixel electrode, without etching the pixel electrode, and the well is filled with a-Se. |
| US11508855B2 |
Varactor structure with relay conductive layers
A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs. |
| US11508854B2 |
Semiconductor device
A semiconductor device includes a first electrode, a first semiconductor region connected to the first electrode and being of a first conductivity type, a second semiconductor region provided on the first semiconductor region, contacting the first semiconductor region and being of a second conductivity type, first metal layers and second metal layers provided on the second semiconductor region and contacting the second semiconductor region, a third semiconductor region provided between the first semiconductor region and the first metal layer, and a second electrode. The third semiconductor region contacts the first and second semiconductor regions and being of the first conductivity type. An impurity concentration of the third semiconductor region is greater than an impurity concentration of the first semiconductor region. The second electrode contacts the first semiconductor region, the second semiconductor region, the first metal layers, and the second metal layers. |
| US11508850B2 |
Manufacturing method of semiconductor device
A manufacturing method of a semiconductor device includes the forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to 300°. |
| US11508848B2 |
Semiconductor device and method for manufacturing the same
The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current. |
| US11508842B2 |
Fin field effect transistor with field plating
An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region. |
| US11508840B2 |
Silicon carbide semiconductor device and power converter
In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film. |
| US11508839B2 |
High electron mobility transistor with trench isolation structure capable of applying stress and method of manufacturing the same
A method of fabricating high electron mobility transistor, including the steps of providing a substrate with active areas, forming a buffer layer, a channel layer and a barrier layer sequentially on the substrate and gate, source and drain on the barrier layer, forming a trench surrounding the channel layer and the barrier layer, and forming a trench isolation structure in the trench, wherein the trench isolation structure applies stress on the channel layer and the barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor. |
| US11508838B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes first, second, and third electrodes, a semiconductor member, and a first insulating member. The semiconductor member includes a first face and a first side face. A third insulating region is between the first face and the third electrode in a second direction. A first insulating region is between the first side face and the third electrode in a first direction. The first side face includes first and second side face portions. The first side face portion is between the first face and the second side face portion in the second direction. At least a first angle between a first plane including the first face and the first side face portion and a second angle between the first plane and the second side face portion is less than 90 degrees. The second angle is different from the first angle. |
| US11508835B2 |
Bipolar transistor and method for producing the same
A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view. |
| US11508833B2 |
Semiconductor device and fabrication method thereof
A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate and forming a plurality of core layers discretely arranged on the substrate. The method also includes forming a first sidewall spacer on a sidewall of a core layer of the plurality of core layers. In addition, the method includes removing the first sidewall spacer on a sidewall of at least one core layer; and forming a second sidewall spacer on the sidewall of the at least one core layer where the first sidewall spacer is removed. The first sidewall spacer is made of a material different from the second sidewall spacer. |
| US11508827B2 |
Air spacer for a gate structure of a transistor
A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes. |
| US11508825B2 |
Semiconductor device and manufacturing method thereof
A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess. |
| US11508823B2 |
Low capacitance low RC wrap-around-contact
A field effect transistor is provided. The field effect transistor includes a first source/drain on a substrate, a second source/drain on the substrate, and a channel region between the first source/drain and the second source/drain. The field effect transistor further includes a metal liner on at least three sides of the first source/drain and/or the second source/drain, wherein the metal liner covers less than the full length of a sidewall of the first source/drain and/or the second source/drain. The field effect transistor further includes a metal-silicide between the metal liner and the first source/drain and/or the second source/drain, and a conductive contact on the metal liner on the first source/drain and/or the second source/drain, wherein the conductive contact is a conductive material different from the conductive material of the metal liner. |
| US11508822B2 |
Source/drain via having reduced resistance
A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion. |
| US11508820B2 |
Single crystal semiconductor structure and method of fabricating the same
A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness hc. |
| US11508819B2 |
Method for forming super-junction corner and termination structure with graded sidewalls
A method for forming a superjunction power semiconductor device includes forming multiple epitaxial layers of a first conductivity type on a semiconductor substrate and implanting dopants of a second conductivity type into each epitaxial layer to form a first group of implanted regions in a first region and a second group of implanted regions in a second region in each epitaxial layer. The multiple epitaxial layers are annealed to form multiple columns of the second conductivity type having slanted sidewalls across the first to last epitaxial layers. The columns include a first group of columns formed by the implanted regions of the first group and having a first grading and a second group of columns formed by the implanted regions of the second group and having a second grading, where the second grading is less than the first grading. |
| US11508817B2 |
Passivation layer for epitaxial semiconductor process
The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. |
| US11508816B2 |
Semiconductor structure and method of forming the same
The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate including a well region and an adjustment region over the well region. An isolation structure is disposed over the substrate and at least partially surrounds the well region and the adjustment region. An epitaxial layer is disposed over the adjustment region and surrounded by the isolation structure. A gate structure is disposed on the epitaxial layer. The present disclosure also provides a method for forming a semiconductor structure. |
| US11508814B2 |
Transistor including two-dimensional (2D) channel
A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer. |
| US11508809B2 |
Semiconductor device and preparation method thereof
The present disclosure discloses a semiconductor device and a preparation method thereof. The semiconductor device includes: an N+ substrate, a plurality of openings opening toward a back surface formed in the N+ substrate; an N− epitaxial layer formed on the N+ substrate, the N− epitaxial layer including: an active area epitaxial layer including a plurality of P++ area rings and a plurality of groove structures, wherein single groove structure is formed on single P++ area ring; a terminal area epitaxial layer including an N+ field stop ring and a plurality of P+ guard rings; a Schottky contact formed on the active area epitaxial layer, a passivation layer formed on the terminal area epitaxial layer, and ohmic contacts formed on the back surface of the N+ substrate and in the plurality of openings. |
| US11508808B2 |
Rectifier device, rectifier, generator device, and powertrain for vehicle
Provided is a rectifier device for a vehicle alternator including a rectifying element for rectifying in an alternator. The rectifying element has an Enhanced Field Effect Semiconductor Diode (EFESD). The EFESD includes a lateral conducting silicide structure and a field effect junction structure integrating side by side. A rectifier, a generator device, and a powertrain for a vehicle are also provided. |
| US11508807B2 |
Semiconductor device having nanosheet transistor and methods of fabrication thereof
Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer. |
| US11508802B2 |
Semiconductor device
A display device according to an embodiment of the present invention includes: an insulating sheet provided from a display region to a drive portion forming region, including, in a curved region, a first film-thickness region having a first film thickness thinner than a film thickness at the display region and a film thickness at the drive portion forming region, and including a first step portion disposed between the display region and the first film-thickness region and a second step portion disposed between the drive portion forming region and the first film-thickness region, first and second wiring lines crossing the first step portion and the second step portion above the insulating sheet and electrically connecting a pixel array portion with a drive portion, and an insulating wall extending from the first step portion to the second step portion between the first wiring line and the second wiring line. |
| US11508801B2 |
Display device
A display device includes: scan lines extending in a first direction; data lines extending in a second direction intersecting the first direction and receiving data voltages; first driving voltage lines extending in the second direction and receiving a first driving voltage; second driving voltage lines extending in the second direction and receiving a second driving voltage different from the first driving voltage; and pixels connected to the scan and data lines. Each of the pixels includes first, second, and third subpixels arranged in the first direction. The first driving voltage lines and the second driving voltage lines are alternately arranged in the first direction. A location of the first driving voltage line in a first pixel differs from a location of the second driving voltage line in a second pixel. The second pixel is adjacent to the first pixel in the first direction. |
| US11508800B2 |
Organic electroluminescent device including arrangement of capacitive electrode between layer of other capacitive electrode and layer of gate electrode
An organic electroluminescent device includes a first transistor, a power supply line layer connected to one current terminal of the first transistor, a capacitive element including a first capacitive electrode connected to a gate of the first transistor, and a second capacitive electrode, a signal line, and a pixel electrode connected to the other current terminal of the first transistor, the first capacitive electrode is provided on a layer over the gate of the first transistor, and the power supply line layer is provided on a layer between the first capacitive electrode and the signal line. |
| US11508798B2 |
Display device having circular, oval, polygonal frame with opening in bending portion
In an organic electroluminescence (EL) display device, a display region and a first frame region are defined in a substantially circular shape or a substantially oval shape, and in a bending portion, an opening is formed in an inorganic layered film, and a frame flattening film is provided to fill the opening. An end portion of the opening on the display region side is formed along an arc of the first frame region on the bending portion side. |
| US11508793B2 |
Organic light emitting diode display
An organic light emitting diode display includes a flexible substrate including a folding area and a flat area, a first insulating layer on the flexible substrate having a first opening, a first conductor on the first insulating layer, and a second insulating layer covering the first conductor with the first insulating layer also having the first opening. The organic light emitting diode display further includes a second conductor on the second insulating layer, a third insulating layer covering the second conductor and the second insulating layer, and a filling material in the first opening. A thickness of the filling material in the first opening is less than a thickness from a bottom surface of the first insulating layer to an upper surface of the second insulating layer. |
| US11508791B2 |
OLED display panel and display device
The present disclosure provides an organic light-emitting diode (OLED) display panel and a display device. Because, in this structure, a light transparency area is included in an electronic device display area, external light passes through the light transparency area and enters a camera. Thus, the camera can be directly positioned under the display panel without the need of forming a hole, thus solving the problems existing in prior art where the electronic device display area cannot display images due to formation of the hole. Full screen display is achieved. |
| US11508789B2 |
Display device and method of manufacturing the same
The present disclosure provides a display device with a display panel, an input sensing unit, and a protective member. The input sensing unit is disposed on the display panel. The protective member includes an insulating material and is disposed on the input sensing unit. The protective member includes a first protective portion and a second protective portion disposed on the first protective portion, where a first modulus of the first protective portion is greater than a second modulus of the second protective portion. The second protective portion with the lower modulus absorbs external impacts, and the first protective portion with the higher modulus disperses the absorbed impact and prevents the display panel from being deformed by an external force. Therefore, the impact resistance of the display device is improved. |
| US11508787B2 |
Display device
A display device, an electronic device, or a lighting device that is unlikely to be broken is provided. A flexible first substrate and a flexible second substrate overlap with each other with a display element provided therebetween. A flexible third substrate is bonded on the outer surface of the first substrate, and a flexible fourth substrate is bonded on the outer surface of the second substrate. The third substrate is formed using a material softer than the first substrate, and the fourth substrate is formed using a material softer than the second substrate. |
| US11508785B2 |
Display panel and display device for improving touch effects
A display panel and a display device are provided. The display panel includes a light-emitting layer, a first insulation layer, a first metal layer, a second insulation layer, and a second metal layer. The first metal layer includes a bridging layer and a first floating pattern. The second metal layer includes a driving electrode and a sensing electrode disposed in a same layer. This prevents a fracture structure and improves display effects and product performance of the display device. |
| US11508782B2 |
Hard mask for MTJ patterning
In some embodiments, the present disclosure relates to a method to form an integrated chip. The method may be performed by forming magnetic tunnel junction (MTJ) layers over a bottom electrode layer, and forming a sacrificial dielectric layer over the MTJ layers. The sacrificial dielectric layer is patterned to define a cavity, and a top electrode material is formed within the cavity. The sacrificial dielectric layer is removed and the MTJ layers are patterned according to the top electrode material to define an MTJ stack, after removing the sacrificial dielectric layer. |
| US11508780B2 |
Method of manufacturing display apparatus, display apparatus, and structure for manufacturing display apparatus
A method of manufacturing a display apparatus, a display apparatus, and a structure for manufacturing a display apparatus are provided. The method of manufacturing a display apparatus includes: forming a micro-light-emitting diode (LED) chip on a relay substrate such that a chip-side electrode is exposed; transferring the micro-LED chip from the relay substrate to a driving substrate including a driving substrate-side electrode; and bonding the chip-side electrode to the driving substrate-side electrode. |
| US11508771B2 |
Image sensors
An image sensor includes a semiconductor substrate having a first surface and a second surface, a pixel element isolation film extending through an interior of the semiconductor substrate and defining a plurality of active pixels in the semiconductor substrate, and a dummy element isolation film extending through the interior of the semiconductor substrate and extending along at least one side of the active pixels in a plan view and defining a plurality of dummy pixels in the semiconductor substrate. The pixel element isolation film may have a first end that is substantially coplanar with the first surface and has a first width in a first direction parallel to the first surface, and the dummy element isolation film has a first end that is substantially coplanar with the first surface and has a second width that is greater than the first width of the pixel element isolation film. |
| US11508767B2 |
Solid-state imaging device and electronic device for enhanced color reproducibility of images
A solid-state imaging device according to an embodiment includes: a semiconductor substrate including a photoelectric conversion element; a lens disposed above a first light incident surface of the photoelectric conversion element; and a plurality of columnar structures disposed on a surface parallel to the first light incident surface that is located between a second light incident surface of the lens and the first light incident surface of the photoelectric conversion element. The columnar structure includes at least one of silicon, germanium, gallium phosphide, aluminum oxide, cerium oxide, hafnium oxide, indium oxide, tin oxide, niobium pentoxide, magnesium oxide, tantalum pentoxide, titanium pentoxide, titanium oxide, tungsten oxide, yttrium oxide, zinc oxide, zirconia, cerium fluoride, gadolinium fluoride, lanthanum fluoride, and neodymium fluoride. |
| US11508766B2 |
Molded image sensor chip scale packages and related methods
Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second cavity wall may be coupled to the first side of the image sensor and extend therefrom. The first cavity wall and the second cavity wall may form a cavity over the image sensor. A transparent layer may be coupled to the first cavity wall and the second cavity wall. A redistribution layer (RDL) may be coupled to the second side of the image sensor. At least one interconnect may be directly coupled to the RDL. A mold material may encapsulate a portion of the RDL, a portion of the image sensor, and a side of each cavity wall, and a portion of the transparent layer. |
| US11508765B2 |
Active pixel sensing circuit structure and active pixel sensor, display panel and display device
The present disclosure provides an active pixel sensing circuit structure, an active pixel sensor, a display penal and a display device, aiming to reduce an area of the active pixel sensing circuit structure. A control electrode of a second transistor in the active pixel sensing circuit structure is located in a first metal layer. A first voltage signal line, a second voltage signal line, and an output signal line are located in a second metal layer that is located on a side of the first metal layer facing away from the substrate. A first electrode of a photodiode is connected to the control electrode of the second transistor through a first connection line. The first connection line is located in a third metal layer that is located on a side of the second metal layer facing away from the substrate. |
| US11508764B2 |
Solid-state imaging device
An imaging device incudes a pixel array including pixels arranged in columns and rows, one of the columns including a first pixel in a first row and a second pixel in a second row; a first signal line, to which the first pixel is coupled, and a second signal line, to which the second pixel is coupled, extending in a column direction of the pixels; and a first shield line, to which the first pixel is coupled, extending in the column direction. The first signal line, the first shield line, and the second signal line are arranged along a row direction of the pixels in that order. |
| US11508763B2 |
Method for manufacturing array substrate, array substrate and display device
The present disclosure provides a method for manufacturing an array substrate, an array substrate, and a display device. By first forming holes in a first thin film transistor, then simultaneously performing hydrogen supplementation on the first thin film transistor and a second thin film transistor, and then forming holes in the second thin film transistor, the first thin film transistor and the second thin film transistor can be repaired and compensated in different degrees by hydrogen supplementation. |
| US11508755B2 |
Stacked ferroelectric structure
The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost. |
| US11508753B2 |
Embedded ferroelectric FinFET memory device
Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a substrate. A gate dielectric is disposed over the substrate and between the source/drain regions. A gate electrode is disposed on the gate dielectric. A polarization switching structure is disposed on the gate electrode. A pair of sidewall spacers is disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure. |
| US11508750B2 |
Three-dimensional memory device including a peripheral circuit and a memory stack
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and an insulating structure extending vertically through the memory stack, the first semiconductor layer, and the second semiconductor layer. |
| US11508749B2 |
Cutoff gate electrodes for switches for a three-dimensional memory device and method of making the same
A semiconductor structure includes a first-conductivity-type well located in a semiconductor substrate, a semiconductor active area region located adjacent to the a first-conductivity-type well, a first transistor including a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, such that the transistor is located on the semiconductor active area region, and a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well. |
| US11508746B2 |
Semiconductor device having a stack of data lines with conductive structures on both sides thereof
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials. |
| US11508745B2 |
Three-dimensional memory device having a shielding layer and method for forming the same
Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral device is formed on a substrate. A first interconnect layer including a first plurality of interconnects is formed above the peripheral device. A shielding layer including a conduction region is formed above the first interconnect layer. A second interconnect layer including a second plurality of interconnects is formed above the shielding layer. The conduction region of the shielding layer covers an area of the first and second plurality of interconnects in the first and second interconnect layers. A plurality of memory strings each extending vertically above the second interconnect layer are formed. |
| US11508737B2 |
SRAM cell and logic cell design
An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height. |
| US11508732B2 |
Semiconductor devices having air spacer
A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure. |
| US11508728B2 |
Semiconductor memory device, method of driving the same and method of fabricating the same
A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string. |
| US11508727B2 |
Insulated gate bipolar transistor module, conductor installing structure therefor, and inverter
An IGBT module, a conductor installing structure for the IGBT module and an inverter are provided. The conductor installing structure for the IGBT module includes a substrate, a conductor and an insulation sleeve sleeved on the conductor and insulatedly isolating the conductor from the substrate. In the conductor installing structure for the IGBT module according to the present disclosure, by using the insulation sleeve sleeved on the conductor to insulatedly isolating the conductor from the substrate, the comparative tracking index of the IGBT module is improved, thereby improving the creepage distance of the IGBT module. In addition, compared with conventional technologies of spraying insulation varnish or insulation paste, the insulating property of the insulation sleeve can be better detected and guaranteed, and the bounding between the insulation sleeve and the substrate can be better enhanced, improving the insulation reliability. |
| US11508725B2 |
Layout construction for addressing electromigration
A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device. |
| US11508724B2 |
Composite power element
A composite power element includes a substrate structure, an insulation layer, a dielectric layer, a MOSFET, and a Zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The Zener diode is formed in a circuit element formation region of the substrate structure, and includes a Zener diode doping structure that is formed in the substrate structure and is covered by the insulation layer. The Zener diode doping structure includes a first P-type doped region and a first N-type doped region that is formed on an inner side of the first P-type doped region. The Zener diode further includes a Zener diode metal structure that is formed on the dielectric layer and sequentially passes through the dielectric layer and the insulation layer to be electrically connected to the first P-type doped region and the first N-type doped region. |
| US11508722B2 |
Semiconductor device structure with series-connected transistor and resistor and method for forming the same
A semiconductor device structure includes an isolation structure disposed in a semiconductor substrate. The semiconductor device structure also includes a gate electrode and a resistor electrode disposed in the semiconductor substrate. The isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure. The S/D region is electrically connected to the resistor electrode. |
| US11508718B2 |
Semiconductor device
A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities of a first conductivity type, and a concentration of the impurities in the connection doped region is higher than that in the first well regions. The first well regions extend into the substrate to a depth larger than that of the connection doped region. A first portion of the connection doped region is disposed in the first well regions and a second portion of the connection doped region contacts the substrate. |
| US11508713B2 |
Methods of manufacturing semiconductor package and package-on-package
A method of manufacturing a semiconductor package includes forming a laser reactive polymer layer on a substrate; mounting a semiconductor device on the substrate; irradiating at least a portion of the laser reactive polymer layer below the semiconductor device with a laser having a wavelength capable of penetrating through the semiconductor device on the substrate to modify the laser reactive polymer layer to have a hydrophilic functional group; and forming a first encapsulation material layer between the semiconductor device and the substrate. |
| US11508712B2 |
Method of manufacturing a package-on-package type semiconductor package
A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof. |
| US11508711B2 |
Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
A memory die includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures extending through the alternating stack, and each of the memory stack structures includes a respective vertical semiconductor channel and a respective memory film, drain regions located at a first end of a respective one of the vertical semiconductor channels, and a source layer having a first surface and a second surface. The first surface is located at a second end of each of the vertical semiconductor channels, and a semiconductor wafer is not located over the second surface of the source layer. |
| US11508704B2 |
Method of repairing light emitting device and display panel having repaired light emitting device
A display panel including a circuit board having first pads, a plurality of light emitting devices disposed on the circuit board and having second pads, at least one of the light emitting devices including a repaired light emitting device, and a metal bonding layer bonding the first pads and the second pads, in which the metal bonding layer of the repaired light emitting device has at least one of a thickness and a composition different from that of the metal bonding layer of the remaining light emitting devices. |
| US11508699B2 |
Display panel and pixel structure thereof
A display panel and a pixel structure are provided. The pixel structure includes a substrate, a micro light emitting diode (micro LED or μLED), a sidewall structure, a filling layer, and a reflective layer. The substrate has a bearing surface, and the micro LED is disposed on the bearing surface directly or indirectly. The sidewall structure is disposed on the bearing surface and defines at least one accommodation cavity to accommodate the micro LED. The filling layer is filled in the accommodation cavity and surrounds the micro LED. The reflective layer covers a top surface of the filling layer and has a plurality of light-transmissible windows. The micro LED forms, in a vertical projection direction, a vertical projection region in an overlapping region on the reflective layer. Among the light-transmissible windows, those having longer distances to the vertical projection region have larger areas. |
| US11508692B2 |
Package structure and method of fabricating the same
A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion. |
| US11508691B2 |
Semiconductor structure with nano-twinned metal coating layer and fabrication method thereof
A semiconductor structure includes a first substrate including a first contact structure located on a first pad, and a second substrate including a second contact structure on a second pad. The first contact structure includes a first metal base layer covered by a first nano-twinned metal coating layer. The second contact structure includes a second nano-twinned metal coating layer on the second pad. The first contact structure is connected to the second contact structure, thereby forming a bonding interface between the first nano-twinned metal coating layer and the second nano-twinned metal coating layer. |
| US11508690B2 |
Laser compression bonding device and method for semiconductor chip
A laser compression bonding device and method for a semiconductor chip are proposed. The device includes a conveyor unit that transports a semiconductor chip and a substrate, and a bonding head that includes a bonding tool for applying a pressure to the chip and substrate, a laser beam generator for emitting a laser beam, a thermal imaging camera for measuring temperatures of the surfaces of semiconductor chip and substrate, and a compression unit for controlling a pressure applied by the bonding tool and a position thereof, wherein the compression unit includes a mount on which the bonding tool is detachably mounted, and a servo motor and a load cell that apply a pressure to the mount or control a position thereof. The servo motor is controlled with two values for pressure application and positioning. |
| US11508689B2 |
Mounting apparatus and mounting system
A mounting apparatus for stacking and mounting two or more semiconductor chips at a plurality of locations on a substrate includes: a first mounting head for forming, at a plurality of locations on the substrate, temporarily stacked bodies in which two or more semiconductor chips are stacked in a temporarily press-attached state; and a second mounting head for forming chip stacked bodies by sequentially finally press-attaching the temporarily stacked bodies formed at the plurality of locations. The second mounting head includes: a press-attaching tool for heating and pressing an upper surface of a target temporarily stacked body to thereby finally press-attach the two or more semiconductor chips configuring the temporarily stacked body altogether; and one or more heat-dissipation tools having a heat-dissipating body which, by coming into contact with an upper surface of another stacked body positioned around the target temporarily stacked body, dissipates heat from the another stacked body. |
| US11508687B2 |
Semiconductor package
A semiconductor package may include a substrate including a first coupling terminal and a second coupling terminal, a first chip disposed on the substrate, the first chip including a first pad and a second pad, and a connection structure connecting the first coupling terminal to the first pad. A portion of the connection structure may be in contact with a first side surface of the first chip. The connection structure may include a connection conductor electrically connecting the first pad to the first coupling terminal. |
| US11508685B2 |
Stacked semiconductor package
A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other. |
| US11508682B2 |
Connection electrode and method for manufacturing connection electrode
A connection electrode includes a first metal film, a second metal film, a mixed layer, and an extraction electrode. The second metal film is located on the first metal film, and the extraction electrode is located on the second metal film. The mixed layer includes a mix of metal particles of the first and second metal films. As viewed in a first direction in which the first metal film and the second metal film are on top of each other, at least a portion of the mixed layer is in a first region that overlaps a bonding plane between the extraction electrode and the second metal film. |
| US11508676B2 |
Density-graded adhesion layer for conductors
Density-graded adhesion layers on conductive structures within a microelectronic package substrate are described. An example is a density-graded adhesion layer that includes a dense region proximate to a conductive structure that is surrounded by a less dense (or porous) region adjacent to an overlying dielectric layer. Providing such a graded adhesion layer can have a number of benefits, which can include providing both mechanical connections for improved adhesion with a surrounding dielectric layer and provide hermetic protection for the underlying conductive structure from corrosive species. The adhesion layer enables the conductive structure to maintain its as-formed smooth surface which in turn reduces insertion loss of signals transmitted through the conductive structure. |
| US11508665B2 |
Packages with thick RDLs and thin RDLs stacked alternatingly
A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers. |
| US11508664B2 |
Interconnect structure including graphene-metal barrier and method of manufacturing the same
An interconnect structure may include a graphene-metal barrier on a substrate and a conductive layer on the graphene-metal barrier. The graphene-metal barrier may include a plurality of graphene layers and metal particles on grain boundaries of each graphene layer between the plurality of graphene layers. The metal particles may be formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers. |
| US11508658B2 |
Semiconductor device package and method of manufacturing the same
The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed. |
| US11508657B2 |
Semiconductor devices having 3-dimensional inductive structures
Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component. |
| US11508655B2 |
Semiconductor package structure and method for manufacturing the same
A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad. |
| US11508651B2 |
Chip-on-film packages and display apparatuses including the same
A chip-on-film package includes a base film having a top surface and a bottom surface, and a circuit region; a source driver chip and a gate driver chip mounted on the circuit region; a first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive via that connects the first and second conductive lines to each other; a first row of bonding pads on the circuit region and connected to the source driver chip; a second row of bonding pads on the circuit region and connected to the source driver chip and the gate driver chip; and a test pad outside the circuit region and connected to the first and second conductive lines and the conductive via. |
| US11508649B2 |
Semiconductor package including substrate with outer insulating layer
A semiconductor package may include a substrate and a semiconductor chip on the substrate. The substrate may include an inner insulating layer, a redistribution layer in the inner insulating layer, an outer insulating layer on the inner insulating layer, a connection pad provided in the outer insulating layer and electrically connected to the redistribution layer, and a ground electrode in the outer insulating layer. A top surface of the connection pad may be exposed by a top surface of the outer insulating layer, and a level of the top surface of the connection pad may be lower than a level of the top surface of the outer insulating layer. A level of a bottom surface of the ground electrode may be higher than a level of a top surface of the redistribution layer, and the outer insulating layer covers a top surface of the ground electrode. |
| US11508647B2 |
Semiconductor device
A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor, a normally-on transistor, a first diode, and a Zener diode; a first terminal provided on the semiconductor package; a plurality of second terminals provided on the semiconductor package, and the second terminals being lined up in a first direction; a third terminal provided on the semiconductor package; a plurality of fourth terminals provided on the semiconductor package; and a plurality of fifth terminals provided on the semiconductor package, and the fifth terminals being lined up in the first direction. |
| US11508643B2 |
Thermal interface formed by condensate
Methods and apparatus of forming a thermal interface with condensate are described. In an example, a device may be disposed in a test environment or a test apparatus. An amount of condensate may be accumulated on a heat sink to coat the heat sink with a layer of condensate. The coated heat sink may be disposed on the device, where the layer of condensate is directed towards the device, and the disposal of the coated heat sink causes the layer of condensate to spread among voids between the heat sink and the device to form a thermal interface that includes the condensate. A test may be executed on the device with the thermal interface comprising the condensate between the coated heat sink and the device. |
| US11508639B2 |
System in package (SiP) semiconductor package
A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor. |
| US11508638B2 |
Semiconductor device and power converter
A semiconductor substrate has a first surface and a second surface that includes an inner region and an outer region. The semiconductor substrate includes a drift layer of a first conductivity type and a terminal well region of a second conductivity type. The terminal well region includes a portion that extends from between the inner region and the outer region toward the outer region. A first electrode is on the first surface. A second electrode is on at least part of the inner region and electrically connected to the terminal well region, and has its edge located on a boundary between the inner region and the outer region. A peripheral structure is provided on part of the outer region, away from the second electrode. A surface protective film covers the edge of the second electrode and at least part of the outer region and has the peripheral structure engaged therein. |
| US11508628B2 |
Method for forming a crystalline protective polysilicon layer
Disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. In one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree Celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched. |
| US11508626B2 |
Dual metal silicide structures for advanced integrated circuit structure fabrication
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer. |
| US11508624B2 |
Gate-all-around device with different channel semiconductor materials and method of forming the same
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first semiconductor layer including a first semiconductor material in a first area of a substrate; alternately depositing second semiconductor layers and third semiconductor layers over the first semiconductor layer and over the substrate to form a semiconductor layer stack, wherein the second semiconductor layers include a second semiconductor material, the third semiconductor layers include the first semiconductor material, the second semiconductor material is different from the first semiconductor material, and a bottom surface of one of the second semiconductor layers contacts the first semiconductor layer in the first area and contacts the substrate in a second area of the substrate; planarizing a top surface of the semiconductor layer stack; and patterning the semiconductor layer stack to form a first semiconductor structure in the first area and a second semiconductor structure in the second area. |
| US11508619B2 |
Electrical connection structure and method of forming the same
Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion. |
| US11508618B2 |
Multicolor self-aligned contact selective etch
Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. |
| US11508617B2 |
Method of forming interconnect for semiconductor device
A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via. |
| US11508615B2 |
Semiconductor device structure and methods of forming the same
A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer. |
| US11508614B2 |
Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate
A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction. |
| US11508613B2 |
Method of healing an implanted layer comprising a heat treatment prior to recrystallisation by laser annealing
The invention relates to a method of healing defects related to implantation of species in a donor substrate (1) made of a semiconducting material to form therein a plane of weakness (5) in it separating a thin layer (4) from a bulk part of the donor substrate. The method comprises a superficial amorphisation of the thin layer, followed by application of a heat treatment on the superficially amorphised thin layer. The method comprises application of laser annealing to the superficially amorphised thin layer after the heat treatment, to recrystallise it in the solid phase. |
| US11508611B2 |
Enhanced lift pin design to eliminate local thickness non-uniformity in teos oxide films
Implementations disclosed herein generally provide a lift pin that can improve the deposition rate and uniform film thickness above lift pin areas. In one implementation, the lift pin includes a first end coupling to a shaft, the first end having a pin head, and the pin head having a top surface, wherein the top surface is planar and flat, and a second end coupling to the shaft, the second end having a flared portion, wherein the flared portion has an outer surface extended along a direction that is at an angle of about 110° to about 140° with respect to a longitudinal axis of the lift pin. |
| US11508609B2 |
Wafer chuck assembly
Some examples provide a vacuum wafer chuck assembly for supporting a wafer. An example chuck assembly comprises a chuck hub and a centering hub disposed within the chuck hub. Chuck arms are mounted to the chuck hub, with each chuck arm extending radially between a proximal end adjacent the chuck hub, and a distal end remote therefrom. A plurality of centering cams is provided, each cam mounted at or towards a distal end of a chuck arm and being movable radially inwardly or outwardly relative to the centering hub to engage or release an edge of a supported wafer in response to a rotational movement of the centering hub. At least one vacuum pad is provided for supporting the wafer during a wafer centering or wafer processing operation. |
| US11508605B2 |
3D semiconductor memory device and structure
A 3D semiconductor device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where a second metal layer is disposed atop the first metal layer; a plurality of logic gates including the first metal layer and first transistors; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the mini arrays includes at least two rows by two columns of memory cells, where each memory cell includes one of the second transistors or one of the third transistors, and where one of the second transistors is self-aligned to one of the third transistors, being processed following a same lithography step. |
| US11508602B2 |
Cleaning tool
A method includes transmitting a radiation toward an electrostatic chuck, receiving a reflection of the radiation, analyzing the reflection of the radiation, determining whether a particle is present on the electrostatic chuck based on the analyzing the reflection of the radiation, and moving a cleaning tool to a location of the particle on the electrostatic chuck when the determination determines that the particle is present. |
| US11508600B2 |
Holding device
A holding device includes: a plate-shaped member having a first surface approximately orthogonal to a first direction; heat generating resistors and temperature measuring resistors disposed in respective segments formed by virtually dividing at least part of the plate-shaped member, the segments being arranged in a direction orthogonal to the first direction; and an electricity supply section that forms electricity supply paths for the heat generating resistors and the temperature measuring resistors. The holding device holds an object on the first surface of the plate-shaped member. The position of the temperature measuring resistors in the first direction differs from the position of the heat generating resistors in the first direction. A specific temperature measuring resistor that is at least one of the temperature measuring resistors includes a plurality of resistor elements disposed at different positions in the first direction and connected to one another in series. |
| US11508599B2 |
Pick-up device and pick-up method
A pick-up device 10 for picking up a semiconductor chip 100 attached to a front surface of a sheet material 110 is provided with: a stage 12 that includes a material a part or the entirety of which is capable of transmitting a destaticizing electromagnetic wave having an ionization effect and that attracts and holds a rear surface of the sheet material 110; a jacking-up pin 26 for jacking up the semiconductor chip 100 from the rear side of the stage 12; and a destaticizing mechanism 20 that destaticizes charge generated between the semiconductor chip 100 and the sheet material 110 by irradiating the rear surface of the semiconductor chip 100 with the destaticizing electromagnetic wave that is made to pass through the sheet material 110 from the rear side of the stage 12. |
| US11508594B2 |
Substrate container system
A substrate container system comprises a container body having a bottom face, a front opening that enables passage of a substrate, and a back opening opposing the front opening, the back opening having a width smaller than that of the front opening; and a back cover that covers the back opening and establishes sealing engagement with the container body, wherein the back cover comprises a first gas inlet structure that bendingly extends under the bottom face of the container body upon assembly; wherein the first gas inlet structure comprises a downward facing gas intake port opposing the bottom face of the container body. |
| US11508592B2 |
Reticle retaining system
The instant disclosure discloses a reticle retaining system comprising an inner pod and an outer pod. The inner pod is configured to receive a reticle that includes a first identification feature. The inner pod comprises an inner base having a reticle accommodating region generally at a geometric center thereof and surrounded by a periphery region, and an inner cover configured to establish sealing engagement with the inner base. The inner base has a first observable zone defined in the reticle accommodating region correspondingly arranged to allow observation of the first identification feature. The outer pod is configured to receive the inner base. The outer pod comprises an outer base having a second observable zone defined thereon observably aligned to the first observable zone of the inner pod upon receiving the inner pod, and an outer cover configured to engage the outer base and cover the inner pod. |
| US11508589B2 |
Substrate processing method, substrate processing apparatus and recording medium
When performing a liquid processing on a substrate W being rotated and removing a processing liquid by a cleaning liquid, a cleaning liquid nozzle 421 configured to discharge a cleaning liquid slantly with respect to a surface of the substrate W toward a downstream side of a rotational direction of the substrate W and a gas nozzle 411 configured to discharge a gas toward a position adjacent to a central portion side of the substrate W when viewed from a liquid arrival position R of the cleaning liquid are moved from the central portion side toward a peripheral portion side. A rotation number of the substrate is varied such that rotation number in a period during which the liquid arrival position R moves in the second region becomes smaller than a maximum rotation number in a period during which the liquid arrival position moves in the first region. |
| US11508588B2 |
Substrate treatment device and substrate treatment method
A substrate treatment device according to an embodiment includes: a liquid treatment part configured to supply a liquid onto a substrate to form a liquid film remaining in a liquid state on the substrate; an imaging part configured to capture an image of a front surface of the substrate, on which the liquid film remaining in the liquid state is formed; a determination part configured to determine a quality of a formation state of the liquid film based on the captured image of the substrate; and a post-treatment part configured to treat the substrate on which the liquid film is formed, when the determination part determines that the formation state of the liquid film is good. |
| US11508585B2 |
Methods for chemical mechanical polishing and forming interconnect structure
A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer. |
| US11508583B2 |
Selective high-k formation in gate-last process
A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening. |
| US11508581B2 |
Semiconductor device having IGBT and diode with field stop layer formed of hydrogen donor and helium
Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided. |
| US11508579B2 |
Backside metal photolithographic patterning die singulation systems and related methods
Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street. |
| US11508575B2 |
Low warp fan-out processing method and production of substrates therefor
A method of fan-out processing includes providing or obtaining a fused glass laminate sheet or wafer having a core layer and a first clad layer and a second clad layer, the core layer comprising a core glass having a core glass coefficient of thermal expansion αcore, the first clad layer and the second clad layer each comprising a clad glass having a clad glass coefficient of thermal expansion αclad, where αclad>αcore; affixing integrated circuit devices to the second clad layer of the laminate sheet or wafer; forming a fan-out layer on or above the integrated circuit devices; and removing some of the first clad layer to decrease warp of the sheet or wafer with integrated circuit devices and a fan-out layer thereon. A method of producing a laminate sheet or wafer having a selected CTE is also disclosed. |
| US11508574B2 |
Semiconductor manufacturing apparatus and manufacturing method of semiconductor device
A semiconductor manufacturing apparatus according to an embodiment includes: a stage to have a plurality of pins to hold a semiconductor substrate having a first surface on which a film to be etched is formed and a second surface positioned on an opposite side to the first surface; a nozzle to eject a liquid chemical toward the first surface of the semiconductor substrate from above the stage; and an optical measurer to radiate light toward the second surface of the semiconductor substrate from a side of the stage during ejection of the liquid chemical, and to measure a displacement amount of the semiconductor substrate based on a state of reception of light reflected on the second surface. |
| US11508570B2 |
SiC film structure
A SiC film structure for obtaining a three-dimensional SiC film by forming the SiC film in an outer circumference of a substrate using a vapor deposition type film formation method and removing the substrate, the SiC film structure including: a main body having a three-dimensional shape formed of a SiC film and having an opening for removing the substrate; a lid configured to cover the opening; and a SiC coat layer configured to cover at least a contact portion between the main body and an outer edge portion of the lid and join the main body and the lid. |
| US11508566B2 |
Use of anthranilic acid derivative as matrix for MALDI mass spectrometry
A use of an anthranilic acid derivative as a matrix for a MALDI Mass spectrometry, comprising: preparing a matrix compound represented by the following formula: wherein X is selected from hydrogen and a hydroxyl group, and Y is selected from hydrogen, a methyl group or an acetyl group, provided that when X is hydrogen, Y is hydrogen or an acetyl group, and when X is a hydroxyl group, Y is a methyl group; applying the matrix compound and an analyte onto a sample holder; and analyzing the analyte by the MALDI mass spectrometer. |
| US11508565B2 |
Ion guide device and ion guide method
An ion guide device includes a plurality of ring electrodes disposed in parallel, wherein each ring electrode includes at least 4 electrode units separated from each other, a channel for ion transmission is formed inside the plurality of ring electrodes, and an arrangement direction of the plurality of ring electrodes defines an axial direction of ion transmission; an radio-frequency voltage source, for applying out-of-phase radio-frequency voltages on the neighboring electrode units belonging to the same ring electrode, and applying in-phase radio frequency voltages on a neighboring electrode units along the axial direction, thereby forming an radio-frequency multipole field that confine ions in the ion guide device; and a direct-current voltage source, wherein the ions are transmitted off-axis and focused to a position closer to an inner surface of the ring electrode under a combined action of the radio-frequency voltage and the direct-current voltage. |
| US11508564B2 |
Ion pumps and ion pump elements
An ion pump includes an evacuateable envelope having a chamber. A first and a second cathode are disposed within the chamber and spaced apart from one another. An anode is spaced apart from and between the first and second cathodes. The anode has an anode body with a textured surface that defines capture regions for fixing material sputtered from the first and second cathodes and controlling size of sputter depositions shed from the anode. |
| US11508562B2 |
Low contamination chamber for surface activation
An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, and an adjustable bottom electrode. The low contamination chamber is configured to adjust a distance between the adjustable top electrode and the adjustable bottom electrode in response to a desired density of plasma and a measured density of plasma measured between the adjustable top electrode and the adjustable bottom electrode during a surface activation process. The low contamination chamber further includes an outlet. |
| US11508561B2 |
Plasma processor
A plasma processing apparatus, for releasing plasma-converted gas from plasma head for performing process, detects the pressures of a gas prior to application of a voltage to electrodes of the plasma head, the gas being supplied from gas supply section to a plasma head, and allow initiation of process by the plasma processing apparatus based on the detected pressures. |
| US11508559B2 |
Portable plasma device
The present disclosure relates to a portable plasma device which is convenient to carry and has excellent performance and is capable of simply, uniformly, and locally treating an inner surface of a microstructure such as a microwell plate by easily adjusting a plasma flame. |
| US11508558B2 |
Thermal repeatability and in-situ showerhead temperature monitoring
Embodiments described herein generally related to a substrate processing apparatus, and more specifically to an improved showerhead assembly for a substrate processing apparatus. The showerhead assembly includes a chill plate, a gas plate, and a gas distribution plate having a top surface and a bottom surface. A plurality of protruded features contacts the top surface of the gas distribution plate. A fastener and an energy storage structure is provided on the protruded features. The energy storage structure is compressed by the fastener and axially loads at least one of the protruded features to compress the chill plate, the gas plate and the gas distribution plate. |
| US11508554B2 |
High voltage filter assembly
Embodiments described herein are applicable for use in all types of plasma assisted or plasma enhanced processing chambers and also for methods of plasma assisted or plasma enhanced processing of a substrate. More specifically, embodiments of this disclosure include a broadband filter assembly, also referred to herein as a filter assembly, that is configured to reduce and/or prevent RF leakage currents from being transferred from one or more RF driven components to a ground through other electrical components that are directly or indirectly electrically coupled to the RF driven components and ground with high input impedance (low current loss) making it compatible with shaped DC pulse bias applications. |
| US11508551B2 |
Detection and correction of system responses in real-time
A detection and correction method for an electron beam system are provided. The method includes emitting an electron beam towards a specimen; modulating a beam current of the electron beam to obtain a beam signal. The method further includes detecting, using an electron detector, secondary and/or backscattered electrons emitted by the specimen to obtain electron data, wherein the electron data defines a detection signal. The method further includes determining, using a processor, a phase shift between the beam signal and the detection signal. The method further includes filtering, using the processor, the detection signal based on the phase shift. |
| US11508546B2 |
System and method for low-noise edge detection and its use for process monitoring and control
In one embodiment, a method includes generating a model trained to predict a low-probability stochastic defect, calibrating, using unbiased measurement data, the model to a specific lithography process, patterning process, or both to generate a calibrated model, using the calibrated model to predict the low-probability stochastic defect; and modifying, based on the low-probability stochastic defect, a variable, parameter, setting, or some combination of a manufacturing process of a device. |
| US11508544B2 |
Thermoelectric field emission electron source and electron beam application device
To stabilize an emitted electron beam, a thermoelectric field emission electron source includes: an electron source having a needle shape; a metal wire to which the electron source is fixed and configured to heat the electron source; a stem fixed to an insulator and configured to energize the metal wire; a first electrode having a first opening portion and arranged such that a tip of the electron source protrudes from the first opening portion; a second electrode having a second opening portion; and an insulating body configured to position the first electrode and the second electrode such that a central axis of the first opening portion and a central axis of the second opening portion coincide with each other, and to provide electrical insulation between the first and second electrodes, so as to provide a structure that reduces an amount of gas released when the first electrode is heated. |
| US11508537B2 |
Operating device for a steering wheel of a vehicle
An operating device for a steering wheel comprises an operating element, which can be selectively rotated about a first rotation axis and a second rotation axis for controlling a control system by means of an actuation, wherein the operating element can be rotated to an actuation stage from a starting position, wherein the first rotation axis is coaxial to the longitudinal axis of the operating element, and the second rotation axis is substantially transverse to the first rotation axis, wherein a force application point has a mechanical advantage with respect to the second rotation axis when actuated about the second rotation axis, and wherein the force application point has no substantial mechanical advantage in relation to the second rotation axis when the operating element is actuated about the first rotation axis, in order to prevent a simultaneous actuation of the operating element about the first and second rotation axes. |
| US11508528B2 |
Electrolytic capacitor and method for producing same
An electrolytic capacitor includes a capacitor element having: an anode; a dielectric layer covering at least a part of the anode body; a solid electrolyte layer covering at least a part of the dielectric layer; and a cathode lead-out layer covering at least a part of the solid electrolyte layer. The cathode lead-out layer includes a carbon layer covering at least a part of the solid electrolyte layer, a first metal layer covering at least a part of the carbon layer, and a second metal layer covering at least a part of the first metal layer. The first metal layer contains first metal particle, and the second metal layer contains second metal particles and a second binder resin. The first metal layer contains no binder resin, or contains a first binder resin in a volume ratio smaller than a volume ratio of the second binder resin contained in the second metal layer. |
| US11508523B2 |
Multi-layer ceramic electronic component
A multi-layer ceramic electronic component includes: a ceramic body including a multi-layer unit having a side surface facing in a direction of a first axis and including internal electrodes laminated in a direction of a second axis orthogonal to the first axis and having end portions on the side surface, and a side margin including a first inner layer adjacent to the side surface and including a first region containing a glass component, a first outer layer outside of the first inner layer, and a ridge positioned at an end portion of the first outer layer in the direction of the second axis and including a second region containing a glass component at a lower concentration than a concentration of the glass component of the first region, the side margin having a dimension of 13 μm or less in the direction of the first axis; and an external electrode. |
| US11508521B2 |
Metal terminal-equipped electronic component and method for producing metal terminal- equipped electronic component
A metal terminal-equipped electronic component includes: an electronic component having a terminal electrode; a conductive cloth member joined to the terminal electrode as a metal terminal; and a cushioning member supporting the electronic component and the cloth member, in which the cloth member is joined to at least a mounting surface of the cushioning member and a joint surface of the cushioning member to which the electronic component is joined, and the terminal electrode of the electronic component is joined to the cloth member on the joint surface of the cushioning member. |
| US11508519B2 |
Continous heat treatment device and method for alloy workpiece or metal workpiece
Disclosed are a continuous heat treatment device and method for a sintered Nd—Fe—B magnet workpiece. The device comprises a first heat treatment chamber, a first cooling chamber, a second heat treatment chamber, and a second cooling chamber continuously disposed in sequence, as well as a transfer system disposed among the chambers to transfer the alloy workpiece or the metal workpiece; both the first cooling chamber and the second cooling chamber adopt a air cooling system, wherein a cooling air temperature of the first cooling chamber is 25° C. or above and differs from a heat treatment temperature of the first heat treatment chamber by at least 450° C.; a cooling air temperature of the second cooling chamber is 25° C. or above and differs from a heat treatment temperature of the second heat treatment chamber by at least 300° C. The continuous heat treatment device and method can improve the cooling rate and production efficiency and improve the properties and consistency of the products. |
| US11508518B2 |
Coil device with predetermined gap arrangement
A coil device includes a core and a plurality of coils arranged in the core. A distance of a second gap formed by portions of the core located inside at least one of the coils is larger than that of a first gap formed by other portions of the core located between the coils next to each other. |
| US11508516B2 |
Wireless charging module and electronic device thereof
The present disclosure is related to a wireless charging module and an electronic device thereof. The wireless charging module includes a base, at least one magnetic shielding sheet, and a coil. The base includes at least two metal melting regions. Each metal melting region includes an opening, and a blocking region disposed at the opening. The magnetic shielding sheet is disposed on the base. The magnetic shielding sheet partially exposes the two metal melting regions and the openings. The coil is disposed on the magnetic shielding sheet. The coil includes two leads. The two leads are respectively disposed on the two metal melting regions. The two leads are disposed in the blocking regions and the openings. The electronic device includes the wireless charging module and a power supply. The wireless charging module is electrically connected to the power supply. |
| US11508515B2 |
Common mode choke coil
A common mode choke coil includes a core, and first and second coils opposed to each other and wound on the core. The core can have a square shape, or an elongated shape having a long axis and a short axis when viewed in a direction along a central axis of the core. Each of the first and second coils is a single-layer coil. An area of a cross-section of the core taken perpendicular to a circumferential direction of the core is constant in the circumferential direction of the core. The cross-section of the core has a quadrilateral shape. |
| US11508513B2 |
Coil-embedded ceramic substrate
A coil-embedded ceramic substrate includes a plurality of ceramic layers including multi-turn coil patterns provided thereon. At least one ceramic layer of the plurality of ceramic layers includes thereon a multi-turn coil pattern and dummy patterns not electrically connected to the multi-turn coil pattern. The multi-turn coil pattern winds around and extends parallel or substantially parallel to sides of the ceramic layer. The dummy patterns are each parallel or substantially parallel to corresponding ones of the sides of the ceramic layer as an extension of portion of the coil pattern in an extending direction. |
| US11508506B2 |
Lead and thermal disconnect for ramping of an MRI or other superconducting magnet
A superconducting magnet (10) includes a cryogenic container (22, 32) containing a superconducting magnet winding (20). A sealed electrical feedthrough (36) passes through the cryogenic container. A contactor (40) inside the cryogenic container has an actuator (42) and feedthrough-side and magnet-side electrical terminals (46, 47). A high temperature superconductor (HTS) lead (60) also disposed in the cryogenic container has a first end (62) electrically connected with the magnet-side electrical terminal of the contactor and a second end (64) electrically connected to the superconducting magnet winding. A first stage thermal station (52) thermally connected with the first end of the HTS lead has a temperature (T1) lower than the critical temperature (TC,HTS) of the HTS lead. A second stage thermal station (54) thermally connected with the second end of the HTS lead has a temperature (T2) lower than a critical temperature (TC) of the superconducting magnet winding (20). |
| US11508504B2 |
Electric winding body with optimised performance characteristics and improved protection against overheating
The invention relates to an electric winding body which has improved performance characteristics as a result of being impregnated with a thermoplastic material filled with phase change material. These performance characteristics relate to improved heat dissipation, vibration damping, fixing of the coils, and improved protection against overheating by utilizing the sensitive and latent heat storage properties when the polymer units transition from the semi-crystalline state into the amorphous state. |
| US11508502B2 |
Soft magnetic alloy and magnetic component
A soft magnetic alloy or the like combining high saturated magnetic flux density, low coercive force and high magnetic permeability μ′ having the composition formula (Fe(1−(α+β))X1αX2β)(1−(a+b+c+d+e))BaSibCcCudMe. X1 is one more elements selected from the group consisting of Co and Ni, X2 is one or more elements selected from the group consisting of Al, Mn, Ag, Zn, Sn, As, Sb, Bi, N, O and rare earth elements, and M is one or more elements selected from the group consisting of Nb, Hf, Zr, Ta, Ti, Mo, W and V. 0.140 |
| US11508496B2 |
Opto-electric cable
Disclosed is an opto-electric cable including one or more electrical conductors. Each conductor includes an electrically conductive core and an electrically insulating layer surrounding it. The cable also includes an optical unit embedded within one of the electrically conductive cores. The optical unit includes at least two optical fibers and a single buffer jointly surrounding all the optical fibers. Each optical fiber includes a core, a cladding and a coating. Since all the optical fibers of the optical unit are jointly surrounded—and protected—by a single buffer, an optical unit with a reduced size is obtained. This allows reducing the cross section of the electrical conductor in which the optical unit is arranged. In particular, electrical conductors with cross section lower than 10 mm2 are obtained. |
| US11508493B2 |
Aluminum alloy for cable conductor
Provided is an aluminum alloy for a cable conductor. Specifically, the present invention relates to an aluminum alloy for a cable conductor, which is excellent in both mechanical properties, such as tensile strength, at room temperature and high temperatures and elongation, and electrical conductivity, is simple to manufacture at low costs, and is eco-friendly. |
| US11508491B2 |
Radiation source for nondestructive inspection, and method and apparatus for manufacturing same
An irradiation target is formed into a sphere. The spherical irradiation target can be iridium metal containing natural or enriched iridium. The radiation source can be manufactured by manufacturing a spherical irradiation target, accommodating the spherical irradiation target in a rotating capsule, and rotating an axial flow impeller by a downward flow of a reactor primary coolant, whereby the rotating capsule is rotated. This radiation source provides an improved nondestructive inspection image having a high geometric resolution, and has no radiation source anisotropy and also has high target recyclability. |
| US11508488B2 |
Heat transfer systems for nuclear reactor cores, and related systems
A system for transferring heat from a nuclear reactor comprises a nuclear reactor comprising a nuclear fuel and a reactor vessel surrounding the nuclear reactor and a heat transfer system surrounding the nuclear reactor. The heat transfer system comprises an inner wall surrounding the nuclear reactor vessel, first fins coupled to an outer surface of inner wall, an outer wall between the inner wall and a surrounding environment, and second fins coupled to an inner surface of the outer wall and extending in a volume between the outer surface of the inner wall and the inner surface of the outer wall, the outer surface of the inner wall and the first fins configured to transfer heat from the nuclear reactor core to the second fins and the inner surface of the outer wall by thermal radiation. The heat transfer system may be directly coupled to the nuclear reactor vessel, or may be coupled to an external reflector surrounding the nuclear reactor vessel. Related heat transfer systems and systems for selectively removing heat from a nuclear reactor are disclosed. |
| US11508486B2 |
Multi-node, cyclic nuclear fusion reactor with single-cycle, charged cathode
A controlled fusion process is provided that can produce a sustained series of fusion reactions: a process that (i) uses a substantially higher reactant density of the deuterium and tritium gases by converging cationic reactants into the higher reaction density at a target cathode rather than relying on random collisions, the converging producing a substantially higher rate of fusion and energy production; (ii) uses a substantially lower input of energy to initiate the fusion; (iii) can be cycled at a substantially higher cycle frequency; (iv) has a practical heat exchange method; (v) is substantially less costly to manufacture, operate, and maintain; and, (vi) has a substantially improved reaction efficiency as a result of not mixing reactants with products. |
| US11508482B2 |
Systems and methods for remotely-enabled identification of a user infection
Systems and methods for identifying a condition of a user. A treatment apparatus is configured to be manipulated by the user for performing an exercise, and an interface is communicably coupled to the treatment apparatus. One or more sensors are configured to sense one or more characteristics of an anatomical structure of the user. A processing device and a memory is communicatively coupled to the processing device. The memory includes computer readable instructions, that when executed by the processing device, cause the processing device to: receive, from the sensors, one or more sensor inputs representative of the one or more of characteristics of the anatomical structures; calculate an infection probability of a disease based on the one or more characteristics of the anatomical structures; and output, to the interface, a representation of the infection probability. |
| US11508481B2 |
Machine-learned hormone status prediction from image analysis
An analytics system uses one or more machine-learned models to predict a hormone receptor status from a H&E stain image. The system partitions H&E stain images each into a plurality of image tiles. Bags of tiles are created through sampling of the image tiles. The analytics system trains one or more machine-learned models with training H&E stain images having a positive or negative receptor status. The analytics system generates, via a tile featurization model, a tile feature vector for each image tile a test bag for a test H&E stain image. The analytics system generates, via an attention model, an aggregate feature vector for the test bag by aggregating the tile feature vectors of the test bag, wherein an attention weight is determined for each tile feature vector. The analytics system predicts a hormone receptor status by applying a prediction model to the aggregate feature vector for the test bag. |
| US11508479B2 |
Automated question generation and response tracking
There is a need for solutions that monitor memory loss with reduced caretaker involvement. This need can be addressed by, for example, selecting a first question from a group of multiple questions to ask a user of a computing device based one or more attributes associated with each question in the group of multiple questions; receiving a first answer by the user of the computing device to the first question; determining, from the first answer, one or more behavioral attributes associated with user response to the first question; and determining, based on the one or more behavioral attributes, a cognitive capability of the user of the computing device. |
| US11508478B2 |
Patient data collection system and method
Various systems and methods for collecting patient data are discussed herein. According to some systems and methods, a timer may be started, and a blood pressure data collection system is actuated to obtain a blood pressure measurement of a patient upon the expiration of the timer. The timer may be incorporated into a patient data collection system or method to ensure the patient is relaxed and calm prior to taking a blood pressure measurement. An event may be sensed by an environmental sensor system and the timer may be started in response to sensing the event. A clinician leaving a room where the patient is disposed is one example of an event. An interruption may be sensed by the environmental sensor system and the timer may be terminated in response to sensing the interruption. The clinician entering the room where the patient is disposed in one example of an interruption. |
| US11508476B2 |
Infusion devices and methods
Medical devices, systems, and methods related thereto a glucose monitoring system having a first display unit in data communication with a skin-mounted assembly, the skin-mounted assembly including an in vivo sensor and a transmitter. The first display unit and a second display unit are in data communication with a data management system. The first display unit comprises memory that grants a first user first access level rights and the second display unit comprises memory that grants a second individual second access level rights. |
| US11508474B2 |
Event reconstruction for a medical device
A device for graphically reconstructing information received from a medical device is provided. The device comprises an event processor configured to process information received from a medical device by receiving electrocardiogram (ECG) recordings and determining at least one cardiac event based on the ECG recordings, receiving data corresponding to non-cardiac event(s), determining a time of occurrence or a time period associated with the cardiac event(s), determining times of occurrences and time periods associated with the non-cardiac event(s), correlating the time of occurrence or time period associated with the cardiac event(s) and the non-cardiac event(s), identifying one or more gaps in the ECG recordings, and reconstructing the ECG recordings during the one or more gaps based at least in part on the received non-cardiac data. The event processor is also configured to generate a graphical representation of the processed information based on the cardiac event(s) and non-cardiac event(s). |
| US11508470B2 |
Electronic medical data tracking system
Techniques for addressing various technical problems associated with managing medical data are described herein. One or more medical data tracking applications can execute on an electronic medical data tracking system. Such a computer system can include one more computing devices, such as for example a mobile computing device and a central computing system, that can optionally communicate with each other to send and receive information associated with a patient. The mobile computing device can be configured as an employee identification card, and can be configured to detect and identify patients, gestures, medical devices, and medicine associated with medical procedures. |
| US11508469B2 |
Hospital bed having wireless network connectivity
A system that monitors various conditions of a plurality of hospital beds located in different rooms of a healthcare facility is provided. Alternatively or additionally, other types of equipment may be monitored by the system. Various configurations of network interface units that are coupleable to or integrated into a hospital bed are also disclosed. The system receives data from the hospital beds and/or other equipment and initiates a communication to a wireless communication device of at least one designated caregiver in response to the received data being indicative of an alarm condition. |
| US11508467B2 |
Aggregation, partitioning, and management of healthcare data for efficient storage and processing
Methods, systems, and computer-readable media are provided for aggregating, partitioning, and storing healthcare data. Healthcare data is collected from various disparate healthcare data sources. The data is aggregated into batches of the same type of data. From here, the data is partitioned according to the data's originating healthcare data source. The aggregated and partitioned healthcare data is then stored in a long term storage data store. This system of storing healthcare data allows for efficient retrieval and processing by computing solutions that need access to batches of healthcare data. The system also reduces costs associated with storing data as duplicate storage is eliminated. |
| US11508466B2 |
Methods, systems, and devices for determining multi-party collocation
Methods, systems, and computer-readable media are provided for analyzing amounts of time spent by clinicians caring for patients. Clinician locations, patient locations, patient data, and clinician electronic health record activity may be used to facilitate generation of one or more predictive models. Such predictive models will provide, among other things, a decision support tool for scheduling patient-clinician appointments to minimize, at least partially, patient wait times. |
| US11508465B2 |
Systems and methods for determining event probability
Systems and methods for data unfolding are disclosed. For example, it may be desirable or necessary to increase a data set, such as for increasing accuracy of one or more predictive models. Data set proliferation without introducing unnecessary bias may be important for increasing such accuracy. Described herein are system and methods that allow for data set proliferation by generating records based on whether an event occurred with respect to an entity during multiple time intervals. A record may be generated for each time interval and the associated data may be unfolded and disassociated, at least partly, from other records related to the entity. Those records may then be used for data analytics and/or predictive model generation, for example. |
| US11508464B1 |
Technology platform for care planning and coordination
Platform for care coordination and planning. Integration of care planning tool, frontend applications, and customer support platform to assist in trust administration for beneficiaries who may have disabilities. The platform may be used to provide planning, concierge, and fiduciary services. |
| US11508462B2 |
Control of trion density in carbon nanotubes for electro-optical and opto-electric devices
An optoelectronic system can include a single walled carbon nanotube (SWNT) device. The SWNT can include a carrier-doping density with optical conditions that control trion formation that respond via optical, electrical, or magnetic stimuli. The carrier-doping density can include a hole-polaron or electron-polaron concentration. |
| US11508456B2 |
Semiconductor memory device capable of increasing flexibility of a column repair operation
A semiconductor memory device includes a memory cell array, a bit-line switch, a block switch, and a column decoder. The memory cell array includes memory blocks coupled to at least one word-line and each of the memory blocks includes memory cells. The bit-line switch is connected between a first half local input/output (I/O) line of a first memory block and a second half local I/O line of the first memory block. The block switch is connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block adjacent to the first memory block. The column decoder includes a repair circuit that controls connections by applying a first switching control signal to the bit-line switch and a second switching control signal to the block switch. |
| US11508454B2 |
Data storage device and method of operating the same
A data storage device including a memory device and a memory controller is disclosed. The memory controller including a super block includes a parity controller in communication with a memory device including a plurality of pages and configured to generate a first parity using data to be written to a first group of pages among the plurality of pages, and generate a second parity using data to be written to a second group of pages among the plurality of pages, a write operation controller configured to control the memory device to store the first parity and the second parity, and an error correction circuitry coupled to apply the first parity and the second parity to correct at least one of the plurality of pages arranged to belong to the first group of pages and the second group of pages. |
| US11508453B2 |
Encoding test data of microelectronic devices, and related methods, devices, and systems
Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed. |
| US11508451B2 |
Storage device that determines write area of read reclaim operation based on estimated read count of reclaim area and operating method of the storage device
A storage device includes a nonvolatile memory device that includes a first storage area and a second storage area. A controller of the storage device controls the nonvolatile memory device and performs a read reclaim operation of reading data stored in the first storage area of the nonvolatile memory device and writing the read data in the second storage area. In the read reclaim operation, the controller is further configured to allow the nonvolatile memory device to perform sample read operations on the first storage area and to determine locations of the second storage area, at which the data are to be written, based on results of the sample read operations. |
| US11508444B2 |
Memory cell sensing
Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices. |
| US11508440B1 |
Periodic write to improve data retention
A nonvolatile memory control method includes a step of writing, repeatedly to a nonvolatile memory cells. The method continues with detecting when writing reaches a writing threshold value. Upon reaching the writing threshold, the method continues with driving a charge to at least one parasitic area intermediate at least two charge storage areas of the nonvolatile memory cells to improve data retention in at least one of the at least two charge storage areas of the nonvolatile memory cells. |
| US11508437B2 |
Restoring memory cell threshold voltages
Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell. |
| US11508434B2 |
Semiconductor memory device and method for operating the same
There are provided a semiconductor memory device and a method for operating the same. The semiconductor memory device includes: a memory cell array with a plurality of memory cells programmed to a plurality of program states; a peripheral circuit configured for performing a program operation on selected memory cells among the plurality of memory cells through a plurality of program loops; a current sensing circuit for determining a verify result of each of the plurality of program states by performing an individual state current sensing operation on the selected memory cells among the memory cells; and a control logic for controlling the current sensing circuit to perform the individual state current sensing operation, based on a number of program loops, among a plurality of program loops, that are performed. |
| US11508431B2 |
Logical operations using a logical operation component
An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier. |
| US11508428B2 |
Voltage supply circuit, memory cell arrangement, transistor arrangement, and methods thereof
An electronic circuit may be operated based on two or more supply voltages ramped in accordance with a digital control scheme, the digital control scheme may include ramping a voltage value of a first output voltage generated via a first digitally controlled voltage converter from a first target voltage value to a third target voltage value such that the voltage value of the first output voltage matches a second target voltage value during a first ramp interval and the third target voltage value during a second ramp interval; and ramping a voltage value of a second output voltage generated via a second digitally controlled voltage converter from the first target voltage value to the second target voltage value such that the voltage value of the second output voltage matches the second target voltage value during the first ramp interval, and the second target voltage value during the second ramp interval. |
| US11508423B2 |
Noise shielding circuit and chip
A chip includes a processor, a memory, and a storage controller of the memory. There is an access path between the processor and the storage controller, and the processor reads data from or writes data into the memory by using the storage controller through the access path. The chip further includes a shielding circuit. The shielding circuit is configured to shield a signal on the access path when the processor is powered off. |
| US11508420B2 |
Memory device, memory system, and operation method of memory device
A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device. |
| US11508419B2 |
Page buffer and memory device including the same
A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer. |
| US11508418B2 |
System for performing reference voltage training operation
A system to perform a reference voltage training operation may include: a controller configured to output a dock signal, a chip selection signal, a command address and data; and a semiconductor device configured to enter a training mode to control the level of a reference voltage when the chip selection signal and the command address are a first logic level combination in synchronization with the clock signal, configured to enter an ID setting mode to set a storage ID when the chip selection signal and the command address are a second logic level combination, and configured to enter an ID selection mode to update a voltage code that is generated in the training mode when the chip selection signal and the command address are a third logic level combination. |
| US11508417B2 |
Memory cell device and method for operating a memory cell device
In accordance with an embodiment, a memory cell device includes at least one memory cell; a first switch connected between the at least one memory cell and a reference potential node; a second switch connected between the at least one memory cell and the reference potential node, and switch driver logic adapted to put the first switch selectively into one of at least three operating states by activation or deactivation of a first subcircuit of the switch driver logic, wherein the at least three operating states comprises an on state, an off state, and a conductive state in which an electrical conductivity of the first switch is lower than in the on state and higher than in the off state, and put the second switch selectively into one of the at least three operating states by activation or deactivation of a second subcircuit of the switch driver logic. |
| US11508415B2 |
Semiconductor memory package structure and semiconductor memory system
A semiconductor memory package structure includes at least one semiconductor die and a lead group. The at least one semiconductor die includes a chip enable terminal. The lead group is configured to electrically connect the chip enable terminal to an external circuit board and includes a first pin and a second pin coupled to the chip enable terminal. The at least one semiconductor die and the lead group are formed as an integral entity using an insulating material. |
| US11508414B2 |
Storage module with reduced airflow impedance and improved storage device dynamics performance
A cooling system for cooling a set of components in a compute module and an array of storage devices in a storage module, the array of storage devices comprising rows and columns. The storage module is wider than the compute module to accommodate a larger backplane. The backplane has large vertical vent openings for accommodating connectors of storage devices connecting to the backplane. Pairs of divider walls positioned between adjacent columns of storage devices form large channels for increased airflow between columns of storage devices and reduced airflow between adjacent rows of storage devices. The design allows for increased cooling performance and reduced acoustic energy (noise). |
| US11508410B2 |
Magnetic tape cartridge with increased data storage capacity
A tape cartridge for retaining a magnetic tape, the tape cartridge being configured to be selectively positioned substantially within a tape drive, includes a cartridge body and a cartridge hub. The cartridge body includes a cartridge length from a front to a rear of the cartridge body, and a cartridge width from a first side to a second side of the cartridge body. The cartridge hub is positioned within the cartridge body. The cartridge hub is configured so that the magnetic tape is wound around the cartridge hub within the cartridge body. The cartridge hub includes a hub diameter. The cartridge length and the cartridge width provide boundaries for a maximum wound tape diameter as the magnetic tape is wound around the cartridge hub within the cartridge body. A ratio of the maximum wound tape diameter to the hub diameter is at least approximately 3.50:1. |
| US11508402B1 |
Slider assemblies having recesses with solder structures for magnetic recording devices, and related methods of forming slider assemblies
Aspects of the present disclosure generally relate to slider assemblies for magnetic heads of magnetic recording devices. In one aspect, a slider assembly for magnetic recording devices includes a slider and an anti-reflection coating (ARC) structure disposed on the slider. The ARC structure includes an outer surface facing away from the slider, and a recess extending into the outer surface to define a recessed surface. The slider assembly includes a soldered structure disposed on the recessed surface and at least partially in the recess of the ARC structure. In one aspect, a method of forming a slider assembly includes forming an anti-reflection coating (ARC) structure on a slider. The ARC structure includes an outer surface facing away from the slider. The method includes forming a recess in the ARC structure, and forming a solder structure on a recessed surface and at least partially in the recess of the ARC structure. |
| US11508401B1 |
Magnetic recording devices having cross-track current flow to facilitate downtrack magnetic field enhancements
Aspects of the present disclosure generally relate to a magnetic recording head of a magnetic recording device that facilitates generating a downtrack magnetic bias field to enhance writing. During magnetic writing using the magnetic recording head, a bias current is directed in a cross-track direction on the trailing side of the main pole. Bias current flowing in the cross-track direction on a leading side of the main pole is reduced or eliminated. The bias current flowing in the cross-track direction on the trailing side of the main pole facilitates generating a magnetic field in a downtrack direction. The magnetic field in the downtrack direction is a bias field generated using the bias current. The magnetic bias field in the downtrack direction facilitates enhanced writing performance and increased areal density capability (ADC) for magnetic recording. |
| US11508399B2 |
Magnetic disk device and read/write processing method
According to one embodiment, a magnetic disk device includes a disk, a head, and a controller setting a rewrite threshold value for executing a rewrite process of different tracks in a first sector group including at least one first sector continuous from a first parity sector in which error correction processing in units of tracks is executable based on the first parity sector and including the first parity sector, and a second sector group including at least one second sector continuous in which the error correction processing in units of tracks is unexecutable, and rewriting the first sector group and the second sector group with different frequencies. |
| US11508397B2 |
Method and system for generating mixed voice data
The present disclosure discloses a method and system for generating mixed voice data, and belongs to the technical field of voice recognition. In the method for generating mixed voice data according to the present disclosure, a pure voice and noise are collected first, normalization processing is performed on the collected voice data, randomization processing is performed on processed data, then GAIN processing is performed on the data, and finally filter processing is performed to obtain mixed voice data. The system for generating mixed voice data according to the present disclosure includes a collecting unit, a calculating unit, and a storage unit, the collecting unit being electrically connected to the calculating unit, and the calculating unit being connected to the storage unit through a data transmitting unit. The present disclosure provides the method and the system to meet the data requirement of deep learning. |
| US11508392B1 |
Automated conversation content items from natural language
A conversation augmentation system can automatically augment a conversation with content items based on natural language from the conversation. The conversation augmentation system can select content items to add to the conversation based on determined user “intents” generated using machine learning models. The conversation augmentation system can generate intents for natural language from various sources, such as video chats, audio conversations, textual conversations, virtual reality environments, etc. The conversation augmentation system can identify constraints for mapping the intents to content items or context signals for selecting appropriate content items. In various implementations, the conversation augmentation system can add selected content items to a storyline the conversation describes or can augment a platform in which an unstructured conversation is occurring. |
| US11508391B2 |
Device to amplify and clarify voice
A voice enhancing device amplifies and clarifies the voice of a user with hypophonia or other voice issues. The device includes a collar of either rigid or a soft material that is shaped to comfortably sit on the shoulders of the user. One or more microphone arrays are adjustably mounted to the collar to capture audio of the user talking. An electronics module enhances the captured audio signal and generates an enhanced audio signal that drives at least one speaker adjustably attached to the collar. The electronic controller implements one or more of an AGC amplifier to correct amplitude variation in spoked words, adaptive filtering to actively filter out background noise, a variable attack and decay function to improve intelligibility of the spoken words, a diphthong modification function to clarify the spoken words, and an echo cancelation function to reduce echo and feedback in the enhanced audio. |
| US11508390B1 |
Voice transmitter assembly
A voice transmitter assembly for enhancing verbal communication for a user wearing a face mask includes a clip that has a first member which is biased against a second member to engage a face mask. A microphone is coupled to the second member of the clip to capture words spoken by the user. A speaker is coupled to the first member of the clip to emit audible sounds to a listener. The speaker is in communication with the microphone thereby facilitating the speaker to emit sounds captured by the microphone. In this way the speaker can enhance the listener's ability to hear the words spoken by the user. |
| US11508388B1 |
Microphone array based deep learning for time-domain speech signal extraction
A device for processing audio signals in a time-domain includes a processor configured to receive multiple audio signals corresponding to respective microphones of at least two or more microphones of the device, at least one of the multiple audio signals comprising speech of a user of the device. The processor is configured to provide the multiple audio signals to a machine learning model, the machine learning model having been trained based at least in part on an expected position of the user of the device and expected positions of the respective microphones on the device. The processor is configured to provide an audio signal that is enhanced with respect to the speech of the user relative to the multiple audio signals, wherein the audio signal is a waveform output from the machine learning model. |
| US11508387B2 |
Selecting audio noise reduction models for non-stationary noise suppression in an information handling system
Selecting audio noise reduction models for noise suppression in an information handling system (IHS), including performing calibration and configuration of an audio noise reduction selection model, including: identifying contextual data associated with contextual inputs to the IHS; training, based on the contextual data, the audio noise reduction selection model, including generating a configuration policy including configuration rules, the configuration rules for performing actions for selection of a combination of audio noise reduction models to reduce combinations of noise sources associated with the IHS; performing steady-state monitoring of the IHS, including: monitoring the contextual inputs of the IHS, and in response, accessing the audio noise reduction selection model, identifying configuration rules based on the monitored contextual inputs, applying the configuration rules to select a particular combination of audio noise reduction models, applying particular combination of audio noise reduction models to reduce a particular combination of noise sources associated with the IHS. |
| US11508382B2 |
System, device and method for enforcing privacy during a communication session with a voice assistant
A system, device and method for enforcing privacy during a communication session with a voice assistant are disclosed. In response to a determination that an environment of a first voice assistant device is not private, a first secure communication session between the first voice assistant device and an application server is suspended. In response a determination that one or more other voice assistant devices have been authorized for communication with the application server is made and input to transfer the first secure communication session, a second secure communication session between a second voice assistant device and the application server is initiated. The first secure communication session between the first voice assistant device and the application server is terminated in response to successful initiation of the second secure communication session. |
| US11508379B2 |
Asynchronous ad-hoc distributed microphone array processing in smart home applications using voice biometrics
Voice biometrics scoring is performed on received asynchronous audio outputs from microphones distributed at ad hoc locations to generate confidence scores that indicate a likelihood of an enrolled user speech utterance in the output, a subset of the outputs is selected based on the confidence scores, and the subset is spatially processed to provide audio output for voice application use. Alternatively, asynchronous spatially processed audio outputs and corresponding biometric identifiers are received from corresponding devices distributed at ad hoc locations, audio frames of the outputs are synchronized using the biometric identifiers, and the synchronized frames are coherently combined. Alternatively, uttered speech associated with respective ad hoc distributed devices is received and non-coherently combined to generate a final output of uttered speech. The uttered speech is recognized from respective spatially processed outputs generated by the respective devices using biometrics of talkers enrolled by the devices. |
| US11508377B2 |
System and method for detecting fraud rings
A system and method may identify a fraud ring based on call or interaction data by analyzing by a computer processor interaction data including audio recordings to identify clusters of interactions which are suspected of involving fraud each cluster including the same speaker; analyzing by the computer processor the clusters, in combination with metadata associated with the interaction data, to identify fraud rings, each fraud ring describing a plurality of different speakers, each fraud ring defined by a set of speakers and a set of metadata corresponding to interactions including that speaker; and for each fraud ring, creating a relevance value defining the relative relevance of the fraud ring. |
| US11508376B2 |
Providing virtual personal assistance with multiple VPA applications
The activities of multiple virtual personal assistant (VPA) applications are coordinated. For example, different portions of a conversational natural language dialog involving a user and a computing device may be handled by different VPAs. |
| US11508375B2 |
Electronic apparatus including control command identification tool generated by using a control command identified by voice recognition identifying a control command corresponding to a user voice and control method thereof
An electronic apparatus is provided. The electronic apparatus includes a microphone, a transceiver, a memory configured to store a control command identification tool based on a control command identified by a voice recognition server that performs voice recognition processing on a user voice received from the electronic apparatus, and at least one processor configured to, based on the user voice being received through the microphone, acquire user intention information by performing the voice recognition processing on the received user voice, receive status information of external devices related to the acquired user intention information from a device control server, identify a control command for controlling a device to be controlled among the plurality of external devices by applying the acquired user intention information and the received status information of the external devices to the control command identification tool, and transmit the identified control command to the device control server. |
| US11508374B2 |
Voice commands recognition method and system based on visual and audio cues
A method and system for voice commands recognition. The system comprises a video camera and a microphone producing an audio/video recording of a user issuing vocal commands and at least one processor connected to the video camera and the microphone. The at least one processor has an associated memory having stored therein processor executable code causing the processor to perform the steps of: obtain the audio/video recording from the video camera and the microphone; extract video features from the audio/video recording and store the result in a first matrix; extract audio features from the audio/video recording and store the result in a second matrix; apply a speech-to-text engine to the audio portion of the audio/video recording and store the resulting syllables in a text file; and identify via a neural network the vocal commands of the user based on the first matrix, the second matrix and the text file. |
| US11508373B1 |
Systems and methods to translate a spoken command to a selection sequence
Systems and methods to translate a spoken command to a selection sequence are disclosed. Exemplary implementations may: obtain audio information representing sounds captured by a client computing platform; analyze the sounds to determine spoken terms; determine whether the spoken terms include one or more of the terms that are correlated with the commands; responsive to determining that the spoken terms are terms that are correlated with a particular command stored in the electronic storage, perform a set of operations that correspond to the particular command; responsive to determine that the spoken terms are not the terms correlated with the commands stored in the electronic storage, determining a selection sequence that causes a result subsequent to the analysis of the sounds; correlate the spoken terms with the selection sequence; store the correlation of the spoken terms with the selection sequence; and perform the selection sequence to cause the result. |
| US11508372B1 |
Natural language input routing
Techniques for performing runtime ranking of skill components are described. A skill developer may generate a rule indicating a skill component is to be invoked at runtime when a natural language input corresponds to a specific context. At runtime, a virtual assistant system may implement a machine learned model to generate an initial ranking of skill components. Thereafter, the virtual assistant system may use skill component-specific rules to adjust the initial ranking, and this second ranking is used to determine which skill component to invoke to respond to the natural language input. Overtime, if a rule results in beneficial user experiences, the virtual assistant system may incorporate the rule into the machine learned model. |
| US11508364B2 |
Electronic device for outputting response to speech input by using application and operation method thereof
An artificial intelligence (AI) system is provided. The AI system simulates functions of human brain such as recognition and judgment by utilizing a machine learning algorithm such as deep learning, etc. and an application of the AI system. A method, performed by an electronic device, of outputting a response to a speech input by using an application, includes receiving the speech input, obtaining text corresponding to the speech input by performing speech recognition on the speech input, obtaining metadata for the speech input based on the obtained text, selecting at least one application from among a plurality of applications for outputting the response to the speech input based on the metadata, and outputting the response to the speech input by using the selected at least one application. |
| US11508363B2 |
Speech processing apparatus and method using a plurality of microphones
A speech processing apparatus includes a plurality of microphones configured to receive a plurality of input signals, and processing circuitry configured to generate a spatial filtering signal corresponding to the plurality of input signals through spatial filtering, generate estimated noise information by integrating directional noise information representing a level of a noise signal received from a direction of interest with diffuse noise information representing levels of noise signals received from various directions based on whether the plurality of input signals have directionality, and generate an estimated speech signal by filtering the spatial filtering signal based on the estimated noise information. |
| US11508362B2 |
Voice recognition method of artificial intelligence robot device
A voice recognition method of an artificial intelligence robot device is disclosed. The voice recognition method includes collecting a first voice spoken by a user and determining whether a wake-up word of the artificial intelligence robot device is recognized based on the collected first voice; if the wake-up word is not recognized, sensing a location of the user using at least one sensor and determining whether the sensed location of the user is included in a set voice collection range; if the location of the user is included in the voice collection range, learning the first voice and determining a noise state of the first voice based on the learned first voice; collecting a second voice in an opposite direction of the location of the user according to a result of the determined noise state of the first voice; and extracting a feature value of a noise based on the second voice and removing the extracted feature value of the noise from the first voice to obtain the wake-up word. The artificial intelligence robot device may be associated with an artificial intelligence module, an unmanned aerial vehicle (UAV), a robot, an augmented reality (AR) device, a virtual reality (VR) device, devices related to 5G services, and the like. |
| US11508359B2 |
Using backpropagation to train a dialog system
Techniques described herein use backpropagation to train one or more machine learning (ML) models of a dialog system. For instance, a method includes accessing seed data that includes training tuples, where each training tuple comprising a respective logical form. The method includes converting the logical form of a training tuple to a converted logical form, by applying to the logical form a text-to-speech (TTS) subsystem, an automatic speech recognition (ASR) subsystem, and a semantic parser of a dialog system. The method includes determining a training signal by using an objective function to compare the converted logical form to the logical form. The method further includes training the TTS subsystem, the ASR subsystem, and the semantic parser via backpropagation based on the training signal. As a result of the training by backpropagation, the machine learning models are tuned work effectively together within a pipeline of the dialog system. |
| US11508357B2 |
Extended impersonated utterance set generation apparatus, dialogue apparatus, method thereof, and program
An extended role play-based utterance set generation apparatus includes a first data store storing role play-based utterance sets and a second data store storing non-role-played utterance sets. The role play-based utterance sets include a first query and a role play-based response to the query. The non-role-played utterance sets include a second query and a non-role-played response to the query. The disclosed technology determines similarity between the role play-based response and the non-role-played response. Upon determining that the role play-based response is the same or similar to the non-role-played response, the disclosed technology generates an association between the role play-based response and the second query and extends the role play-based utterance sets in the first data store with the second query. |
| US11508352B2 |
Method and system for noise suppression
Aspects of the invention are directed towards a system and method for noise suppression. One or more embodiments of the invention describe the method comprising steps of receiving noise by a microphone and deriving a noise signal from the noise, the noise produced by a fan of a fire/smoke detection unit while drawing air and detecting the speed of the fan of the fire/smoke detection unit. The method further describes steps of amplifying the noise signal by the amplifier received from the microphone and producing an anti-phase noise signal by shifting a phase of the amplified noise signal received from the amplifier wherein the anti-phase noise signal is dependent on the detected speed of the fan. The method further describes steps of outputting the anti-phase noise signal through a speaker to suppress the noise produced by the fan of the fire/smoke detection unit while drawing the air. |
| US11508351B2 |
Multi-task deep network for echo path delay estimation and echo cancellation
A method of echo path delay destination and echo cancellation is described in this disclosure. The method includes: obtaining a reference signal, a microphone signal, and a trained multi-task deep neural network, wherein the multi-task deep neural network comprises a first neural network and a second neural network; generating, using the first neural network of the multi-task deep neural network, an estimated echo path delay based on the reference signal and the microphone signal; updating the reference signal based on the estimated echo path delay; and generating, using the second neural network of the multi-task deep neural network, an enhanced microphone signal based on the microphone signal and the updated reference signal. |
| US11508347B1 |
Portable acoustical road barrier
A portable acoustic road barrier for use with a road divider is disclosed comprising a frame having a lower horizontal panel frame portion, a first and a second vertical panel frame portion and an upper horizontal panel frame portion. A first and a second mount from the frame for removably securing the frame to the road divider. A sheet of acoustical blocking material is secured to the panel frame portions. The sheet of acoustical blocking material is flexible for enabling the sheet of acoustical blocking material and reinforcing tape to be rolled as a single unit for transportation. |
| US11508346B2 |
Miniature ultrasonic transducer package
A package design for a micromachined ultrasound transducer (MUT) utilizing curved geometry to control the presence and frequency of acoustic resonant modes is described. The approach consists of reducing in number and curving the reflecting surfaces present in the package cavity to adjust the acoustic resonant frequencies to locations outside the band of interest. The design includes a cavity characterized by a curved geometry and a MUT mounted to a side of a substrate facing the cavity with a sound emitting portion of the MUT facing an opening in the substrate. The substrate is disposed over an opening of the cavity with the substrate oriented such that the MUT located within the cavity. |
| US11508345B1 |
Systems and methods for facilitating transactions of musical stems between users of an online gaming platform and mixing of the musical stems
Systems and methods for facilitating transactions of musical stems between users of an online gaming platform and mixing of the musical stems are disclosed. Exemplary implementations may: store information regarding tracks; transmit a purchase request regarding a given stem; receive a notification of the assignment of the right to use the given stem, wherein the assignment is recorded on a blockchain; obtain the given stem, generate an arrangement based on one or more stored tracks and the given stem, and playing back the generated arrangement. |
| US11508341B2 |
Keyboard device for keyboard instrument
A keyboard device for a keyboard instrument, capable of largely reducing noise generated when a hammer contacts a lower limit stopper during key release immediately after key depression. The keyboard device includes a keyboard chassis disposed on a keybed, keys pivotally supported on the chassis, hammers pivotally supported on the chassis below the keys and each vertically pivotally moved, an intermediate rail mounted on the chassis below a rotational shaft of the hammers and its vicinity in a state floating from the keybed, and a lower limit stopper mounted on the intermediate rail, such that each hammer is placed thereon via its placement-contact portion when in a key-released state and contacts the same from above via the placement-contact portion when pivotally moving downward in accordance with key release after being moved upward by key depression, whereby further pivotal motion of the hammer is stopped. |
| US11508338B2 |
Register spill/fill using shared local memory space
A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device. |
| US11508335B2 |
Display apparatus and display method with brightness conversion
A display apparatus includes at least one memory and at least one processor which function as a processing unit, a display control unit, and a setting unit. The processing unit is configured to perform first image processing and second image processing. The display control unit is configured to perform control to perform a first display based on a result of the first image processing and a second display based on a result of the second image processing, together. The setting unit is configured to set upper-limit brightness of the second display. An Electro-Optical Transfer Function (EOTF) type of the first display and an EOTF type of the second display are EOTF types dealing with high dynamic range (HDR). The processing unit converts brightness of an image according to the upper-limit brightness and the EOTF type of the first display in the second image processing. |
| US11508333B2 |
Automatically adjusting screen brightness based on screen content
Disclosed are examples for adjusting screen brightness based on screen content being presented on a display screen of a mobile device. The described examples may determine a time at which the screen content is to be evaluated. The screen content is categorized based on the evaluation. A category of the screen content may be input into a machine learning algorithm that may be used to determine whether a screen brightness adjustment is appropriate. If a screen brightness adjustment is appropriate, a degree of the screen brightness adjustment may be determined. |
| US11508331B1 |
Image uniformity compensation device
The disclosure provides an image uniformity compensation device. The image uniformity compensation device includes a local pre-compensation circuit, a chromaticity uniformity compensation circuit, a local post-compensation circuit, and a luminance uniformity correction circuit. A local pre-conversion performed by the local pre-compensation circuit includes the following. An image frame is divided into multiple regions, and each of the regions is converted from an optical non-linear domain to an optical linear domain to generate a corresponding region in multiple regions of a converted frame. A local post-conversion performed by the local post-compensation circuit includes the following. An image frame is divided into multiple regions, and each of the regions is converted from the optical linear domain to the optical non-linear domain to generate a corresponding region in multiple regions of a converted frame. |
| US11508330B2 |
Display device and method based on discarding bits from a bit sequence
The present disclosure provides a device, in particular a multifocal display device. The device includes: a display element configured to generate an image; and a controller configured to control the display element according to at least a first bit sequence provided over a first determined time period and a second bit sequence provided over a second determined time period, in order to generate the image with one or more colors, the bit sequences including for each color a number of bits of different significance. Moreover, the device is configured to generate the first bit sequence from an original bit sequence based on discarding at least one bit of a color and to generate the second bit sequence from the original bit sequence based on discarding at least one other bit of the color. |
| US11508326B2 |
Display apparatus and operating method thereof
A display apparatus includes a display panel including a plurality of pixels, each pixel of the plurality of pixels having a plurality of light-emitting devices; a storage configured to store a plurality of calibration matrices for each pixel of the plurality of pixels; a processor configured to identify a calibration matrix according to input data of the plurality of pixels and to calibrate modulation data corresponding to the input data based on the identified calibration matrix; and a panel driver configured to drive the display panel by applying a driving signal generated from the calibrated modulation data to the light-emitting devices of the plurality of pixels, wherein the plurality of calibration matrices includes a white calibration matrix and a color calibration matrix. |
| US11508325B2 |
Pixel structure, method of driving the same and display device
The present disclosure provides a pixel structure, a method of driving the same and a display device. The pixel structure includes gate lines, data lines, and a plurality of subpixels arranged in an array form. Subpixels in each row correspond to two gate lines. Each data line corresponds to the subpixels in two adjacent columns, and each data line is arranged between the two adjacent columns of subpixels. Among the subpixels in each row, three adjacent subpixels are in different colors and forms a complete pixel unit. Among the subpixels in each column, three adjacent subpixels are in different colors and forms the complete pixel unit. Among the subpixels in two adjacent columns, the subpixels in two adjacent rows form two complete pixel units each including three subpixels, and two of the three subpixels are shared by the two pixel unit. |
| US11508320B2 |
Pixel of an organic light emitting diode display device, and organic light emitting diode display device
A pixel of an OLED display device includes a first capacitor, a second capacitor, a first transistor configured to generate a driving current, a second transistor configured to transfer a data voltage to a first node, a third transistor configured to diode-connect the first transistor, a fourth transistor configured to transfer an initialization voltage to the second node, a fifth transistor configured to transfer a reference voltage to the first node, a sixth transistor configured to couple a drain of the first transistor and an anode of an organic light emitting diode, a seventh transistor configured to transfer the initialization voltage to the anode of the organic light emitting diode, an eighth transistor configured to transfer the initialization voltage to the drain of the first transistor, and the organic light emitting diode. |
| US11508319B2 |
Source driver and display device including the same
A source driver capable of improving sensing accuracy even when a black image signal is provided to reduce motion blur during a sensing period for sensing signals of pixels of a display panel, and a display device including the same. The source driver includes an output buffer configured to output a source signal; a voltage terminal applied with a black image signal of a preset voltage level; a source output terminal connected to a data line of a display panel; and a switch circuit configured to connect one of an output terminal of the output buffer and the voltage terminal to the source output terminal, wherein the switch circuit connects the voltage terminal to the source output terminal during a black image insertion period of a sensing period in which a pixel of the display panel is sensed. |
| US11508318B2 |
Light emitting display device
A light emitting display device includes: a first driving transistor; a first anode electrically connected to the first driving transistor; a first capacitor electrically connected to a gate electrode of the first driving transistor; a second driving transistor disposed to be adjacent to the first driving transistor; a second anode electrically connected to the second driving transistor; a second capacitor electrically connected to a gate electrode of the second driving transistor; a driving voltage line which applies a driving voltage to the first driving transistor and the second driving transistor; and a first connecting member electrically connecting the gate electrode of the first driving transistor and the first capacitor, where the driving voltage line is disposed between the first connecting member and the second anode in a plan view. |
| US11508315B2 |
Pixel sensing circuit and pixel sensing method
An embodiment relates to a pixel sensing circuit and a pixel sensing method and, more particularly, to a pixel sensing circuit and a pixel sensing method for reducing the size of a source driver IC by sharing some components in a pixel sensing circuit and for sensing a pixel using a pixel sensing circuit in which some components are shared. |
| US11508312B2 |
Organic light emitting display device
An organic light emitting display device includes a first display area in which first sub-pixels are disposed, a second display area in which second sub-pixels are disposed in a density lower than the first display area, and a gate driver at least a part of which overlaps the second display area. |
| US11508310B2 |
Scan driver and organic light emitting display apparatus including the same
A scan driver and an organic light emitting display apparatus including the same, where a narrow bezel is realized, are provided. The scan driver includes a plurality of stages, wherein each of the plurality of stages includes a Q1 node controller controlling a voltage of a Q1 node by using first and second clock signals whose phases are opposite to each other, a QB node controller controlling a voltage of a QB node by using the first and second clock signals, an output clock signal, and a start signal, a first transistor outputting a gate low voltage as a scan signal while the QB node is activated, and a second transistor outputting a gate high voltage as the scan signal while a Q2 node is activated, and outputting the gate low voltage as the scan signal when the Q2 node is bootstrapped to a voltage lower than the gate low voltage. |
| US11508305B2 |
Light emitting diode display and driving method thereof for reducing brightness change due to refresh rate variation
A driving method of LED display, configured to be applied to an LED display capable of varying a refresh rate thereof and able to reduce brightness changes due to refresh rate variation, is disclosed in the present disclosure. This driving method includes: controlling an organic light-emitting diode of the LED display by an emission signal having a plurality of frame periods, with each of the frame periods having a PWM part with a duty ratio; detecting whether a change in the refresh rate of the LED display exists; and performing a compensation procedure when the change is detected, with the compensation procedure compensating a brightness difference of the organic light-emitting diode occurring due to the change in the refresh rate by adjusting the duty ratio of the PWM part. Said LED display is also disclosed. |
| US11508303B1 |
Display apparatus
A display apparatus is provided to include a pixel array composed of a plurality of pixels. Each pixel includes a pulse-generating unit producing a first pulse and a second pulse with opposite phases; a first switching unit; a light-emitting unit; and a second switching unit. The first switching unit, the light-emitting unit, and the second switching unit are connected in series, the first switching unit is controlled by the first pulse, and the second switching unit is controlled by the second pulse, and the first switching unit and the second switching unit are configured to be turned on or turned off synchronously. |
| US11508301B2 |
Pixel circuit, display substrate, display panel and pixel driving method
An embodiment of the present disclosure provides a pixel circuit, including: a reference writing circuit configured to write a reference voltage to a control electrode of a driving transistor; a data writing circuit configured to write a data voltage to a threshold compensation circuit; the threshold compensation circuit configured to acquire a threshold voltage of the driving transistor, and to supply a first control voltage to the control electrode of the driving transistor and supply a second control voltage to a second electrode of the driving transistor; a reset circuit configured to write a reset voltage to the pixel circuit; and the driving transistor having a first electrode electrically coupled to a first operating voltage terminal and the second electrode electrically coupled to a first electrode of a light emitting element, and configured to drive the light emitting element to emit light. |
| US11508300B2 |
Display device
A display device includes: pixels arranged in a matrix; a plurality of write signal lines for selecting a pixel row to which a data voltage is to be written; a gate driver that supplies a gate signal; a plurality of data signal lines for writing the data voltage; a data driver that supplies the data voltage; a data selector circuit that supplies, per at least one data signal line by time division, the data voltage; and a controller. Each of the pixels includes a light-emitting element, a capacitor element, and a drive transistor that supplies a current in accordance with the voltage held by the capacitor element to the light-emitting element. The controller causes the gate driver and the data driver to perform an initialization operation on pixels in a second pixel row after a period during which a write operation is performed on pixels in a first pixel row. |
| US11508296B2 |
Image display system for displaying high dynamic range image
An image generation apparatus outputs image data to a display apparatus, performs inverse conversion on image data, and transmits the image data to the display apparatus through an external data transmission line. The display apparatus includes a display device that is capable of displaying a High Dynamic Range (HDR) image or a Standard Dynamic Range (SDR) image through the external data transmission line. The inverse conversion is performed with respect to light emission characteristics of the display device. The image data is generated by the light emission characteristic inverse conversion unit. The transmission is performed in a case where light emission characteristics of the display device approximate an Electro-Optical Transfer Function (EOTF) of the HDR, a bit precision of image data is no lower than a bit precision of the external data transmission line, and an image of the HDR is to be displayed on the display device. |
| US11508291B2 |
Display panel for reducing number of fixed potential lines in function display region, and display apparatus
A display panel and a display apparatus are provided. The display panel has a conventional display region and a function display region for arranging an optical function element, and includes first pixel circuits and first fixed potential lines that are located in the conventional display region and electrically connected to the first pixel circuits, and further includes second pixel circuits and second fixed potential lines that are located in the function display region and are electrically connected to the second pixel circuits. m1 first pixel circuit groups are provided between two adjacent first fixed potential lines, m2 second pixel circuit groups are provided between two adjacent second fixed potential lines, m1 and m2 are each a positive integer greater than or equal to 1, and m2>m. |
| US11508286B2 |
Method for driving a display panel, display driving device and electronic device
Provided are a method for driving a display panel, a display driving device and an electronic device. The method includes: acquiring any one frame of the picture to de displayed; dividing the any one frame of the picture to be displayed into a first partition picture, a second partition picture and a third partition picture; displaying the first partition picture in the first display region, displaying the second partition picture in the second display region, and displaying the third partition picture in the third display region; where in a same frame of picture to be displayed, a density A1 of sub-pixels for displaying the first partition picture, a density A2 of sub-pixels for displaying the second partition picture and a density A3 of sub-pixels for displaying the third partition picture satisfy that A1≤A2≤A3; and where sub-pixels in the second display region include first sub-pixels and second sub-pixels. |
| US11508285B2 |
Systems and methods for spatio-temporal dithering
In one embodiment, the system may receive a target pixel value for a pixel of an image of a series of images. The system may determine an error-modified target pixel value based on the target pixel value and a first error value. The system may generate a quantized pixel value corresponding to the error-modified target pixel value for display by the pixel of the image. The system may determine an aggregated representation of quantized pixel values displayed by the pixel of the image and corresponding pixels of one or more preceding images of the series of images. The system may determine a second error value based on the aggregated representation of the quantized pixel values and the first error-modified target pixel value. The system may dither at least a portion of the second error value to at least a corresponding pixel of a next image in the series of images. |
| US11508284B2 |
Grayscale compensation method and apparatus, display device
Disclosed are a grayscale compensation method and apparatus, and a display device. The grayscale compensation method includes obtaining a basic grayscale of each compensation device; obtaining an equivalent lighting duration of the each compensation device, where the equivalent lighting duration is a duration of lighting the compensation device with a preset grayscale obtained by converting an actual lighting duration of the compensation device; if the equivalent duration reaches a preset time point, obtaining a grayscale compensation parameter corresponding to the compensation device by searching a table according to the preset time point and the basic grayscale, and performing grayscale compensation on a sub-pixel in the compensation device according to the grayscale compensation parameter and the basic grayscale. |
| US11508283B2 |
Data driving device and panel driving method of data driving device
The present disclosure relates to a data driving device and a panel driving method of the data driving device. More particularly, it relates to a data driving device and a panel driving method of the data driving device in which a programmable gamma circuit is applied to a gamma voltage circuit of the data driving device and some components of a channel circuit are used in common so as to reduce the size of the data driving device. |
| US11508280B2 |
Display device, display driver, and failure inspection method
An operational amplifier has a first input terminal and an output terminal connected to a second input terminal of the operational amplifier, and output nodes connected to the source lines of a display panel. During a failure inspection mode, the connection between the output node and the output terminal of the operational amplifier included in another output circuit among one output circuit and the other output circuit is disconnected and the output node instead of the output terminal is connected to the second input terminal of the operational amplifier. A pair of source lines connected to the output nodes of the one output circuit and the other output circuit are linked to each other, and signals attained by acquiring and binarizing voltages outputted from the operational amplifier in the other output circuit as a monitor voltage at different timings are acquired as first and second failure determination signals. |
| US11508279B2 |
Gate driving circuit, display device and method for driving display device
Embodiments of the present disclosure relate to a gate driving circuit, a display device, and a method for driving a display device. It is possible to reduce deterioration of the transistor controlled by a first QB node and a second QB node by alternately driving the first QB node and the second QB node of a gate circuit. In addition, by sensing a deterioration deviation between a transistor controlled by the first QB node and a transistor controlled by the second QB node and adjusting a driving period of the first QB node and a driving period of the second QB node based on the sensing result, it is possible to maximize or at least increase the lifetime of the transistor controlled by the first QB node and the transistor controlled by the second QB node, thereby improving the reliability of the gate circuit. |
| US11508277B2 |
Display driving system, display module, method for driving display screen, and electronic device
An electronic device includes a display screen, where the display screen includes a first display region and a second display region, and a display driving system including a first emission (EM) signal output end configured to send a first EM signal to the display screen, where the display driving system further includes a second EM signal output end configured to send a second EM signal to the display screen, where the first EM signal controls the first display region to display an image in a first time period, and the second EM signal controls the second display region not to display an image in the first time period. |
| US11508274B2 |
Display panel driving device
The present disclosure relates to a technique for determining a fault of a data line disposed in a display panel using a data driving device. The data driving device may determine a fault of a data line by supplying a data voltage corresponding to a greyscale value to a data line and checking whether another data line is influenced by the data voltage. |
| US11508273B2 |
Built-in test of a display driver
A display driver includes image processing circuitry, driver circuitry, and test circuitry. The image processing circuitry is configured to generate first output data during a first display update period and generate second output data during a second display update period. The driver circuitry is configured to update a display panel based on the first output data during the first display update period and update the display panel based on the second output data during the second display update period. The test circuitry is configured to test the image processing circuitry during a test period disposed between the first display update period and the second display update period. |
| US11508272B2 |
Display system for a vehicle
Described is a display system for a vehicle. The display system uses one or more active displays integrated into a new vehicle or coupled as an aftermarket product in an existing vehicle. The new vehicle with integrated displays of the system may be provided to a purchaser for a reduced cost for participation in the advertisement system. The system operates to provide nearby vehicle occupants, pedestrians, or others with advertisement and/or emergency messages using the displays. The display system can show advertising messages or emergency messages on the active displays that are relevant to the location of the vehicle. The system may operate to prioritize the advertisement messages or emergency messages that will be displayed based on determinations made by a server of the system. |
| US11508269B2 |
Portable, self-illuminating traffic sign
A portable, self-illuminating traffic sign having a sign face with two opposite sides. One side indicates a first traffic signal, and the other side indicates a second traffic signal. Light assemblies are attached to each side of the sign. The light assemblies emit light that may match the predominant color of one of the sides of the sign. A battery may be disposed in a pole that connects to the sign. A handlegrip allows for the sign to be held and provides a switch to allow for the lights to be selectively turned on and off. The light assemblies are disposed within collar assemblies so as to reduce, or prevent, light emitted from the light assemblies reflecting off of the sign faces. |
| US11508267B2 |
Stretchable display device
A stretchable display device is provided. The display device includes a stretchable display panel, a flexible printed circuit board connected to the stretchable display panel, and a connecting circuit connecting the stretchable display panel and the flexible printed circuit board. The flexible printed circuit board includes a non-deformation region and a deformation region outside the non-deformation region. The flexible printed circuit board further includes a stretchable base substrate, a circuit component on the base substrate, and a compensating layer on the base substrate. The compensating layer is locally disposed in the non-deformation region and the circuit component is locally disposed in the non-deformation region. |
| US11508266B2 |
Flexible panel, manufacturing method thereof and display apparatus
The present disclosure provides a flexible panel, a manufacturing method thereof and a display apparatus. The flexible panel includes a substrate, and the substrate includes a display region, a frame region and a bendable region, the frame region surrounding the display region and disposed at the periphery of the display region, the bendable region disposed on a side of the frame region distal to the display region and abutting on the frame region, at least one groove is disposed in the substrate and recessed from a side surface of the substrate at an edge of the frame region, and respectively provided at at least one end of a boundary between the frame region and the bendable region, and one end of an orthographic projection of the groove on the substrate coincides with one end of the boundary. |
| US11508264B2 |
Label and manufacturing method
A method of manufacturing a label with a suspension handle includes providing a first layered material including a support layer and a releasable first front layer. A front surface of the first front layer is coated with a first detachment promoter layer, leaving a zone free of the first promoter layer. A handle area of the first promoter layer is coated with a second detachment promoter layer. A second layered material includes a second front layer and an adhesive layer. While the second detachment promoter layer is wet, the components are coupled, so the adhesive layer adheres to the free zone. The second detachment promoter layer-adhesive layer solidifies to bind the layers. In the second layer thickness, a suspension handle is separated from the handle area. A secondary label is superposed only over the first layer detachment promoter, and forms a label surround in the first front layer. |
| US11508263B2 |
Low complexity conversion to Montgomery domain
Disclosed herein is an apparatus for calculating a cryptographic component R2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises a processor configured to set a start value to be equal to R mod n, perform b iterations of a shift and subtract operation on the start value to produce a base value, wherein the start value is set to be equal to the base value after each iteration, set a multiplication operand to be equal to the base value, and perform k iterations of a Montgomery modular multiplication of the multiplication operand with the multiplication operand to produce an intermediate result, wherein the multiplication operand is set to be equal to the intermediate result after each iteration, wherein the shift and subtract operation comprises determining a shifted start value which is equivalent to the start value multiplied by two, and subtracting n from the shifted start value if the shifted start value is greater than or equal to n. |
| US11508262B2 |
Secure reading and writing apparatus, secure reading and writing method, and program
Data is efficiently read from and written in a sequence without an access position being revealed. A secure reading and writing apparatus (1) receives a read command or a write command as input, and, when the read command is input, outputs a secret text [a[x]] which is an x-th element of a secret text sequence [a], and, when the write command is input, adds the secret text [a[x]] which is the x-th element of the secret text sequence [a], to a secret text [d]. A secure reading part (12) reads the secret text [a[x]] which is the x-th element from the secret text sequence [a]. A buffer addition part (13) adds a secret text [c] of an unreflected value c to the secret text [a[x]]. A buffer appending part (14) appends a secret text [x] and the secret text [d] to a write buffer [b]. When the number of elements of the write buffer [b] exceeds a predetermined value, a secure writing part (15) adds a value indicated with a secret text vector [b1] to an access position of the secret text sequence [a] which is indicated with a secret text vector [b0]. |
| US11508252B2 |
Systems and methods for automated response data sensing-based next content presentation
Systems and methods for automatic generation of a content presentation plan are disclosed herein. The method can include receiving content identification information, retrieving objective information for the one or several objectives identified for inclusion in a content presentation plan, identifying at least one prerequisite skill for completion of at least one of the one or several objectives, generating at least one remediation question configured to delineate between users having mastery of the at least one prerequisite skill and users not having mastery of the at least one prerequisite skill, pre-selecting remedial content for providing to users identified as not having mastery of the at least one prerequisite skill, selecting objective content corresponding to the at least one objectives, and creating a content presentation plan containing the at least one remediation question, the remedial content, and the objective content. |
| US11508249B1 |
Secure testing using a smartphone
Method for taking a test using a smartphone including placing the smartphone into connection with a device, placing the device on a head of a person with the smartphone in a position in which a display of the smartphone is visible to the person, coupling the smartphone to the device and displaying test questions on the display. Cheating is detected by, for example, monitoring presence of the device on the head of the person by periodically obtaining biometric data from the person and analyzing a change in the biometric data relative to previously obtained biometric data for the person, and when a change is present, stopping display of the test questions and generating and transmitting a communication to a test-providing institution derived from the change in biometric data. |
| US11508243B2 |
Intersection travel coordination via V2X communication
Methods and apparatuses are provided for use in wireless communication devices to provide a capability for vehicles to actively perform traffic planning with regard to other vehicles, for example, within a region comprising an intersection and possibly wherein the intersection is not associated with a device or service for such or similar purposes. Such underlying techniques may reduce traffic congestion in certain instances by allowing two or more vehicles to negotiate or otherwise coordinate safe traversal within a region comprising an intersection. Moreover, the traffic planning techniques may be of use for a variety and/or mixture of different types of vehicles, paths, intersections, etc. |
| US11508241B2 |
Parking area mapping using image-stream derived vehicle description and space information
In certain embodiments, a vehicle may obtain a video stream via a camera system of the vehicle. The video stream may be processed to extract one or more feature vectors from the video stream. Based on the feature vectors extracted from the video stream, vehicle description information related to one or more parked vehicles in the parking area may be determined. Space information indicating locations of the parked vehicles relative to available parking spaces in the parking area may also be determined based on the feature vectors extracted from the video stream. A mapping of the parking area may then be generated based on the vehicle description information and the space information. |
| US11508236B2 |
Devices and methods for recognizing driving behavior based on movement data
Electronic devices and methods for recognizing driving behavior are provided. The electronic devices may perform the methods to obtain first electronic signals encoding movement data associated with the electronic device from the at least one sensor at a target time point; operate logic circuits to determine whether the first electronic signals encoding movement data meets a precondition; and upon the first electronic signals encoding movement data meeting the precondition, send second electronic signals encoding movement data within a predetermined time period associated with the target time point to a remote server. |
| US11508235B2 |
Road lighting
Systems, devices, and methods are disclosed in which one or more light sources, a detector, a processor and a controller are configured such that light from the one or more light sources improves the ability of a human or automated motor vehicle driver to identify and avoid pedestrians. The one or more light sources may provide spot illumination to moving objects or pedestrians on a road surface, with the spot illumination following the moving object or pedestrians along the portion of the road surface. The one or more light sources may project images on the ground or on other surfaces. The light source may be carried by a pedestrian or on personal transport used by a pedestrian. The light sources may be stationary and provide lighting for a pedestrian street crossing. |
| US11508230B2 |
Methods and systems for automatically generating a remedial action in an industrial facility
Systems and methods of preventing an event occurrence or mitigating effects of an event occurrence in an industrial facility are disclosed herein. In some embodiments, a first input is received from a first sensor and, based at least in part on the first input, an initial action is automatically generated. In response to the initial action, a second input is received from a second sensor and, based at least in part of the received first and second inputs, a likelihood of an event occurrence is determined. Based at least in part of the determined likelihood, a remedial action configured to prevent the occurrence of the event occurrence is automatically generated. In some embodiments, the remedial action is generated in real-time and can be directed to a process condition, environmental condition, or secondary source. |
| US11508228B2 |
Systems, methods and devices for the rapid assessment and deployment of appropriate modular aid solutions in response to disasters
An embodiment of a disaster response system is disclosed that includes a communication and monitoring environment (CME). The CME includes an incident command infrastructure, and a communication infrastructure configured to exchange data with the incident command infrastructure. The communication infrastructure includes a network comprising a plurality of sensor assemblies that are configured to wirelessly communicate with the communication infrastructure. The sensor assemblies are configured to acquire data that includes at least one of environmental conditions, motion, position, chemical detection, and medical information. One or more of the sensors are configured to aggregate data from a subset of the plurality of sensors. The CME is configured to detect an incident based on at least the data acquired by the sensor assemblies. |
| US11508226B2 |
Inventory control system with integrated ID tags
The inventory control system process includes steps for printing a circuit to a sheet stock having at least one ID tag formed therewith such that the circuit is carried by the ID tag, assigning a unique identification code to the circuit associated with the ID tag, removing the ID tag carrying the circuit from the sheet stock, associating the removed ID tag with a product, and entering the product into an inventory control system secured in connection with a user account accessible only by an authorized user associated with the user account, for real-time location tracking of the product thereof by way of the circuit. |
| US11508224B2 |
Integrated security network
A security system architecture and method of operation that combines a local security network with control panel and sensors, a central monitoring station (CMS), and a separate operator computer server that provides a web portal for both the homeowner and CMS, that maintains a persistent connection between the control panel and CMS allowing failsafe dual-path signaling. This dual-path signaling technique is extended to provide an effective “smash and grab alarm”, and various approaches to dual-path signal management are disclosed including handshaking, persistent domain monitoring, relayed Operator 3-to-CMS signaling, etc. Improved processes for remotely accessing video are also disclosed along with an improved process for remote control panel configuration, and control panel interfacing with home automation appliances. |
| US11508214B2 |
Simulcast pari-mutuel gaming machine with casino and lottery styled wagers for continuous play
An gaming machine for and method of par-mutuel wagering that allows individuals to continuously place multiple casino and lottery styled pari-mutuel wagers on simulcast live and/or recorded pari-mutuel race events. The gaming machine includes a display screen to provide a graphic display of a plurality of pari-mutuel gaming options to a player, and a selection device operable by the player to select at least one of the pari-mutuel gaming options displayed on the screen, the selection device operable by the player to input a wager corresponding to the selected at least one pari-mutuel gaming option. The gaming machine has the ability to be linked to a network of gaming machines in pari-mutuel and/or other wagering venues. |
| US11508213B2 |
Enabling financial transactions for electronic gaming machines
A client device, a system and a method for enabling financial transactions for electronic gaming machines are described. The client device includes an electronic gaming machine processor, a printer, a printer sharing module, one or more wireless communication modules, a slot cabinet, a backend server, and a master gateway. The slot cabinet houses the electronic gaming machine, printer, and a wireless communications module. The electronic funds transfer terminal receives fund transfer requests from patrons and communicates the requests to an aggregator communicatively coupled to the backend server. The backend server in turn transmits the request to the master gateway that communicates with financial networks and maintains a database of transactions made through the client devices. The master gateway communicates transaction data related to the fund transfer request and the gaming limits and gaming rules to the backend server. Compliant transactions that are approved by the financial network(s) receive a corresponding voucher validation code. The voucher validation code is communicated to the electronic funds transfer terminal through the backend server and aggregator for printing at the printer of the slot cabinet and delivery to the patron. |
| US11508207B2 |
Methods and systems for controlling a graphical user interface in a live-casino environment
Methods and systems for controlling a graphical user interface in a live-casino environment are provided. The method comprises, at a plurality of remote electronic devices, each having a display apparatus and at least one user input device: displaying a graphical representation comprising a live video stream of a physical table game surface upon which a turn-based live casino game involving betting is played. The game surface has a plurality of player areas. The graphical representation further comprises a plurality of graphical player elements for each player area. The method includes determining which of the player areas is associated with each remote electronic device, and for each launch of a game cycle of the live casino game, updating the graphical representation on each display apparatus. And digitally zooming in on one predefined area of the game surface based on the determined associated player area for the individual remote electronic device. |
| US11508206B2 |
Gaming system and method which enables multiple players to simultaneously play multiple individual games or group games on a central display
The present disclosure provides a gaming system including a central controller, a central display which includes a plurality of display segments and a plurality player stations. The display segments are configured to each separately display one of a plurality of games, to co-act to display a plurality of games, or to co-act to display one game. Each player station is configured to enable a player to play one or more of the games displayed by the display segments. The gaming system enables a plurality of players to play a group game on the central display, a plurality of players to simultaneously play multiple group games on the central display, and a plurality of players to each simultaneously play multiple individual games on the central display. |
| US11508203B2 |
Electrical computers and digital processing systems involving interprogram or interprocess communication regarding amusement devices and games
Some embodiments may include interaction among sports books. Various other systems and methods are described. |
| US11508202B1 |
Modular display and dispensing system
A modular display and dispensing assembly for the sale of items, includes a base adapted to be securely mounted to a substrate at a prescribed display and dispensing location on the substrate; and at least one display and dispensing module for mounting on the base, each display and dispensing module including a housing for mounting on the base, and a drawer for holding the items for sale, the drawer adapted to be removably positioned and secured in the housing for dispensing the items for sale while the drawer is secured in the housing, each drawer including a first lengthwise divider for varying at least one widthwise compartment size in the drawer and a second widthwise divider for varying at least one lengthwise compartment size in the drawer, for holding different size items for sale. |
| US11508201B2 |
Bucket and vending machine
Disclosed is a bucket applied in a vending machine, including a bucket body, a first driving mechanism and a second driving mechanism. The bucket body includes an inner cavity and two ports in communication with the inner cavity respectively. The two ports are arranged at an interval in a first preset direction. The first driving mechanism and the second driving mechanism are arranged at an interval in the bucket body in a second preset direction, and are respectively configured to detachably mate with a dispensing assembly of a storage column of the vending machine, to provide power to the dispensing assembly. Also disclosed is a vending machine including multiple storage columns and the aforementioned bucket. |
| US11508197B2 |
Secure transport container
An apparatus includes a controller configured to initiate attachment of a first locking bar of a transport container to a first anchor point of a structure by adjusting the first locking bar from a first unlocked state to a first locked state. The controller is also configured to confirm a locking of the first locking bar to the first anchor point. The controller is further configured to, in response to confirming the locking, initiate a release of a second locking bar of the transport container from a second anchor point by adjusting the second locking bar from a second locked state to a second unlocked state. |
| US11508191B1 |
Vehicle diagnostic interface device
A vehicle interface device for diagnosing, scanning and programming an electrical system of a vehicle having a housing and being connectable to an electrical system of a vehicle, a local diagnostic computer, and a remote diagnostic computer. The vehicle interface device is selectively switchable for operation in either a local mode or a remote mode. In the local mode, the vehicle interface device is connected with the local diagnostic computer and operates as a pass-thru device. In the remote mode, the vehicle interface device is connected with the remote diagnostic computer. |
| US11508187B2 |
Pupil detection device
A pupil detection device includes: a filter weight learner configured to generate a target image on the basis of pupil coordinate data acquired from a learning image and learn weights of a plurality of filters in order to generate a filtered image, by filtering the learning image using the plurality of filters, that is within a predetermined reference range of the target image; a split image generator configured to generate a pupil region split image for an input image using the plurality of filters having the learned weights; and a pupil coordinate detector configured to remove noise of the pupil region split image, select at least one of a plurality of pixels from which noise is removed, and detect pupil coordinates. |
| US11508185B2 |
Method and system for collecting facial recognition data
A method for collecting facial recognition data includes: locating a first face area from an Nth image frame; extracting a first facial feature defined with S factors; acquiring a second facial feature extracted from a second face area shown in an (N−1)th image frame at a corresponding position; determining whether the first face area is relevant to the second face area, and assigning to the first face area a tracing code; determining whether to store the first facial feature according to a similarity level of the first facial feature to existent data; storing and inputting the first facial feature into a neural network to generate an adjusted feature defined with T factors if the similarity level of the first facial feature to the existent data is not lower than a preset level, wherein T is not smaller than S; acquiring adjusted data generated by inputting the existent data into the neural network; determining whether the person is a registered one according to a similarity level of the adjusted feature to adjusted data; and using the stored first facial feature for training the neural network if the person is a registered one. |
| US11508183B2 |
Biometric information authentication device
A biometric information authentication device includes an authentication unit to change an authentication threshold value used for authentication to increase difficulty of authentication when authentication of biometric information by checking against registered biometric information is unsuccessful a predetermined number of times. |
| US11508182B2 |
Electronic circuit having fingerprint sensing function and method for sensing fingerprint image
An electronic circuit adapted to drive a panel including a plurality of fingerprint sensing zones is provided. The electronic circuit includes a fingerprint sensing circuit. The fingerprint sensing circuit is configured to determine at least two fingerprint sensing zones to perform a fingerprint sensing operation according to a touch area and receive a fingerprint sensing signal corresponding to fingerprint sensing data from the at least two fingerprint sensing zones. The fingerprint sensing circuit rearranges the fingerprint sensing data from the at least two fingerprint sensing zones. In addition, an electronic device and a method for sensing a fingerprint image are also provided. |
| US11508179B2 |
Electronic device, fingerprint image processing method and related products
Provided is an electronic device. The electronic device includes a screen provided with a first polarizer, a second polarizer arranged below the screen, and an optical fingerprint identification module arranged below the second polarizer. The polarization direction of the first polarizer is the same with the polarization direction of the second polarizer. The first polarizer and the second polarizer are configured to filter a first optical noise. The second polarizer is configured to filter a second optical noise. The first optical noise is light from screen light of the screen and directing to the optical fingerprint recognition module. The second optical noise is light from the screen light, directing away from the optical fingerprint recognition module and reflected by a glass cover on an outer side of the screen. |
| US11508178B2 |
Fingerprint sensor and display device including the same
A fingerprint sensor includes a substrate, a sensor pixel disposed on the substrate and including a light sensing element through which a sensing current flows according to an amount of incident light, a light-blocking conductive layer disposed on the sensor pixel and including a plurality of holes, a first fingerprint pad disposed on the substrate, and a conductive connector connected to the first fingerprint pad and to which a predetermined voltage is applied. The light-blocking conductive layer is electrically connected to the conductive connector. |
| US11508176B2 |
Display substrate and method for manufacturing the same, display apparatus
A display substrate having a fingerprint recognition region includes an array substrate, and a light shielding layer disposed at a side of the array substrate and at least located in the fingerprint recognition region. The material of the light shielding layer is an insulating material. A portion of the light shielding layer located in the fingerprint recognition region is provided with a plurality of light transmission holes, and each of the plurality of light transmission holes is configured to provide a transmission channel for fingerprint imaging light. |
| US11508175B2 |
Electronic device
An electronic device includes a display panel including a base substrate and a plurality of pixels disposed on a front surface of the base substrate to display an image, a cover panel in which an opening part is defined, a fingerprint sensor spaced by a predetermined gap from the cover panel and accommodated in the opening part, and an adhesive member accommodated in the opening part and disposed between the fingerprint sensor and the display panel, and the opening part includes a side surface having a step. |
| US11508172B2 |
Identifying location of shreds on an imaged form
Disclosed herein is a machine learning application for automatically reading filled-in forms. There are multiple steps involved in using a computer to accurately read a handwritten form. First, the system identifies the form. Second, the system identifies what parts of the form are important. Third, the important parts are extracted as image data (known as shreds). Finally, fourth, the system interprets the shreds. This application is focused on steps two and three of that overall process. The disclosed techniques relate to training a machine learning system on a given series of forms such that when provided future filled-in forms within that series, the system is able to extract the portions of the filled-in form that are important/relevant. |
| US11508171B2 |
Dynamic detection of cross-document associations
Systems and methods are configured to generate a set of related document objects for a predictive entity and/or to generate an optimal document sequence for a set of related document objects. In one embodiment, a set of related document objects for a predictive entity is generated by processing entity metadata features associated with the predictive entity using an entity-document correlation machine learning model, and an optimal document sequence is generated for the set of related document objects by processing the set of related document objects using a document sequence optimization machine learning model. |
| US11508170B2 |
Digital handwriting synthesis
Digital handwriting synthesis techniques and systems are described that are configured to process text represented using text fields into one or more digital ink strokes to represent the text as handwritten data when rendered in a user interface of a computing device. Additionally, the digital handwriting synthesis techniques are configurable using normalization parameters to adjust an output from a machine learning model such that these techniques are extensible across a wide range of machine learning models and may be used to support a wide range of different digital ink styles. Further, the techniques described herein also support customization via “few shot conditioning” in which the digital ink styles may be further customized based on a user input and in this way support previously unseen digital ink styles. |
| US11508169B2 |
System and method for synthetic image generation with localized editing
Embodiments described herein provide a system for generating synthetic images with localized editing. During operation, the system obtains a source image and a target image for image synthesis and selects a semantic element from the source image. The semantic element indicates a semantically meaningful part of an object depicted in the source image. The system then determines the style information associated with the source and target images. Subsequently, the system generates a synthetic image by transferring the style of the semantic element from the source image to the target image based on the feature representations. In this way, the system can facilitate localized editing of the target image. |
| US11508167B2 |
Convex representation of objects using neural network
Methods, systems, and apparatus including computer programs encoded on a computer storage medium, for generating convex decomposition of objects using neural network models. One of the methods includes receiving an input that depicts an object. The input is processed using a neural network to generate an output that defines a convex representation of the object. The output includes, for each of a plurality of convex elements, respective parameters that define a position of the convex element in the convex representation of the object. |
| US11508160B2 |
Vehicular vision system
A vehicular vision system includes an electronic control unit (ECU) and at least one exterior viewing camera. The camera connects with the ECU via a coaxial cable. Image data captured by the camera is converted at a serializer to serialized image data that is carried to the ECU via the coaxial cable. The serialized image data carried to the ECU by the coaxial cable is de-serialized at the de-serializer of the ECU to form de-serialized image data. Responsive at least in part to processing at the ECU of de-serialized image data, the vehicular vision system is operable to detect an object viewed by the camera. Responsive at least in part to determination by the vehicular vision system that the equipped vehicle and the detected object may collide, the vehicular vision system, at least in part, controls a braking system of the equipped vehicle. |
| US11508156B2 |
Vehicular vision system with enhanced range for pedestrian detection
A vision system for a vehicle includes a camera and an electronic control unit (ECU) with an image processor. The ECU generates a reduced resolution frame of captured image data and the ECU determines a reduced resolution detection result based on pedestrian detection using the reduced resolution frame of captured image data. The ECU, responsive to processing by the image processor of image data, generates a cropped frame of captured image data and the ECU determines a cropped detection result based on pedestrian detection using the cropped frame of captured image data. Responsive to determining the reduced resolution detection result and determining the cropped detection result, the ECU merges the reduced resolution detection result and the cropped detection result into a final pedestrian detection result. The final pedestrian detection result is indicative of presence of a pedestrian within the field of view of the camera. |
| US11508153B2 |
Method for generating tag of video, electronic device, and storage medium
A method for generating a tag of a video, an electronic device, and a storage medium are related to a field of natural language processing and deep learning technologies. The detailed implementing solution includes: obtaining multiple candidate tags and video information of the video; determining first correlation information between the video information and each of the multiple candidate tags; sorting the multiple candidate tags based on the first correlation information to obtain a sort result; and generating the tag of the video based on the sort result. |
| US11508152B2 |
Methods and systems for evaluating the capacity of a container
Empowered by augmented reality (AR) technologies, the present disclosure allows a user to display virtual content in a physical reality and turn an AR-ready handheld mobile device into a dimension measuring tool. The present disclosure allows the user to first display a virtual container asset, with its actual size in physical reality, in any given configuration, and then create a virtual dimensional equivalent of an item-to-be-fit based on dimensional data captured by a 6-degree-of-freedom (6DoF) device or the like. Finally, the user can place the virtual item into the virtual container to evaluate the capacity and fit in the given configuration. |
| US11508145B2 |
Method for evaluating environmental noise of device, apparatus, medium and electronic device
The present disclosure provides a method, apparatus, medium, and electronic device for evaluating environmental noise of device. The method comprises obtaining original image data to be displayed; determining at least part of the original image data to be displayed as source data; obtaining comparison data according to the source data; obtaining a difference value according to the comparison data and the source data; and evaluating environmental noise of device according to the difference value. |
| US11508143B2 |
Automated salience assessment of pixel anomalies
According to one implementation, a system for performing automated salience assessment of pixel anomalies includes a computing platform having a hardware processor and a system memory storing a software code. The hardware processor is configured to execute the software code to analyze an image for a presence of a pixel anomaly in the image, obtain a salience criteria for the image when the analysis of the image detects the presence of the pixel anomaly, and classify the pixel anomaly as one of a salient anomaly or an innocuous anomaly based on the salience criteria for the image. The hardware processor is further configured to execute the software code to disregard the pixel anomaly when the pixel anomaly is classified as an innocuous anomaly, and to flag the pixel anomaly when the pixel anomaly is classified as a salient anomaly. |
| US11508139B2 |
Information processing apparatus and non-transitory computer readable medium
An information processing apparatus includes a processor configured to extract a mark specified in advance from an image of a document; and acquire a character string by performing character recognition on a region located in a particular direction with respect to a position of the mark, the direction being associated in advance with the mark. |
| US11508138B1 |
Systems and methods for a 3D home model for visualizing proposed changes to home
The following relates generally to light detection and ranging (LIDAR) and artificial intelligence (AI). In some embodiments, a system: receives LIDAR data generated from a LIDAR camera; measures a plurality of dimensions of a room of the home based upon processor analysis of the LIDAR data; builds a 3D model of the room based upon the measured plurality of dimensions; receives an indication of a proposed change to the room; modifies the 3D model to include the proposed change to the room; and displays a representation of the modified 3D model. |
| US11508137B2 |
Storage medium storing information processing program, information processing apparatus, information processing system, and information processing method for enlarging/reducing an object in a virtual space
A three-dimensional object for which three orthogonal object axes are set is disposed in a virtual space. One or two of the three object axes are determined as an enlargement/reduction axis, based on an orientation of the three-dimensional object in the virtual space. A user's operation input is associated with the enlargement/reduction axes. The three-dimensional object is at least enlarged or reduced based on the association of the user's operation input with the enlargement/reduction axes. |
| US11508136B2 |
Collaborative augmented reality
Augmented reality presentations are provided at respective electronic devices. A first electronic device receives information relating to modification made to an augmented reality presentation at a second electronic device, and the first electronic device modifies the first augmented reality presentation in response to the information. |
| US11508135B2 |
Augmented reality content generators including 3D data in a messaging system
The subject technology selects a set of augmented reality content generators from available augmented reality content generators, the selected set of augmented reality content generators comprising at least one augmented reality content generator for applying a three-dimensional (3D) effect. The subject technology causes display of a carousel interface including selectable graphical items, each selectable graphical item corresponding to a respective augmented reality content generator. The subject technology receives a selection of a first selectable graphical item from the selectable graphical items, the first selectable graphical item including a first augmented reality content generator for applying a first 3D effect. The subject technology applies, to first image data and first depth data, the first augmented reality content generator corresponding to the selected first selectable graphical item. The subject technology generates a message including the applied first augmented reality content generator to the first image data and the first depth data. |
| US11508134B2 |
Augmented reality display device and augmented reality display method
An augmented reality (AR) display device includes a camera that captures a background image; a distance measuring sensor that measures a distance to a real object in the background image; a position and orientation sensor that detects the position of the camera and the shooting direction of the camera; a controller that recognizes the real object from the background image captured by the camera and associates the predetermined AR object with the recognized real object; a display displaying an image of the associated AR object; and a memory that stores data of the real object and the AR object associated with each other. The controller determines whether or not the real object is movable from the measurement result of the distance measuring sensor, and arranges the AR object according to the current position of the real object when the position of the real object associated with the AR object moves. |
| US11508131B1 |
Generating composite stereoscopic images
A system, method or compute program product for generating composite images. One of the systems includes a capture device to capture an image of a physical environment; and one or more storage devices storing instructions that are operable, when executed by one or more processors of the system, to cause the one or more processors to: obtain an image of the physical environment as captured by the capture device, identify a visually-demarked region on a surface in the physical environment as depicted in the image, process the image to generate a composite image of the physical environment that includes a depiction of a virtual object, wherein a location of the depiction of the virtual object in the composite image is based on a location of the depiction of the visually-demarked region in the image, and cause the composite image to be displayed for a user. |
| US11508124B2 |
Throttling hull shaders based on tessellation factors in a graphics pipeline
A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive launch time interval of the domain shader and a hull shader latency. In some cases, the throttling circuitry includes a first counter that is incremented in response to launching a thread group from the buffer and a second counter that modifies the first counter based on a measured latency of the domain shader. |
| US11508122B2 |
Bounding box estimation and object detection
Disclosed are techniques for estimating a 3D bounding box (3DBB) from a 2D bounding box (2DBB). Conventional techniques to estimate 3DBB from 2DBB rely upon classifying target vehicles within the 2DBB. When the target vehicle is misclassified, the projected bounding box from the estimated 3DBB is inaccurate. To address such issues, it is proposed to estimate the 3DBB without relying upon classifying the target vehicle. |
| US11508117B1 |
Extended reality space generating apparatus and method
An extended reality space generating apparatus and method are provided. The extended reality space generating apparatus generates a plurality of plane plates, a plate coordinate and a normal vector corresponding to each of the plane plates based on a plurality of point clouds, wherein the point clouds correspond to a real space. The extended reality space generating apparatus compares the plate coordinates and the normal vectors of the plane plates in a visual window to generate an effective plane plate set. The extended reality space generating apparatus generates an extended reality space corresponding to the real space based on the effective plane plate set. |
| US11508116B2 |
Method and system for automated camera collision and composition preservation
There is described herein systems and methods for camera colliders and shot composition preservation within a 3D virtual environment that prevent a virtual procedural camera from getting stuck behind an object, or penetrating into an object, when filming a subject, while at the same time also maintaining the screen composition of the subject in the camera shot. |
| US11508115B2 |
Quotidian scene reconstruction engine
A stored volumetric scene model of a real scene is generated from data defining digital images of a light field in a real scene containing different types of media. The digital images have been formed by a camera from opposingly directed poses and each digital image contains image data elements defined by stored data representing light field flux received by light sensing detectors in the camera. The digital images are processed by a scene reconstruction engine to form a digital volumetric scene model representing the real scene. The volumetric scene model (i) contains volumetric data elements defined by stored data representing one or more media characteristics and (ii) contains solid angle data elements defined by stored data representing the flux of the light field. Adjacent volumetric data elements form corridors, at least one of the volumetric data elements in at least one corridor represents media that is partially light transmissive. The constructed digital volumetric scene model data is stored in a digital data memory for subsequent uses and applications. |
| US11508112B2 |
Early release of resources in ray tracing hardware
Techniques are disclosed for improving the throughput of ray intersection or visibility queries performed by a ray tracing hardware accelerator. Throughput is improved, for example, by releasing allocated resources before ray visibility query results are reported by the hardware accelerator. The allocated resources are released when the ray visibility query results can be stored in a compressed format outside of the allocated resources. When reporting the ray visibility query results, the results are reconstructed based on the results stored in the compressed format. The compressed format storage can be used for ray visibility queries that return no intersections or terminate on any hit ray visibility query. One or more individual components of allocated resources can also be independently deallocated based on the type of data to be returned and/or results of the ray visibility query. |
| US11508111B1 |
Augmented reality shader programs
A computer-implemented method, including receiving, through an editor for designing augmented-reality effects, a plurality of shader programs each for an augmented-reality to be rendered for an augmented-reality effect; compiling each of the shader programs of augmented-reality object separately into corresponding shader modules; generate a merged shader module based on the shader modules; analyzing, according to one or more criteria, the merged shader module to identify fragment-shader instructions and vertex-shader instructions; splitting the merged shader module into a single fragment-shader module comprising the identified fragment-shader instructions and a single vertex-shader module comprising the identified vertex-shader instructions; and providing the single fragment-shader module and the single vertex-shader module to a graphics processing unit (GPU) to render the augmented-reality objects. |
| US11508110B2 |
System and method for efficient multi-GPU rendering of geometry by performing geometry analysis before rendering
A method for graphics processing. The method including rendering graphics for an application using graphics processing units (GPUs). The method including dividing responsibility for processing a plurality of pieces of geometry of an image frame during an analysis pre-pass phase of rendering between the plurality of GPUs, wherein each of the plurality of pieces of geometry is assigned to a corresponding GPU. The method including determining in the analysis pre-pass phase overlap of each the plurality of pieces of geometry with each of a plurality of screen regions. The method including generating information at the plurality of GPUs regarding the plurality of pieces of geometry and their relations to the plurality of screen regions based on the overlap of each the plurality of pieces of geometry with each of the plurality of screen regions. The method including assigning the plurality of screen regions to the plurality of GPUs based on the information for purposes of rendering the plurality of pieces of geometry during a subsequent phase of rendering. |
| US11508108B2 |
Method for simulating fluids interacting with submerged porous materials
A method for generating one or more visual representations of a porous media submerged in a fluid is provided. The method can be performed using a computing device operated by a computer user or artist. The method includes defining a field comprising fluid parameter values for the fluid, the fluid parameter values comprising fluid velocity values and pore pressures. The method includes generating a plurality of particles that model a plurality of objects of the porous media, the plurality of objects being independently movable with respect to one another, determining values of motion parameters based at least in part on the field when the plurality of particles are submerged in the fluid, buoyancy and drag forces being used to determine relative motion of the plurality of particles and the fluid, and generating the one or more visual representations of the plurality of objects submerged in the fluid based on the values of the motion parameters. |
| US11508107B2 |
Additional developments to the automatic rig creation process
The disclosure provides methods and systems for automatically generating an animatable object, such as a 3D model. In particular, the present technology provides fast, easy, and automatic animatable solutions based on unique facial characteristics of user input. Various embodiments of the present technology include receiving user input, such as a two-dimensional image or three-dimensional scan of a user's face, and automatically detecting one or more features. The methods and systems may further include deforming a template geometry and a template control structure based on the one or more detected features to automatically generate a custom geometry and custom control structure, respectively. A texture of the received user input may also be transferred to the custom geometry. The animatable object therefore includes the custom geometry, the transferred texture, and the custom control structure, which follow a morphology of the face. |
| US11508103B2 |
Matched array general talent architecture system and method
A matched array technology system and method for displaying in a two-dimensional array the structured interactions between management and a plurality of employees in an organization. Axes contain proxy values of employee and manager expectations scaled to yield a matched array and an alignment vector containing cells representing target alignment between employee and manager expectations. A scatter plot of multiple employee positions portrays the pattern of talent alignment and distribution, representing the talent architecture for the organization. The talent architecture is characterized by multiple static and dynamic metrics that identify normative opportunities to improve organization alignment, and measure organization talent management performance, especially in relation to the reference and general alignment vectors of the array. |
| US11508101B2 |
Dynamic dual-tracer PET reconstruction method based on hybrid-loss 3D convolutional neural networks
This present invention discloses a dynamic dual-tracer PET reconstruction method based on a hybrid-loss 3D CNN, which selects a corresponding 3D convolution kernel for a 3D format of dual-tracer PET data, and performs feature extraction in a stereoscopic receptive field (down-sampling) and the reconstruction (up-sampling) process, which accurately reconstructs the three-dimensional concentration distributions of two different tracers from the dynamic sinogram. The method of the invention can better reconstruct the simultaneous-injection single-acquisition dual-tracer sinogram without any model constraints. The scanning time required for dual-tracer PET can be minimized based on the method of the present invention.Using this method, the raw sinogram data of dual tracers can be reconstructed into two volumetric individual images in a short time. |
| US11508095B2 |
Hierarchical point cloud compression with smoothing
A system comprises an encoder configured to compress attribute information for a point cloud and/or a decoder configured to decompress compressed attribute for the point cloud. To compress the attribute information, multiple levels of detail are generated based on spatial information. Also, attribute values are predicted based on the level of details. A decoder follows a similar prediction process based on level of details. Also, attribute correction values may be determined to correct predicted attribute values and may be used by a decoder to decompress a point cloud compressed using level of detail attribute compression. In some embodiments, an update operation is performed to smooth attribute correction values taking into account an influence factor of respective points in a given level of detail on attributes in other levels of detail. |
| US11508094B2 |
Point cloud compression
A system comprises an encoder configured to compress attribute information and/or spatial for a point cloud and/or a decoder configured to decompress compressed attribute and/or spatial information for the point cloud. To compress the attribute and/or spatial information, the encoder is configured to convert a point cloud into an image based representation. Also, the decoder is configured to generate a decompressed point cloud based on an image based representation of a point cloud. In some embodiments, an encoder may be configured to further compress points omitted from the image based representation. Also, in some embodiments, a decoder may be configured to decode points compressed outside of an image based representation or in a separate image based representation. |
| US11508093B2 |
Screen coding methods and systems based on mass center coincidence
A screen coding method and system based on mass center coincidence. The screen coding method based on mass center coincidence includes: constructing a plurality of coding unit models composed of a combination of a plurality of geometric figures with coincident mass centers, where vertices of the geometric figures do not coincide; and filling in data information to each vertex of the coding unit models according to a method of data information arrangement of a plurality of data combinations to generate a coding unit so as to implement different data lengths of the same coding unit. As such, a data length of the coding unit can be controlled, so that when more data needs to be coded, the overall size of the coding unit does not need to be changed, which greatly improves coding efficiency. |
| US11508092B2 |
Edge-based crop yield prediction
Implementations are described herein for edge-based real time crop yield predictions made using sampled subsets of robotically-acquired vision data. In various implementations, one or more robots may be deployed amongst a plurality of plants in an area such as a field. Using one or more vision sensors of the one or more robots, a superset of high resolution images may be acquired that depict the plurality of plants. A subset of multiple high resolution images may then be sampled from the superset of high resolution images. Data indicative of the subset of high resolution images may be applied as input across a machine learning model, with or without additional data, to generate output indicative of a real time crop yield prediction. |
| US11508089B2 |
LiDAR assisted wheel encoder to camera calibration
A method of wheel encoder to camera calibration, including receiving a LiDAR (Light Detection and Ranging) signal, receiving a camera signal, receiving a wheel encoder signal, calibrating the camera signal to the LiDAR signal, calibrating the wheel encoder signal to the LiDAR signal and calibrating the camera signal to the wheel encoder signal based on the calibration of the camera signal to the LiDAR signal and the wheel encoder signal to the LiDAR signal. |
| US11508085B2 |
Display systems and methods for aligning different tracking means
A display system including: display apparatus; display-apparatus-tracking means; input device; processor. The processor is configured to: detect input event and identify actionable area of input device; process display-apparatus-tracking data to determine pose of display apparatus in global coordinate space; process first image to identify input device and determine relative pose thereof with respect to display apparatus; determine pose of input device and actionable area in global coordinate space; process second image to identify user's hand and determine relative pose thereof with respect to display apparatus; determine pose of hand in global coordinate space; adjust poses of input device and actionable area and pose of hand such that adjusted poses align with each other; process first image, to generate extended-reality image in which virtual representation of hand is superimposed over virtual representation of actionable area; and render extended-reality image. |
| US11508077B2 |
Method and apparatus with moving object detection
A processor-implemented method of detecting a moving object includes: estimating a depth image of a current frame; determining an occlusion image of the current frame by calculating a depth difference value between the estimated depth image of the current frame and an estimated depth image of a previous frame; determining an occlusion accumulation image of the current frame by adding a depth difference value of the occlusion image of the current frame to a depth difference accumulation value of an occlusion accumulation image of the previous frame; and outputting an area of a moving object based on the occlusion accumulation image. |
| US11508075B2 |
Method and apparatus for tracking target
Disclosed are target tracking methods and apparatuses. The target tracking apparatus performs target tracking on an input image obtained in a first time period within a single time frame, using a light neural network in a second time period of the single time frame. The target tracking apparatus may perform target tracking on input images generated within the same time frame. |
| US11508073B2 |
Method for determining angle of tips of ripper shanks in dozer machines
A method for determining an angle of a tip of a ripper shank includes a controller receiving an input command. The controller estimates an angle of the tip based on one or more parameters of the input command. Further, the controller acquires a video feed of the ripper shank and detects an object in the video feed. The controller identifies the object as one of the ripper shank or a component movable with a movement of the ripper shank based on a match of a color of the object to a predefined color and a match of a profile of the object to a predefined profile. The controller co-relates the profile to an angular value in a map table and sets the angular value to be an actual angle of the tip over the angle of the tip estimated based on the input command. |
| US11508069B2 |
Method for processing event data flow and computing device
The present disclosure provides a method for processing an event data flow and a computing device. The method includes: reading a plurality of pieces of event data with a first duration sequentially from the event data flow; with respect to each piece of event data with the first duration, analyzing the event data to acquire time-difference information about each event within the first duration; and generating an image frame presenting a change in movement within the first duration in accordance with the time-difference information about each event within the first duration. |
| US11508066B2 |
Systems and methods to process electronic images for continuous biomarker prediction
Systems and methods are disclosed for processing digital images to predict at least one continuous value comprising receiving one or more digital medical images, determining whether the one or more digital medical images includes at least one salient region, upon determining that the one or more digital medical images includes the at least one salient region, predicting, by a trained machine learning system, at least one continuous value corresponding to the at least one salient region, and outputting the at least one continuous value to an electronic storage device and/or display. |
| US11508064B2 |
Computer-readable recording medium having stored therein information processing program, method for processing information, and information processing apparatus
A method includes: acquiring a training data set including pieces of training data, each of the pieces including an image of a training target, first annotation data representing a rectangular region in the image, and second annotation data; training, based on the image and the first annotation data, an object detection model specifying a rectangular region including the training target; training, based on the image and the second annotation data, a neural network; and calculating a first index value related to a relationship of a pixel number, the trained estimation model and the calculated first index value being used in a determination process that determines, based on the calculated first index value and a second index value relationship between a pixel number in an output result and an estimation result, whether or not a target in a target image is normal. |
| US11508061B2 |
Medical image segmentation with uncertainty estimation
Systems and methods for generating a segmentation mask of an anatomical structure, along with a measure of uncertainty of the segmentation mask, are provided. In accordance with one or more embodiments, a plurality of candidate segmentation masks of an anatomical structure is generated from an input medical image using one or more trained machine learning networks. A final segmentation mask of the anatomical structure is determined based on the plurality of candidate segmentation masks. A measure of uncertainty associated with the final segmentation mask is determined based on the plurality of candidate segmentation masks. The final segmentation mask and/or the measure of uncertainty are output. |
| US11508057B2 |
Inspection system and method for vehicle underbody
An inspection system for a vehicle underbody in an in-line process includes: a vehicle recognition unit for acquiring a vehicle ID by recognizing a vehicle entering an inspection process; a vision system that photographs the vehicle underbody through a plurality of cameras disposed under a vehicle moving direction (Y-axis) and disposed at vertical and diagonal angles along a width direction (X-axis) of the vehicle; and an inspection server that detects assembly defects of a component by performing at least one of a first vision inspection that matches an object image for each component through a rule-based algorithm or a secondary deep-learning inspection through a deep-learning engine by acquiring a vehicle underbody image photographed by operating the vision system with setting information suitable for a vehicle type and a specification according to the vehicle ID. |
| US11508052B2 |
Systems and methods for quantifying light flares in images
Systems, methods, and computer-readable media are disclosed for identifying light flares in images. An example method may involve receiving an image from an imaging device, the image including data indicative of a flare artifact originating from a region of the image. The example method may also involve determining, based on the image data, a first array of pixels extending radially outwards from the region and a second array of pixels extending radially outwards from the region. The example method may also involve creating, based on the image data, a flare array, the flare array including the first array of pixels and the second array of pixels. The example method may also involve determining, based on the flare array, a peak flare artifact value indicative of a size of the flare artifact. The example method may also involve determining, based on the peak flare artifact value, a flare artifact score for the imaging device. |
| US11508036B2 |
Image processing apparatus and image processing method for decoding raw image data encoded with lossy encoding scheme
An image processing apparatus decodes encoded RAW data that includes subband data being encoded with lossy encoding scheme, and determines one of a plurality of classifications based on the decoded subband data, wherein the plurality of classifications are based on a feature of an image. The apparatus also obtains correction data corresponding to the determined classification, and corrects recomposed data, which is obtained by applying frequency recomposition to the decoded subband data, based on the correction data, in order to obtain the corrected data as decoded RAW data. |
| US11508035B2 |
Image retargeting method and device
A method for controlling an electronic device is provided. The method includes obtaining an intermediate image by preprocessing an original image, obtaining a saliency feature map of the intermediate image by performing semantic saliency analysis on the intermediate image, performing adaptability calculation according to the saliency feature map and a retargeted target equipment condition, and determining a retargeting mode of the original image according to the result of the adaptability calculation, and performing retargeting processing on the original image according to the determined mode. |
| US11508027B2 |
Methods and apparatus to perform symbol-based watermark detection
An example symbol-based watermark detection method disclosed herein includes, in response to a comparison of a first count of occurrences of a first potential symbol value corresponding to a first symbol within a watermark and a second count of occurrences of a second potential symbol value corresponding to the first symbol, (i) determining a first accumulated signal to noise ratio value corresponding to the occurrences of the first potential symbol value, (ii) determining a second accumulated signal to noise ratio value corresponding to the occurrences of the second potential symbol value, and (iii) selecting one of the first or the second potential symbol value having a greatest accumulated signal to noise ratio value as a likely symbol value for the first symbol. The example method also includes concatenating the likely symbol value with other likely symbol values corresponding to other symbols of the watermark to detect the watermark. |
| US11508026B2 |
System for navigating transportation service providers to fulfill transportation requests authorized by an organization
In one embodiment a first transportation request is received from a computing device of a member of an organization. It is determined that the first transportation request is authorized according to preapproval criteria associated with a travel account of the member of the organization, wherein the travel account is funded by the organization. The first transportation request is communicated to a transportation service provider to service the transportation request. |
| US11508025B1 |
System and method for updating data for computing devices included in an aircraft
A data updating system for computing devices included in an aircraft, wherein one computing device in a first group of computing devices is, and one other computing device in a second group of computing devices is not, when the data of the computing device is updated, liable to affect the safety of the operator carrying out the maintenance on the aircraft. The system includes a data loading device, a connection connecting the data loading device with the computing device in the second group, and a data router connected to the data loading device, the data router transferring updating data to the computing devices in the first group only when a command by an operator in the cockpit of the aircraft is detected. |
| US11508024B2 |
System and method of identity verification
A system and method of verifying the identity of a user or registrant. The user or registrant provides identification information and registration information. The identification information may be a visual representation of an identifying item associated with location information. In some embodiments, the identification information may be a visual representation of a government issued identity. An identification module verifies the identification information and compares the verified identification information to the registration information. |
| US11508020B2 |
Method for operating a power consumption metering system and power consumption metering system
A method for operating a power consumption metering system and a power consumption metering system are disclosed. In an embodiment a method include measuring, by a sensor deployed at a monitored site, high speed power consumption values over time to obtain a high speed value pattern of power consumption with a resolution of more than 1000 values per second, determining one or more harmonics of the high speed value pattern, measuring, by the sensor, low speed power consumption values over time to obtain a low speed value pattern of the power consumption with a resolution of less than 100 values per second, providing the harmonics and the low speed value pattern to a cloud based data processing system and identifying a status of a power consumer of the monitored site dependent on the measured harmonics and the low speed value pattern. |
| US11508018B2 |
Work information management system and work information management method
The present invention comprises: a wearable sensor that is worn by a worker, the wearable sensor having a sensor that receives sensor data from a sensing object, and a transmitter that transmits to a terminal the sensor data received by the sensor; and a computer that determines operation content for the worker on the basis of the sensor data received from the wearable sensor, and outputs the result of the determination to a display unit. |
| US11508013B2 |
Systems and methods for pet insurance underwriting, rating, adjustments, and enrollment
Systems and methods for pet insurance enrollment, adjustment, and utilization are provided herein. In some embodiments, one or more pet insurance offerings and a pet insurance enrollment process are available to a user through a mobile application on a mobile computing device. In some embodiments, a preliminary premium rate is calculated based on background information provided by a user through the mobile application. In some embodiments, a pet tracker forms a portion of the system, and an adjusted premium rate can be calculated based on pet monitoring data received directly or indirectly from the pet tracker. In some embodiments, pet monitoring data acquired from a plurality of pet trackers are used to develop, inform, and refine one or more pet insurance actuarial models. |
| US11508012B2 |
System and method for generating proactive underwriting offers using social media data
Pursuant to some embodiments, systems, methods, apparatus and computer program code for proactive underwriting are provided. Pursuant to some embodiments, a computer implemented processing method is provided which includes identifying, by an insurance processing platform, an action by an entity that matches at least a first trigger rule. A proactive underwriting template is selected based on the at least first trigger rule, where the proactive underwriting template defines a number of data items required to complete the proactive underwriting template. The insurance processing platform is operated to automatically collect data associated with the plurality of required data items, and to perform a proactive underwriting analysis using the collected data. An underwriting determination is then rendered based on the proactive underwriting analysis. |
| US11508010B2 |
Automatic assignment of locations to mobile units via a back-end application computer server
A back-end application computer server may access a location data store containing information about a set of locations to be visited, including location identifiers and location coordinates. The computer server may then prioritize the locations to be visited. A mobile unit data store may contain information about a set of mobile units, including mobile unit identifiers, mobile unit location coordinates, and mobile unit communication addresses. The computer server may then automatically assign each location to a mobile unit based on the location coordinates, the mobile unit location coordinates, at least one geo-fence, and said prioritization. Indications of assigned locations may be transmitted to each mobile unit via the associated mobile unit communication address, and electronic messages may be exchanged to support an interactive user interface display associated with assignments of locations to mobile units. According to some embodiments, the back-end computer server facilitates collection of location information from mobile devices. |
| US11508008B2 |
Apparatus and methods for detection, monitoring, and delay in a computer network
Computing apparatus detects and monitors rapid changes in a computer network. The computing apparatus implements delays and other actions to ameliorate potentially adverse effects in the computer network caused by such changes. |
| US11508007B2 |
System and method for identifying vehicles for a purchaser from vehicle inventories
Processing of vehicle inventory information is described that allows vehicles that satisfy financial institution's financing requirements, as well as a purchaser's requirements are described. The inventory information is processed to determining eligible vehicles that meet the purchaser's requirements. The financial requirements are determined from financial booking information that describes how a financial institution determines the financing for vehicles providing a list of vehicles which can be financed by a financial institution while meeting the purchaser's requirements. |
| US11508005B2 |
Automated, dynamic digital financial management method and system
An automated, dynamic digital financial management tool is described herein. The financial management tool enables a user to access all forms of payments, debt and transactions to be deducted automatically depending on which form of payment is chosen. The financial management tool documents every item/service purchased. The documentation enables a company/manufacturer/store to provide marketing and recall information to the user. The financial management tool is able to include any and/or all financial aspects of a user's life. The financial management tool is able to be implemented using a universal card. The financial management tool is able to include a pay station to receive payments. The financial management tool is able to include automated services. |
| US11508004B2 |
Alternative form factor for financial inclusion
According to some embodiments, apparatus and methods are provided. A connector attachment includes a housing, wherein the connector attachment is selectively connectable to a mobile device; and a first token stored within the connector attachment, wherein the first token is operative to execute a transaction with a second token. Numerous other aspects are provided. |
| US11507991B2 |
Systems and methods for scaling framed images
This application relates to systems and methods for scaling and assembling framed images, and to offering the framed images for purchase. In some embodiments, a computing device is configured to receive a first customer selection of a frame style and a frame size, where the frame size indicates dimensions of a frame window. The computing device is also configured to receive a second customer selection of a mat style. Further, the computing device is configured to determine, based at least on the dimensions of the frame window and the mat style, a mat size, where the mat size includes dimensions of a mat window. The computing device is also configured to determine, based at least on the dimensions of the mat window, an image size for an image. For example, the computing device may execute a rule-based model, or a machine learning model, to determine the image size. |
| US11507990B2 |
Lottery syndicate system
The present invention relates to a lottery syndicate system. The system includes a server for receiving confirmation of a lottery syndicate member, with a mobile internet device, being at a geographic location to qualify as a member of a lottery ticket syndicate. Typically, the geographic location is a store which has increased patronage by virtue of the lottery syndicate members being at that location. |
| US11507978B2 |
Dynamic display of driver content
Systems and methods are disclosed configured to identify a location where current or predicted ride requests exceed a threshold within a time period. Driver location information for one or more drivers is used to identify a driver to satisfy the identified current or predicted ride requests at the location that exceed the threshold within the time period. In response to determining that a driver has at least a first likelihood of accepting a ride request at the location within the time period, item content is selected using a history of establishments frequented by the driver. The selected item of content, associated with a token, is provided for presentation on a display to the driver. In response to determining that the identified driver accepted the ride request at the location within the time period, the token is enabled to be utilized by the identified driver at an entity. |
| US11507977B2 |
Methods and systems for presentation of media collections with automated advertising
Systems, devices, media, instructions, and methods are provided for presentation of media collections with automated advertising. In one embodiment, display time data associated for a first plurality of content elements and a first advertising element as displayed on a first device are used in adjusting a presentation order for a second content collection comprising a second plurality of content elements and at least a second advertising element, where a placement of the second advertising element within the presentation order is based on the display time data. In some embodiments, a ratio of advertising to content elements is targeted over time for a user based on user interactions with various content and advertising elements. |
| US11507973B2 |
System and methods for determining location of pop displays with wireless beacons using mobile applications on mobile devices
Systems and methods for using wireless beacons in point of purchase (“POP”) displays to facilitate the delivery of consumer oriented content to mobile devices is disclosed herein. Wireless beacons may be used to broadcast wireless signals from POP displays, where the wireless signals include data packets with unique identifiers for the wireless beacons. A wireless signal from a POP display may be received by a mobile device. The mobile device may provide the unique identifier in the wireless signal and a retail location of the mobile device to a remote server. The retail location of the mobile device may he provided by a mobile application (e.g., a retailer app) on the mobile device. The remote server may determine the retail location of the POP display by associating the retail location of the mobile device with the wireless beacon. |