| Document | Document Title |
|---|---|
| US11425445B2 |
Display device, display method, projector, and recording medium
A display device displays a guidance display for guiding a control operation on a display screen when receiving the control operation. The display device includes an operation source determination part that determines a source of the control operation based on the control operation received and a guidance display generator that, according to the determined source, displays the guidance display corresponding to the source on the display screen. |
| US11425444B2 |
Content display system, content display method, and recording medium with content displaying program recorded thereon
A content display system includes a first acquisition processor that acquires first content registered on a management terminal; a first display processor that causes the display device to display the first content acquired by the first acquisition processor; a second acquisition processor that acquires second content based on an operation on a portable terminal by a user when the first content is displayed on the display device; and a second display processor that causes the display device to display the second content acquired by the second acquisition processor. |
| US11425443B2 |
Multimedia device connected to at least one electronic device and controlling method thereof
A multimedia device and controlling method thereof are disclosed, by which heterogeneous devices are controlled under at least two different communication protocols. The present invention includes displaying a guide message for controlling at least one function of the electronic device, receiving a remote control signal corresponding to a 1st function among the at least one function from a 1st remote controller of the electronic device, saving data for identifying the 1st function and the received remote control signal in a memory by mapping the data and the received remote control signal to each other, displaying a graphic image including the data for identifying the 1st function, if the data for identifying the 1st function is selected by a 2nd remote controller of the multimedia device, extracting the remote control signal mapped to the 1st function, and transmitting the extracted remote control signal to an external device. |
| US11425441B2 |
Programmatic TV advertising placement using cross-screen consumer data
The current invention relates to a computer-generated method for optimizing placement of advertising content to consumers' TV's using a programmatic TV bidding model. The system can allocate advertising campaigns and plans to various inventory types based on the probability of accurate consumer matching. Consumer matching can be achieved by generation of look-alike models in a consumer's device graph to predict future consumption behavior. The system includes an interface through which an advertiser can access relevant information about inventory and success of a given placement. |
| US11425439B2 |
Processing content streaming
A system for providing streaming services. The system includes a plurality of users each for generating a stream of an event on a connection of a public network. The system also includes a server configured to receive a plurality of the generated streams, determine content for at least one output stream, and output the at least one output stream on a connection of a public network, with at least one user receiving the at least one output stream. The content is determined based on one or more of content received from input streams, content requested by a viewer, and the user profiles of the contributors. |
| US11425434B2 |
Managing concurrent content playback
A content server may receive from a user device a request for a content asset and may send to the playback device a permit for accessing the content asset. The permit may be used by the content server in order to enforce a concurrency restriction, or a number of concurrent playbacks of one or more content assets desired or permitted by the playback device. In response to receiving a request for a content asset segment associated with a content asset, the content server may determine whether the number of permits currently granted to the playback device exceeds the number of desired or permitted accesses by the playback device, or a group of playback devices, to the content asset or one or more content assets. If so, then the content server may discontinue sending to the playback device any further content asset segments associated with that content asset. |
| US11425433B2 |
Content delivery control apparatus, content delivery control method, program, and content delivery control system
The present disclosure relates to a content delivery control apparatus, a content delivery control method, a program, and a content delivery system capable of achieving commonality of conditions associated with transcoding at the time of content delivery in different CDNs and supporting a standard upload interface.In a case in which definition information is stored in a metadata file, an original data stream is controlled on the basis of the definition information. Meanwhile, in a case in which access information for accessing the definition information is stored in the metadata file, then the definition information is requested on the basis of the access information, and transcoding of an original stream is controlled on the basis of the definition information received in response to the request. The present disclosure is applicable to a content delivery system that delivers a content using SDP. |
| US11425432B2 |
Techniques for efficiently performing subsequence-based encoding for a media title
In various embodiments, an interpolation-based encoding application encodes a first subsequence included in a media title at each encoding point included in a first set of encoding points to generate encoded subsequences. Subsequently, the interpolation-based encoding application performs interpolation operation(s) based on the encoded subsequences to estimate a first media metric value associated with a first encoding point that is not included in the first set of encoding points. The interpolation-based encoding application then generates an encoding recipe based on the encoded subsequences and the first media metric value. The encoding recipe specifies a different encoding point for each subsequence included in the media title. After determining that the encoding recipe specifies the first encoding point for the first subsequence, the interpolation-based encoding application encodes the first subsequence at the first encoding point to generate at least a portion of an encoded version of the media title. |
| US11425426B2 |
Method and apparatus for encoding/decoding image
The present invention relates to an image encoding/decoding method and device, and the image encoding method or device according to an embodiment of the present invention may encode a position of a reference coefficient within a current transform block to be encoded, and encoding skip region information of a skip region selected on the basis of the position of the reference coefficient. The skip region information may represent whether or not coefficients within the skip region have an identical coefficient value. |
| US11425423B1 |
Memory storage for motion estimation and visual artifact redcution
At least a method and an apparatus are provided for efficiently encoding or decoding a video frame to smooth out or reduce visual distortions such as visual artifact between different video subsections encoded with different compression methods within a video frame. In addition, an improved memory storage is provided for applying a raster scan search strategy for finding a reference image for the input video frame by applying a shift-based input addressing scheme to write to the memory storage and a corresponding shift-based output addressing scheme to read from the memory storage. |
| US11425422B2 |
Parameter set syntax elements and variables in video coding
Example methods and devices for coding video data are disclosed. An example device for coding video data includes memory configured to store the video data, and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine a value of a first syntax element indicative of whether a first constraint is applicable, the first constraint being that rectangular slices are not used for a plurality of pictures. The one or more processors are also configured to decode the plurality of pictures of the video data in accordance with the value of the first syntax element. |
| US11425416B2 |
Video decoding method and device, and video encoding method and device
A video decoding method and device for determining whether a prediction mode of a current block is an affine mode; splitting, when the prediction mode of the current block is the affine mode, a luma block of the current block into a plurality of sub luma blocks having a square shape based on a predefined sub block size; determining a mean luma motion vector for four neighboring sub luma blocks among the plurality of sub luma blocks, by using a motion vector of an upper-left sub luma block of the four sub luma blocks and a motion vector of a lower-right sub luma block of the four sub luma blocks; determining the mean luma motion vector to be a motion vector of a current sub chroma block corresponding to the four sub luma blocks; and performing prediction on the current sub chroma block by using the determined motion vector, in a video encoding and decoding process are suggested. |
| US11425414B2 |
Method and apparatus for video coding
Aspects of the disclosure provide methods and an apparatus for video coding. The apparatus includes processing circuitry that decodes coding information of a current block from a coded video bitstream. The coding information can indicate an inter merge mode for the current block. The processing circuitry can prune, for the current block, a merge candidate list including at least one merge candidate based on motion information and a flag associated with each of the at least one merge candidate. Each of the at least one merge candidate can be of a respective neighboring block of the current block. The flag can indicate whether an alternative half pixel (half-Pel) interpolation filter (IF) is used for the respective neighboring block. The processing circuitry can reconstruct a sample in the current block based on one of the at least one merge candidate. |
| US11425409B2 |
Encoder, decoder, encoding method, and decoding method
A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector. |
| US11425405B2 |
Cross-component adaptive loop filter in video coding
An example device for decoding video data includes one or more processors implemented in circuitry and configured to: decode a coding tree unit (CTU) of video data, the CTU including a luminance (luma) block and a chrominance (chroma) block, to produce a decoded luma block and a decoded chroma block; determine that a chroma sample of the decoded chroma block is on a first side of an adaptive loop filter (ALF) virtual boundary and that a co-located luma sample of the decoded luma block is on a second side of the ALF virtual boundary, the co-located luma sample being co-located with the chroma sample, the first side being different than the second side; and in response to determining that the chroma sample is on the first side and the luma sample is on the second side, disable cross-component adaptive loop filtering (CC-ALF) for the chroma sample. |
| US11425401B2 |
Scaling list data-based image or video coding
According to the disclosure of the present document, scaling list data transferred from an adaptation parameter set (APS) can be signaled through a hierarchical structure, and restrictions are placed on the scaling list data transferred from the APS, whereby the amount of data to be signaled for video/image coding can be reduced, and easiness in implementation can be provided. |
| US11425400B2 |
Adaptive scaling list control for video coding
An example method includes decoding, from a coded video bitstream, an explicitly defined scaling list; determining, based on values of one or more syntax elements decoded from a sequence parameter set (SPS) of the coded video bitstream, a set of block types to which the explicitly defined scaling list is eligible for application; and applying the explicitly defined scaling list to a block included in the set of block types. |
| US11425395B2 |
Encoding and decoding using tiling
Video coding using tiling may include encoding a current frame by identifying a tile-width for encoding a current tile of the current frame, the tile-width indicating a cardinality of horizontally adjacent blocks in the current tile, identifying a tile-height for encoding the current tile of the current frame, the tile-height indicating a cardinality of vertically adjacent block in the current tile, and generating an encoded tile by encoding the current tile, such that a row of the current tile includes tile-width horizontally adjacent blocks from the plurality of blocks, and a column of the current tile includes tile-height vertically adjacent blocks from the plurality of blocks. Encoding the current frame may include outputting the encoded tile, wherein outputting the encoded tile includes including an encoded-tile size in an output bitstream, the encoded-tile size indicating a cardinality of bytes for including the encoded tile in the output bitstream. |
| US11425390B2 |
Method and apparatus for image encoding and image decoding using temporal motion information
Disclosed herein are a decoding method and apparatus and an encoding method and apparatus that perform inter-prediction using a motion vector predictor. For a candidate block in a col picture, a scaled motion vector is generated based on a motion vector of the candidate block. When the scaled motion vector indicates a target block, a motion vector predictor of the target block is generated based on the motion vector of the candidate block. The motion vector predictor is used to derive the motion vector of the target block in a specific inter-prediction mode such as a merge mode and an AMVP mode. |
| US11425389B2 |
Most probable mode list construction for matrix-based intra prediction
Devices, systems, and methods for digital video coding, which includes matrix-based intra prediction methods for video coding, are described. In a representative aspect, a method for video processing includes generating, for a conversion between a current video block of a video and a coded representation of the current video block, a most probable mode (MPM) list based on a rule, where the rule is based on whether a neighboring video block of the current video block is coded with a matrix based intra prediction (MIP) mode, and performing the conversion between the current video block and the coded representation of the current video block using the MPM list, where the conversion applies a non-MIP mode to the current video block, and where the non-MIP mode is different from the MIP mode. |
| US11425387B2 |
Simplified local illumination compensation
A method of processing video data includes determining, by processing circuitry, a plurality of neighboring samples for predicting a current block. The plurality of neighboring samples are arranged outside of a region of a current picture, the region comprising the current block, a row of samples adjacent to a top row of the current block, and a column of samples adjacent to a left column of the current block. The method further comprises deriving, by the processing circuitry, local illumination compensation information for the current block using the plurality of neighboring samples and generating, by the processing circuitry, a prediction block using the local illumination compensation information. |
| US11425383B2 |
Method and apparatus for sub-picture based raster scanning coding order
A method and apparatus for sub-picture based raster scanning coding order. The method includes dividing an image into even sub-pictures, and encoding parallel sub-pictures on multi-cores in raster scanning order within sub-pictures, wherein from core to core, coding of the sub-picture is independent around sub-picture boundaries, and wherein within a core, coding of a sub-picture is at least one of dependent or independent around sub-picture boundaries. |
| US11425382B2 |
Encoding method, decoding method, encoding apparatus, and decoding apparatus
An encoding method which allows reduction in the amount of codes is provided. The encoding method includes: setting step S11 for setting a quantization matrix set; quantization step S12 for performing quantization on a target block using the selected quantization matrix; and encoding step S13 for encoding, in a mutually associated manner, the target block which has been subjected to the quantization and identification information for identifying the quantization matrix set which has been set. In setting step S11, a quantization matrix set selected from a plurality of quantization matrix sets is set as the quantization matrix set to be used to perform the quantization on the target block, the plurality of quantization matrix sets including a custom quantization matrix set which is arbitrarily specified and a plurality of defined quantization matrix sets which have been respectively defined in advance. |
| US11425378B2 |
Method and apparatus of transform type assignment for intra sub-partition in video coding
A method and apparatus of prediction for video coding are disclosed. According to the method, when the Intra Sub-Partition (ISP) mode is applied to a block, the block is partitioned into multiple sub-blocks horizontally or vertically. A target horizontal transform and a target vertical transform are determined from a candidate transform set for each of the multiple sub-blocks according to a target setting belonging to a setting group comprising unified setting and block setting. The target horizontal transform and the target vertical transform selected are then applied to each of the multiple sub-blocks. According to another method, a target horizontal and vertical transform are determined from a candidate transform set without a transform index for the current block according to unified setting, wherein the unified setting comprises two or more Intra modes or Intra-related modes. |
| US11425377B2 |
Arbitrary and wrap-around tile grouping
A video coding mechanism is disclosed. The mechanism includes partitioning a first picture into a plurality of tiles. A group of the tiles is assigned into a first tile group. The first tile group is a rectangular shape that wraps around the first picture in a horizontal direction and a vertical direction. The first tile group is encoded into a bitstream. A flag is encoded into a parameter set in the bitstream to indicate the first tile group is an arbitrary tile group. The bitstream is stored for communication toward a decoder. |
| US11425376B2 |
Image signal encoding/decoding method and apparatus therefor
An image signal decoding method according to an embodiment of the present disclosure comprises the steps of: partitioning the current picture into a plurality of tiles; decoding partition information indicating a slice type, the partition information indicating whether a rectangular slice is to be applied; determining the number of slices in the current picture; and defining the slices using the tiles. |
| US11425375B2 |
Boundary block partitioning in video coding
A partitioning method comprises determining whether a current block of a picture is a boundary block and whether the size of the current block is larger than a minimum allowed quadtree leaf node size; and if the current block is the boundary block and the size of the current block is not larger than the minimum allowed quadtree leaf node size (MinQTSize), applying forced binary tree (BT) partitioning to the current block. A method comprises making a determination that a current block of a picture is a boundary block and that a size of the current block is less than or equal to a minimum allowed quadtree (QT) leaf node size (MinQTSize); and applying, in response to the determination, forced binary tree (BT) partitioning to the current block. |
| US11425373B2 |
Intra-prediction mode-based image processing method and device therefor
Disclosed are an intra-prediction mode-based image processing method and a device therefor. Particularly, a method for processing an image on the basis of an intra-prediction mode may comprise the steps of: configuring a reference sample to be used for prediction of a current block on the basis of width information and height information of the current block when the current block is a non-square block; deriving an intra-prediction mode of the current block; and generating a prediction sample of the current block by using the reference sample on the basis of the intra-prediction mode of the current block. |
| US11425366B2 |
Test image measuring device, display device and luminance correcting method
A display device relates to a test image measuring device, and includes a housing including one side in which an opening is defined, and a reflector provided to be inclined by a predetermined angle from another side of the housing facing the opening, where a display device including a display unit and an imaging unit is provided above the opening, and a test image displayed from the display unit is photographed by the imaging unit through the reflector. |
| US11425359B2 |
Apparatus and method for generating three-dimensional image
The present invention provides a depth image generation apparatus comprising: a light source for generating light to be emitted toward an object in order to solve an SNR problem caused by resolution degradation and an insufficient amount of received light, while not increasing the amount of emitted light when photographing a remote object; a first optical system for emitting, as a dot pattern and at the object, the light generated by the light source; an image sensor receiving the light reflected by the object, so as to convert the received light into an electrical signal; an image processor for acquiring depth data through the electrical signal; and a control unit connected to the light source, the first optical system, the image sensor and the image processor, wherein the control unit controls the first optical system so as to scan the object by moving the dot pattern in a preset pattern. |
| US11425356B2 |
System and method to calibrate an uncollimated laser diode for 3D imaging applications
A system and method to calibrate an uncollimated laser diode for three-dimensional imaging applications. A method includes providing an optical comparator having an uncollimated laser diode as a light source to generate a shadow with sharp boundaries when used to illuminate an opaque occluder, wherein a two lines source model of light propagation is used to describe a behavior of the uncollimated laser diode, the two lines source model defined by two three-dimensional (3D) lines as model parameters, the uncollimated laser diode calibrated by estimating the two lines as a function of a sample of a ray field emitted by the uncollimated laser diode. |
| US11425354B2 |
Plant feature detection using captured images
Described are methods for identifying the in-field positions of plant features on a plant by plant basis. These positions are determined based on images captured as a vehicle (e.g., tractor, sprayer, etc.) including one or more cameras travels through the field along a row of crops. The in-field positions of the plant features are useful for a variety of purposes including, for example, generating three-dimensional data models of plants growing in the field, assessing plant growth and phenotypic features, determining what kinds of treatments to apply including both where to apply the treatments and how much, determining whether to remove weeds or other undesirable plants, and so on. |
| US11425352B2 |
View synthesis
A method for synthesizing an image of a view from images of N (N>2), implemented by an image synthesis device. The method includes: projecting, to a position corresponding to the image of the view to be synthesized, N depth maps associated with the N views, respectively; for at least one given pixel of at least one projected depth map, for which a depth value has been associated on completion of projection, modifying the depth value of the at least one given pixel if an item of reliability information associated with the depth value is at a certain value, the modification using the depth value of a pixel whose position corresponds to that of the at least one given pixel, in at least one other projected depth map, which generates at least one modified projected depth map. |
| US11425351B2 |
Method and system for creating an out-of-body experience
A computer-implemented method for inducing an Out of Body Experience (OBE) in a user through an augmented/virtual reality (ARNR) system, the OBE including an exit state and a disembodiment state, the method comprising the steps of (a) changing the user viewpoint from body-centered viewpoint to distanced viewpoints, thereby inducing an OBE exit state, and (b) showing to the user his/her own body from the distanced viewpoints, thereby inducing an OBE disembodiment state. |
| US11425348B2 |
Optical display device and method of operating an optical display device
An optical display device includes a plurality of emitters configured to emit electromagnetic radiation in a main emission direction and at least one optical modulation unit which has an adjustable focal length. The emitters are arranged in a main plane and are separately controllable from one another. The optical modulation unit is arranged downstream of the emitters in the main emission direction. Images of the emitters are generated by means of the optical modulation unit, the images of the emitters each having a distance from the main plane which can be predetermined by means of the adjustable focal length. Methods of operating an optical display device are also disclosed. |
| US11425342B2 |
Systems and methods for media projection surface selection
Methods and systems are provided for automatically selecting a target area to project content thereon. For example, a projection device receives content to be projected and content attributes of the content. The projection device also captures images of candidate areas and determines candidate area characteristics based on the captured images. The projection device generates a respective quality-of-projection indicator based on the content attributes and the candidate area characteristics. The projection device selects the candidate area with the highest quality-of-projection indicator as the target area on which the content is to be projected. |
| US11425340B1 |
System and method for managing service and non-service related activities associated with a waste collection, disposal and/or recycling vehicle
Systems and methods are provided for using video/still images captured by continuously recording optical sensors mounted on waste collection vehicles used in in the waste collection, disposal and recycling industry for operational and customer service related purposes. Optical sensors are integrated into the in-cab monitor as well as the onboard computer, digital video recorder and other external devices. |
| US11425338B2 |
Refrigerator, and system and method for controlling same
A food management system includes a computing apparatus, and a refrigerator including a storage chamber and configured to transmit an image of the storage chamber to the computing apparatus. The computing apparatus may include a communication device; and a processing device configured to identify a food from an image received from the refrigerator through the communication device and to transmit information related to the food identified by the refrigerator through the communication device. The processing device may identify the food using different processes from different images. |
| US11425337B2 |
Camera system, event recording system and event recording method
To reduce complication of a configuration of a vehicle while suppressing an increase in weight of the vehicle, a camera system mounted on a vehicle includes an imaging unit to capture multiple frame images of an outside of the vehicle per cycle and an image processor to obtain the multiple frame images from the imaging unit and separate the multiple frame images into a first given number of frame images as a recognition target and a second given number of frame images as a storage target to be stored in an image recorder. The image processor separately outputs the first and second given numbers of frame images to be recognized and stored, respectively. |
| US11425335B2 |
Protecting privacy in video content
A method of protecting privacy in video may include classifying, via a trained multi-level neural network, a plurality of objects within frames of a video content. Training the multi-level neural network may include inputting a plurality of pixels of at least one frame, fitting the pixels into different layers, and assigning weights to individual components within the layers. The method may also include determining if the classified objects are private objects or non-private objects, tracking the detected objects between each frame of the video content within a threshold distance of movement, and masking the private objects. |
| US11425333B2 |
Video management system (VMS) with embedded push to talk (PTT) control
Embodiments include a system, method, and computer program product that enable video management of a plurality of video feeds with Push to Talk (PTT) communications. Some embodiments monitor a plurality of video feeds using a VMS graphics user interface (GUI) where a plurality of video feeds are video feed components of an interactive multimedia media object (IMMO) displayed in the VMS GUI. Some embodiments include receiving a selection of a first talk group that is associated with the IMMO, where members of the first talk group may view the video feed components and communicate via PTT. Subsequently, some embodiments include receiving a second selection of a second talk group, associating the second talk group with the IMMO, and enabling PTT communications among members of the second talk group and an operator of the VMS. |
| US11425319B2 |
Solid-state imaging device and imaging system
In a solid-state imaging device, first electric charge is generated by at least two first photoelectric conversion elements in a first exposure period. At least two pieces of the first electric charge are added in a floating diffusion. A first memory stores a first pixel signal that is based on the first electric charge. Second electric charge is generated by at least one second photoelectric conversion element in a second exposure period. At least part of the second exposure period overlaps at least part of the first exposure period. The second electric charge is held in the floating diffusion. A second memory stores a second pixel signal that is based on the second electric charge. |
| US11425318B2 |
Sensor and control method
The present technology relates to a sensor and a control method that achieve flexible acquisition of event data.A pixel block of the sensor includes one or more pixels each configured to receive light and perform photoelectric conversion to generate an electrical signal and an event detecting section configured to detect an event that is a change in electrical signal of each of the pixels. The sensor switches connections between a plurality of the pixel blocks. The present technology is applicable to a sensor configured to detect events that are changes in electrical signal of pixels, for example. |
| US11425315B2 |
Video communications method and apparatus, terminal, and computer-readable storage medium
A video communications method is provided, including: respectively displaying video images of at least two terminals in at least two display subareas of a video communication interface in a video chat session of the at least two terminal; obtaining a first special effect display instruction; and adding a first special effect to the at least two display subareas based on the first special effect display instruction. The method also includes transmitting the first special effect display instruction to a second terminal of the at least two terminals, the second terminal being an action recipient of the first special effect; and selecting, among multiple end special effects, a target end special effect to be added to the video images of the at least two terminals according to a body action occurred in the video image of the second terminal. |
| US11425313B1 |
Increasing dynamic range of a virtual production display
Disclosed here are various techniques to increase dynamic range of an image recorded from a display. A processor performing preprocessing splits an input image containing both bright and dark regions into two images, image A containing bright regions, and image B containing dark regions. The display presents image A and image B in alternating fashion. Camera is synchronized with the display to record image A and image B independently. In postprocessing, a processor obtains the recorded images A and B. The processor increases the pixel value of the recorded image A to obtain image A with increased pixel value. Finally, the processor increases pixel value of the image recorded from the display by combining the first recorded image with increased pixel value and the second recorded image. |
| US11425308B2 |
Robotically movable display synchronously movable with robotically movable camera for displaying captured images in identical orientation
A system includes a robotic camera and a robotic display. The robotic camera has a robotic camera mount that moves an image capture device such as a camera and the robotic display has a robotic display mount that moves an image display device, such as a video display. The robotic mounts are used to synchronously move the camera and display so that they are in positions where captured images are displayed in the same orientation, e.g. images captured in a portrait orientation are displayed by the display in the same orientation and images captured in a landscape orientation are displayed by the display in the same orientation. |
| US11425306B2 |
Zoom in or zoom out with slow-motion video capture
Aspect for a device for generating video content are described. The device includes a first camera and one or more processors coupled to the first camera and configured to receive a first set of frames captured by the first camera at a first rate, process the first set of frames to generate video content for display, receive a selection to zoom in or zoom out, during the zoom in or zoom out to a zoom threshold for the first camera, receive a second set of frames captured by the first camera at a second rate that is less than the first rate, process the second set of frames to generate video content for display, and generate video content for playback, at a third rate that is less than the first rate, that includes the first set of frames and the second set of frames. |
| US11425304B1 |
Reducing global motion and rolling shutter in a dual camera system
A method to reduce a motion blur and a rolling shutter effect, comprising, receiving a main image frame, a main timing and a main exposure from a main camera, receiving a secondary image frame, a secondary timing and a secondary exposure from a secondary camera, correcting the secondary image frame to the main image frame, determining a delta timing based on the main timing and the secondary timing, determining a delta exposure based on the main exposure and the secondary exposure, determining a discrete motion of offset sequences based on the secondary image frame, determining a row-wise motion blur kernel based on the main image frame and the discrete motion of offset sequences and determining a spatially varying kernel deconvolution based on the main image frame and the row-wise motion blur kernel. |
| US11425302B2 |
Image pickup apparatus, image pickup method, and non-transitory computer-readable storage medium for adjusting a parameter to correct influence depending on an in-focus position
An image pickup apparatus includes a sensor configured to pick up a plurality of images different in in-focus position in an optical axis direction, an adjustment unit configured to adjust a parameter relating to image pickup to correct influence caused by an effective F-number varied depending on an in-focus position when at least a part of the plurality of images is picked up, and a synthesis unit configured to synthesize the plurality of images. |
| US11425301B2 |
Image processing apparatus, information processing apparatus, image processing method, and information processing method
An image processing apparatus obtains image data and transmits the image data to an external apparatus. The image processing apparatus applies first image processing to the image data and receives a result of second image processing applied in the external apparatus to a part of the image data corresponding to a partial area of an entire image represented by the image data, prior to receiving a result of the second image processing applied in the external apparatus to the entirety of the image data corresponding to the entire image. The image processing apparatus, when causing a display apparatus to display the image data that has been transmitted to the external apparatus, causes the display apparatus to display the image data along with an indicator indicating a status of the second image processing being applied to the image data in the external apparatus. |
| US11425295B2 |
Integrated substrate for anti-shake apparatus
An integrated substrate for an anti-shake apparatus defined with an optical axis includes: a substrate, a lens module, an anti-shake apparatus and an image-sensing module. The substrate includes a frame having, a predetermined thickness. The frame includes a first surface, a second surface, a first circuit layout, and a second circuit layout. The lens module is located above the substrate on the optical axis. The anti-shake apparatus is furnished between the lens module and the substrate. The image-sensing module has an active side and an inactive side, and the inactive side is furnished onto the second surface. The active side is located on the optical axis in a manner of facing the lens module. The anti-shake apparatus is coupled to the first circuit layout, while the image-sensing module is coupled to the second circuit layout. The first and second circuit layouts comprise a plurality of first and second metal leads, respectively. |
| US11425291B2 |
Camera module
A camera module includes: a lens module including a plurality of lenses; a housing accommodating the lens module; a reflection module disposed in front of the lens module; an image sensor module configured to receive light passing through the lens module; and a light blocking portion disposed in the housing and positioned in a space between the lens module and the image sensor module. The light blocking portion includes: a first light blocking plate including a first window having a first opening through which the light is allowed to pass; and a second light blocking plate including a second window having a second opening through which the light is allowed to pass. The first window includes a first inner wall including a first inclined surface, and the second window includes a second inner wall including a second inclined surface. |
| US11425289B2 |
Systems and methods for adjusting position of photosensitive chip of image acquisition device
The present disclosure provides a method for adjusting a position of a photosensitive chip of an image acquisition device. The method may include determining a first symmetrical axis and a second symmetrical axis of the photosensitive chip. The first symmetrical axis may divide the photosensitive chip into a first portion and a second portion, and the second symmetrical axis may divide the photosensitive chip into a third portion and a fourth portion. The method may further include adjusting the position of the photosensitive chip from an initial position to an adjusted position. When the photosensitive chip is at the adjusted position, a first image resolution corresponding to the first portion may be substantially equal to a second image resolution corresponding to the second portion, and a third image resolution corresponding to the third portion may be substantially equal to a fourth image resolution corresponding to the fourth portion. |
| US11425287B2 |
Apparatus for protecting a camera from foreign debris contamination
An apparatus for protecting a camera from foreign debris incudes a first body and a second body removably coupled to the first body. The first body has a first inner surface and a first outer surface opposite the first inner surface. The first inner surface defines a first cavity. The first inner surface has an inner circumference. The first body includes a protrusion extending directly from the first inner surface toward the first cavity. The protrusion extending along an entirety of the inner circumference of the first inner surface and is shaped as a half-torus. The second body has a second inner surface and a second outer surface opposite the second inner surface. The second inner surface defines a second cavity. The second cavity is in fluid communication with the first cavity to facilitate flow of the fluid from the first cavity to the second cavity. |
| US11425286B2 |
Housing assembly for image capture devices
A housing assembly for an image capture device is disclosed. The housing assembly includes: a front housing portion defining an opening; a rear housing portion that is connected (secured) to the front housing portion so as to form a watertight seal therebetween; a mounting structure, which is configured as a discrete component that is separate from the front housing portion and the rear housing portion and connected (secured) to the front housing portion adjacent to the opening; a first sealing member that is positioned between the mounting structure and the front housing portion and configured to form a watertight seal therebetween; an integrated sensor-lens assembly (ISLA) that is connected (secured) to the mounting structure such that the ISLA extends through the opening in the front housing portion; and a second sealing member that is positioned between the ISLA and the mounting structure and configured to form a watertight seal therebetween. |
| US11425283B1 |
Blending real and virtual focus in a virtual display environment
Methods and systems are presented for generating a virtual scene rendering of a captured scene based on a relative position of a camera and a virtual scene display in a stage environment, along with real and virtual lens effects. The details might include determining the camera position and virtual display position in the stage environment, and determining a depth value of a virtual scene element displayed on the virtual scene display. A desired focus model can then be determined from focus parameters of the camera, the depth value, and a desired lens effect, and an adjusted focus for the virtual scene element can be determined from the desired focus model. The adjusted focus can then be applied to the camera, the image of the virtual scene element on the virtual scene display, or pixels representing the virtual scene element in a composite image captured by the camera. |
| US11425281B1 |
Color image processing using models of overlapped response spectra for retinal cone cells
Techniques of color image processing involve performing a transformation for each color channel that mixes intensity values from other channels to produce a new intensity value for that channel. The new intensity values, representing the effect of overlapped response spectra of the S, M, and L cones, then provide values of the sensitivities of the photoreceptors of each of the cones. These values of the sensitivities form the basis of more accurate color image processing. For example, compression ratios of gamma-compressed color images may be increased when more the sensitivities are more accurate. |
| US11425278B2 |
Storage medium storing instructions for causing mobile terminal to communicate with communication device based on whether wireless connection between mobile terminal and communication device via access point is established
A mobile terminal includes: a user interface; and first and second interfaces. The mobile terminal is configured to execute: determining whether to set the user interface to an allowing state allowing a password of an access point to be entered; based on determining to set the user interface to the allowing state, setting the user interface to the allowing state; after the mobile terminal performs a specific communication using a first communication method with a device via the first interface, transmitting, to the device, the password entered via the user interface; after the device connects the access point using the transmitted password, communicating with the device via the access point; and based on determining not to set the user interface to the allowing state and after the specific communication is performed, communicating with the device using a second communication method via the second interface without intervention of the access point. |
| US11425276B2 |
Electronic device
An electronic device includes a first controller compliant with a first storage standard, a second controller compliant with a second storage standard, a switching unit that switches setting information between first setting information corresponding to the first storage standard and second setting information corresponding to the second storage standard, and a connection establishing unit that executes processing of establishing connection between an external storage device and one of the first controller or the second controller, the one of the first controller or the second controller compliant with the setting information set by the switching of the switching unit. |
| US11425266B2 |
Electronic apparatus, information processing apparatus, and communication system
An electronic apparatus includes circuitry to receive a request for generating electronic data from an information processing apparatus via a first communication network, generate the electronic data, receive storage destination information designating a storage destination of the electronic data from the information processing apparatus via the first communication network, and transmit the generated electronic data to the storage destination via a second communication network, different from the first communication network, based on the storage destination information received from the information processing apparatus. |
| US11425264B2 |
Image reading apparatus, image reading system, and image reading method
An image reading apparatus is configured to be connected to an external terminal via a network. The image reading apparatus includes a transmitter, a reading section, and a controller. The controller executes an image generation process of generating a single first image file from image data of a document read by the reading section and causes the transmitter to transfer the first image file to the external terminal connected via the network. The controller executes a compression rate determination process of determining a compression rate of a second image file in the image generation process based on a transfer rate of the network when the first image file is transferred to the external terminal and a reading rate of the reading section. |
| US11425263B2 |
Validity information conditions for a protocol data unit session for background data transfer
Apparatuses, methods, and systems are disclosed for using validity information conditions for a protocol data unit session for background data transfer. One method for using validity information conditions for a protocol data unit session for background data transfer includes a device determining validity information for the protocol data unit session for the background data transfer. The device initiates release of the protocol data unit session if a condition of the validity information is not satisfied. |
| US11425259B2 |
Machine learning-based audio codec switching
Described herein are techniques, devices, and systems for providing an optimal voice experience over varying radio frequency (RF) conditions while using EVS audio codecs. A user equipment (UE) may adaptively transition between using a music-capable EVS codec (e.g., EVS-FB) as a default audio codec that provides a first audio bandwidth and a different EVS audio codec that provides a second audio bandwidth that is less than the first audio bandwidth. The transition to the different EVS audio codec may occur in response to determining a value indicative of a RF condition associated with a serving base station is less than a threshold value, which allows for providing preserving at least a minimal level of voice quality in degraded RF conditions. |
| US11425246B2 |
Systems and methods for shifting call handling across multi-region service clusters
A system for handling calls in a network includes a memory storing instructions and a processor configured to execute the instructions to perform operations. The operations include receiving information about the calls for a time interval, determining, for the time interval, a total cost associated with handling the calls, including a network cost associated with transmitting data over the network, a processing cost for processing the information related to the calls, and a cost of dynamically reassigning master and slave roles to a plurality of nodes in the network. The operations further include determining an assignment of the master and slave roles for a plurality of accounts being handled by the plurality of nodes that results in the total cost having a minimum value, and implementing the optimal assignment among the plurality of the accounts based on the determination. |
| US11425245B2 |
Method and system for capturing data of actions
Described herein is a system and method for capturing data associated with actions attempted by an automated agent. The system described herein captures data associated with the actions attempted by an automated agent during the messaging session between an automated agent and the user and present a summary of the actions in a messaging platform. In an embodiment, the automated agent uploads data associated with actions attempted during the messaging session to a server. The server captures the data associated with the actions and generates a description of each action that was attempted. The server generates a summary including the description of each action. The summary of the actions are rendered in the messaging platform. |
| US11425240B2 |
Detection of spoofed calls using call header
Implementations described herein relate to methods, systems, and computer-readable media to label incoming phone calls. A method to label an incoming phone call includes detecting the incoming phone call associated with a caller identifier (ID), determining a location associated with the call, and analyzing a call header of the call to determine one or more call characteristics. The method further includes determining, based on the location and the call characteristics, if the location is spoofed and determining, based on the caller ID and the call characteristics, if an access network associated with the call is spoofed. The method further includes applying a trained machine learning model to determine whether the call is a robocall. The method further includes assigning a label to the call that indicates whether the call is a spoofed call or is the robocall and sending the label to a callee device associated with the call. |
| US11425235B2 |
Radio frequency module and communication device
A radio frequency module includes: a module substrate that includes a principal surface on which external-connection terminals are disposed; a power amplifier that is disposed on the principal surface of the module substrate and amplifies a radio frequency transmission signal; and a heat dissipator that dissipates heat of the power amplifier. The heat dissipator includes: a heat dissipation plate that covers a surface of the power amplifier which is opposite to a surface that faces the module substrate; and at least a first leg that extends from the heat dissipation portion toward the principal surface of the module substrate. |
| US11425232B2 |
Faulty distributed system component identification
A system for detecting a communications computer network node malfunction by analysis of network traffic output by the network node. Low latency packet capture nodes copy network traffic and transmit it to an analytics engine, which may use machine learning techniques, including long short-term memory (LSTM) neural networks, to determine a likelihood that the output of one data router in a network is suffering from a software malfunction, hardware malfunction, or network connectivity issue, and preserve overall data quality in the network by causing cessation of traffic by the malfunctioning node of the network. |
| US11425227B2 |
Automotive can decoding using supervised machine learning
Techniques for identifying certain signals sent over the CAN bus between components of a vehicle are provided herein. Specifically, certain testing maneuvers designed to engage the component of interest are provided to a technician for performing on the vehicle. The messages can be captured from the CAN bus and analyzed, using supervised machine learning algorithms, to isolate the message ids and the byte numbers so that the values of the component of interest may be observed for determining performance metrics. Once identified, these performance metrics may be used to compare with other vehicles or improve the design and performance of the vehicle. |
| US11425224B2 |
Disaggregated and distributed composable infrastructure
Novel tools and techniques are provided for implementing intent-based disaggregated and distributed composable infrastructure. In some embodiments, a computing system might receive, over a network, a request for network services from a customer, the request comprising desired characteristics and performance parameters, without specific information regarding any of hardware, hardware type, location, or network for providing the requested services. The computing system might identify network resources based at least in part on the desired characteristics and performance parameters, might establish transport links between the identified two or more network resources (which may be disaggregated and distributed), might configure (in some cases, based on derived distributable synchronization state(s)) at least one of the identified network resources to simulate zero (or near-zero) latency and/or to simulate zero (or near-zero) distance between the identified network resources, and might allocate the identified two or more network resources for providing the requested network services. |
| US11425222B2 |
Dynamically managing data sharing
A computer-implemented method according to one embodiment includes identifying an event, utilizing a server device, determining a match between the event and an historical event, utilizing the server device, identifying historical data sharing behavior associated with the historical event, utilizing the server device, determining, by the server device, one or more data sharing actions to be performed during the event, utilizing the historical data sharing behavior, and automatically implementing the one or more data sharing actions in response to an initialization of the event, utilizing the server device. |
| US11425218B1 |
Component state management for web application development
A library may be provided that is useable in conjunction with a front-end user interface component management framework. The library may include one or more functions that provide custom hooks that allow a developer to expose state information outside of the front-end user interface component management framework, for example, to other aspects of a web application that uses such a framework. Hooks within the library may allow a developer to persist state of components for global use as well. |
| US11425216B2 |
Virtual private network (VPN) whose traffic is intelligently routed
A request is received from a client device over a Virtual Private Network (VPN) tunnel. The request is received at a first one of a plurality of edge servers of a distributed cloud computing network. A destination of the request is determined and an optimized route for transmitting the request toward an origin server is determined. The optimized route is based at least in part on probe data between edge servers of the distributed cloud computing network. The request is transmitted to a next hop as defined by the optimized route. |
| US11425213B2 |
System and method for modifying a preference
A method for profile matching includes receiving, from a first user, a first preference regarding a second user. The method includes receiving, from the second user, a second preference regarding the first user. The method also includes determining, based on the first preference and the second preference, to allow the first user to modify the first preference. The method also includes receiving, from the first user, a request to modify the first preference. The method also includes modifying the first preference. |
| US11425210B2 |
Methods and systems for provisioning a user profile on a media processor
Aspects of the subject disclosure may include, for example, detecting a plurality of mobile devices in proximity to a device. Further embodiments can include identifying a user identifier associated with each of the plurality of mobile devices resulting in a plurality of user identifiers. Additional embodiments can include obtaining a user profile associated with each of the plurality of user identifiers resulting in a plurality of user profiles. Also, embodiments can include identifying a first user profile having a first priority among the plurality of user profiles. Further embodiments can include provisioning the first user profile on a media processor or set top box and providing media content for presentation on a display according to the first user profile. Other embodiments are disclosed. |
| US11425207B2 |
Receiving device estimating that a communication device is in an incommunicable state
A receiving device includes processing circuitry to determine timings for generating monitoring-side keep alive signals at same timings as timings when a plurality of communication devices transmit monitored-side keep alive signals, to generate a plurality of monitoring-side keep alive signals at a plurality of timings determined, and to estimate a communication device in an incommunicable state based on a comparison result of a number of monitoring-side keep alive signals generated thereafter and a number of monitored-side keep alive signals received thereafter when the plurality of monitoring-side keep alive signals are generated, if a number of the received monitored-side keep alive signals is smaller than a number of the generated monitoring-side keep alive signals. |
| US11425204B2 |
Method of system of assigning a seating position in instances of a game
Disclosed is a computer-implemented method of (and system for) operating instances of a game having a plurality of game positions that can be occupied by players, such as a poker-type game. The method comprises assigning a player a plurality of weights relating to game positions, where each weight indicates a bias towards placement of the player at a game position. When a player has played in a first game at a given position, the weights are updated to indicate an altered bias towards placement at each position. The player is then assigned to a second game based on the updated weights. |
| US11425203B2 |
Commissioning a virtualized network function
Certain aspects provide a method of commissioning a virtualized network function (VNF), including: at a commissioning virtual machine instantiated in a virtualized environment of a customer network, configuring a remote access connection facility for accessing the commissioning virtual machine remotely from outside of the customer network, wherein the commissioning virtual machine has access to a virtual infrastructure manager (VIM) component of the virtualized environment; causing, via the remote access connection facility, configuration of a VNF manager component within the commissioning virtual machine; and causing, via the remote access connection facility, the configured VNF manager component to instruct the VIM component to instantiate one or more virtual machines in the virtualized environment, the one or more virtual machines being operable to perform at least a part of the VNF. |
| US11425202B2 |
Session processing method and device
Embodiments of a session processing method and a device relating to a data network are provided. The method includes a data-network network element in the data network receiving a data network access request sent by a session management function (SMF) network element of the data network, where the data network access request includes an identifier of user equipment UE and a session address to be used by the UE. The data-network network element sends a response message to the SMF, where the response message instructs the SMF to allow the UE to access the data network, so that the SMF establishes a data packet unit session of the UE. The data-network network element detects, based on the session address or the identifier of the UE, that the data packet unit session of the UE needs to be processed, generates a session processing request, and instructs, by using the session processing request, the SMF to process the data packet unit session of the UE. |
| US11425200B2 |
Gas turbine engine communication gateway with internal sensors
A communication adapter of a gas turbine engine of an aircraft includes an internal sensor system including a plurality of sensors within the communication adapter, a memory system, and processing circuitry. The processing circuitry is configured to receive a plurality of time series data at the communication adapter from an engine control during operation of the gas turbine engine, record a plurality of internal sensor data versus time in the memory system based on the internal sensor system until an end condition is met, correlate the time series data with the internal sensor data based on an alignment in time to form an enhanced data set, and transmit the enhanced data set from the communication adapter to an offboard system based on a transmit condition. |
| US11425198B2 |
Communication system for air conditioner, and air conditioner
Provided is a communication system for an air conditioner including a housing and a control board accommodated in the housing. The communication system includes: a communication conversion unit accommodated in the housing and configured to acquire a required electric signal from the control board and to convert the electric signal into a digital signal for wire transmission; a cable having a first end connected to the communication conversion unit, the cable being drawn out of the housing to outside; and an antenna unit connected to a second end of the cable located outside the housing, the antenna unit being configured to establish wireless communication with a base station. |
| US11425194B1 |
Dynamically modifying a cluster of computing nodes used for distributed execution of a program
Techniques are described for managing distributed execution of programs. In some situations, the techniques include dynamically modifying the distributed program execution in various manners, such as based on monitored status information. The dynamic modifying of the distributed program execution may include adding and/or removing computing nodes from a cluster that is executing the program, modifying the amount of computing resources that are available for the distributed program execution, terminating or temporarily suspending execution of the program (e.g., if an insufficient quantity of computing nodes of the cluster are available to perform execution), etc. |
| US11425193B2 |
Systems, methods, and media for causing an action to be performed on a user device
Systems, methods, and media for causing an action to be performed on a user device are provided. In some implementations, the systems comprise: a first user device comprising at least one hardware processor that is configured to: detect a second user device in proximity to the first user device; receive a user input indicative of an action to be performed; determine a plurality of candidate devices that are capable of performing the action, wherein the plurality of candidate devices includes the second user device; determine a plurality of device types corresponding to the plurality of candidate devices; determine a plurality of priorities associated with the plurality of candidate devices based at least in part on the plurality of device types; select a target device from the plurality of candidate devices based at least in part on the plurality of priorities; and cause the action to be performed by the target device. |
| US11425188B2 |
Apparatus and method for transmitting and receiving information related to multimedia data in a hybrid network and structure thereof
An apparatus and method for transmitting and receiving information related to multimedia data in a hybrid network and a structure thereof are provided. The transmission method includes generating transmission characteristic information about the media data, and transmitting the transmission characteristic information. The transmission characteristic information includes valid range information about the transmission characteristic information. |
| US11425184B2 |
Initial bitrate for real time communication
A method for determining an initial bitrate for a communication includes receiving a communication request to establish a digital communication between a first user device and a second user device associated with a plurality of features including a geographical identifier identifying a geographical location associated with the first user device, a first network type connection associated with the first user device, a second network type connection associated with the second user device, and an average bitrate for a previous digital communication of the first user device. The method includes determining, using an initial bitrate predictor model configured to receive the plurality of features as feature inputs, an initial bitrate for the digital communication between the first user device and the second user device, and establishing the digital communication between the first user device and the second user device at the determined initial bitrate. |
| US11425182B1 |
Systems and methods for dynamically encoding media streams
The disclosed computer-implemented method may include (1) receiving a media stream, (2) determining a first priority level for the media stream, (3) generating one or more first encoded segments from a first segment of the media stream based on the first priority level, (4) determining, while generating the one or more first encoded segments, a second priority level for the media stream, the second priority level being different than the first priority level, (5) generating one or more second encoded segments from a second segment of the media stream based on the second priority level, and (6) streaming the one or more first encoded segments and the one or more second encoded segments to one or more client devices. Various other methods, systems, and computer-readable media are also disclosed. |
| US11425181B1 |
System and method to ingest one or more video streams across a web platform
System and method to ingest one or more video streams across a web platform are disclosed. The system an input module configured to receive at least one web address associated of the corresponding video streams across the web platform, a video analysis module configured to analyse content of the video streams, a token receiving module configured to identify contact detail associated to the user on receiving a prompt from the contact detail; to generate an automated message to transfer contact detail of the user and to receive an access token from the user, a video exception module configured to enable the user to debug a video retrieving process if a prompt is not generated from the contact detail and to create at least one of a set of rules, a set of logic or a combination thereof, to analyse the content of the video streams. |
| US11425178B1 |
Streaming playlist including future encoded segments
Techniques for low latency streaming, for example in a broadcasting environment, are described herein. In some examples, a playlist may include both currently encoded segments, which are segments that are fully encoded at or before playlist generation, and also future encoded segments, which are segments that have not yet been fully encoded at playlist generation. In some cases, the inclusion of future encoded segments in a playlist may result in a player requesting a segment that has not yet been fully encoded at the time that the request is received by the server. In some examples, even though the segment is not yet fully encoded, the server may nevertheless save and process the request, for example by transmitting encoded portions of the requested segment as those portions are made available by the encoder. |
| US11425176B2 |
Transmitting conference application content during a network conference
System and methods for transmitting conference application content during a network conference. In an embodiment, a method is provided for transmitting conference application content during a network conference. The method includes participating in a network conference using a client application, selecting a conference application from a plurality of conference applications, and running the conference application from the client application during the network conference. The method also includes identifying application content from the conference application, and transmitting the application content and a conference application identifier to attendees of the network conference. |
| US11425173B2 |
Methods and nodes supporting lawful intercept
The present invention relates to methods, systems, LI systems and nodes in a telecommunication network for providing bandwidth optimization by means of a tokenizer functionality and a restore functionality. It is further provided a token-content-synch process for synchronizing the tokenizer functionality and the restore functionality. |
| US11425172B2 |
Application security for service provider networks
Systems, methods, and apparatuses may include a network onboarding manager for configuring network security features at application hosting sites of a service provider network, for instance, as part of a procedure for deploying an application onto the service provider network. The network onboarding manager may generate a security profile for the application. The security profile may include information indicating a security posture of the application with respect to network security features needed to deploy the application, which the system may use to generate and send configuration data to the hosting sites. One or more operations may be performed based on a user input received at a developer portal (e.g., via a user interface), or automatically based on one or more API calls made by the network onboarding manager and/or based on one or more security profile templates. |
| US11425171B2 |
Method and system for cryptographic attribute-based access control supporting dynamic rules
The present invention mainly relates to the field of information technology, and specifically to a method and system for cryptographic attribute-based access control supporting dynamic rules. In the system, the protected object is stored in an encrypted form, only the access request satisfying the access policy in attribute-based access control can be authorized to decrypt the object, which ensures that the access to data in an unsecure environment can be authorized according to a security policy, and supports dynamic policy and real-time authorization of attributes. The method and system for cryptographic attribute-based access control supporting dynamic rules in this invention have already separated from traditional encryption system framework, are totally new attribute-based access control model, method and system supporting cryptographic determination, can achieve more secure, diversified, dynamic and flexible access authorization, are suitable for large-scale organizations or information systems, and can be applied to the environments such as Cloud computing, grid computing, and distributed computing. |
| US11425170B2 |
System and method for deploying and configuring cyber-security protection solution using portable storage device
This disclosure provides a system and method for deploying and configuring a cyber-security protection solution using a portable storage device. The portable storage device may include a memory storing instructions to be executed by a computing device. When executed, the instructions may cause the computing device to implement a cyber-security protection solution that is configured to scan a second storage device and determine whether the second storage device is usable in a protected environment. |
| US11425163B2 |
Control of cyber physical systems subject to cyber and physical attacks
Methods, systems, and computer readable media to control a cyber physical system using an observer-based controller are described. |
| US11425162B2 |
Detection of malicious C2 channels abusing social media sites
Methods, apparatuses and computer program products implement embodiments of the present invention that include protecting a computing device by specifying one or more Internet sites that are accessible by one or more computing devices that communicate over a data network and identifying process binaries that executed on the computing devices accessed and retrieved data from any of the specified one more Internet sites. The identified process binaries are classified into a plurality of classes of matching process binaries, and for a given class, a count of the computing devices that that executed one of the process binaries of the given class is computed. When determining that the count of the computing devices is less than a predefined threshold, a preventive action is initiated to inhibit command and control (C2) channel transmissions from any of the computing devices that executed any of the process binaries of the given class. |
| US11425154B2 |
System and method of detecting anomalies in a technological system
Disclosed herein are systems and methods for detecting anomalies in a technological system. In one aspect, an exemplary method comprises, intercepting, by a duplicator running on an upper-level element of the technological system at least one outgoing data packet addressed to a middle-level element of the technological system, sending, by the duplicator, information about the intercepted at least one outgoing data packet to a monitor using a secure connection, the monitor running on the middle-level element, intercepting, by the monitor, at least one incoming data packet, comparing, by the monitor, the information received from the duplicator with the intercepted at least one incoming data packet, and detecting, by the monitor, an anomaly in the technological system when the intercepted at least one incoming data packet does not conform to the information received from the duplicator. |
| US11425148B2 |
Identifying malicious network devices
Embodiments provide for maliciousness scores to be determined for IP addresses and/or network domains. For example, a request to evaluate malicious activity with respect to an IP address/network domain may be received. Multiple, and in some cases disparate, third-party systems may provide malicious activity information associated with the IP address and/or network domain. A feature set may be extracted from the malicious activity information and statistical values may be calculated from the extracted data and added to the feature set. The features set may be provided to a machine learning model as input and a maliciousness score/classification may be returned. A remedial action may be performed in accordance with the output of the machine learning model. |
| US11425147B2 |
In-service data plane encryption verification
A method of executing in-session encryption verification includes receiving a plurality of client data packets for transmission through a network; receiving one or more test data packets for verifying an encryption device; merging the client data packets and the one or more test packets into a data stream; selecting security parameters for each packet in the data stream based on a corresponding packet type; encrypting each packet in the data stream using the encryption device and the corresponding security parameters; and transmitting the data stream comprising encrypted packets through the network. The method also includes decrypting the encrypted packets at a receiving system using congruent techniques. |
| US11425143B2 |
Sleeper keys
A system includes an authorization token with a memory configured to store user attributes including a record of previous usage of the data store by the user, pre-authorization data for the user, and an access signature for accessing contents of a data store. The authorization token receives an authorization request. Session attributes are collected associated with a file path used by the user to request access to a file. A consistency measure is determined associated with whether the file path used by the user to request access to the file is consistent with a previous file path stored in a record of previous usage of the data store by the user. In response to determining that the consistency measure is greater than a threshold value, the access signature is provided to the data store, thereby granting the user access to the file. |
| US11425142B2 |
Location based authentication
A method of enabling a user to access recorded data associated with an event, the method comprising determining the location of a user's device at a control unit, confirming the location is within a predetermined vicinity and that the user's device was at the location within a predetermined period and the control unit enabling access for the user to the data if the location of the user's device in the predetermined period is confirmed. |
| US11425141B2 |
Reduced user authentication input requirements
Techniques disclosed herein enable a system to reduce user authentication requirements during a user's travels by analyzing transportation data and/or event data sent to the user via a communication service, e.g. email. The system may analyze the data in order to determine where the user will be at some future time and, ultimately, to then validate access requests against such determinations to mitigate the need for heightened user authentication requirements while the user is traveling. For instance, the system may identify an airline reservation sent to the user and enable the user to confirm that she has corresponding travel plans. Once she confirms her travel plans, the system may refrain from increasing authentication requirements from Single-Factor Authentication (SFA) to Multi-Factor Authentication (MFA) input requirements for access requests that match the confirmed travel plans. |
| US11425140B1 |
Secure and efficient cross-service sharing of subscriber data
A configuration management service provides data identifying its subscribers to a secure sharing service that executes in an account that has a higher security level than a service account used to provide the configuration management service. The secure sharing service securely determines whether each subscriber has authorized producer services to share resource configuration data with the configuration management service. If a subscriber has authorized such sharing, information identifying the subscriber can be stored in a location accessible to the producer services. If a subscriber has not authorized such sharing, the secure sharing service will not make the subscriber's information available to the producer services. The producer services can use the subscriber data to provide resource configuration data to the configuration management service only for those subscribers that subscribe to both the configuration management service and to the producer services. |
| US11425135B2 |
Method for platform user management using badge system
Provided is a platform user management method using a badge system performed by a computing device. The method comprises granting a badge generation permission to a first user account, generating a first badge according to a request for using the badge generation permission of the first user account, granting the first badge to the second user account and activating a first permission to a second user account when the first badge is equipped to the second user account. |
| US11425126B1 |
Sharing of computing resource policies
A policy management service receives a request to associate a version of a computing resource policy as a default version of the policy. In response to the request, the service identifies, from a policy database, an entry for the default version of the policy. The service updates the entry in order to associate the version specified in the request as the default version of the policy. This results in the version of the policy becoming applicable to control access to the computing resources associated with principals associated with the default version of the policy. |
| US11425125B2 |
Shared resource identification
A method for sharing resource identification includes receiving, at a lookup service, from a first application executing on a particular device associated with a user, a resource identifier (ID) request requesting the lookup service to provide the first application access to a resource ID that identifies the particular device. The method also includes determining, by the lookup service, whether the first application executing on the particular device is authorized to access the resource ID. When the first application is authorized to access the resource ID, the method includes obtaining, by the lookup service, the resource ID and transmitting, by the lookup service, to the first application executing on the particular device, the resource ID. |
| US11425122B2 |
System and method for providing a configuration file to client devices
A solution for circumventing censorship is disclosed. A first device connects to a first server hosted in a content delivery network (CDN). The CDN routes the first device's connection request to the first server. The first server responds by providing the first device with a configuration file that contains a plurality of second servers for the first device to access. The first device disconnects from the first server and hops between one or more of the plurality of second servers contained in the configuration file. By distributing the configuration file from a first server hosted in a CDN, the first device obfuscates the true endpoint of the connection. Thus, the first device obtains the configuration file without drawing the ire of censors. By hopping from server-to-server, the first device stays one step ahead of censors. Accordingly, a multi-prong approach to staying a step ahead of eavesdroppers, sniffers, and censors is described. |
| US11425120B2 |
Systems for authenticating digital contents
A system for authenticating digital contents includes a computing platform having a hardware processor and a memory storing a software code. According to one implementation, the hardware processor executes the software code to receive digital content, identify an image of a person depicted in the digital content, determine an ear shape parameter of the person depicted in the image, determine another biometric parameter of the person depicted in the image, and calculate a ratio of the ear shape parameter of the person depicted in the image to the biometric parameter of the person depicted in the image. The hardware processor is also configured to execute the software code to perform a comparison of the calculated ratio with a predetermined value, and determine whether the person depicted in the image is an authentic depiction of the person based on the comparison of the calculated ratio with the predetermined value. |
| US11425116B2 |
Data backup and transfer system, method and computer program product
A backup system having a plurality of accounts for copying selected data between one or more account user computers and a system computer where an account user's computer connects to the system computer via the Internet. Selected data is copied between the account user's computer and the system computer including, documents, media files, and email in any file type or format. Additionally, the system is compatible with all types of computers, including personal data assistants and mobile telephones, and all types of operating systems. All of the software to operate the system is resident on the system computer with no hardware or software required on the account user computer beyond a conventional web browser. The system also includes a scheduler, a contacts manager, a reminder generator and file transfer system for third-party users. |
| US11425112B1 |
Systems and methods for blockchain validation and data record access employing a blockchain configured banking core and blockchain configured federation proxies
Blockchain validation systems including a blockchain configured banking core (BCBC) hosted on a server, a blockchain configured component coupled to the BCBC, permitting transfer of data records to the BCBC for storage thereon, and a number of blockchain configured federation proxies facilitating identification of access rules and execution of blockchain validation mechanisms. Methods for blockchain validation involving permitting interaction amongst a plurality of external computing systems associated with a plurality of entities in a manner bypassing a BCBC hosted on a server, through a blockchain configured component accessible by the external computing systems, permitting data record transfer to the BCBC over an independent verification network, managing the data records using blockchain configured federation proxies, and selectively distributing data records to the entities. |
| US11425111B2 |
Attestation token sharing in edge computing environments
Various approaches for implementing attestation using an attestation token are described. In an edge computing system deployment, an edge computing device includes an attestable feature (e.g., resource, service, entity, property, etc.) which is accessible from use of an attestation token, by the operations of: obtaining a first instance of a token that provides proof of attestation for an accessible feature of the edge computing device, with the token including data to indicate trust level designations for the feature as attested by an attestation provider; receiving, from a prospective user of the feature, a request to use the feature and a second instance of the token, with the second instance of the token originating from the attestation provider; and providing access to the feature based on a verification of the instances of the token, by using the verification to confirm attestation of the trust level designations for the feature. |
| US11425109B2 |
Secure and accurate provisioning system and method
A method and system for provisioning credentials is disclosed. The method includes receiving an encrypted data packet including a first passcode and credentials in encrypted form, and a second passcode. The second passcode is compared to a first passcode. If the passcodes match, then a server computer can transmit a token associated with the credentials to a service provider computer. |
| US11425102B2 |
Air gap system and method using out of band signaling
A method of communicating and securing data on a network with an air-gap device that includes switching of a first air-gap such that a second air-gap is generated between a second port and a first communication circuit to one or more devices, and such that a second operable connection is generated between a first communication circuit to the one or more devices and a third port. The air gap-device includes a first interface comprising a first port, the first interface being part of the first communication circuit to the one or more devices a second interface comprising the second port; a third interface comprising the third port; and a physical relay array block operably coupled to and corresponding to the first, second and third interfaces, with the physical relay array block configured for physical switching between a first and second configuration that generates the first and second switching. |
| US11425093B2 |
Device specific website filtering using a bifurcated domain name system
Systems and techniques for location independent website filtering using bifurcated domain name system are described herein. A domain name system (DNS) request may be received. A unique device identifier may be received for the requesting device. The ISP may provide external network services to the services gateway. The DNS service provider may maintain a website filtering policy. The DNS request may be forwarded to the DNS service of the ISP. The DNS service of the ISP may respond with a DNS resolution. An access control request may be forwarded to the DNS service provider external to the ISP. A website filtering policy associated with the device identifier may be used to determine website access. The DNS service provider external to the ISP may respond with a grant/block status. Based on the returned grant/block status, the services gateway may respond to the requesting device with the DNS resolution or access denial. |
| US11425090B2 |
Systems and methods for associating website visitors with a sticky dynamic internet protocol (IP) address
The disclosure is directed to, among other things, systems and methods for associating website visitors with a sticky dynamic internet protocol (IP) address. An example method may include identifying one or more first web-based cookies associated with a first IP address or one or more first user agents associated with the first IP address as being received by a web server associated with a website. The example method may also include determining a density measurement for the first IP address, the density measurement being a maximum number of the one or more first web-based cookies or the one or more first user agents that are identified as being received at the web server at a single time. The example method may also include determining that the density measurement is less than or equal to a threshold value. The example method may also include determining, based on the density measurement being less than or equal to the threshold value, that the first IP address is a first sticky dynamic IP address. |
| US11425088B2 |
Content delivery network optimization system
A CDN traffic is optimized by a client-side system that maps the servers in the CDN system. Content requests from client devices for domain names are forwarded to servers in the CDN system that may be selected from the map to prevent a cache miss in the a server for a particular request for content. |
| US11425077B2 |
Method and system for determining a spam prediction error parameter
Method and server for determining a spam prediction error parameter for a spam prediction parameter are disclosed. The method includes: receiving a plurality of emails destined to a plurality of users where a given email has a spam prediction parameter and a user-interaction parameter indicative of whether an associated recipient of the plurality of users agrees with the spam prediction parameter, and clustering the plurality of emails into at least two clusters having respective subsets of emails. For a given cluster the method includes determining a ground truth parameter by analyzing its subset of emails and the associated user-interaction parameters, and assigning the ground truth parameter to the given cluster. For the given email, the method includes generating the spam prediction error parameter based on a difference between the spam prediction parameter and the ground truth parameter, and storing the spam prediction error parameter in association with the given email. |
| US11425074B1 |
Methods, apparatuses, and systems for providing an event evaluation framework
In general, embodiments of the present invention provide systems, methods and computer readable media for a defining and executing state machines that act based on messages received on a message queue. |
| US11425073B2 |
Multi-tiered anti-spamming systems and methods
Embodiments are provided for reducing unwanted messages or spam within a real-time social networking service. According to certain aspects, a synchronous analysis module may operate in coordination with an asynchronous analysis module. Each of the synchronous analysis module and the asynchronous analysis module analyzes an incoming message from a user account to determine whether the incoming message has characteristics of spam, whereby the synchronous analysis is at a lower latency than the asynchronous analysis. The asynchronous analysis is afforded the ability to identify certain spam characteristics that the synchronous analysis may identify during its lower latency analysis. |
| US11425069B2 |
Handling of oversized email attachments
Systems and methods herein provide for improved handling of oversized email attachments. An example system can identify an oversized email attachment before an email is sent, by comparing the size of the attachment to a maximum file size at an email server. The user can then be notified that the attachment is over the allowable file size before sending the email. The system can also un-attach the oversized file, compress it using a suitable compression method, and reattach a compressed file. The compression can be done at the sender's request or automatically. |
| US11425064B2 |
Customized message suggestion with user embedding vectors
A message may be suggested to a user participating in a conversation using one or more neural networks where the suggested message is adapted to the preferences or communication style of the user. The suggested message may be adapted to the user with a user embedding vector that represents the preferences or communication style of the user in a vector space. To suggest a message to the user, a conversation feature vector may be computed by processing the text the conversation with a neural network. A context score may be computed for one or more designated messages, where the context score is computed by processing the user embedding vector, the conversation feature vector, and a designated message feature vector with a neural network. A designated message may be selected as a suggested message for the user using the context scores. The suggestion may then presented to the user. |
| US11425063B2 |
Content selection
One or more systems and/or techniques for generating a content item from content within a content area are described herein. A first boundary and a second boundary may be defined for a content area based upon a first user input and a second user input, such as swipe gestures. A content item may be generated based upon content within the content area. In an example, a beginning boundary designator may be displayed for the first boundary and an ending boundary designator may be displayed for the second boundary in response to one or more swipe gestures of a user interface. In an example, the content item may be stitched to a second content item to create a stitched content item. |
| US11425057B2 |
Packet processing
A memory of a network device is divided into first blocks, each first block being divided into second blocks, and each second block including a first storage space and second storage space. When a packet is stored, second blocks occupied by the packet are determined based on a packet length and a first storage space length, and the packet is stored into a first storage space of each of the second blocks. For each of the second blocks, a PD corresponding to the second block is generated, and stored into a second storage space of the second block. When a packet is read, the second blocks to be read are determined based on a start address of the packet. A packet fragment is read from a first storage space of the second blocks to be read, and the read packet segments are composed into the second packet to be sent. |
| US11425054B1 |
User-configured multi-location service deployment and scaling
Techniques are described for a location-aware service-oriented application deployment management (“SOADM”) service that abstracts the complexities of deploying distributed applications in a cloud provider network providing many possible deployment zones of one or multiple types. These deployment zone types can include traditional cloud provider regions and availability zones as well as so-called edge locations (e.g., cloud provider operated edge locations, customer-operated edge locations, third-party operated edge locations, communications service provider (CSP) associated edge locations). The SOADM service enables users to create service group configurations representing a service-oriented application, including its constituent services and dependent resources, and specify distribution strategies for deploying and/or redistributing application services and resources, among other configurations. Using such configurations, the SOADM service automatically deploys and scales simple or complex, single or multi-service applications for users across any number of deployment zones and deployment zone types. |
| US11425047B2 |
Traffic analysis method, common service traffic attribution method, and corresponding computer system
This application provides a traffic analysis method and apparatus, and a computer system. The method includes: obtaining a plaintext feature and a ciphertext feature of a packet in traffic, where the ciphertext feature includes a length feature of an encrypted field in the packet; and analyzing the traffic based on the plaintext feature and the ciphertext feature, to identify a service or an application to which the traffic belongs. The method may be used for service identification or application identification. The ciphertext feature is introduced in traffic analysis, so that traffic identification accuracy is improved in a packet encryption scenario. In addition, this application further provides a common service traffic attribution method and apparatus, and a computer system. |
| US11425046B2 |
Probabilistic packet marking with fast adaptation mechanisms
At an Edge Node, a method of handling data packets in order to mark the packets with respective packet values indicative of a level of importance. The method comprises implementing a variable rate token bucket to determine an estimated arrival rate of a flow of packets. The method comprises receiving a data packet, updating the estimated arrival rate to an updated arrival rate based on a token level of the token bucket and generating a random or pseudo-random number within a range with a limit determined by the updated arrival rate. The method further comprises identifying an operator policy which determines a level of service associated with the flow of packets, and a Throughput Value Function (TVF) associated with said policy, and then applying the TVF to the random number to calculate a packet value. The packet value is included in a header of the packet. |
| US11425038B2 |
Packet header field extraction
Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline. |
| US11425029B2 |
Internal network monitoring system and method
In an internal network monitoring method for monitoring an internal network, a specified network packet, which is scheduled to be transmitted via a specified path, is inspected. A packet characteristic is extracted from a data link layer of the specified network packet. The specified network packet is directly transmitted via the specified path if the packet characteristic does not comply with a preset condition. The specified network packet is redirected to be transmitted via another path different from the specified path or mirroring the specified network packet to create a mirror packet if the packet characteristic complies with the preset condition. |
| US11425024B2 |
Thread network routing control
Provided is a machine-implemented method for operating a device in a network, comprising entering the device into a non-router membership relation with a self-organizing subnet of the network; receiving at least one message making known parameters of the subnet, the at least one message comprising a centrally-generated and propagated sequence number; detecting, based on the received at least one message comprising a sequence number, a deterioration in propagation of said at least one message; and responsive to the detecting, entering the device into a router membership relation with the self-organizing subnet of the network. |
| US11425016B2 |
Black hole filtering
A system related to black hole filtering is provided. The system can allow a dynamic routing protocol on a network device to determine whether a route learned by the dynamic routing protocol is a black hole route. The route may be learned through another source. In response to a determination that the route is the black hole route, the dynamic routing protocol may generate a routing update that indicates the route as the black hole route. The dynamic routing protocol may then advertise the routing update to each neighbor network device. |
| US11425012B2 |
Dynamically generating visualizations of data based on correlation measures and search history
Described embodiments provide systems and methods for generating visualizations of data based on correlation measures and search history. An analysis engine may access data observed from a data source over time. The analysis engine may determine a variation of each of at least a first metric and a second metric of the data, over time. A correlation engine may determine a correlation measure between the first metric and a second metric, over time. The correlation engine may generate, responsive to the correlation measure being greater than a reference level, a visualization of the first metric and the second metric varying in time, on a device to display to a user. |
| US11425008B2 |
Virtual private network manager
Methods, computer systems, and computer-storage medium are provided for monitoring, analyzing, and providing reports regarding direct access technologies, for example DirectAccess, VPN, or VPN-like technologies. User activity associated with DirectAccess servers can be filtered by server location to allow administrators to determine which users, and how many users, utilized or are utilizing each DirectAccess server, which can be identified by geographic locations. In some cases, this information can be used to address technical support issues or to determine which resources of an entity may be under- or over-utilized. |
| US11425007B2 |
Label-based rules for squelching visible traffic in a segmented network environment
In a segmented network environment, a traffic flow graph provides visibility into the connections between workloads or groups of workloads under management of a segmentation policy. Squelching rules may be applied to hide traffic in the traffic flow graph that meets specified criteria. The squelching rules may be label-based rules that enable configuration of squelching rules that apply to group of workloads and enable configurations to be rapidly updated as workloads or added or dropped from the network or as their configurations change. Additionally, squelching rules may be applied based on characteristics of the traffic data or based on an identity of an administrator viewing the traffic flow graph. |
| US11424997B2 |
Secured network management domain access system
A secured network management domain access system includes a chassis housing a master I/O module that is configured to provide a network management domain, and a management module coupled to the master I/O module. The management module includes an enclosure controller coupled to the master I/O module via a first communication channel, and that retrieves master I/O module secured access information from the master I/O module via the first communication channel. The management module also includes a management service coupled to the enclosure controller via a second communication channel and to the master I/O module via a third communication channel, and that retrieves the master I/O module secured access information from the enclosure controller via the second communication channel, and performs validation operations with the master I/O module via the third communication channel such that the management service may securely access the network management domain via the master I/O module. |
| US11424996B2 |
Method for controlling display device, and display device according thereto
A display device according to an embodiment of the present disclosure includes: a display; a communication unit configured to communicate with at least one other display device; a memory storing one or more instructions; and a control unit including at least one processor configured to perform at least one of the one or more instructions. According to an embodiment of the present disclosure, provided are a display device capable of selectively blocking outbound traffic generated in the display device and generally applying the blocking of outbound traffic to a plurality of display devices and a method for configuring the display device. |
| US11424995B1 |
Management of a network via a GUI of user relationships
Briefly, methods and/or apparatuses are described for network management via a graphical user interface (GUI). |
| US11424994B2 |
Traffic-controlled processing of application requests
A request processor includes a request handler and a traffic controller. The request handler is configured to communicate requests received from a source application to corresponding service providers over a network. Each of the requests defines a target action to be performed by the corresponding service provider on a target application. The traffic controller is configured to generate a user interface and perform one of a plurality of traffic control actions on each of the requests based on a user control input through the user interface. The plurality of traffic control actions includes allowing communication of a request to the corresponding service provider by the request handler, holding a communication of a request to the corresponding service provider, and turning back a request to the source application for manual fulfillment. |
| US11424993B1 |
Artificial intelligence system for network traffic flow based detection of service usage policy violations
At an artificial intelligence based service to detect violations of resource usage policies, an indication of a first data set comprising a plurality of network traffic flow records associated with at least a first device of a set of devices may be obtained. Using the first data set, a machine learning model may be trained to predict whether resource usage of a particular device of a particular network violates a first resource usage acceptability criterion. In response to determining, using a trained version of the model, that the probability that a second device has violated the acceptability criterion exceeds a threshold, one or more actions responsive to the violation may be initiated. |
| US11424992B2 |
Mesh communication network provision
A method of provisioning mesh communication networks is disclosed. The method involves simulating the performance of a proposed network design to ensure the proposed network design meets service level criteria before provisioning a network in accordance with the proposed network design. Such simulations are required to be comprehensive because highly improbable events can be sufficient to result in a mesh network not meeting the stringent performance criteria which such networks are required to meet. Known methods of provisioning rely on exhaustively listing the mesh network states which would adversely impact the service offered by a proposed network design as part of simulating the performance of the proposed network design—this is an error prone exercise since relevant network states can be missed. A simulation technique is proposed in which the network state after each event is represented by a weighted graph indicating a measure of path cost for each of the links in the mesh network. A graph searching algorithm is applied to seek a path across the graph, thereby systematically exploring paths over mesh network which could provide a suitable route for the service in the simulated network state represented in the graph. Networks are thus provisioned which meet stringent performance criteria without being over-engineered. |
| US11424991B2 |
Change impact simulation analysis
A system for simulating network configurations includes data processing hardware and memory hardware in communication with the data processing hardware. The memory hardware stores instructions that when executed on the data processing hardware cause the data processing hardware to perform operations. The operations includes receiving one or more parameter changes for a production network model of a network. The operations also include generating a simulation network model including the one or more parameter changes. Another operation includes analyzing the simulated network flow within the simulation network model. The operations also include generating a report including an impact of the parameter changes on the network. The operations may also include receiving a production network log including a recorded workflow for the production network model and simulating the production workflow of the production network log within the simulation network model to generate a simulated network log. |
| US11424989B2 |
Machine-learning infused network topology generation and deployment
Techniques are described herein for deploying, monitoring, and modifying network topologies comprising various computing and network nodes deployed across multiple workload resource domains. A deployment system may receive operational data from a network topology deployed across multiple workload resource domains, such as public or private cloud computing environments, on-premise data centers, and the like. The operational data may be provided to a trained machine-learning model, and output from the trained model may be used, along with constraint inputs and resource inventories of the workload resource domains, to determine updated topology models which may be deployed within the workload resource domains. |
| US11424988B2 |
Dynamic assignment of signals to ports in an access platform
Signals may be forwarded to a variety of ports for transmission. The signals may be modulated for transmission. The forwarding of signals to ports may be accomplished by forwarding the signals to one or more signal modulators using a processing unit. The mapping of signals to ports may change responsive to a triggering event. |
| US11424987B2 |
Segment routing: PCE driven dynamic setup of forwarding adjacencies and explicit path
An apparatus and method for path creation element driven dynamic setup of forwarding adjacencies and explicit path. In one embodiment of the method, a node receives an instruction to create a tunnel between the node and another node. The node creates or initiates the creation of the tunnel in response to receiving the instruction, wherein the tunnel comprises a plurality of nodes in data communication between the node and the other node. The node maps a first identifier (ID) to information relating to the tunnel. The node advertises the first ID to other nodes in a network of nodes. |
| US11424983B2 |
Dynamically reconfiguring data plane of forwarding element to account for operating temperature
Some embodiments of the invention provide a network forwarding element that can be dynamically reconfigured to adjust its data message processing to stay within a desired operating temperature or power consumption range. In some embodiments, the network forwarding element includes (1) a data-plane forwarding circuit (“data plane”) to process data tuples associated with data messages received by the IC, and (2) a control-plane circuit (“control plane”) for configuring the data plane forwarding circuit. The data plane includes several data processing stages to process the data tuples. The data plane also includes an idle-signal injecting circuit that receives from the control plane configuration data that the control plane generates based on the IC's temperature. Based on the received configuration data, the idle-signal injecting circuit generates idle control signals for the data processing stages. Each stage that receives an idle control signal enters an idle state during which the majority of the components of that stage do not perform any operations, which reduces the power consumed and temperature generated by that stage during its idle state. |
| US11424978B2 |
Fast forwarding re-convergence of switch fabric multi-destination packets triggered by link failures
A network device receives multi-destination packets from a first node and forwards at least a first of the multi-destination packets to another network device using a first multi-destination tree with respect to the network device. The network device detects that a link associated with the first multi-destination tree satisfies one or more criteria and, in response to detecting that the link satisfies the one or more criteria, selects a second multi-destination tree with respect to the network device. The network device forwards at least a second of the multi-destination packets to the other network device using the second multi-destination tree. |
| US11424977B2 |
Method and system for performing effective orchestration of cognitive functions in distributed heterogeneous communication network
This disclosure relates to method and system for performing effective orchestration of cognitive functions (CFs) in a distributed heterogeneous communication network. In one embodiment, the method may include determining a fault or a performance issue and associated causes, related to a set of network slices in the distributed heterogeneous communication network or a set of services across the set of network slices, using CFs associated with each of the set of services or with each of the set of network slices. The method may further include determining possible resolutions for the fault or the performance issue based on the associated causes, identifying a resolution by evaluating each of the possible resolutions for at least one of a suitability to or an impact on the set of services or the set of network slices, and implementing the resolution on one or more affected network segments of the set of network slices. |
| US11424972B2 |
User terminal and radio communication method
In future radio communication systems, an uplink control channel will be transmitted properly. A user terminal has a receiving section that receives frequency hopping information, which indicates whether frequency hopping for an uplink control channel is enabled or not, and a control section that applies at least one of a spreading factor for a time-domain orthogonal cover code, a configuration of a demodulation reference code and a base sequence, to the uplink control channel, based on the frequency hopping information. |
| US11424970B1 |
Converting GMSK impulse responses and optimal sequences
Optimal GMSK training sequences are generated by applying a base sequence to the in-phase component of the even samples and rotating the base sequence by 2k-1 and applying the second sequence to the quadrature component of the odd samples. Using the optimal GMSK training sequence a channel estimate can be generated. Filtering the channel estimate converts the channel impulse response to one that can be used with a non-GMSK signal e.g. PSK or QAM. |
| US11424968B1 |
Retimer training during link speed negotiation and link training
Disclosed retimer modules and methods enable equalizer training during link speed negotiation. One illustrative retimer module includes: an analog to digital converter that uses a sampling clock to digitize a receive signal; an equalizer that converts the digitized receive signal into an equalized signal; a decision element that derives a receive symbol stream from the equalized signal; and a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed. |
| US11424967B2 |
Communication device, communication method thereof, information processing device, control method thereof, and computer-readable storage medium
A communication device communicates a radio frame including a preamble and a data field of a physical layer (PHY). The preamble includes an L-STF (Legacy Short Training Field), an L-LTF (Legacy Long Training Field), an L-SIG (Legacy Signal Field), an EHT-SIG-A (Extremely High Throughput Signal A Field), an EHT-STF, and an EHT-LTF, and the EHT-SIG-A includes a field indicating a standard that the radio frame complies with. |
| US11424960B1 |
Exponential scaling for wireless roaming events in facilities
Techniques for a scalable wireless network feature for maintaining communications between wireless devices accessing a facility are described herein. A virtual partition for each wireless virtual local area network (VLAN) of a plurality of VLANs may be maintained. A virtual partition is configured to process mapping requests from one or more wireless devices of a particular VLAN of the VLANs. A threshold may be maintained that is associated with roaming per second events by the one or more wireless devices of the facility. A new virtual partition for a new VLAN may be instantiated based on information from the one or more wireless devices indicating that the roaming per second events exceed the threshold. One or more components of an intermediate distribution frame may be updated with mapping data to utilize with new wireless devices accessing the facility and for communicating with the new virtual partition for the new VLAN. |
| US11424957B2 |
Relay device
A relay device, connected to another relay device by a communication line, includes: multiple ports having two redundant ports connected to communication lines for providing redundant transfer paths between relay devices; a disruption determination unit determining whether a frame transmitted from a target relay device and received through one of the redundant ports is disrupted; an abnormality transmitter transmitting an abnormality detection frame to the target relay device when the frame is disrupted; a response receiver determining whether a response frame is received from the target relay device after the abnormality transmitter transmits the abnormality detection frame; and an abnormality determination unit determining that an abnormality occurs in one of the communication lines between the target relay device and the relay device when the response frame is not received. |
| US11424956B2 |
Transmission system for control data
A control bus (165) permits the transmission of a message (205) of a predetermined message length. A method (300) for transmitting pieces of information on the control bus (165) includes transmitting a message (205). The message includes a first field (210) and a second field (215). The first field (210) contains a variable reference to a type of information, and the second field (215) contains a piece of information of the type of information referred to in the first field (210). |
| US11424949B2 |
Point of entry (POE) splitter circuitry
The present invention is directed to a CATV & MoCA® device, such as a passive, point of entry (POE) splitter or a RF amplifier. In the passive, POE splitter, a resistive splitter network connects plural “MoCA® only” ports, e.g., four, five or eight, to two or more “MoCA® and CATV” ports. The MoCA® only ports and MoCA® and CATV ports are connected to a MoCA® rejection filter, which is in turn connected to an input connected to a service provider. In the passive, POE splitter or the RF amplifier, an intuitive female coaxial port layout and marking scheme assists technicians with correctly connecting the POE splitter or RF amplifier to the correct coaxial cables at a customer's premises. The port layout also simplifies the circuitry design parameters on a printed circuit board (PCB) by orienting the “CATV & MoCA®” output ports at similar distances from a CATV input port of the POE splitter or RF amplifier. |
| US11424948B2 |
Managing communication between gateway and building automation device
A method for managing communication with a building automation device, the method being performed in a gateway, the method including the steps of: establishing communication with the building automation device over a first communication protocol; installing executable software instructions on the building automation device over the first communication protocol to provide a capability to communicate over a second communication protocol; and establishing communication with the building automation device over the second communication protocol. |
| US11424946B2 |
System and method for improving content fetching by selecting tunnel devices
A method for fetching a content from a web server to a client device is disclosed, using tunnel devices serving as intermediate devices. The tunnel device is selected based on an attribute, such as IP Geolocation. A tunnel bank server stores a list of available tunnels that may be used, associated with values of various attribute types. The tunnel devices initiate communication with the tunnel bank server, and stays connected to it, for allowing a communication session initiated by the tunnel bank server. Upon receiving a request from a client to a content and for specific attribute types and values, a tunnel is selected by the tunnel bank server, and is used as a tunnel for retrieving the required content from the web server, using standard protocol such as SOCKS, WebSocket or HTTP Proxy. The client only communicates with a super proxy server that manages the content fetching scheme. |
| US11424944B2 |
Transaction-enabled systems for providing provable access to a distributed ledger with a tokenized instruction set
Transaction-enabling systems including a controller are disclosed. The controller can access a distributed ledger including an instruction set, tokenize the instruction set, interpret an instruction set access request, and, in response to the instruction set access request, provide a provable access to the instruction set. |
| US11424942B2 |
Blockchain integrated stations and automatic node adding methods and apparatuses
A blockchain integrated station receives a first configuration instruction after accessing a certificate authority network. The blockchain integrated station initiates an authentication application to a certificate authority center of the certificate authority network based on a first network address indicated in the first configuration instruction. The blockchain integrated station receives a digital certificate from the certificate authority center after the certificate authority center determines that the authentication application passes verification. The blockchain integrated station receives a second configuration instruction after accessing a blockchain network. The blockchain integrated station sends the digital certificate to a first blockchain node in the blockchain network based on a second network address indicated in the second configuration instruction, where the digital certificate is used to trigger the first blockchain node to add the blockchain integrated station as a new blockchain node in the blockchain network. |
| US11424939B1 |
Privacy preserving attestation
Described implementations obtain a proof of valid attestation data. The attestation data may include configuration data of a host computing system. A prover service may receive the attestation data. The prover service may generate a proof to prove that the attestation data includes valid configuration data of the host computer system, without revealing sensitive or private information of the host computing system. The proof may be a zero-knowledge proof. |
| US11424938B1 |
Credentialed miners for a blockchain
A system for credentialing a miner for a blockchain system is provided. The system interacts with a Trusted Witness to obtain a witness statement attesting to the identity of the miner. The witness statement includes a miner public key of the miner and a signed miner public key signed using the corresponding miner private key. The system provides to a notary the witness statement and signed bylaws signed using the miner public key. The system receives from the notary a digital identity signed by the notary that includes an identification of the notary, the witness statement, and the signed bylaws. The miner uses the digital identity when participating in mining for the blockchain system. |
| US11424935B2 |
Tampering detection system and method for detecting tampering
A tampering detection system according to an embodiment includes one or more first terminals connectable to any of one or more peers and one or more detectors. The first terminal includes an acquiring unit acquiring a block hash in a blockchain from the peer, and a transmitting unit transmitting a first transaction record that contains a first digitally signed message containing the block hash and data based on a transaction content of the first terminal and contains a digital signature for the first digitally signed message, to the peer. The detector includes a receiving unit receiving the blockchain from the peer and a detecting unit detecting blockchain tampering if the digital signature contained in the first transaction record in a block of the blockchain is invalid or if the blockchain contains no block hashes identical to the block hash contained in the first transaction record in the block. |
| US11424934B2 |
Securely distributing medical prescriptions
A medical treatment machine, such as a dialysis machine (e.g., a home dialysis machine, such as a home hemodialysis machine or a home peritoneal dialysis machine) can receive a digital prescription file that defines parameters of a medical treatment to be administered to a patient. The digital prescription file can be prepared and delivered in such a way that the medical treatment machine can confirm that the issuer (e.g., provider) of the digital prescription file is an authorized issuer without having any a priori knowledge of the particular issuer. The digital prescription file can be delivered irrespective of the inherent security (or lack thereof) of the transmission medium in a tamper-evident format using minimal resources necessary to verify the validity of the digital prescription file and its issuer. The digital prescription file may be delivered to the dialysis machine using a network cloud-based connected health system. |
| US11424933B2 |
Method and apparatus for exchanging messages
A method and to an apparatus for achieving cryptographic protection of a plurality of messages in a message exchange, for example, in particular the cryptographic protection being implemented by means of digital signatures and nonces is provided. The nonces are not transmitted directly, but rather can be reproducibly calculated from preceding messages, wherein a checksum of a previous message is also considered for each nonce. Consideration is implemented in such a way that cryptographical calculations in particular intended for the creation of the digital signature and the nonce may be calculated one single time and not separately for the nonce and the digital signature. |
| US11424930B2 |
Systems and methods for providing account information
Systems and methods for accessing account information are provided. For example, an indication to launch an application that may provide account information may be received. A determination may be made regarding whether the indication is an initial interaction with the application. If the indication is an initial interaction, one or more credentials may be received via an interface that may be displayed via the application. If the indication is not the initial interaction, a token may be accessed. A request that may include the credentials or token may then be generated and transmitted such that credentials or token may be used to authenticate a device that includes the application and a user thereof, a new token may be generated, and a response with the new token and/or account information may be transmitted. The account information may then be displayed by an interface of the application. |
| US11424928B2 |
Preventing malformed ciphertext attacks on privacy preserving biometric authentication
Embodiments may include techniques to prevent illegal ciphertexts using distance computations on homomorphic and/or functional encrypted templates while detecting whether the resulting distance does not meet requirements for validity. For example, a method may comprise receiving and storing enrollment information from a client computer system, the enrollment information comprising an encrypted enrollment template of authentication data and a plurality of randomly generated encrypted templates, receiving an additional encrypted template to be used to authenticate the user from the client computer system, authenticating the user by determining distances between the received additional encrypted template and the stored encrypted enrollment template and the each of the stored plurality of randomly generated encrypted templates, and determining that authentication is successful when the received additional encrypted template meets distance requirements relative to the stored encrypted enrollment template and the each of the stored plurality of randomly generated encrypted templates. |
| US11424926B2 |
Tokenized encryption system for preserving anonymity while collecting behavioral data in networked systems
The present disclosure is generally directed to systems and methods for providing privacy to a user of a user device that is used for interacting with a networked software platform. A server computer coupled to the user device receives a hashed device ID of the device and generates a unique user ID in the form of a unique number. The user ID can be used by the server and other entities to gather information related to the activities of the user with respect to the networked software platform, which can be, for example, a video game platform, a social media platform, or a health-related diagnostic tool. The identity of the user remains anonymous during the information gathering procedures because neither the device ID nor the identity of the user is transmitted over the network when the user is participating in activities of the networked software platform. |
| US11424919B2 |
Protecting usage of key store content
Protecting usage of key store content at a given user device of an end user includes receiving the key store content at the given user device. The key store content includes key materials encrypted using encryption credentials compatible with the given user device. The key store content is in a format compatible with the given user device. The encrypted key materials of the key store content are imported to a protected key store of the given user device, wherein all the key materials of the key store content are imported at one go. The key materials are stored at the protected key store in the encrypted form, and are non-exportable from the key store. Internally within the protected key store, one or more key store integrated services of the given user device are allowed to access the non-exportable key materials for use, via key references only. |
| US11424907B2 |
Countermeasures for side-channel attacks on protected sign and key exchange operations
Embodiments are directed to countermeasures for side-channel attacks on protected sign and key exchange operations. An embodiment of storage mediums includes instructions for commencing a process including an elliptic curve scalar multiplication (ESM) operation including application of a secret scalar value; splitting the secret scalar value into two random scalar values; counting a number of leading ‘0’ bits in the scalar value and skipping the number of leading ‘0’ bits in processing; performing an ESM iteration for each bit of the secret scalar value beginning with a most significant ‘1’ bit of the scalar value including a Point Addition operation and a Point Double operation for each bit on randomized points; performing ESM operation dummy iterations equal to the number of leading ‘0’ bits; and returning an output result for the ESM operation. |
| US11424905B1 |
Retimer with mesochronous intra-lane path controllers
First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal. |
| US11424902B2 |
System and method for synchronizing nodes in a network device
System and method for synchronizing a plurality of nodes to a timing signal using a daisy-chain network having a forward transmission path and a reverse transmission path connected at a midpoint. Latency of the timing signal to the midpoint of the daisy-chain network is determined, a respective latency of the timing signal from the node to the midpoint of the daisy-chain network is determined, and a respective timing offset for each of the plurality of nodes is calculated. A local time-of-day counter at each of the plurality of nodes is adjusted based upon the respective timing offset of the node to synchronize the plurality of nodes to the timing signal. |
| US11424901B2 |
Method and apparatus for synchronous signaling between link partners in a high-speed interconnect
Loop timing is performed in a Reconciliation Sublayer (RS) so that the transmit clock frequency can be adjusted to be equal to the receive clock frequency for the entire PHY (including the physical coding sublayer (PCS)). One of two partners is selected to be the timing Slave to the other. If only one partner is capable of loop timing, that partner becomes the Slave. If both partners are capable of loop timing, symmetry breaking can be used to determine which partner should become Slave. |
| US11424891B1 |
Method and system for multi-carrier packet communication with reduced overhead
A method and system for minimizing the control overhead in a multi-carrier wireless communication network that utilizes a time-frequency resource is disclosed. In some embodiments, one or more zones in the time-frequency resource are designated for particular applications, such as a zone dedicated for voice-over-IP (VoIP) applications. By grouping applications of a similar type together within a zone, a reduction in the number of bits necessary for mapping a packet stream to a portion of the time-frequency resource can be achieved. In some embodiments, modular coding schemes associated with the packet streams may be selected that further reduce the amount of necessary control information. In some embodiments, packets may be classified for transmission in accordance with application type, QoS parameters, and other properties. In some embodiments, improved control messages may be constructed to facilitate the control process and minimize associated overhead. |
| US11424890B2 |
Method and system of wireless TDMA communication for industrial machine-to-machine communication
A communication method for wireless communication uses a TDMA (Time Division Multiple Access) super-frame structure for scheduling uplink and downlink transmissions between a first node and a second node, the second node receives receiving a downlink transmission from the first node and transmits an uplink response to the first node. The transmission of the uplink response is performed in an uplink frame of the super-frame structure. The uplink frame includes a field for uplink payload data and a field for time indicating data. The transmission of the uplink response includes transmitting time stamps in the time indicating data field, the time stamps indicating a time instance of the receiving of the downlink transmission, and the time instance of the transmitting of the uplink response. The time instances are determined using the clock of the second node. |
| US11424888B2 |
Demodulation reference signal configuration
Apparatuses, methods, and systems are disclosed for demodulation reference signal configuration. One apparatus (200) includes a receiver (212) configured to receive (502) a demodulation reference signal configuration for a physical downlink shared channel. The apparatus (200) also includes the receiver (212) configured to receive (504) a demodulation reference signal based on the demodulation reference signal configuration. |
| US11424885B2 |
Method and device used in UE and base station for wireless communication
The present disclosure provides method and device used in UE and base station for wireless communication. A UE receives a first signaling and then operates N radio signals respectively in N time-frequency resource blocks. The first signaling indicates N1 time-frequency resource blocks; the N1 time-frequency resource blocks respectively belong to N1 frequency sub-bands in frequency domain; any of the N time-frequency resource blocks is one of the N1 time-frequency resource blocks, N being a positive integer greater than 1 and no greater than N1; the N radio signals respectively comprise N first-type reference signals, and an antenna port for transmitting each of the N first-type reference signals is associated with a first antenna port. |
| US11424882B2 |
Method and device for wireless communication in UE and base station
A method and a device in a UE and a base station for wireless communications are provided in the present disclosure. A UE first receives a first signaling, the first signaling is used for indicating M first-type time window(s) in a first sub-band, and the M first-type time window(s) in the first sub-band is(are) reserved for a first-type reference signal, M being a positive integer; the UE then determines that it is only needed to receive the first-type reference signal in M1 first-type time window(s) of the M first-type time window(s) in a first sub-band, M1 being a positive integer no greater than the M. The present disclosure is advantageous in avoiding possible loss of performance in Unlicensed Spectrum resulting from belated determination of beam link failure due to the fact that the reference signal is not transmitted on time. |
| US11424875B2 |
Method and network for transferring wireless transmit/receive unit capability information
A base station and a method for use by a base station for receiving, from a network controller using an interface for communication between the base station and the network controller, a wireless transmit receive unit (WTRU) information transfer message, wherein the WTRU information transfer message includes uplink physical channel support information, frequency division duplex (FDD) and time division duplex (TDD) parameters including TDD specific parameters, hybrid automatic repeat request (HARQ) information, supported modulation scheme information, shared channel information, and based on the received WTRU information transfer message, transmitting information to the WTRU to control at least uplink transmissions of the WTRU. |
| US11424873B2 |
Uplink control information transmission method and apparatus for use in cellular mobile communication system
A communication method and apparatus of a terminal in a mobile communication system are provided. The communication method includes generating uplink control information for at least one activated cell; configuring, if the activated cell belongs to a Master Cell Group (MCG) under a control of a Master evolved Node B (MeNB), an uplink control channel based on the uplink control information of the activated cell belonging to the MCG; and transmitting the uplink control channel to a Primary Cell (PCell). |
| US11424868B2 |
Method and apparatus for user equipment processing timeline enhancement in mobile communications
Various solutions for processing timeline enhancement with respect to user equipment and network apparatus in mobile communications are described. An apparatus may determine a normal processing time. The apparatus may determine a specific processing time. The apparatus may use the normal processing time when performing an initial transmission. The apparatus may use the specific processing time when performing a retransmission. |
| US11424865B2 |
Variable-level integrity checks for communications in process control environments
The described methods and systems enable process control devices to transmit and receive device variable values in a manner that enables the receiving device to verify the integrity of the received values on a variable-by-variable basis. To facilitate verification of integrity, any desired number of variables in a message may have a data integrity check in the message. For each received value that has a data integrity check, the receiving device can calculate its own data integrity check based on the received value and a seed (known to both the transmitting and receiving devices), which it can then compare to the received data integrity check to verify if the received value has been altered during communication. |
| US11424864B2 |
Data packet retransmission method and apparatus
Data packet retransmission by a radio link control (RLC) protocol entity of a transmit end is described herein. The retransmission includes sending a target sequence number and a first data packet to a MAC entity of the transmit end and recording a quantity of times the target sequence number is transmitted to the MAC entity of the transmit end at an RLC layer. In accordance with receiving the target sequence number and a negative acknowledgement that are sent by the MAC entity, obtaining the RLC layer transmission count corresponding to the target sequence number. In accordance with determining the RLC layer transmission count is less than an RLC layer transmission threshold, sending a retransmission instruction based on the first data packet to the MAC entity. In accordance with a retransmission condition at the RLC layer being met, the RLC entity of the transmit end triggers retransmission at the RLC layer. |
| US11424860B2 |
Selection between code types for encoding information bits
Methods and apparatus are provided for selecting a code type. A type of code is selected from a set of code types to use as an inner code for a concatenated encoding scheme for encoding information bits of a channel, wherein the selection is based on one or more channel coding parameters including a false alarm detection objective for the channel. A codeword is generated by encoding the information bits using the type of codes selected as the inner code and an outer code. The generated codeword is transmitted. |
| US11424858B2 |
Transmitting apparatus and modulation method thereof
A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. |
| US11424854B2 |
PDCCH sending method and apparatus, and PDCCH blind detection method and apparatus
A PDCCH sending method and apparatus, and a PDCCH blind detection method and apparatus are provided. The method includes: determining, by a terminal device, a blind detection capability of the terminal device; performing, by the terminal device, PDCCH blind detection in one time unit based on PDCCH configuration information and the blind detection capability of the terminal device, where the blind detection capability of the terminal device includes N maximum quantities, of blind detection times, corresponding to N subcarrier spacings in the time unit and/or N maximum quantities, of channel estimation control channel elements CCEs, corresponding to the N subcarrier spacings in the time unit, where N is a positive integer. |
| US11424851B2 |
Dynamic bit width determination for resource block group mask
Methods, systems, and devices for wireless communications are described. Some wireless communications network may operate in accordance with an open-RAN (ORAN) network specification which may support functional splitting between the ORAN distributed unit (O-DU) and the ORAN radio unit (RU) located at a base station. The O-DU may communicate with the O-RU using control messaging, and the O-DU may signal whether various resource block groups are used for data allocation by enabling or disabling bits in a bit mask parameter in a header of the control message. To increase communications efficiency and reduce overhead, the O-DU may dynamically configure the number of bits included in a bit mask based on a radio access technology (RAT) type. The O-DU may determine the size of the bit mask in the control message based on the RAT type and may generate the control message that includes the bit mask. |
| US11424848B2 |
Flexible grid optical spectrum transmitter, receiver, and transceiver
A management system configured to manage one or more optical transmitters in an optical network utilizing an optical spectrum, wherein the management system is configured to track at least one of said multiple optical transmitters by specifying a spectral position and spectral width of the portion of the optical spectrum containing a coherent optical signal generated by the at least one optical transmitter, wherein the spectral width is ‘n’ bins where n is an integer greater than 1 and each bin is a same size. |
| US11424847B2 |
Time and wavelength division multiplexing
A method for scheduling resources for a Wavelength Division Multiplexed, WDM, Passive Optical Network, PON. The WDM PON comprises a central hub (201) and a plurality of remote Optical Network Terminals, ONTs, (220) handling different types of communications traffic. The method (450) comprises receiving (452) a notification message from the plurality of remote Optical Network Terminals, ONTs, indicating a loading status of the ONT, and allocating (454) one or more slots to a plurality of the ONTs based on the received notification messages from the ONTs, wherein the plurality of ONTs (220) handle different types of communications traffic. The slots (301) are allocated based on the received notification messages as a time slot which is time division multiplexed with further time slots, and the slots are further allocated based on the received notification messages as an optical wavelength of a plurality of optical wavelengths of the WDM PON. |
| US11424845B2 |
Electronic apparatus and control method thereof
An electronic apparatus includes an interface circuitry; a display; a memory storing one or more instructions; and a processor configured to execute the one or more instructions to: receive a broadcast signal of any one of a plurality of channels through the interface circuitry, control the display to display an image of a content based on the received broadcast signal, identify timing when the content switches from a first content to a second content having a different type than the first content based on a change in a video characteristic defined corresponding to the type of the content, and perform a first operation related to the second content based on the identified timing. |
| US11424843B2 |
Cellular signal degradation based detection of events
Methods and apparatus are provided for determining first frequency band signal strengths and second frequency band signal strengths for multiple devices connected to a cellular base station. Variations that fall within a threshold for the first frequency band signal strength and outside the threshold for second frequency band signal strengths may indicate a casual factor attenuating signals more at one frequency than the other. Alerts can be triggered for the causal factor to further verify the causal factor or notify appropriate authorities. |
| US11424842B2 |
Signal analysis method and signal analysis module
A signal analysis method is described. The signal analysis method includes: receiving a time-and-value discrete input signal, the input signal being associated with a signal source; determining at least one jitter component of the input signal; determining a step response based on the input signal, the step response being associated with at least the signal source; determining a counter function based on the step response, the counter function being configured to cancel error terms in a finite-time transform of the step response to frequency domain; superposing the step response and the counter function, thereby obtaining a modified step response; and transforming the modified step response to frequency domain, thereby obtaining a transfer function being associated with at least the signal source. Further, a signal analysis module for analyzing a time-and-value discrete input signal being associated with a signal source is described. |
| US11424841B1 |
System and method for measuring phase noise
A system and method are provided for measuring absolute phase noise of a test signal from a DUT using a reference source for generating an RF reference signal, a mixer for mixing the RF reference signal and an input signal, an adjustable DC voltage source for outputting a DC voltage, and a PLL for maintaining a 90 degree quadrature between the RF reference and input signals. The method includes mixing RF calibration signals and the RF reference signal to provide calibration phase signals, at least one of the RF calibration signals having one-tone AM modulation; monitoring modulation tone frequency of the one-tone AM modulation; adjusting the DC voltage output by the adjustable DC voltage source to minimize a voltage level of the tone frequency being monitored; mixing the test signal and the RF reference signal to provide a measurement phase signal for measuring absolute phase noise of the test signal. |
| US11424836B2 |
Path computation engine and method of configuring an optical path for quantum key distribution
A path computation engine, PCE, (100) for an optical communications network comprising a plurality of nodes and a plurality of links. The PCE comprises a processor and memory comprising instructions executable by the processor whereby the PCE is operative to: receive a request to configure a quantum key, Qkey, path from a first node to a second node in the optical communications network for a quantum key distribution, QKD, signal for a quantum key for a secure data transmission signal; calculate a feasible Qkey path from the first node to the second node that is logically different to a traffic path from the first node to the second node for the secure data transmission signal, wherein the Qkey path is feasible if an optical signal power originating from the secure data transmission signal within the Qkey path, caused by optical interference of the secure data transmission signal with the QKD signal, is below a predetermined threshold value; and generate a control signal comprising instructions arranged to configure said feasible Qkey path. |
| US11424830B2 |
Laser module for optical data communication system
A laser module includes a laser source and an optical marshalling module. The laser source is configured to generate and output a plurality of laser beams. The plurality of laser beams have different wavelengths relative to each other. The different wavelengths are distinguishable to an optical data communication system. The optical marshalling module is configured to receive the plurality of laser beams from the laser source and distribute a portion of each of the plurality of laser beams to each of a plurality of optical output ports of the optical marshalling module, such that all of the different wavelengths of the plurality of laser beams are provided to each of the plurality of optical output ports of the optical marshalling module. An optical amplifying module can be included to amplify laser light output from the optical marshalling module and provide the amplified laser light as output from the laser module. |
| US11424829B2 |
Systems and methods for interfacing optical line terminals with optical modules
Circuitry of an optical line terminal (OLT) can be controlled to be compatible with optical modules of different optical protocols having different electrical connectivity requirements. In some embodiments, the OLT has a controller that is configured to communicate with an optical module plugged or otherwise mated with a socket of the OLT in order to discover a module type of the optical module. Based on the detected module type, the controller is configured to control the electrical characteristics of the OLT circuitry so that it is compatible with the electrical and operational requirements of the optical module. Thus, the OLT is compatible for use with any of a plurality of optical module types. |
| US11424827B1 |
Optical tracking system
An optical detector system provides output to an optical tracking system to facilitate optical communications by tracking a beam of incoming light using a fast-steering mirror (FSM). The optical detector system comprises an array of optical photodetectors, such array comprising one or more quad cells. The incoming light passes through one or more optical elements to generate a specified beam shape, such as a bar or cross, on the array. The resulting output from the array is highly responsive to changes in position of the reshaped beam on the array. As a result, noise equivalent angle (NEA) of the optical detector system representing pointing error is substantially reduced. A reduction in NEA facilitates more precise alignment, allowing incoming light to be aligned to a smaller area. For example, the incoming light may be aligned to a single mode optical fiber connected to a receiver system. |
| US11424825B2 |
Multi-wavelength power sensing
In some examples, a multi-wavelength power meter may include a first coupler to separate optical signals from an optical line terminal and an optical network terminal to ascertain a reduced percentage of total power related to the optical signals. A second coupler may receive the separated optical signals, combine the separated optical signals, and output the combined optical signals to an optical fiber. A filter may be communicatively connected to the optical fiber to isolate at least one specified wavelength or wavelength range of the combined optical signals. A photodiode may be communicatively connected to the filter for power measurement of the at least one specified wavelength or wavelength range. |
| US11424824B2 |
OSNR spectrum estimation apparatus, OSNR spectrum estimation method, and program
An OSNR spectrum estimation apparatus includes an OSNR estimation unit configured to cause an optical node to estimate an OSNR of a predetermined transmission line using a probe light of a predetermined wavelength in a predetermined number of wavelength channels, the predetermined number being less than the number of all wavelength channels; and an OSNR spectrum calculation unit configured to calculate an OSNR spectrum of all the wavelength channels from OSNRs of the predetermined number of wavelength channels measured by the optical node. |
| US11424823B2 |
Time slot multiplexing method and apparatus, and communication device
A method and an apparatus for time slot multiplexing, and a communication device. At least one multiplexing node group in a subnet of a TDMA communication system may be determined according to a connection relationship among all nodes in the subnet, where a shortest communication link between every two nodes in each multiplexing node group includes at least the preset quantity of nodes, the preset quantity of nodes includes the two nodes, and the preset quantity is no less than 4. For each multiplexing node group, a multiplexing time slot allocated to the multiplexing node group is determined, and each node in the multiplexing node group is controlled to transmit data in the multiplexing time slot. The time slots can be shared by the nodes in the multiplexing node group, and therefore multiple nodes can transmit data in the multiplexing time slot. |
| US11424822B2 |
Modular channelizer
An example of a channelizer includes a plurality of receiver circuits, an individual receiver circuit including a frequency demultiplexer that is configured to demultiplex a plurality of subchannels and a time-division demultiplexer coupled to the frequency demultiplexer, the time-division demultiplexer configured to time-division demultiplex the plurality of subchannels to provide a plurality of time-division outputs, an individual time-division output including portions of data from each of the plurality of subchannels; and a plurality of switch circuits, each configured to receive a different time-division output of the plurality of time-division outputs from the individual receiver. |
| US11424821B2 |
Layer-2 connectivity from switch to access node/gateway
Methods, systems, and apparatuses for providing layer-2 connectivity through a non-routed ground segment network, are described. A system includes a non-autonomous gateway in communication with a satellite configured to relay data packets. The non-autonomous gateway is configured to receive the data packets from the satellite at layer-1 (L1) of the OSI-model, generate a plurality of virtual tagging tuples within the layer-2 packet headers of the plurality of data packets. The non-autonomous gateway is further configured to transmit, at layer-2 (L2) of the OSI-model, the virtually tagged data packets. Each of the packets may include a virtual tagging tuple and an entity destination. The system further includes a L2 switch in communication with the non-autonomous gateway. The L2 switch may be configured to receive the data packets and transmit the data packets to the entity based on the virtual tuples associated with each of the data packets. |
| US11424819B2 |
Data broadcast method and apparatus
A data broadcast method includes obtaining, by a satellite base station, a plurality of pieces of data that are to be broadcast. The plurality of pieces of data are a same type of data including compensation values of Doppler frequency shifts, change rates of Doppler frequency shifts, transmission delays, change rates of transmission delays, timing advances TAs, change rates of TAs, or angles of a plurality of beams that respectively correspond to a plurality of beams generated by the satellite base station. The satellite base station determines reference data and a difference between each piece of data in the plurality of pieces of data and the reference data. The satellite base station sends first indication information and a plurality of pieces of second indication information to a terminal device. The first indication information indicates the reference data. |
| US11424817B2 |
Enhanced LDACS system having mesh network topology and associated methods
An enhanced L-band Digital Aeronautical Communications System (LDACS) may include LDACS ground stations, and LDACS airborne stations configured to communicate with the LDACS ground stations. Each LDACS airborne station may be configured to collect respective routing metrics, and each LDACS airborne station may be selectively operable as at least one of a host and client. The enhanced LDACS may also include a peer-to-peer server configured to establish a mesh network topology from the LDACS airborne stations based upon the routing metrics, and selectively operate each LDACS airborne station as at least one of the host and client. |
| US11424815B2 |
RF signal repeater device management for 5G wireless networks
A method for performing monitoring, commissioning, upgrading, analyzing, load balancing, remediating, and optimizing the operation, control, and maintenance of a plurality of remotely located RF signal repeater devices in a wireless network arranged to operate as an Internet of Things (IoT) network. Electronic RF signal repeater devices are employed as elements in the wireless network and communicate wireless radio frequency (RF) signals for a plurality of users. An RF signal repeater device may be arranged to operate as a donor unit device that provides RF signal communication between one or more remotely located wireless base stations, or other donor unit devices on the wireless network. Also, an RF signal repeater device may be arranged to operate as a service unit device that provides wireless RF signal communication between one or more user equipment devices (UEs) and a donor unit device or a wireless base station. |
| US11424812B1 |
Video based channel state information
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a video-based channel state information (VCSI) configuration. The UE may cause a camera to capture channel state information (CSI) video based at least in part on one or more VCSI measurement parameters indicated in the VCSI configuration. The UE may derive, from the CSI video, one or more VCSI measurements using a machine learning model indicated in the VCSI configuration. The UE may transmit a VCSI report that includes the one or more VCSI measurements. Numerous other aspects are described. |
| US11424810B2 |
Method and device for random access for beam failure recovery
A method for random access for beam failure recovery. In the method, a random access configuration for the beam failure recovery is received. In the event of a beam failure, a random access procedure is performed according to the random access configuration. |
| US11424809B2 |
Apparatus and method for beam failure recovery
The disclosure relates to technology for assigning resources to user equipment for a beam failure recovery by a base station. The base station identifies a beam failure random access channel (BRACH) resource holding beam correspondence with a synchronization signal (SS) block resource covering the user equipment, and assigns the user equipment one or more BRACH preambles for each BRACH resource assigned to the user equipment, excluding the BRACH resource holding beam correspondence with the SS block resource covering the user equipment. |
| US11424807B2 |
Enhanced frequency compression for overhead reduction for CSI reporting and usage
In accordance with an example embodiment of the present invention, a method comprising: selecting, by a user equipment, a subset of linear combination coefficients from a linearized two-dimensional matrix having columns of frequency domain components and rows of spatial beams components for channel state information determination, wherein the number of linear combination coefficients in the subset is less than all of the linear combination coefficients; determining indication comprising information associated with column indices of the selected subset of linear combination coefficients from the linearized two-dimensional matrix, wherein the indication excludes the index of the column with lowest index of the linearized two-dimensional matrix; determining compressed channel state information comprising locations in the linearized two-dimensional matrix of the subset of linear combination coefficients and corresponding values of the linear combination coefficients at those locations; and reporting, from the user equipment toward the base station, the compressed channel state information. |
| US11424804B2 |
UE capability space frequency multi TRP user equipment peak to average power ratio reduction
A configuration to reduce a UE PAPR due to a transmission of a PAPR reduction signal into a UE null space. The apparatus establishes a connection with a base station. The apparatus transmits, to the base station, an SFMT report including an indication of a capability of the UE to process a signal form the base station that includes an SFMT transmission. The apparatus receives, from the base station, a downlink PAPR reduction signal based on the SFMT report of the UE. |
| US11424803B2 |
Communication method and device
Example communication methods and devices are provided. One example method includes a first device determines a first channel state information CSI report based on a precoding matrix type, where the precoding matrix type is a compressed type or an uncompressed type. The first device sends the first CSI report to a second device, where the first CSI report includes a CSI part 1 and a CSI part 2, the CSI part 1 indicates a number of bits of the CSI part 2 and the precoding matrix type, the CSI part 2 indicates wideband precoding matrix indicator (PMI) information, the wideband PMI information indicates an oversampling factor of a preset orthogonal beam vector and/or an index of the preset orthogonal beam vector, and the preset orthogonal beam vector is a spatial-domain orthogonal basis vector selected by the first device from a spatial-domain basis vector set. |
| US11424801B2 |
Techniques for transmitting sidelink channel state information feedback
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a sidelink channel state information (CSI) reference signal (CSI-RS). The UE may transmit, based at least in part on the sidelink CSI-RS, a CSI report on a physical sidelink feedback channel. Numerous other aspects are provided. |
| US11424797B2 |
Data transmission method and apparatus
Disclosed are a data transmission method and apparatus. The method includes: receiving, by a terminal, a media access control (MAC) signaling sent by a base station; receiving, by the terminal, downlink control information (DCI) sent by the base station; searching for a preset mapping relationship by the terminal; determining, by the terminal, a target beam used by the target antenna panel to transmit data according to the target beam indication information corresponding to the target antenna panel; and transmitting data by the terminal with the base station via the target beam corresponding to the target antenna panel. |
| US11424795B2 |
Precoding a transmission from a multi-panel antenna array
The invention relates to a wireless communication device configured for use in a wireless communication system, wherein, based on one or more structural properties of a multi-panel antenna array describing how the antenna array is structured into multiple panels, a precoder is selected to be applied for a transmission from the multi-panel antenna array; and wherein an information indicative of the determined precoder is signaled to a transmit radio node; the invention further refers to a transmit radio node configured for transmitting via a multi-panel antenna array in a wireless communication system, wherein signaling indicating one or more structural properties of a multi-panel antenna array describing how the antenna array is structured into multiple panels is transmitted to the wireless communication device. |
| US11424794B1 |
Methods and systems for wireless communication in a reflective environment
A method for wireless communication in a reflective environment includes (a) receiving first wireless signals at a first antenna assembly at least partially via a first reflective environment, (b) generating a first electrical signal from a first antenna element of the first antenna assembly in response to the first wireless signals, the first antenna element having a first polarization, (c) generating a second electrical signal from a second antenna element of the first antenna assembly in response to the first wireless signals, the second antenna element having a second polarization different from the first polarization, (d) shifting phase of at least one of the first electrical signal and the second electrical signal, and (e) after shifting phase, combining at least the first electrical signal and the second electrical signal to generate a combined electrical signal. |
| US11424791B2 |
Machine learning model selection in beamformed communications
Methods, systems, and devices for wireless communications are described in which a base station may develop a number of different predictive models for each of a number of different functions. The different functions may be used to determine various beamforming parameters for beamformed communications between a user equipment (UE) and a base station. The base station may provide the models to a UE, and the UE may then use such models to determine values for one or more beamforming parameters. A same function (e.g., a beam prediction function to identify a transmit/receive beam for communications) may have multiple different models, which may be provided to the UE by the base station, which may be used based on particular channel conditions or locations of a UE. The UE or base station may select which model of the multiple predictive models is to be used for communications. |
| US11424785B2 |
Targeted rectangular conditioning
A vectoring controller for configuring a vectoring processor that jointly processes DMT communication signals to be transmitted over, or received from, a plurality of N subscriber lines according to a vectoring matrix. In accordance with an embodiment, the vectoring controller is configured, for given ones of a plurality of tones, to enable the given tone for direct data communication over a first set of N−Mk targeted lines out of the plurality of N subscriber lines, and to disable the given tone for direct data communication over a second disjoint set of Mk supporting lines out of the plurality of N subscriber lines, Mk denoting a non-null positive integer. The vectoring controller is further configured to configure the vectoring matrix to use an available transmit or receive power at the given tone over the second set of Mk supporting lines for further enhancement of data signal gains at the given tone over the first set of N−Mk targeted lines. |
| US11424783B2 |
Transceiver having radio-frequency front-end circuit, dedicated radio-frequency front-end circuit, and switchable matching circuit integrated in same chip
A transceiver includes a radio-frequency (RF) front-end circuit, a dedicated RF front-end circuit, and a switchable matching circuit. The RF front-end circuit deals with communications of at least a first wireless communication standard. The dedicated RF front-end circuit deals with communications of a second wireless communication standard only. The switchable matching circuit is coupled to the RF front-end circuit, the dedicated RF front-end circuit, and a signal port of a chip. The switchable matching circuit provides impedance matching between the signal port and the RF front-end circuit when the RF front-end circuit is in operation, and provides impedance matching between the signal port and the dedicated RF front-end circuit when the dedicated RF front-end circuit is in operation. The RF front-end circuit, the dedicated RF front-end circuit, and the switchable matching circuit are integrated in the chip. |
| US11424779B2 |
Heterogeneous bus bridge circuit and related apparatus
A heterogeneous bus bridge circuit and related apparatus are provided. The heterogeneous bus bridge circuit is configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses that are different from the RFFE bus. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). In examples discussed herein, the heterogeneous bus bridge circuit can be configured to selectively activate an auxiliary bus for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus. |
| US11424773B2 |
Low complexity transmitter structure for active antenna systems
Various embodiments disclosed herein provide for a low complexity transmitter structure for active antenna arrays by reducing the number of digital predistortion extraction loops that need to be performed. Digital predistortion (DPD) corrects any non-linearities in a power amplifier. By determining which power amplifiers have similar characteristics in an array, and thus may use similar predistortion coefficients, once the DPD coefficients are determine for one of the grouped power amplifiers, DPD can be performed on each of the grouped power amplifiers based on the DPD coefficients. |
| US11424768B2 |
Radio frequency module and communication device
A radio frequency module includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board; a power amplifier disposed on the module board; a low noise amplifier disposed on the module board; a transmission filter (a first acoustic wave filter) disposed on one of the first principal surface and the second principal surface; and a reception filter (a second acoustic wave filter) disposed on one of the first principal surface and the second principal surface. An absolute value of a temperature coefficient of frequency (TCF) of the transmission filter is smaller than an absolute value of a TCF of the reception filter, and a distance between the transmission filter and the power amplifier is shorter than a distance between the reception filter and the power amplifier. |
| US11424767B2 |
Out-of-band compensation of active electronic device
Systems and methods for controlling power amplifier (PA) performance metrics such as linearity and stability based on out-of-band feedback are presented. Various embodiments provide for synthesizing negative baseband termination using a feedback network between the drain and gate bias paths of the PA, so that the intermodulation distortion (IMD) is suppressed without an increase in system complexity. Other embodiments include a feedback network topology between the drain and gate bias paths of the PA that provides stability enhancement of the PA without the need for conventional stability networks in the radio frequency (RF) path. The out-of-band feedback nature of the approach means that the continuous wave (CW) RF performance is not perturbed, enabling conventional design techniques to be used for the input and output matching networks while enhancing aspects of the PA performance. |
| US11424766B1 |
Method and device for energy-efficient decoders
A method and device for energy-efficient decoders. The decoder device can include a plurality of decoder modules configured to process an input data signal having a plurality of forward error correction (FEC) codewords. This plurality of decoder modules can include at least a first decoder followed by a second decoder. The first decoder can be low-power to first eliminate most of the errors of the codewords and the second decoder can be high-performance to correct the remaining errors. Alternatively, the first decoder can be high-performance to correct the codewords until the low-power decoder can correct the remaining errors. A classifier module can be included to determine portions of the codewords to be directed to any one of the plurality of decoder modules. These implementations can be extended to use additional decoders with different decoding algorithms and optimized to maximize decoder performance given a maximum power constraint. |
| US11424760B2 |
System and method for data compaction and security with extended functionality
A system and method for highly efficient encoding of data that includes extended functionality for asymmetric encoding/decoding and network policy enforcement. In the case of asymmetric encoding/decoding the original data is encoded by an encoder according to a codebook and sent to a decoder, but the output of the decoder depends on data manipulation rules applied at the decoding stage to transform the decoded data, into a different data set from the original data. In the case of network pokey enforcement, a behavior appendix into the codebook, such that the encoder and/or decoder at each node of the network comply with network behavioral rules, limits, and policies during encoding and decoding. |
| US11424758B2 |
Conversion and folding circuit for delay-based analog-to-digital converter system
An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit. |
| US11424756B2 |
Successive approximation register analog-to-digital converter with embedded filtering
A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter. |
| US11424755B2 |
System and method for a super-resolution digital-to-analog converter based on redundant sensing
A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components. |
| US11424752B2 |
Interleaved analog-to-digital converter (ADC) gain calibration
An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction. |
| US11424749B1 |
Analog lock detector for a phase lock loop
An analog lock detector for a phase lock loop includes a detector, a logic gate, a delay circuit, and a guard gate inverter. The detector outputs up and down signals relating synthesized and reference frequencies. The logic gate outputs an initial lock signal combining the up and down signals. While the synthesized and reference frequencies are locked, the initial lock signal has a steady state except during brief intervals. The delay circuit outputs a delayed lock signal that time delays the initial lock signal by a delay amount, which matches a maximum allowed duration of the brief intervals while locked. A guard gate inverter outputs a final lock signal that combines the initial lock signal and the delayed lock signal. The final lock signal has the steady state indicating when the synthesized frequency is locked to the reference frequency, but without the brief intervals of deviation from the steady state. |
| US11424746B1 |
Reference-less clock and data recovery device and method
A reference-less dock and data recovery device includes a CDR circuit, an oscillator circuit, and a processor. The CDR circuit is configured to generate a first clock signal through synchronization according to a data signal having a first frequency in a first time period. The oscillator circuit is configured to output an oscillating clock signal according to the first clock signal, A frequency of the oscillating clock signal is substantially identical to that of the first clock signal. The processor oversamples the data signal having a second frequency in a second time period to generate a simulated preparation signal conforming to the second frequency. The CDR circuit is configured to generate a second clock signal through synchronization according to the simulated preparation signal. Before generating the second clock signal, the CDR circuit is synchronized to the oscillating clock signal to maintain outputting of the first clock signal. |
| US11424743B2 |
Operator control device for a vehicle and method for operating such an operator control device
An operator control device for a vehicle, and a method for operating such an operator control device is disclosed. The operator control device is for controlling safety-relevant functions. To this end, the operator control device has at least one user interface having at least one user input panel for user input and a sensor system for identifying a user input in the area of the user input panel, wherein the sensor system has at least one capacitive sensor device having a first, electrically conductive sensor structure and a second, capacitive sensor device having a second, electrically conductive sensor structure, the sensor structures being arranged beneath the user interface in the area of the user input panel. The first sensor structure and the second sensor structure are each configured in comb-like and/or meanderous fashion and arranged in intermeshing fashion at least in a subarea of the user input panel. |
| US11424742B2 |
Superconducting switching devices and processes of forming
Superconducting switching devices of electrically-polarizable ferroelectric materials and electrically conductive materials with control electrodes. Superconducting states of the superconducting switching devices are determined by polarization states of the electrically-polarizable ferroelectric materials and voltages applied to the control electrodes. |
| US11424739B2 |
Feedback-based transistor driver
A device for driving a control terminal of a transistor includes an input terminal, a transformer including an input winding and an output winding, the input winding being coupled to the input terminal, an n-stage buffer circuit configured to generate a drive signal for the control terminal of the transistor, the n-stage buffer circuit being coupled to a first end of the output winding, and a positive feedback path coupled to an output of a stage of the n-stage buffer circuit to provide a DC offset to an input of the n-stage buffer circuit. |
| US11424738B2 |
Driving circuit
The object is to provide a technology enabling appropriate driving of an IGBT. A driving circuit is a driving circuit that drives an IGBT by controlling the gate voltage of the IGBT, and includes a first charging capability and a second charging capability. The first charging capability increases the gate voltage up to a threshold voltage of the IGBT, and a second charging capability increases the gate voltage beyond the threshold voltage. An increase in the gate voltage with the first charging capability per unit time is higher than an increase in the gate voltage with the second charging capability per unit time. |
| US11424737B2 |
Semiconductor device and electronic device
In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit. The time from the input of a signal to the input terminal of the first circuit to the output of a signal from an output terminal of the inverter circuit depends on the potential of the back gate of the second transistor. |
| US11424736B1 |
Adaptive clock duty-cycle controller
Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices, and combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal. |
| US11424735B2 |
Duty correction device and method, and semiconductor apparatus using the same
A duty correction device includes a global duty correction circuit and a local duty correction circuit. The global duty correction circuit performs a global duty correction operation on a first clock signal and a second clock signal based on a local correction signal. The local duty correction circuit performs a local duty correction by detecting phases of the first and second clock signals, and enables the local correction signal when a number of the local duty correction operation reaches a threshold value. |
| US11424734B2 |
Low voltage clock swing tolerant sequential circuits for dynamic power savings
Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain. |
| US11424733B2 |
Calibration device and calibration method
A calibration device includes a signal generator and a processor. The signal generator is configured to provide an input signal to a filter circuit, wherein the filter circuit has a real time constant and is configured to receive the input signal to output an output signal. The processor is configured to calculate a real gain according to the output signal and the input signal, compare the real gain with a target gain to obtain a comparison result and determine whether to adjust the real time constant of the filter circuit according to the comparison result. The present disclosure also provides a calibration method. |
| US11424732B2 |
Acoustic wave devices with common ceramic substrate
An acoustic wave component is disclosed. The acoustic wave component can include a bulk acoustic wave resonator and a surface acoustic wave device. The bulk acoustic wave resonator can include a first portion of a ceramic substrate, a first piezoelectric layer positioned on the ceramic substrate, and electrodes positioned on opposing sides of the first piezoelectric layer. The surface acoustic wave device can include a second portion of the ceramic substrate, a second piezoelectric layer positioned on the ceramic substrate, and an interdigital transducer electrode on the second piezoelectric layer. |
| US11424731B2 |
Elastic wave device
An elastic wave device includes an interdigital transducer electrode, a dielectric film, and a frequency adjustment film are disposed on a LiNbO3 substrate. When Euler Angles of the LiNbO3 substrate are within a range of about 0°±5°, within a range of about θ±1.5°, within a range of about 0°±10°, the interdigital transducer electrode includes a main electrode, a film thickness of the main electrode normalized by a wavelength determined in accordance with an electrode finger pitch of the interdigital transducer electrode is denoted as T, and a density ratio of a material of the main electrode to Pt is denoted as r, the film thickness of the main electrode and θ of the Euler Angles satisfy θ=−0.05°/(T/r−0.04)+31.35°. |
| US11424728B2 |
Piezoelectric acoustic resonator manufactured with piezoelectric thin film transfer process
A method and structure for a transfer process for an acoustic resonator device. In an example, a bulk acoustic wave resonator (BAWR) with an air reflection cavity is formed. A piezoelectric thin film is grown on a crystalline substrate. One or more patterned electrodes are deposited on the surface of the piezoelectric film. An etched sacrificial layer is deposited over the one or more electrodes and a planarized support layer is deposited over the sacrificial layer. The support layer is etched to form one or more cavities overlying the electrodes to expose the sacrificial layer. The sacrificial layer is etched to release the cavities around the electrodes. Then, a cap layer is fusion bonded to the support layer to enclose the electrodes in the support layer cavities. |
| US11424726B2 |
Differential amplifier
A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal. |
| US11424719B2 |
Multi-bandwidth envelope tracking integrated circuit
A multi-bandwidth envelope tracking (ET) integrated circuit (IC) (ETIC) is provided. The multi-bandwidth ETIC may be coupled to an amplifier circuit(s) for amplifying a radio frequency (RF) signal modulated in a wide range of modulation bandwidth. In examples discussed herein, the multi-bandwidth ETIC includes an ET voltage circuit configured to generate a modulated voltage based on a supply voltage. The supply voltage may be dynamically adjusted to cause the modulated voltage to transition quickly from one voltage level to another voltage level, particularly when the RF signal is modulated in a higher modulation bandwidth, without compromising efficiency of the ET voltage circuit. As such, the multi-bandwidth ETIC may generate different modulated voltages based on the modulation bandwidth of the RF signal, thus making it possible to employ the multi-bandwidth ETIC in a wide range of wireless communication devices, such as a fifth-generation (5G) wireless communication device. |
| US11424714B2 |
Angled polymer solar modules
This specification describes angled polymer solar modules, methods for producing angled polymer solar modules, and methods for installing angled polymer solar modules. In some examples, a method includes producing a flat polymer sheet including one or more photovoltaic cells. The method includes applying force to the flat polymer sheet to curve the flat polymer sheet in at least one region, forming an angled polymer sheet from the flat polymer sheet. The method includes mounting the angled polymer sheet on a roof deck such that the photovoltaic cells are angled with respect to the roof deck by virtue of the at least one region being curved. |
| US11424713B1 |
Method to control an inverter and inverter with improved controls
A motor drive including an inverter and control logic and a method implemented by the control logic to protect an inverter. The method includes determining a temperature value of a temperature associated with the inverter; preventing restarting of the inverter if the temperature value exceeds a first temperature threshold; and preventing restarting of the inverter if the temperature value exceeds a second temperature threshold that is smaller than the first temperature threshold and the inverter was shut down due to a high load condition. |
| US11424712B2 |
Safe state of an electric machine
The invention relates to an inverter for controlling an electric machine on a voltage source having a first and a second potential. The inverter comprises a plurality of bridge circuits which each comprise a first flow control valve, a second flow control valve and a connector for the electric machine, and a first interface for receiving individual control signals for the flow control valves and a second interface for detecting a switch-off signal. Each first flow control valve is configured to control current between the high electrical potential and the associated connector, and each second flow control valve is configured to control current between the associated connector and the low electrical potential. A switch-off device is configured to close either all first or all second flow control valves as a function of the shut-off signal and independently of signals on the first interface. |
| US11424710B2 |
Motor driving device
A motor driving device includes an acquisition unit configured to acquire multiple pieces of data in data acquisition periods having different lengths; a selection unit configured to select a piece of data from among the multiple pieces of data, based on timing at which a switching circuit switches switching devices; and a control unit configured to control the switching circuit based on the selected data. |
| US11424709B2 |
Method and apparatus for riding through power disruptions of a drive circuit
An electrical ride-through (ERT) unit is configured to apply a voltage to a drive circuit during disruptions of line voltage to the drive circuit. The ERT unit includes a capacitor on an ERT circuit that is prevented from applying the voltage to the drive circuit during normal operation of the drive circuit, and applies the voltage to the drive circuit during a voltage drop on the drive circuit. |
| US11424708B2 |
Estimating method for estimating rotor frequency of motor
An estimation method for estimating a rotor frequency of a motor during freewheeling, includes: applying a fixed input voltage and one selected from a plurality of stator frequencies to the motor sequentially so as to perform frequency scanning; detecting a stator current value of the motor corresponding to the selected stator frequency; calculating a stator current slope of the stator current values sequentially; defining a target period from a start point where the stator current slope varies from positive to negative to an end point where the stator current slope varies from negative to positive; and determining that a difference between the scanned stator frequency and the rotor frequency is within a preset value, then designating any of the corresponding stator frequencies during the target period as an estimated value of the rotor frequency. |
| US11424704B2 |
Controlled switching current of an on-load tap changer of a wind turbine
The invention relates to a method for controlling a wind turbine which comprises a transformer has a variable turns ratio such as an on load tap changer transformer. The adjustment of the turns ratio is possible when a primary side current or a secondary side current of the transformer is less than a switching current threshold. The method comprises operating the wind turbine so that the primary or secondary side current is above the switching current threshold. In response to obtaining a condition for changing the turns ratio of the transformer, the wind turbine is operated so that the primary or secondary side current is reduced below the switching current threshold so that the turns ratio can be changed during the temporary current reduction. |
| US11424692B2 |
Multi-level single-phase AC-to-DC converter
System and methods for power conversion are provided. Aspects include a first switching module comprising a first set of switches, wherein the first set of switches comprise wide-bandgap devices having a first bandgap, a second switching module comprising a second set of switches, wherein the second set of switches comprise semiconductor devices having a second bandgap, and wherein the first bandgap is larger than the second bandgap, an alternating current (AC) power source connected to the first switching module and the second switching module, a first capacitor bank, a second capacitor bank, and a controller configured to operate the first switching module and the second switching module to create a first direct current (DC) voltage across the first capacitor bank and a second direct current (DC) voltage across the second capacitor bank. |
| US11424690B2 |
Semiconductor switching arrangement
A semiconductor switching arrangement contains at least two half-bridge modules that each have an AC voltage connection, a positive DC voltage busbar, a negative DC voltage busbar, and at least one AC voltage busbar. The AC voltage connections are electrically interconnected by the AC voltage busbar. The aim is to improve the current distribution to the half-bridge modules arranged electrically in parallel. To this end, at least in the region of the AC voltage connections, the positive DC voltage busbar and the negative DC voltage busbar extend over an area containing the AC voltage busbar. Two of the at least two half-bridge modules are arranged adjacently such that the AC voltage surfaces of the two of the at least two half-bridge modules are adjacently arranged in relation to each other. Ideally a converter can contain at least one such semiconductor switching arrangement. |
| US11424689B2 |
Power conversion device
A power conversion device includes a case, a power module, a smoothing capacitor and a high-voltage connection portion. The power module is housed in the case. The smoothing capacitor is fixed to the case by capacitor fixing bolt, and suppresses voltage fluctuations. In the high-voltage connection portion, the power module and the smoothing capacitor are electrically connected. The locations at which the smoothing capacitor is fixed to the case by the capacitor fixing bolts correspond to the capacitor fixing points. The capacitor fixing points are arranged at positions that avoid corner portions of the smoothing capacitor. The power module and the smoothing capacitor are disposed adjacent to each other at the high-voltage connection portion. |
| US11424688B2 |
Modular power converter
A modular power converter with wide-bandgap semiconductors, in particular SiC semiconductors. The modular power converter has at least two base units. The base units are connected together on the input side, and each base unit has an input circuit on the input side and an output circuit on the output side. The input circuit and the output circuit are each formed by the wide-bandgap semiconductors arranged in a B6-bridge circuit. An intermediate circuit capacitor is connected in parallel with the input circuit and the output circuit forming an intermediate circuit. The input circuits of the base units or a sub-quantity of the base units are arranged in a series circuit. At least one inductor is arranged between each pair of input circuits. |
| US11424684B2 |
High performance two stage power converter with enhanced light load management
A two-stage power converter can incorporate a buck pre-regulator and a resonant bus converter. Such a converter may be operated to achieve unconditional soft switching operation (zero voltage switching a/k/a ZVS) over a wide input and output range, while delivering excellent power conversion efficiency at lower power levels and in a no load condition. |
| US11424681B2 |
Multiphase switching power supply device
Provided is a switching power supply device capable of easily realizing multi-phase operation and current balancing with the number of operation phases depending on the amount of load. The switching power supply device includes: a main circuit; a control circuit (2) configured to output a reference pulse signal; an entire current detection circuit CT0 configured to detect an output current of the entire main circuit as an entire current; a plurality of individual current detection circuits CTn provided corresponding to a plurality of power conversion units and configured to detect output currents of respective ones of the plurality of power conversion units as respective individual currents; and a pulse corrector (3) configured to generate individual pulse signals for respective ones of the plurality of power conversion units on the basis of the entire current, the individual currents and the reference pulse signal, and to output, to the plurality of power conversion units, respective ones of the individual pulse signals for the plurality of power conversion units as drive signals for respective switching elements, wherein the pulse corrector (3) determines the number of operation phases N′ for the power conversion units on the basis of the entire current and, to the same number of power conversion units as the determined number of operation phases N′, outputs respective ones of the individual pulse signals. |
| US11424679B2 |
Buck boost converter cell for MMC
The present disclosure relates to a converter cell (4) for an MMC. The cell comprises a primary energy storage (Cm), an inductor (Lf), and a secondary energy storage (Cf); and first and second converter valves (T1, T2). The secondary energy storage (Cf) is connected in series with the first converter valve (T1), and together with said first converter valve in parallel with the inductor (Lf), and the primary energy storage (Cm) is connected in series with the second converter valve (T2), and together with said second converter valve (T2) in parallel with the inductor (Lf). |
| US11424675B2 |
Dielectric energy converter
A circuit design for efficiently transferring significant levels of electrical power with non-inductive circuit elements. Power is transferred using synchronously-switched capacitive elements in such a way that both discharge from the power source and charge transferred to a load (and/or back to the power supply) are supplied as low duration, high-intensity current pulses. The synchronous power transfer alternates between connecting capacitive charge storage elements in parallel and in series so that both step-up and step-down topologies may be readily realized. |
| US11424674B2 |
Circuit assembly for intermediate circuit balancing
The disclosure relates to a circuit assembly (1) for intermediate circuit balancing of an intermediate circuit voltage UZK of a DC intermediate circuit fed by an alternating mains voltage UN for supplying a voltage to one or more devices, the circuit having a voltage divider (SP) configurable in terms of the voltage divider ratio and including a plurality of electric two-terminal devices (R1, R2, . . . , R6) by which the intermediate circuit voltage UZK is divided into voltage portions at each two-terminal device, the circuit having at least one first intermediate circuit capacitor (C1) chargeable to a first portion UZK,1 of the intermediate circuit voltage UZK, and the circuit having at least one second intermediate circuit capacitor (C2) chargeable to a second portion UZK,2 of the intermediate circuit voltage UZK. |
| US11424671B2 |
Overvoltage protection circuit and operation method thereof
Disclosed is an overvoltage protection circuit and method thereof. The overvoltage protection circuit includes a charge/discharge circuit configured to be charged or discharged based on a source voltage of a first transistor included in a non-isolated converter and a comparison circuit, based on a voltage charged in the charge/discharge circuit exceeding a threshold voltage, turn off a power supply circuit supplying power to the non-isolated converter. |
| US11424670B2 |
Drive device for switch
A drive device performs switching of at least one switch configuring an electrical power converter. The drive device includes a control section that generates a drive signal for the switch and transmits the drive signal, and at least one drive circuit that receives the transmitted drive signal. The control section generates speed adjustment information for adjusting a switching speed of the switch and transmits the speed adjustment information to the drive circuit. The drive circuit includes a speed calculation section that receives the transmitted speed adjustment information and calculates command switching speed information of the switch based on the received speed adjustment information, and a drive section that performs switching of the switch based on the received drive signal and the calculated command switching speed information. |
| US11424669B2 |
Rotor with winding carrier and coil element embedded therein
A rotor (1) for an electric machine (21) with a central rotor axis (A) is specified. The rotor comprises—at least one superconducting coil element (3) with a local winding axis (a), and—at least one winding carrier (5) into which the coil element (3) is embedded, —wherein a cohesive connection is formed between the winding carrier (5) and the coil element (3), —wherein the cohesive connection is provided on a connecting surface (11c) which forms only a first partial region of the entire contact surface (11a, 11b, 11c) between coil element (3) and winding carrier (5). Also specified are a machine with a rotor (1) of said type and a production method for a rotor (1) of said type. |
| US11424665B2 |
Apparatus for assembling a permanent magnet motor rotor
An apparatus for assembling a permanent magnet motor rotor includes a first-end positioning assembly, a plurality of connectors, and a second-end positioning assembly. The first-end positioning assembly is utilized to fix a first-end rotor core. The second-end positioning assembly is utilized to fix a second-end rotor core. The connectors are utilized to connect and fix the first-end positioning assembly with the second-end positioning assembly. Each first longitudinal axis of each first positioning element of the first end positioning assembly is different from each second longitudinal axis of each second positioning element of the second end positioning assembly. In addition, a method for assembling a permanent magnet motor rotor is also provided. |
| US11424663B2 |
Motor
A motor includes a commutator, a bracket including a conductive brush, first and second wall parts, and first and second deformable parts. The conductive brush is in contact with the commutator. The first wall part includes a first surface extending along a first surface of the conductive brush. The second wall part includes a second surface extending along a second surface of the conductive brush located on a side opposite the first surface of the conductive brush. The first deformable part is in contact with both the first surface of the conductive brush and the first surface of the first wall part, and is deformable in response to movement of the conductive brush. The second deformable part is in contact with both the second surface of the conductive brush and the second surface of the second wall part, and is deformable in response to movement of the conductive brush. |
| US11424656B2 |
Motor device
This motor device is provided with, e.g.: a motor having a motor case and a shaft supported by the motor case so as to be capable of rotating about a rotation center; a housing in which the motor is housed; and an elastic member interposed between the motor case and the housing. A first concave part in communication with both sides of the elastic member in the axial direction is provided between the outer peripheral surface of the elastic member and a cylindrical surface of the housing. |
| US11424652B2 |
Lubricant supported electric motor including magnetic rotor centering
A lubricant supported electric motor including a stator presenting a stator raceway, and a rotor extending along an axis and rotatable relative to the stator. The rotor presents a rotor raceway disposed in spaced relationship with the stator raceway to define a gap there between. A lubricant is disposed in the gap for supporting the rotor relative to the stator. The rotor includes a plurality of rotor poles arranged adjacent the rotor raceway in circumferentially spaced relationship with one another, and the stator includes a plurality of stator poles extending radially towards the rotor in circumferentially spaced relationship with one another along the stator raceway. A plurality of stator coil windings are wrapped around the plurality of stator poles and individually controllable for generating a magnetic force to center the rotor within the stator with carefully-timed adjustments to magnetic fields generated by the stator. |
| US11424651B2 |
Rotor
A rotor that includes a shaft; a rotor core that is attached to the shaft and that is configured of a plurality of electric steel plates that are stacked; and a permanent magnet that is embedded in the rotor core, wherein: a coolant supply port that supplies a coolant to the rotor core is provided in the shaft, and at least two electric steel plates of the plurality of electric steel plates each include a first portion that has a first thickness in a rotational axis direction and a second portion that has a second thickness in the rotational axis direction, which is thinner than the first portion, the second portion extending in a radial direction and configuring a flow path through which the coolant supplied from the coolant supply port of the shaft flows. |
| US11424648B1 |
Dynamic operation adjustment in wireless power transfer system
A wireless power transfer system is provided having a wireless transmission system with an input to receive input power from an input power source, a transmission antenna configured to couple with a receiver antenna associated with a wireless receiver system in a peripheral device, and a transmission controller configured to generate AC wireless signals including wireless power signals and wireless data signals. The transmission controller is further configured to derive a coupling factor based on coupling data sent from the wireless receiver system to the wireless transmission system, generate an update frequency based on the derived coupling factor, and transmit the update frequency to the wireless receiver system in the peripheral device, whereby the peripheral device provides coupling data to the wireless transmission system based on the update frequency. |
| US11424646B2 |
Pillow with wireless charging
A bed has a mattress. A first wireless charging array is positioned on a top side of the mattress nearer a head of the mattress. A pillow is configured to be positioned atop the first wireless charging array. The pillow includes a second wireless charging array located on an underside of a pillow. The second wireless charging array is configured to receive energy from the first wireless charging array. A companion device is configured to use the energy. An energy storage device is within the pillow. The energy storage device is configured to store charge received by the first wireless charging array. The energy storage device is configured to supply power to the companion device. |
| US11424641B1 |
Flexible load management system
A flexible load management (FLM) system and technique adaptively monitors and manages power consumption of a premises. The FLM system includes a virtual critical load panel (vCLP) that utilizes circuit breakers in combination with companion modules (i.e., intelligent controllers) to vary a prioritization arrangement of loads in the premises by time of day, season or even dynamically. The vCLP is a prioritized enumeration (i.e., prioritization) of the loads within the premises, wherein the loads are considered sufficiently important such that they are protected by a local power source. The vCLP is dynamically configurable by a user in real time according to an instantaneous demand for the prioritized loads that is used to determine a number of branch circuits associated with the loads that is able to be powered-on at any time. |
| US11424638B2 |
Control device with a switch circuit configured to electrically connect a battery and a device
A control device for a wireless power supply system includes a battery configured to supply power to a first device, a power reception coil, a power reception circuit connected to the power reception coil and configured to adjust a voltage generated by the power reception coil to charge the battery, and a switch circuit connected between the battery and the first device and configured to detect the adjusted voltage applied to the battery. The switch circuit is further configured to, when the adjusted voltage is not detected, electrically connect the battery and the first device, and when the adjusted voltage is detected, electrically disconnect the battery and the first device. |
| US11424636B2 |
Micro-grid smart output adaptor
A system for a vehicle includes a converter configured to, responsive to a first signal from a first adaptor indicating a first plug type having a first electrical parameter configuration, output power to the adaptor according to the first electrical parameter configuration, and responsive to a second signal from a second adaptor indicating a second plug type having a second electrical parameter configuration, output power to the adaptor according to the second configuration. |
| US11424632B2 |
USB charging apparatus
An improved USB charging apparatus includes a main body and a plurality of power processing modules arranged in the main body; each one of the power processing modules having two USB charging ports connected thereto, and the two USB charging ports configured to be a first charging port and a second charging port having specifications different from each other; the first charging port and the second charging port arranged adjacent to each other; each one of the power processing modules further comprising a detection control circuit and a switch circuit, allowing each charging circuit to be provided with the charging ports of two types of specifications, such that user can choose one of the charging ports for use depending upon the actual needs. Accordingly, the improved USB charging apparatus is not limited to certain specifications of charging ports only, thereby increasing the use significantly. |
| US11424618B2 |
Converter, arrangement comprising a converter and method for operating same
A converter has a plurality of partial converters, each partial converter having three-phase converter-side supply connections for parallel connection to the same electrical three-phase supply system and three-phase converter-side output connections with a star point for making contact with a star point of a three-phase output system. The converter-side output connections of the three-phase partial converters are connected in parallel. The partial converters each have a converter module for each partial converter-side three-phase supply connection, and the converter modules each have two or more submodules having their outputs connected in series, and a transformer. |
| US11424608B2 |
Devices and methods for electrical cable splices
A splice for a skin-effect effect heating cable including a primary shim configured to be shrunk over part of an insulation layer of a first portion of the heating cable, a secondary shim configured to be shrunk part of the insulation layer of a second portion of the heating cable, a connector configured to electrically couple the first portion of the heating cable and the second portion of the heating cable, and an outer cold shrink tube configured to be shrunk over the primary shim, the secondary shim, and the connector. |
| US11424604B1 |
Flush wallplate electrical box assembly
The Flush Wallplate Electrical Box Assembly deploys and constrains an electrical wallplate such that the wallplate finished face is essentially co-planar to the surrounding wall assembly finish material finished surface. The assembly is comprised of flush wallplate electrical box possessing an integral housing intended to receive the electrical wallplate, an interface flange serving to interface between the electrical box and wall assembly finish materials, an interface placement guide to control the positioning of the interface flange and an element to protect wiring inside the electrical box during wall assembly construction. The form of the electrical box provides for a building and electrical code compliant installation and simplifies box positioning providing minimum variability. The interface flange provides for a consistent termination of wall assembly materials at the periphery of the electrical box. |
| US11424600B1 |
Spark plug
A spark plug includes a tubular metal shell; an insulator including a locking portion locked onto the metal shell; and a cap disposed at a front end side of the metal shell, the cap having a plurality of orifices. The plurality of orifices include orifices with different cross-sectional areas. A sum of the number of one or more largest orifices and the number of one or more large orifices that have a cross-sectional area of larger than or equal to 90% of the one or more largest orifices is smaller than the number of orifices that are other than the one or more largest orifices and the one or more large orifices. A length of the front end portion in an axial direction between a front end of the insulator and a front end of the locking portion is smaller than or equal to 12 mm. |
| US11424596B2 |
Semiconductor layer stack and method for producing same
A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, E F - E V < E G 2 applying to the layer (A) and E L - E F < E G 2 applying to the layer (B), with EF the energy position of the Fermi level, EV the energy position of the valence band, EL the energy position of a conduction band and EL−EV the energy difference of the semiconductor band gap EG, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results. |
| US11424592B2 |
Siloxane mitigation for laser systems
In various embodiments, the concentration and deposition of siloxane materials within components of laser systems, such as laser resonators, is reduced or minimized utilizing mitigation systems that may also supply gas having low siloxane levels into multiple different components in series or in parallel. |
| US11424584B2 |
Current transformer
A current transformer connector (10; 102) for connecting a current transformer of an electrical network to a protection relay via a current transformer data acquisition board (12; 104), is provided. The current transformer connector (10; 102) comprises first and second pairs (14, 20) of first and second current contacts (16, 18, 22, 24), each current contact pair (14, 20) being connectable in use to the current transformer so as to permit current flow from the electrical network through the current contact pairs (14, 20) to the protection relay. Each current contact pair (14, 20) is arranged to be in a short circuit configuration. The first current contact (16, 22) in each current contact pair (14, 20) is arranged to be independently moveable relative to the corresponding second current contact (18, 24) so that during initial insertion of the current transformer data acquisition board (12; 104) into the current transformer connector (10; 102) in use the first current contact (16) of the first current contact pair (14) is configured to separate from the second current contact (18) of the first current contact pair (14) to permit breaking of the short circuit configuration of the first current contact pair (14) and making of an electrical connection between the first current contact pair (14) and the current transformer data acquisition board (12; 104), while the second current contact pair (20) remains in the short circuit configuration. The first current contact (16, 22) in each current contact pair (14, 20) is further arranged to be independently moveable relative to the corresponding second current contact (18, 24) so that during further insertion of the current transformer data acquisition board (12; 104) into the current transformer connector (10; 102) in use the first current contact (22) of the second current contact pair (20) is configured to separate from the second current contact (24) of the second current contact pair (20) to permit breaking of the short circuit configuration of the second current contact pair (20). |
| US11424582B2 |
Ganged coaxial connector assembly
A ganged connector assembly includes: first, second, third and fourth coaxial cables; first, second, third and fourth coaxial connectors, each of the coaxial connectors connected with a corresponding one of the coaxial cables; a shell surrounding the coaxial connectors, the shell configured to electrically isolate each of the coaxial connectors from the other coaxial connectors, wherein the coaxial connectors are arranged in a generally square pattern; and a strain relief boot comprising: first and second cover pieces that are assembled to create a cover around portions of the coaxial cables and the coaxial connectors; and first and second braces that reside within the cover, the first brace being positioned between first and second of the coaxial connectors, and the second brace being positioned between third and fourth of the coaxial connectors. |
| US11424580B2 |
Compact coaxial cable connector for transmitting super high frequency signals
Disclosed is a compact coaxial cable connector for transmitting super-high frequency signals, which is adapted to connect a PCB to a single or multiple super-high frequency coaxial cable signal lines transmitting super-high frequency signals therethrough. The compact coaxial cable connector includes: a single or multiple coaxial cables each including an inner conductor, an outer conductor, a dielectric, and a sheath, wherein the outer conductor, the dielectric, and the sheath are stripped to expose the inner conductor over a predetermined length and a terminal of the exposed inner conductor is brought into electrical contact with a circuit signal line terminal pad formed on the PCB; and a male connector including a shielding can receiving the exposed inner conductors of the single or multiple coaxial cables, securing and protecting ends of the exposed inner conductors, and blocking electromagnetic waves generated from the inner conductors of the single or multiple coaxial cables. |
| US11424579B2 |
Connector and connector device
A connector includes an outer shield, a terminal surrounded by the outer shield, a housing fixed to the outer shield and holding the terminal; and an inner shield surrounded by the outer shield. The outer shield, the inner shield, and two virtual paths that connect the two tip regions of the inner shield to the outer shield by shortest distances, respectively, constitute plural electrically-closed loops surrounding the terminal. The electrically-closed loops include one or more particular electrically-closed loops. Each of the one or more particular electrically-closed loops does not surround any electrically-closed loop among the plurality of electrically-closed loops other than the each of the one or more particular electrically-closed loops. A longest loop length of the one or more loop lengths of the one or more particular electrically-closed loops is shorter than a wavelength of a maximum frequency of a transmission signal flowing through the terminal. This connector reduces resonance of a transmission signal. |
| US11424577B2 |
High-current electrical connector and electrical connector system
A high-current electrical connector (1) is codable for use with a certain mating electrical connector and flexibly and comfortably adaptable to the conditions of a tight installation space in which the high-current electrical connector is used. The insulating body (14) of the high-current electrical connector is retained on the pin contact (11) such that said insulating body can be rotated about the pin axis (S). Thus, the mating electrical connector (4) connected thereto, coded therefor and aligned therewith can be rotatably retained such that the angled cable outlet (42) of the mating electrical connector can be flexibly oriented within the installation space as required. |
| US11424567B2 |
Connector structure
A connector structure is provided, including an insulating body, a plurality of terminals disposed in the insulating body, at least one stopper, and a housing receiving the insulating body and the terminals. A portion of the insulating body is abutted between the housing and the at least one stopper, and contacting portions of the housing and the at least one stopper are structurally combined together. |
| US11424565B2 |
Connector assembly and connector pair
A connector assembly can be attached to a surface of a substrate and has high airtightness to improve reliability. The connector assembly includes: a connector including a connector body and a terminal attached to the body; and a protective member including a wall extending in a longitudinal direction or a width direction of the body and an accommodation unit in which at least a part of four sides of a periphery is defined by the wall, the protective member being attached to the surface of the substrate with the connector accommodated in the accommodation unit. The protective member includes a protective member body made of an insulating material and a protective metal fitting made of a conductive metal integrally formed with the protective member body, and the protective member is placed on the surface of the substrate while coupled to the connector with the connector accommodated in the accommodation unit. |
| US11424564B2 |
Board-to-board connector
A connector includes a rectangular flat-plate housing including a first positioning hole and a second positioning hole, and a contact row and a contact row held on the housing. The housing includes a first pitch side surface and a second pitch side surface on an opposite side of the first pitch side surface. The contact row and the contact row extend from the first pitch side surface to the second pitch side surface. The first positioning hole is disposed between the first pitch side surface and the contact row, and the second positioning hole is disposed between the first pitch side surface and the contact row. |
| US11424561B2 |
Outlet-level electrical energy management system
An electrical receptacle includes a printed circuit board (PCB), a power control unit coupled to the PCB, AC electrical conductors, and an electrical receptacle coupled to the PCB. The electrical contacts are in electrical communication with respective ones of the electrical conductors. A first portion of each electrical conductor is coupled to a power source and a second portion of each electrical conductor is coupled to respective ones of the electrical contacts. The power control unit includes a controller and a switch, the switch operable to selectively establish continuity between the first and second portions of at least one of the electrical conductors. The controller is configured to selectively place the switch into either a closed position or an open position in response to a signal received from an environmental or occupancy sensor. |
| US11424558B2 |
Connection device for the connection of a conductor end
A connection device for the connection of a conductor end includes a housing having a slotted link, a busbar section having a slotted link aligned with the housing slotted link, an d clamping spring assembly rotatably connected with the housing and operable between an open position and a contact position with the conductor end. A rotary lever assembly including a rotary lever element is operably connected with the clamping spring assembly. The rotary lever element has a cam section and a control curve section on which the clamping spring assembly slides during movement into the contact position. A clamping device is arranged on the cam section and is retained by the housing and busbar slotted links. |
| US11424546B2 |
Modified ground planes to increase gains in element patterns of geodesic antennas
A geodesic antenna includes an outer cone. The geodesic antenna also includes an inner cone positioned partially within the outer cone and, together with the outer cone, defining an electromagnetic waveguide. The geodesic antenna further includes multiple driven elements configured to generate electromagnetic waves in a space between the outer and inner cones. In addition, the geodesic antenna includes a ground plane configured to reflect first electromagnetic waves of the generated electromagnetic waves back into the space between the outer and inner cones. The ground plane has a geometric design that prevents at least some second electromagnetic waves of the generated electromagnetic waves from being reflected from the ground plane and forming an interferometer pattern. |
| US11424540B2 |
Antenna system
An antenna system includes a first substrate, the first substrate being a dielectric substrate, a first patch on a first surface of the dielectric substrate and a second patch on a second surface of the dielectric substrate. The first and second patches are coupled to form a first capacitor with the dielectric substrate. A second substrate is coupled to the first substrate and a ground layer is provided on a first surface of the second substrate. An antenna feed is coupled to the second substrate. |
| US11424538B2 |
Feed systems for multi-band parabolic reflector microwave antenna systems
Microwave antenna systems include a parabolic reflector antenna having a feed bore and a feed assembly. The feed assembly includes a coaxial waveguide structure that extends through the feed bore, a sub-reflector, and a first dielectric block that is positioned between the coaxial waveguide structure and the sub-reflector. The coaxial waveguide structure includes a central waveguide and an outer waveguide that circumferentially surrounds the central waveguide. One of the central waveguide and the outer waveguide extends further from the feed bore towards the sub-reflector than the other of the central waveguide and the outer waveguide. |
| US11424528B2 |
Meta-structure antenna system for new generation wireless networks in moving vehicles
Examples disclosed herein relate to a meta-structure (“MTS”) antenna system for next generation wireless networks in moving vehicles. The MTS antenna system includes an MTS antenna mounted on an exterior surface of the moving vehicle and comprising an MTS array of MTS cells, and an internal gateway for communicating wireless signals to the MTS antenna. |
| US11424522B2 |
Reduced thermal resistance attenuator on high-thermal conductivity substrates for quantum applications
Techniques for facilitating reduced thermal resistance attenuator on high-thermal conductivity substrates for quantum applications are provided. A device can comprise a substrate that provides a thermal conductivity level that is more than a defined thermal conductivity level. The device can also comprise one or more grooved transmission lines formed in the substrate. The one or more grooved transmission lines can comprise a powder substance. Further, the device can comprise one or more copper heat sinks formed in the substrate. The one or more copper heat sinks can provide a ground connection. Further, the one or more copper heat sinks can be formed adjacent to the one or more grooved transmission lines. |
| US11424520B2 |
Liquid crystal phase shifter including a liquid crystal layer located between first and second flexible substrates, where a third flexible substrate provides a feed portion
Provided are a liquid crystal phase shifter and an antenna. The liquid crystal phase shifter includes a first substrate, a second substrate, a liquid crystal layer, and at least one phase shift unit. The first substrate includes a first flexible substrate and a first liquid crystal alignment layer located on a side of the first flexible substrate close to the second substrate. The second substrate includes a second flexible substrate and a second liquid crystal alignment layer located on a side of the second flexible substrate close to the first substrate. The phase shift unit includes a microstrip line and a phased electrode. The microstrip line is located between the first flexible substrate and the first liquid crystal alignment layer, and the phased electrode is located between the second flexible substrate and the second liquid crystal alignment layer. |
| US11424517B2 |
Secondary cell and battery pack
A negative electrode terminal includes a flange, and a connection portion disposed on a first surface of the flange. The connection portion is inserted into a terminal attachment hole. The negative electrode terminal includes a first area made of aluminium or an aluminium alloy, and a second area made of copper or a copper alloy. In the flange, the second area is disposed adjacent to the first surface, and the first area is disposed adjacent to the second surface. A boundary between the first area and the second area is disposed between the first surface and the second surface. A thinnest portion of the first area of the flange in the thickness direction of the flange has a thickness of larger than or equal to 0.3 mm. An external electroconductive member made of aluminium or an aluminium alloy is welded to the flange to form a welded portion. |
| US11424513B2 |
Connection module
A connection module attachable to a power storage element group formed by lining up a plurality of power storage elements is provided with a bus bar (connection member) that extends in a vertical direction and is connected to electrode terminals, an insulating protector having a holding portion that holds the bus bar, and a cover that covers the bus bar. The cover is provided with an intake port and an exhaust port positioned above the intake port, and a ventilation passage through which air can flow in the vertical direction is formed between the cover and the holding portion, the ventilation passage being in communication with the intake port and the exhaust port, and the bus bar is arranged inside the ventilation passage. |
| US11424511B2 |
Electrode assembly and electrochemical device comprising electrode assembly
Disclosed is an electrode assembly including two electrodes having polarities opposite to each other, and a separator interposed between the two electrodes, wherein the separator includes: a separator base which includes a porous polymer substrate having a plurality of pores, and a porous coating layer; and an adhesive layer formed on at least one surface of the separator base, provided to face either of the electrodes and containing an adhesive resin, and wherein the adhesion (Peel Strength) between the porous polymer substrate and the porous coating layer and the adhesion (Lami Strength) between the adhesive layer and the electrode satisfy Mathematical Formula 1. An electrochemical device including the separator is also disclosed. In the electrode assembly, the separator shows increased resistance against scratching and the adhesion between the separator and the electrode can be improved. |
| US11424510B2 |
Separator having through-holes sealed by thermoplastic polymer and electrochemical device including the same
Disclosed is a separator for an electrochemical device, interposed between a cathode and an anode to prevent a short circuit between both electrodes. The separator is provided with through-holes having a diameter of 1-20 μm in the thickness direction, and the surfaces of the through-holes are sealed by being coated with a thermoplastic polymer having a melting point equal to or higher than 70° C. and lower than 130° C. An electrochemical device including the separator is also disclosed. The separator can prevent rapid ignition of an electrochemical device in advance. |
| US11424507B2 |
Lead-acid battery having container, positive and negative electrodes, lid, communication chamber, exhaust hole, and vent hole
A lead-acid battery is provided with a lid. A communication chamber is formed inside the lid. In the communication chamber, a first distance between an inner wall and a vent hole in a sidewall is shorter than a second distance between the inner wall and an exhaust hole, and a tip of the inner wall is formed below the vent hole in a direction opposite to the first direction. |
| US11424505B2 |
Vibration-damped battery, battery container, and battery pack for use downhole
A battery, a battery container, and a battery pack, for use downhole in MWD operations, one or more of which incorporates lateral vibration damping. In a preferred embodiment each comprise specialized lateral vibration damping in the form of a plurality of longitudinally-extending resiliently-deformable ridges extending substantially a length of each and circumferentially spaced about an outer periphery. The resiliently-deformable ridges on the battery may be integrally formed and extend radially outwardly from a hollow resiliently-deformable sleeve, and formed of the same resiliently-deformable material of which the sleeve is comprised. The resiliently-deformable ridges on the battery container may extend radially inwardly or outwardly from a periphery thereof. Advantageously, the battery container can thus be free of potting material and thus be reusable when the batteries thereof need be replaced. In all instances the so-configured resiliently-deformable ridges serve to damp severe lateral vibratory forces exerted downhole on such batteries. |
| US11424502B2 |
Battery pack
A battery pack includes: a plurality of battery cells, each including a negative electrode and a positive electrode, the positive and negative electrodes being arranged on a same side of the battery cell; a substrate arranged on the plurality of battery cells and including a first surface and a second surface located on opposite sides of the substrate, and a through hole exposing the negative electrode and the positive electrode of each of the plurality of battery cells; a first conductive plate arranged on the first surface of the substrate and including a first hole; and a second conductive plate arranged on the second surface of the substrate and including a second hole. |
| US11424501B2 |
Deep format pouch for battery cell
A pouch cell includes a generally rectangular cell housing formed of a metal laminated film that includes a box portion and a lid portion that is formed separately from the box portion. The active material including the electrode and an electrolyte is placed into the box portion and the lid portion is welded to the box portion. The box portion and the lid portion are formed and assembled together without using a drawing or a punching process. Instead, the pouch cell housing is formed via a series of folding and welding steps, whereby the pouch cell size is not limited by the draw depth of the metal laminated film. |
| US11424500B2 |
Secondary battery, battery module, and device using secondary battery as power source
The present disclosure relates to a secondary battery, a battery module, and a device using the secondary battery as a power source. The secondary battery includes a casing and a top cover for connecting with the casing. The casing includes an end portion provided with an opening. The top cover is used to cover the opening of the casing. The top cover includes an inserting portion extending into the casing from the opening. A plurality of notches are provided on an inner side of the end portion of the casing or on a side wall of the inserting portion facing the casing. In the secondary battery, the battery module, and the device using the secondary battery as a power source according to the present disclosure, the secondary battery can reduce the possibility of short circuit occurring in the electrode assembly and improve the operational safety of the secondary battery. |
| US11424499B2 |
Battery casing for vehicle
A battery casing for a vehicle includes: a lower panel; a sidewall member provided on an upper surface of the lower panel along a perimeter of the lower panel and configured to house battery modules in an internal space thereof; a cooling unit provided under the lower panel and joined to a lower surface of the lower panel, with a cooling channel provided in the lower panel to cool the battery modules; and a protective panel provided under the cooling unit and configured to protect the battery modules. |
| US11424496B2 |
Battery module
A battery module having a plurality of stacked battery module units is provided. The battery module unit includes a cooling fin in which an interval between two cooling plates facing each other is expandable and contractible. A battery cell is in contact with each of the two cooling plates and having lead tabs at each end. Protruding steps extend from both ends of the cooling plates to maximize a contact area with the lead tabs of the battery cell. Lead tab fasteners are coupled to the protruding steps to fix the lead tabs of the battery cell to the protruding steps. The lead tap fasteners include connecting grooves and connecting protrusions relative to each other to be coupled by a linear relative movement with lead tap fasteners of an adjacent battery module unit. |
| US11424494B2 |
Onboard-battery temperature controller
An onboard-battery temperature controller to be disposed inside a vehicle, near a battery including a plurality of battery cells, is configured to control the temperature of the battery cells. The onboard-battery temperature controller includes a fluid heater, a heat generating body, and an arithmetic and control unit. The fluid heater is configured to heat the battery cells through heat exchange between a heating fluid circulating therein and the battery cells. The heat generating body is configured to be energized and generate heat, to be conducted to the battery cells to heat the battery cells. The arithmetic and control unit is configured to control operations of the fluid heater and the heat generating body on the basis of the temperature of the battery. |
| US11424492B2 |
System and method for operating a rechargeable electrochemical cell or battery
An electrochemical cell management system comprising an electrochemical cell and at least one controller configured to control the cell such that, for at least a portion of a charge cycle, the cell is charged at a charging rate or current that is lower than a discharging rate or current of at least a portion of a previous discharge cycle. An electrochemical cell management method. An electrochemical cell management system comprising an electrochemical cell and at least one controller configured to induce a discharge of the cell before and/or after a charging step of the cell. An electrochemical cell management method. A electrochemical cell management system comprising an electrochemical cell and at least one controller configured to: monitor at least one characteristic of the cell and, based on the at least one characteristic of the cell, induce a discharge and/or control a charging rate or current of the cell. |
| US11424491B2 |
Battery and a system for swapping and/or charging a battery of a mobile robot
A battery configured to be attached to a battery holder for use by a mobile robot comprising: a battery body encapsulating the battery; at least two electrical connectors protruding from the battery body; at least one fixing unit located on the battery body said fixing unit configured to fix the battery to the battery holder; at least two damping pins protruding from the battery body; and at least one battery communication component configured to transmit battery status data. A battery holder configured to hold the battery and at least one of storing, swapping and charging a battery. |
| US11424489B2 |
Battery phenomenon management via resilient material
A device can include a processor; memory accessible by the processor; a housing that includes a battery bay that includes a first surface and a second, opposing surface; a battery package disposed in the battery bay and operatively coupled to the processor; and a resilient material disposed between the battery package and at least one of the first surface and the second surface of the battery bay. |
| US11424485B2 |
Lithium secondary battery electrolyte and lithium secondary battery comprising same
The present disclosure relates to a lithium secondary battery electrolyte and a lithium secondary battery comprising the lithium secondary battery electrolyte, which comprises: a non-aqueous organic solvent including a branched ester-based solvent represented by formula 1; and a lithium salt. |
| US11424482B2 |
Nonaqueous electrolyte solution and nonaqueous electrolyte battery using same
Disclosed herein is a nonaqueous electrolyte solution containing an electrolyte and a nonaqueous solvent, the nonaqueous electrolyte solution including a compound represented by formula (A) and: (1) at least one compound selected from a nitrile compound, an isocyanate compound, a difluorophosphate, a fluorosulfonate, a lithium bis(fluorosulfonyl)imide and a compound represented by the formula (B) below, or (2) a cyclic carbonate compound having a fluorine atom in an amount of 0.01% by mass to 50.0% by mass based on a total amount of the nonaqueous electrolyte solution. In formula (A), R1 to R3 represent optionally substituted organic groups having 1 to 20 carbon atoms, and in formula (B), R4, R5 and R6 independently represent an alkyl group, alkenyl group or alkynyl group having 1 to 12 carbon atoms that may be substituted with a halogen atom, and n represents an integer of 0 to 6. |
| US11424481B2 |
Electrolyte for secondary battery, method of preparing electrolyte, and secondary battery including electrolyte
An electrolyte for a secondary battery, the electrolyte including an ionic liquid polymer including a repeating unit represented by Formula 1: wherein, in Formula 1, CY, R1, R2, R3, X1−, n, and m are the same as described in the specification. |
| US11424470B2 |
Cost-efficient high energy density redox flow battery
Methods and systems are provided for a redox flow battery system. In one example, the redox flow battery is adapted with an additive included in a battery electrolyte and an anion exchange membrane separator dividing positive electrolyte from negative electrolyte. An overall system cost of the battery system may be reduced while a storage capacity, energy density and performance may be increased. |
| US11424469B2 |
Elevated pressure operation of molten carbonate fuel cells with enhanced CO2 utilization
Molten carbonate fuel cells (MCFCs) are operated at elevated pressure to provide increased operating voltage and/or enhanced CO2 utilization with a cathode input stream having a low CO2 content. It has been discovered that increasing the operating pressure of a molten carbonate fuel cell when using a low CO2-content cathode input stream can provide unexpectedly large increases in operating voltage while also reducing or minimizing the amount of alternative ion transport and/or enhancing CO2 utilization. |
| US11424464B2 |
Fuel cell system, method of controlling fuel cell system, and storage medium
A fuel cell system includes fuel cell, electrical storage device that stores electric power generated by the fuel cell, and control device of the fuel cell, the control device performs first control which causes the fuel cell to generate power and increases charging rate of the electrical storage device and second control which restricts output of the fuel cell to be smaller than that in the first control and decreases charging rate of the electrical storage device, and when switching condition, in which electric power demand from the external devices becomes greater than predetermined electric power or state in which electric power demand from the external devices is greater than the predetermined electric power continues for predetermined time, is satisfied, the control device increases power output by the fuel cell during the first control being performed to be larger than that before the switching condition was satisfied. |
| US11424455B2 |
Lithium secondary battery and card with built-in battery
Provided is a lithium secondary battery including: a positive electrode plate being a lithium complex oxide sintered plate; a negative electrode layer; a separator; a positive electrode current collector foil; a negative electrode current collector foil; an electrolytic solution; a pair of exterior films having outer peripheral edges sealed with each other to form an internal space that accommodates the battery elements; a positive electrode tab terminal; and a negative electrode tab terminal, wherein the inner peripheral edge of the sealed part of the exterior films and the outer peripheral edge of the positive electrode plate are apart from each other at a distance Wp of 2.0 to 4.0 mm on the side on which the positive electrode tab terminal is sealed, and the electrolytic solution has a volume of 1.05 to 1.25 times the total void volume of the positive electrode plate, the separator, and the negative electrode layer. |
| US11424435B2 |
High oxidation state periodate battery
The development of a novel battery comprising of high-oxidation-state periodate complex cathode and zinc anode is disclosed. A periodate complex H7Fe4(IO4)3O8 was prepared by a precipitation reaction between Fe(NO3)3 and NaIO4, and was used in battery development for the first time. NaMnIO6 double periodate salts were also synthesized from MnSO4 and NaIO4 using the same techniques. The H7Fe4(IO4)3O8 alone showed specific capacity of 300 mAh g−1; while NaMnIO6 showed specific capacity as high as 750 mAh g−1. Compared to single-electron processes in conventional cathode reactions, the possibility to significantly enhance cathode specific capacity via a multi-electron process associated with valence change from I(VII) to I2 is demonstrated. Novel 3D-printed reserve battery casing designs comprising replaceable electrodes also disclosed. Batteries featuring an ion-exchange membrane dual-electrolyte design are disclosed. Periodate based dry cell batteries utilizing polymer electrolytes are also disclosed. |
| US11424433B2 |
Method for manufacturing electrode
A method for manufacturing an electrode having an irregular shape through a simple process while minimizing the amount of wasted electrode active material is provided. The method results in first to third coating areas formed to be spaced apart from each other on a collector, a plurality of fourth coating areas formed between the first coating area and the second coating area, and a plurality of fifth coating areas formed between the second coating area and the third coating area. The plurality of fourth coating areas and the plurality of fifth coating areas are dislocated from each other when viewed from one side in a width direction of the collector. |
| US11424426B2 |
White organic light emitting device and organic light emitting display device using the same
A white organic light emitting device and an organic light emitting display device using the white organic light emitting device stably implement white light in a tandem-type top emission structure through uniform lifespans according to emitted colors of light despite driving of the white organic light emitting device for a long time. |
| US11424425B2 |
Electroluminescent device, and display device comprising thereof
An electroluminescent device includes a first electrode and a second electrode facing each other; a hole transport layer between the first electrode and the second electrode; a light emitting layer including a first light emitting layer disposed between the hole transport layer and the second electrode and including a first quantum dot and a second light emitting layer between the first light emitting layer and the second electrode and including a second quantum dot; and an electron transport layer between the light emitting layer and the second electrode. Each of the first and second light emitting layers emits first light, each of the first and second quantum dots has a core-shell structure including one or more shells, and the first and second quantum dots have different numbers of shells from each other or have different total thicknesses of the one or more shells from each other. |
| US11424421B2 |
Bio-molecular engineering strategy for efficient perovskite materials and devices
Embodiments relate to a light-harvesting perovskite layer including having deoxyribonucleic acid (DNA) molecules incorporated within the perovskite crystal to serve as an effective carrier transport medium. Some embodiments include formation of a DNA doped MAPbI3, the DNA doped MAPbI3 being formed by using a DNA-hexadecyl trimethyl ammonium chloride (“DNA-CTMA”) complex. The DNA doped MAPbI3 can be used as the light-harvesting perovskite layer in a photovoltaic device. Other molecules such as artemisinin (ART) and melanin are also demonstrated to show the effectiveness in charge and thermal transport. |
| US11424413B2 |
Electroluminesecent material, method for manufacturing same, and luminesecent device
The present disclosure provides an electroluminescent material, a method for manufacturing the electroluminescent material, and a luminescent device, by employing a fluorenyl group showing good planarity and strong visible π-π* absorption as π-based system, and simultaneously introducing a compound containing a carbazole group as an electron donor and a compound containing a pyridine group as an electron acceptor to realize an electroluminescent material, a method for manufacturing the electroluminescent material and a luminescent device with emitting a blue light and a high electroluminescence efficiency. |
| US11424411B2 |
Phenanthrene compounds for organic electronic devices
The invention relates to specific phenanthrenes, the use of the compound in an electronic device, and an electronic device containing at least one of said compounds. The invention further relates to a method for producing the compound and a formulation and composition containing one or more of the compounds. |
| US11424409B2 |
Semiconductor and ferromagnetic insulator heterostructure
A first aspect provides a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor formed over a substrate and a coating of superconductor formed over at least part of the semiconductor; wherein at least some of the nanowires further comprise a coating of ferromagnetic insulator disposed over at least part of the semiconductor. A second aspect provides a method of fabricating a quantum or spintronic device comprising a heterostructure of semiconductor and ferromagnetic insulator, by: forming a portion of the semiconductor over a substrate in a first vacuum chamber, and growing a coating of the ferromagnetic insulator on the semiconductor by epitaxy in a second vacuum chamber connected to the first vacuum chamber by a vacuum tunnel, wherein the semiconductor comprises InAs and the ferromagnetic insulator comprises EuS. |
| US11424408B2 |
ReRAM structure and method of fabricating the same
An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer. |
| US11424406B2 |
Generating self-aligned heater for PCRAM using filaments
A method includes forming a bottom electrode, forming a dielectric layer, forming a Phase-Change Random Access Memory (PCRAM) region in contact with the dielectric layer, and forming a top electrode. The dielectric layer and the PCRAM region are between the bottom electrode and the top electrode. A filament is formed in the dielectric layer. The filament is in contact with the dielectric layer. |
| US11424405B2 |
Post treatment to reduce shunting devices for physical etching process
A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode. |
| US11424403B2 |
Magnetoresistive random-access memory cell having a metal line connection
A method of fabricating an MRAM device, the method including forming a magnetoresistive random-access memory (MRAM) stack comprising a first hard mask, forming sidewall spacers adjacent to the MRAM stack, forming a layer of interconnect metal around and above the MRAM stack, recessing the interconnect metal, forming a layer of a second hard mask over the interconnect metal, and patterning and etching the second hard mask and interconnect metal, forming interconnect metal lines. |
| US11424399B2 |
Integrated thermoelectric devices in Fin FET technology
Operations for integrating thermoelectric devices in Fin FET technology may be implemented in a semiconductor device having a thermoelectric device. The thermoelectric device includes a substrate and a fin structure disposed on the substrate. The thermoelectric device includes a first connecting layer and a second connecting layer disposed on opposing ends of the fin structure. The thermoelectric device includes a first thermal conductive structure thermally and a second thermal conductive structure thermally coupled to the opposing ends of the fin structure. The fin structure may be configured to transfer heat from one of the first thermal conductive structure or the second thermal conductive structure to the other thermal conductive structure based on a direction of current flow through the fin structure. In this regard, the current flow may be adjusted by a power circuit electrically coupled to the thermoelectric device. |
| US11424398B2 |
Thermoelectric conversion material and thermoelectric conversion module
The present invention improves the performance of a thermoelectric conversion material and a thermoelectric conversion module. A thermoelectric conversion material has a mother phase containing a chimney ladder type compound comprising a first element of groups 4 to 9 and a second element of groups 13 to 15 and an additive phase existing at a grain boundary of the mother phase, the mother phase contains a third element to change a lattice constant of the chimney ladder type compound, and the additive phase contains the second element. |
| US11424397B2 |
Electrode material for thermoelectric conversion modules and thermoelectric conversion module using same
Provided are an electrode material for thermoelectric conversion modules capable of preventing cracking and peeling of electrodes that may occur at the bonding parts of a thermoelectric element and an electrode under high-temperature conditions to thereby maintain a low resistance at the bonding parts, and a thermoelectric conversion module using the material. The electrode material for thermoelectric conversion modules includes a first substrate and a second substrate facing each other, a thermoelectric element formed between the first substrate and the second substrate, and an electrode formed on at least one substrate of the first substrate and the second substrate, wherein the substrate is a plastic film, the thermoelectric element contains a bismuth-tellurium-based thermoelectric semiconductor material, a telluride-based thermoelectric semiconductor material, an antimony-tellurium-based thermoelectric semiconductor material, or a bismuth-selenide-based thermoelectric semiconductor material, the electrode that is in contact with the thermoelectric element is formed of a metal material, and the metal material is gold, nickel, aluminum, rhodium, platinum, chromium, palladium, stainless steel, molybdenum or an alloy containing any of these metals. |
| US11424393B2 |
Light-emitting diode and light-emitting module
A light-emitting module and a light-emitting diode are provided. The light-emitting diode includes an epitaxial light-emitting structure to generate a light beam with a broadband blue spectrum. A spectrum waveform of the broadband blue spectrum has a full width at half maximum (FWHM) larger than or equal to 30 nm. The spectrum waveform has a plurality of peak inflection points, and a difference between two wavelength values to which any two adjacent ones of the peak inflection points respectively correspond is less than or equal to 18 nm. |
| US11424392B2 |
Light emitting diode apparatus and manufacturing method thereof
A manufacturing method of a light emitting diode apparatus is provided. This method includes forming a light emitting diode on the substrate, forming a light leakage preventing layer to surround the side surface of the light emitting diode, etching a region corresponding to the light emitting diode in the substrate, and bonding a wavelength converting material to a lower portion of the light emitting diode in the etched region, in which the wavelength converting material includes a semiconductor layer including a quantum well layer. |
| US11424386B2 |
Multi-color light-emitting device and method of manufacturing such a device
A light-emitting device including first, second, and third pixels, wherein: the first pixel includes a two-dimensional light-emitting cell including a vertical stack of a first semiconductor layer of a first conductivity type, of an active layer, and of a second semiconductor layer of the second conductivity type; each of the second and third pixels includes a three-dimensional light-emitting cell including a plurality of nanostructures of same dimensions regularly distributed across the surface of the pixel, each nanostructure including a doped pyramidal semiconductor core of the first conductivity type, an active layer coating the lateral walls of the core, and a doped semiconductor layer of the second conductivity type coating the active layer; and the nanostructures of the second and third pixels have different dimensions and/or a different spacing. |
| US11424384B2 |
Light-emitting device and method of manufacturing the same
A method of manufacturing a light-emitting device includes: arranging a plurality of light-emitting elements each having an upper surface; disposing a first reflective member between the plurality of light-emitting elements such that the upper surface of each of the plurality of light-emitting elements are exposed and such that lateral surfaces of the light-emitting elements are covered with the first reflective member; disposing a light-transmissive member over the upper surface of each of the plurality of light-emitting elements and the first reflective member; forming a plurality of grooves surrounding one or two or more light-emitting elements by removing a portion of the light-transmissive member and a portion of the first reflective member; disposing a second reflective member to fill the plurality of grooves; and cutting the second reflective member to perform singulation. |
| US11424383B2 |
Semiconductor device
A semiconductor device includes: a first semiconductor region; and a first electrode on the first semiconductor region; wherein first semiconductor region includes a first layer and a second layer, the second layer includes a first portion and a second portion adjacent to the first portion, the first portion has a first thickness, the second portion has a second thickness less than the first thickness, the first layer includes a first material and a first dopant, the first material includes multiple elements, the first dopant has a first concentration, the second layer includes a second material and a second dopant, the second material includes multiple elements, the second dopant has a second concentration, one of the elements of the first material of the first layer is different from the elements of the second material of the second layer. |
| US11424378B2 |
Thin-film photovoltaic cell
A photovoltaic device is provided that comprises a photovoltaic active zone being formed of a stack of thin films comprising a first electrode, an absorber film and a metallic electrode. A collection gate is arranged in contact with the first electrode to reduce its electrical resistance and avoid direct physical or electrical contact with the metallic electrode. The photovoltaic active zone includes a plurality of channels, made in the metallic electrode and the absorber film. The collection gate is separated from the metallic electrode and from the absorber film by a dielectric material. |
| US11424377B2 |
Photodiode with integrated, light focusing element
The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface. |
| US11424374B2 |
Camera module optical system
A camera module optical system is provided, having a main axis, including an optical module and an adjustment assembly. The optical module is configured to hold an optical element having an optical axis. The adjustment assembly is configured to adjust the optical axis of the optical module parallel to the main axis. The optical module and the adjustment assembly are arranged along the main axis, wherein the adjustment assembly does not overlap the optical module when viewed in a first direction that is perpendicular to the main axis. |
| US11424371B2 |
Multi-trench Schottky diode
A multi-trench schottky diode includes a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer stacked on the termination trench structure and the interlayer dielectric layer extends between the second trench structure and the third trench structure. The passivation layer is on the first metal layer and the interlayer dielectric layer. The second metal layer on the first metal layer and the passivation layer extends to the first trench structure. Thus, the electric field is dispersed and the voltage breakdown can be avoided with the trench structures in the termination area. |
| US11424370B2 |
Non-volatile memory device and method for manufacturing the same
A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact. |
| US11424369B2 |
Semiconductor device and method for manufacturing semiconductor device
A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M. The third oxide and the fourth oxide include a region where the concentration of the element M is higher than that in the second oxide. |
| US11424368B2 |
Semiconductor device including an oxide semiconductor
A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity. |
| US11424365B2 |
Two dimension material fin sidewall
A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins. |
| US11424360B1 |
Semiconductor device and method for manufacturing the same
A semiconductor device includes a substrate, a dielectric layer, a source region, a drain region, and a metal structure. The substrate has a trench therein, and the dielectric layer is conformally formed over the substrate and the trench. The source region and the least one drain region are in the substrate. The metal structure is filled in the trench and surrounded by the dielectric layer, and the metal structure is disposed between the source region and the drain region. Moreover, the metal structure has a first metal portion and a second metal portion which has a height greater than a height of the first metal portion, and the first metal portion is disposed between the drain region and the second metal portion. |
| US11424353B2 |
Semiconductor structure and method for manufacturing the same
The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a channel layer and a barrier layer that are sequentially superimposed, and a gate region being defined on a surface of the barrier layer; and a p-type semiconductor material layer formed in the gate region, the p-type semiconductor material layer including at least one composition change element, and a component of the composition change element changing along an epitaxial direction. |
| US11424352B2 |
Semiconductor structure and method for manufacturing the same
The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a channel layer, a barrier layer located on the channel layer, a composition change layer located on the barrier layer, and a p-type semiconductor material layer located in the gate region of the composition change layer, wherein a gate region is defined on a surface of the composition change layer, and a material of the composition change layer includes at least one composition change element. |
| US11424351B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device is provided, including: a semiconductor substrate having a first conductivity type of drift region; a transistor section having a gate trench section on an upper surface of the semiconductor substrate; a diode section having a first conductivity type of cathode region on a lower surface of the semiconductor substrate, the cathode region having a higher doping concentration than the drift region; and a buffering region arranged between the transistor section and the diode section, the diode section having a first upper surface side lifetime control region where a first valley portion is provided in a carrier lifetime distribution in a depth direction of the semiconductor substrate, and the buffering region having a second upper surface side lifetime control region where a second valley portion is provided in the carrier lifetime distribution, the second valley portion being wider, in the depth direction, than the first valley portion. |
| US11424350B2 |
Heterojunction bipolar transistor
A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks. |
| US11424346B2 |
Semiconductor device with programmable feature and method for fabricating the same
The present application discloses a semiconductor device with a programmable feature such as anti-fuse and a method for fabricating the semiconductor device. The semiconductor device includes a first insulating layer including a peak portion and an upper portion positioned on the peak portion, and first conductive blocks positioned on two sides of the peak portion. A width of the peak portion is gradually decreased toward a direction opposite to the upper portion, and the first conductive blocks are spaced apart by the peak portion. |
| US11424340B2 |
Memory device and method of forming the same
Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided. |
| US11424336B2 |
Gate contact over active region in cell
A system and method for laying out power grid connections for standard cells are described. In various implementations, gate metal is placed over non-planar vertical conducting structures, which are used to form non-planar devices (transistors). Gate contacts connect gate metal to gate extension metal (GEM) above the gate metal. GEM is placed above the gate metal and makes a connection with gate metal through the one or more gate contacts. Gate extension contacts are formed on the GEM above the active regions. Similar to gate contacts, gate extension contacts are formed with a less complex fabrication process than using a self-aligned contacts process. Gate extension contacts connect GEM to an interconnect layer such as a metal zero layer. Gate extension contacts are aligned vertically with one of the non-planar vertical conducting structures. Therefore, in an implementation, one or more gate extension contacts are located above the active region. |
| US11424334B2 |
Semiconductor device
A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided.The semiconductor device includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is positioned over the first insulating layer and the island-shaped semiconductor layer is positioned over the second insulating layer. The second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer. The semiconductor layer contains a metal oxide, the second insulating layer and the third insulating layer contain an oxide, the first insulating layer contains a metal oxide or a nitride, and the fourth insulating layer contains a metal nitride. |
| US11424331B1 |
Power semiconductor device for improving hot carrier injection
A power semiconductor device for improving a hot carrier injection is provided. A drain field plate is introduced at one side of a drain in a dielectric trench and connected to a drain electrode, having identical electric potential, thereby improving hole injection effects at a drain side of the dielectric trench. A shield gate field plate is introduced at one side of a source electrode in the dielectric trench and is connected to the source electrode or ground, thereby forming a shield gate. While decreasing gate drain parasitic capacitance Cgd, electron injection effects at a source electrode side of the dielectric trench are improved. With a trench etching method, the improvement of hot carrier injection can also be achieved by making carriers avoid a side wall of the dielectric trench on a path. |
| US11424329B2 |
Semiconductor device including indium, silicon and carbon with varying concentrations
A semiconductor device including first to fourth points defined using In ion intensity, Si concentration, and C concentration obtained from SIMS data. The active layer of the device is a first region between the first point and the second point. In addition, the C concentration in a third region between the third point and the fourth point is higher than the C concentration in a second region adjacent to the fourth region along a second direction. Also, the Si concentration in the second region is higher than the Si concentration in the third region. |
| US11424327B2 |
Semiconductor device, method for manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator
A semiconductor device of an embodiment includes an electrode; and a silicon carbide layer in contact with the electrode and including: a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the electrode, in contact with the electrode, and containing at least one oxygen atom bonded to four carbon atoms. |
| US11424326B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region. |
| US11424325B2 |
Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
Before formation of gate insulating films, an oblique ion implantation of oxygen into opposing sidewalls of trenches, from a top of an oxide film mask is performed, forming oxygen ion-implanted layers in surface regions of the sidewalls. A peak position of oxygen concentration distribution of the oxygen ion-implanted layers is inside the oxide film mask. After removal of the oxide film mask, HTO films constituting the gate insulating films are formed. During deposition of the HTO films, excess carbon occurring at the start of the deposition of the HTO films and in the gate insulating films reacts with oxygen in the oxygen ion-implanted layers, thereby becoming an oxocarbon and being desorbed. The oxygen ion-implanted layers have a thickness in a direction orthogonal to the sidewalls at most half of the thickness of the gate insulating films, and an oxygen concentration higher than any other portion of the semiconductor substrate. |
| US11424322B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device may include: a gallium oxide substrate including a first side surface constituted of a (100) plane, a second side surface constituted of a plane other than the (100) plane, and an upper surface; and an electrode in contact with the upper surface, in which the gallium oxide substrate may include: a diode interface constituted of a pn interface or a Schottky interface; and an n-type drift region connected to the electrode via the diode interface, and a shortest distance between the first side surface and the diode interface is shorter than a shortest distance between the second side surface and the diode interface. |
| US11424321B2 |
Semiconductor structure and preparation method thereof
The present invention provides a semiconductor structure and a preparation method thereof. A transition metal and an impurity are co-doped on a buffer layer above a substrate layer to reduce the leakage current of a semiconductor device, to improve the pinch-off behavior, and to avoid the device current collapse, moreover, the ranges of the concentration of the transition metal and the impurity in the buffer layer are controlled to ensure the balance of the leakage current during the dynamic characteristics of the device. |
| US11424318B2 |
Capacitor devices and fabrication methods thereof
A method for fabricating a capacitor device includes providing a substrate; forming a first-layer electrode on the substrate; and forming a conductive layer on the first-layer electrode. The roughness of the first-layer electrode is a first roughness, the roughness of the conductive layer is a second roughness, and the second roughness is smaller than the first roughness. The method further includes forming a dielectric layer on the conductive layer; and forming a second-layer electrode on the dielectric layer. According to the disclosed method and capacitor device, by forming the conductive layer on the first-layer electrode, the roughness of the bottom electrode of the capacitor device is reduced, which effectively reduces the presence of protrusions on the surface of the bottom electrode. Therefore, the breakdown electric voltage of the capacitor device may be improved, and leakage current may be avoided. As such, the reliability of the capacitor device may be improved. |
| US11424313B2 |
Display device
A display device may include a substrate, pixels, a first common voltage line, an outer common voltage trunk line, a first outer common voltage line, and a second outer common voltage line. The substrate may include a display area and a non-display area. The pixels may be disposed on the display area. The first common voltage line may be at least partially disposed on the display area. The outer common voltage trunk line may be disposed on the non-display area, may be electrically connected through the first common voltage line to the pixels, and may include a groove. The first outer common voltage line may protrude from the outer common voltage trunk line. The second outer common voltage line may protrude from the outer common voltage trunk line. The groove may be disposed between the second outer common voltage line and the first common voltage line. |
| US11424311B2 |
Flexible display panel having mask-etching metal connection line in display and non-display areas and fabricating method thereof
A flexible display panel and a fabricating method thereof are provided. The fabricating method has: disposing an active layer and a gate of a switching tube of the flexible display panel sequentially on a substrate, wherein the switching tube is in the display area; disposing a source and a drain on the gate, wherein a signal connection line at same layer as the source and the drain is disposed in the non-display area; disposing a first insulating layer and a metal connection line sequentially on the source and the drain, wherein the first insulating layer and/or the metal connection line further extends into the non-display area and covers the signal connection line. This application increases thickness of film layers on the signal connection line, and also avoids phenomenon that the signal connection line is etched away due to over-etching upon etching the metal connection line, thereby causing disconnection phenomenon. |
| US11424309B2 |
Substrate and display device having a gate driver on array circuit
The A substrate includes a base substrate, a wiring layer, a flexible layer, and a gate driver on array circuit, which are sequentially stacked from bottom to top. One side of the wiring layer is provided with a through hole penetrating the flexible layer to expose the gate driver on array circuit, so that the gate driver on array circuit is electrically connected to the wiring layer with the through hole. |
| US11424306B2 |
Display device and method of manufacturing the same
A display device includes a substrate including a first display area and a second display area, the first display area including a first pixel, and the second display area including a second pixel and a transmissive area, a first pixel electrode and a first emission layer in the first pixel, a second pixel electrode and a second emission layer in the second pixel, an opposite electrode arranged as one body in the first display area and the second display area, and a top layer arranged on the opposite electrode, wherein the opposite electrode and the top layer each have an opening area corresponding to the transmissive area, and wherein a convex portion is around the transmissive area, the convex portion being convex in a top surface direction of the substrate. |
| US11424303B2 |
Array substrate, display panel, and display apparatus having a pixel defining layer with thickness thinning regions
An array substrate may include a base substrate and a pixel defining layer on the base substrate. The pixel defining layer may include a plurality of thickness thinning regions. The thickness thinning regions may have a smaller height than other areas of the pixel defining layer on the base substrate. The plurality of the thickness thinning regions may be configured to guide flow of fillers to form an encapsulating layer on the pixel defining layer. |
| US11424300B2 |
Display apparatus
A display apparatus includes a thin-film encapsulation layer covering pixel on a substrate and including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer having a different length from that of the first inorganic encapsulation layer, a touch electrode located on the thin-film encapsulation layer, a touch contact line spaced apart from the thin-film encapsulation layer and located outside the thin-film encapsulation layer, an insulating layer located on the touch contact line, a touch contact hole formed in the insulating layer and spaced apart from the thin-film encapsulation layer, and a touch connection line extending from the touch electrode toward the touch contact hole and connected to the touch contact line through the touch contact hole. |
| US11424299B2 |
Pressure sensitive display device having touch electrode and light emitting layer
Provided is a pressure sensitive display device including a sensing substrate, a reaction substrate provided on the sensing substrate, and spacers provided between the sensing substrate and the reaction substrate to space the sensing substrate apart from the reaction substrate. Here, the sensing substrate includes a flexible substrate and a touch electrode provided on one surface of the flexible substrate, which faces the reaction substrate. The reaction substrate includes a transparent substrate, a transparent electrode provided on one surface of the transparent substrate, which faces the sensing substrate, and a light emitting layer disposed on the transparent electrode. |
| US11424298B2 |
Display panel and display device
A display panel and a display device are provided. The display panel includes an imaging layer, a pinhole light-shielding layer, a display array layer and a touch layer. The imaging layer, the display array layer and the touch layer are sequentially disposed; the pinhole light-shielding layer is between the imaging layer and the touch layer, and includes light-shielding regions and at least one hole-shaped light-transmitting region that is corresponding to the imaging layer; the display array layer is configured to emit light from a side away from the imaging layer; and the touch layer includes touch mesh patterns formed by conductive wires, and at least one of the touch mesh patterns includes a first mesh corresponding to the hole-shaped light-transmitting region and includes second meshes outside the first mesh, and a size of the first mesh is larger than sizes of the second meshes. |
| US11424294B2 |
Display panel including sub-pixels arranged in an array that comprises N rows and 4M columns and display device having the same
A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array which includes N rows and 4M columns, sub-pixel units in each row is divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit and a fourth sub-pixel unit which are sequentially in four adjacent columns along a first direction. |
| US11424293B2 |
Method for manufacturing display panel
The present disclosure provides a display panel. The light-emitting layers within a same sub-pixel have different thicknesses, and emit light that overlap with each other at the same time, resulting in that the peak of the overall microcavity characteristic curve has a wide range. Thus, the position of the peak of the overall microcavity characteristic curve produced by the sub-pixel can overlap with the position of the peak of the inherent brightness characteristic curve of the light-emitting layer within a wider range of angles, such that the electroluminescence spectrum changes less with change of viewing angles. Therefore, the color shift at different viewing angles is reduced, and there is no substantial difference for visual sensation for color when viewing the OLED display panel including such sub-pixels at different viewing angles. |
| US11424292B2 |
Memory array containing capped aluminum access lines and method of making the same
A cross-point memory device includes first conductive line structures laterally extending along a first horizontal direction, an array of memory pillar structures overlying top surfaces of the first conductive line structures, such that each of the memory pillar structures includes a respective memory element, and second conductive line structures laterally extending along a second horizontal direction and overlying top surfaces of the array of memory pillar structures. At least one of the first conductive line structures and the second conductive line structures each includes a respective aluminum-containing rail and a respective metallic cap strip in contact with a top surface of the respective aluminum-containing rail. |
| US11424288B2 |
Display device having improved alignment
A display device includes: a substrate including a pixel; a scan line for supplying a scan signal to the pixel; a data line for supplying a data signal to the pixel; a first power line for supplying a first driving power source to the pixel; a second power line for supplying a second driving power source to the pixel; and a third power line for supplying a ground voltage to the pixel. The pixel includes: first and second electrodes spaced apart from each other on the substrate; a plurality of light emitting elements, each of the light emitting elements having first and second end portions in a length direction thereof and being arranged between the first electrode and the second electrode; and a first switch electrically connected between the third power line and the first electrode. The first switch is configured to be turned on by a control signal. |
| US11424287B2 |
Light emitting diode integrated with transition metal dichalcogenide transistor and method for manufacturing the same
The inventive concept relates to a light emitting diode integrated with a transition metal dichalcogenide-based transistor and capable of simultaneously fabricating the transistor to have a monolithic integration structure. The transition metal dichalcogenide is formed on the light emitting diode device, thereby providing the light emitting diode integrated with the transistor without affecting the characteristics of the light emitting diode device. |
| US11424279B2 |
Imaging element and electronic device including imaging device
In an imaging element, a plurality of pixels each having a photoelectric conversion part is arranged in a two-dimensional matrix. Some of the plurality of pixels each have a polarizer placed therein on a side of a light beam incidence plane. At least some of pixels having no polarizer placed therein each have a material layer placed therein that prevents transmission of a light beam having a wavelength of a predetermined range, to reduce color mixture in the pixel having the polarizer placed therein. |
| US11424275B2 |
Flexible display device
The present disclosure provides a flexible display device including a substrate, a first metal layer, a first insulating layer and a second insulating layer. The substrate includes an active region and a peripheral region adjacent to the active region. The first metal layer is disposed on the substrate. The first insulating layer is disposed on the first metal layer, and the first insulating layer includes a first via hole disposed in the peripheral region. The second insulating layer is disposed on the first insulating layer, and the second insulating layer includes a second via hole. In a top view direction of the flexible display device, the first via hole is disposed within the second via hole, and the second via hole exposes a portion of a top surface of the first insulating layer. |
| US11424272B2 |
Display panel with pixel structure and display apparatus
A display panel includes a pixel structure, including a plurality of pixel groups, and the pixel group includes: a first switch, having a second end coupled to a first main pixel; a second switch, having a second end coupled to a first sub-pixel; a third switch, having a second end coupled to the first sub-pixel; a first capacitor, having one end coupled to a first end of the third switch and another end coupled to a common electrode; and a fourth switch, having a second end coupled to a second main pixel; a fifth switch, having a second end coupled to a second sub-pixel; a sixth switch, having a second end coupled to the second sub-pixel; a second capacitor, having one end coupled to a first end of the sixth switch and another end coupled to the common electrode. |
| US11424270B2 |
Flexible display device and manufacturing method thereof
A flexible display device and a method of manufacturing thereof are provided. The flexible display device includes a flexible substrate, a thin film transistor disposed on the flexible substrate, a luminescent layer disposed on the thin film transistor, a first retaining wall and a second retaining wall disposed on the thin film transistor, and an encapsulation layer. The encapsulation layer includes a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer covers the first retaining wall, the second retaining wall, and one part of the thin film transistor. A plurality of first grooves are disposed in the first inorganic layer. The organic layer fills the plurality of first grooves and covers the luminescent layer and the other part of the thin film transistor. The second inorganic layer covers the first inorganic layer and the organic layer. |
| US11424269B2 |
Method of fabricating vertical memory device
In a method, a stack structure including a plurality of first interlayer sacrificial layers and a plurality of second interlayer sacrificial layers that are alternately stacked is formed over a substrate. A trench penetrating the stack structure is formed. A channel layer covering a sidewall surface of the trench is formed. The plurality of first interlayer sacrificial layers are selectively removed to form a plurality of first recesses. The plurality of first recesses are filled with a conductive material to form a plurality of channel contact electrode layers. The plurality of second interlayer sacrificial layers are selectively removed to form a plurality of second recesses. A plurality of interfacial insulation layers, a plurality of ferroelectric layers and a plurality of gate electrode layers are formed in the plurality of second recesses. |
| US11424267B2 |
Dielectric extensions in stacked memory arrays
In an example of forming a stacked memory array, a stack of alternating first and second dielectrics is formed. A dielectric extension is formed through the stack such that a first portion of the dielectric extension is in a first region of the stack between a first group of semiconductor structures and a second group of semiconductor structures in a second region of the stack and a second portion of the dielectric extension extends into a third region of the stack that does not include the first and second semiconductor structures. An opening is formed through the first region, while the dielectric extension couples the alternating first and second dielectrics in the third region to the alternating first and second dielectrics in the second region. |
| US11424263B2 |
Boundary design to reduce memory array edge CMP dishing effect
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed within a substrate and a plurality of memory devices disposed within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. The first isolation structure has a protrusion extending outward from an upper surface of the first isolation structure. A logic wall is arranged on the protrusion and surrounds the plurality of memory devices. |
| US11424262B2 |
Microelectronic devices including staircase structures, and related memory devices and electronic systems
A microelectronic device comprises a stack structure, a stadium structure within the stack structure, a source tier underlying the stack structure, and a masking structure. The stack structure has tiers each comprising a conductive structure and an insulating structure. The stadium structure comprises a forward staircase structure, a reverse staircase structure, and a central region horizontally interposed between the forward staircase structure and the reverse staircase structure. The source tier comprises discrete conductive structures within horizontal boundaries of the central region of the stadium structure and horizontally separated from one another by dielectric material. The masking structure is confined within the horizontal boundaries of the central region of the stadium structure and is vertically interposed between the source tier and the stack structure. The masking structure comprises segments horizontally covering portions of the dielectric material horizontally interposed between the discrete conductive structures. Additional devices and electronic systems are also described. |
| US11424261B2 |
Integrated circuit with different memory gate work functions
Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function. |
| US11424258B2 |
Flash and fabricating method of the same
A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The shape angle connects to the first concave surface. |
| US11424255B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate. |
| US11424254B2 |
Semiconductor device and manufacturing method of the same
A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates. |
| US11424252B2 |
Small-area and low-voltage anti-fuse element and array
A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array. |
| US11424250B2 |
Memory
An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap. |
| US11424249B2 |
Method for fabricating a semiconductor device having a trench exposing a sidewall of the contact plug aligned with the sidewall of the substrate
A method including forming an inter-layer insulation layer on a substrate, forming a plug material penetrating the inter-layer insulation layer and contacting a portion of the substrate, forming a contact plug by etching the plug material, forming a trench exposing a side wall of the contact plug by etching the substrate and the inter-layer insulation layer to be aligned with a side wall of the contact plug, forming a gate insulation layer on a surface of the trench and the exposed side wall of the contact plug, and forming a gate electrode partially filling the trench on the gate insulation layer. The method includes an inter-layer insulation layer formed on a substrate, a contact plug penetrating the inter-layer insulation layer and contacting a portion of the substrate, trenches extending in a line shape and aligned with side walls of the contact plug, and a plug spacer positioned between the trenches and surrounding the contact plug. |
| US11424248B2 |
Bitline structure for three-dimensional integrated circuit and method of forming the same
The invention involves a method of manufacturing a bonded semiconductor structure, comprising providing a support substrate which carries a transistor, and providing an interconnect region earned by the support substrate. The interconnect region includes a first multiple bypass bitline having an upper bypass interconnect and upper bypass via. The method includes providing a first conductive bonding layer carried by the interconnect region, wherein the first conductive bonding layer is connected to the upper bypass interconnect through the upper bypass via, and providing a vertical transistor carried by the first conductive bonding layer, the vertical transistor being in communication with the transistor through the interconnect region. The first multiple bypass bitline reduces the impedance experienced by the vertical transistor. |
| US11424245B2 |
Self-aligned gate endcap (SAGE) architecture having gate contacts
Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure. |
| US11424241B2 |
Devices, memory devices, and methods of forming devices
A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described. |
| US11424240B2 |
Semiconductor device and amplifier
A semiconductor device includes an electric circuit configured to include, a transistor, a first pad coupled to a gate or a drain of the transistor, a second pad coupled to the gate or the drain of the transistor, a first wiring that extends from the gate or the drain of the transistor to the first pad, and a second wiring that diverges from the first wiring and extends to the second pad, and a redistribution layer formed over the electric circuit and configured to include a first redistribution coupled to the first pad, and a second redistribution coupled to the second pad to constitute a stub. |
| US11424239B2 |
Diodes for package substrate electrostatic discharge (ESD) protection
Embodiments may relate to a package substrate that is to couple with the die. The package substrate may include a signal line that is communicatively coupled with the die. The package substrate may further include a conductive line. The package substrate may further include a diode communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed. |
| US11424236B2 |
Facilitating alignment of stacked chiplets
In certain embodiments, a method for designing a semiconductor device includes generating a two-dimensional design for fabricating chiplets on a semiconductor substrate. The chiplets are component levels for a multi-chip integrated circuit. The two-dimensional design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The second chiplet is adjacent to the first chiplet on the semiconductor substrate. The second layout is a mirror image of the first layout across a reference line shared by the first chiplet and the second chiplet. The first surface of the first chiplet and the first surface of the second chiplet are both either top surfaces or bottom surfaces. The method further includes generating a photomask according to the design. |
| US11424234B2 |
Flexible foldable display screen and manufacturing method thereof
The present disclosure provides a flexible foldable display screen includes a glass substrate, a flexible screen body disposed on the glass substrate, and a controlling IC disposed at a top of the curing assembling area. The flexible screen body has a curing assembling area defined at an end thereof, and a display area disposed outside the curing assembling area. The glass substrate is disposed at a bottom of the curing assembling area, with the display area exposed from the glass substrate. The display area comprises a pixel sparse area formed at an edge of the display area, and a pixel dense area formed outside the pixel sparse area. A pixel unit density of pixel units in the pixel dense area is greater than that of pixel units in the pixel sparse area. |
| US11424230B2 |
Pixel structure and display device including the pixel structure
A pixel structure, a display device, and a method of manufacturing a pixel structure, the pixel structure including a base substrate; at least one first electrode arranged in an upper portion of the base substrate; at least one second electrode having a circular shape extending along a circumferential direction around the at least one first electrode; and a plurality of LED elements connected to the first and second electrodes. |
| US11424229B2 |
Pixel structure, display device including the pixel structure, and method of manufacturing the pixel structure
A pixel structure, a display device, and a method of manufacturing a pixel structure, the pixel structure including a base substrate; at least one first electrode arranged in an upper portion of the base substrate; at least one second electrode having a circular shape extending along a circumferential direction around the at least one first electrode; and a plurality of LED elements connected to the first and second electrodes. |
| US11424227B2 |
Display panel, display module, and display device
The present invention provides a display panel, a display module, and a display device. The display panel includes a substrate and micro-LEDs. The display module achieves an extremely-narrow-bezel design by attaching a support plate to one side of a flexible drive circuit board of the display panel, bending a bending region, and attaching a bonding region to another side of the support plate. Multiple display modules are arranged in a accommodating chamber defined by a back plate of the display device and are fixed and joined to each other. Accordingly, a narrow-gap joining technology for micro-LED is realized, thus solving a problem that the micro-LED is too small in size, and realizing large-sized micro-LED displays. |
| US11424226B2 |
Light-emitting device and method for producing a plurality of light-emitting devices
The invention relates to a light emitting device comprising: a support, at least two light-emitting elements at a top side of the support, first connection locations and a single second connection location at a bottom side of the support, wherein each light-emitting element comprises a first contact location and a second contact location at a side facing away from the support, each first contact location is connected to one of the first connection locations via a first connection, all of the second contact locations are connected to the second connection location via a second connection, the first connections run along an outer surface of the support, and the second connection runs through the support. |
| US11424224B2 |
LED display panel, LED display apparatus having the same and method of fabricating the same
A display panel including a circuit board having pads, light emitting devices electrically connected to the pads and arranged on the circuit board, each light emitting device having a first surface facing the circuit board, and a buffer material layer disposed between the circuit board and the light emitting devices to fill a space between the circuit board and the light emitting devices, in which the buffer material layer is disposed under the first surfaces of the light emitting devices. |
| US11424223B2 |
LED lighting arrangement
The invention describes an LED lighting arrangement comprising a single-layer carrier comprising a mounting surface, a metal core, and a dielectric layer between the mounting surface and the metal core; at least one LED string comprising a plurality of series-connected LED die packages mounted on the mounting surface, wherein the LED die packages of a string are arranged in a two-dimensional array comprising at least two rows; and at least one micro-via extending through the dielectric layer of the single-layer carrier and arranged to electrically connect the final cathode of an LED string to the metal core of the single-layer carrier. The invention further describes a lighting unit; and a method of manufacturing an LED lighting arrangement. |
| US11424217B2 |
Soldering a conductor to an aluminum layer
An arrangement is disclosed. In one example, the arrangement of a conductor and an aluminum layer soldered together comprises a substrate and the aluminum layer disposed over the substrate. The aluminum forms a first bond metal. An intermetallic compound layer is disposed over the aluminum layer. A solder layer is disposed over the intermetallic compound layer, wherein the solder comprises a low melting majority component. The conductor is disposed over the solder layer, wherein the conductor has a soldering surface which comprises a second bond metal. The intermetallic compound comprises aluminum and the second bond metal and is predominantly free of the low melting majority component. |
| US11424213B2 |
Semiconductor structure including a first surface mount component and a second surface mount component and method of fabricating the semiconductor structure
A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors. |
| US11424212B2 |
Semiconductor package structure and method for manufacturing the same
A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure. |
| US11424211B2 |
Package-on-package assembly with wire bonds to encapsulation surface
Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer. |
| US11424207B1 |
Non-volatile memory with different use of metal lines in word line hook up regions
To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines. |
| US11424205B2 |
Semiconductor interconnect structure and method
A semiconductor device includes a first interconnect structure over first substrate, a first bonding layer over the first interconnect structure, multiple first bonding pads disposed in a first region of the first bonding layer, the first bonding pads having a first pitch, and multiple second bonding pads disposed in a second region of the first bonding layer, the second region extending between a first edge of the first bonding layer and the first region, the second bonding pads having the first pitch, the multiple second bonding pads including multiple pairs of adjacent second bonding pads, wherein the second bonding pads of each respective pair are connected by a first metal line. |
| US11424203B2 |
Semiconductor module and method of manufacturing semiconductor module
A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, contains nickel or copper, and is electrically connected to the semiconductor device; a solder portion containing gold, disposed on the bonding layer; and a protective layer disposed directly on the bonding layer, covering an outer peripheral edge of the bonding layer. |
| US11424199B2 |
Connector formation methods and packaged semiconductor devices
Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector. |
| US11424198B2 |
Semiconductor device with graphene layers and method for fabricating the same
The present application discloses a semiconductor device with graphene layers and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first passivation layer positioned above the substrate, a redistribution layer positioned on the first passivation layer, a first adjustment layer positioned on the redistribution layer, a pad layer positioned on the first adjustment layer, and a second adjustment layer positioned between the pad layer and the first adjustment layer. The first adjustment layer and the second adjustment layer are formed of graphene. |
| US11424197B2 |
Package, package structure with redistributing circuits and antenna elements and method of manufacturing the same
A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation. |
| US11424196B2 |
Matching circuit for integrated circuit die
An integrated circuit (IC) die is disclosed. The IC die can include a signal via extending through the IC die. The IC die can include a transmission line extending laterally within the IC die in a direction non-parallel to the signal via, the transmission line configured to transfer an electrical signal to the signal via. The IC die can include a matching circuit disposed between the transmission line and the signal via. The matching circuit can include inductance and capacitance matching circuitry to compensate for parasitic inductance and capacitance introduced by transition from the IC die to an underlying carrier. |
| US11424192B2 |
Component-embedded substrate
A component-embedded substrate includes a first wiring substrate, an electronic component provided on the first wiring substrate, an intermediate wiring substrate provided around the electronic component on the first wiring substrate and connected to the first wiring substrate via a first connection member, a second wiring substrate provided above the first wiring substrate, the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second connection member, and an encapsulating resin filled between the first wiring substrate and the second wiring substrate and covering the electronic component and the intermediate wiring substrate. Side surfaces of the intermediate wiring substrate are entirely covered by the encapsulating resin. |
| US11424190B2 |
Multi-chip package and manufacture method thereof
A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via. |
| US11424188B2 |
Methods of fabricating integrated circuit devices having raised via contacts
A method of fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer over a semiconductor substrate and forming first and second via contacts in the first dielectric layer and extending below a bottom surface of the first dielectric layer. The method also includes etching back the first dielectric layer to expose upper portions of the first and second via contacts. The method further includes depositing an etch stop layer conformally on the upper portions of the first and second via contacts and on the first dielectric layer. In addition, the method includes depositing a second dielectric layer on the etch stop layer and forming first and second metal lines in the second dielectric layer to be electrically connected to the first via contact and the second via contact, respectively. |
| US11424184B2 |
Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems
A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises an upper portion having a first width, and a lower portion vertically interposed between the upper portion and the contact structures. The lower portion has a tapered profile defining additional widths varying from a second width less than the first width at an uppermost boundary of the lower portion to a third width less than the second width at a lowermost boundary of the lower portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described. |
| US11424176B2 |
Semiconductor device with sealed semiconductor chip
A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires. |
| US11424172B2 |
Semiconductor package
A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the side wall of the first semiconductor chip. |
| US11424169B2 |
Memory device including circuitry under bond pads
Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate. |
| US11424168B2 |
Manufacturing method of semiconductor device and semiconductor manufacturing apparatus involving thickness measurements
Provided is a method for manufacturing a semiconductor device utilizing the feature that there are a plurality of semiconductor substrates to measure the thickness thereof, when measuring the thickness of a plurality of semiconductor substrates upon the laser annealing treatment. For each of at least one semiconductor substrate of the plurality of semiconductor substrates, a laser annealing treatment is performed by controlling a laser beam irradiating the semiconductor substrate based on self-thickness data being data of a result of measurement of a thickness of the semiconductor substrate and reference thickness data being data of a result of measurement of a thickness of at least one semiconductor substrate other than the semiconductor substrate among the plurality of semiconductor substrates. |
| US11424166B2 |
Semiconductor structure and method for forming same
A semiconductor structure and a method for forming same are provided. One form of the forming method includes: providing a base, the base including: a substrate and a channel stack on the substrate, the channel stack including a first channel layer and a second channel layer located on the first channel layer, the first channel layer and the second channel layer being made of different materials, and a first region and a second region, where the channel stack is located in the first region and the second region; forming an interlayer dielectric layer on the substrate exposed from the channel stack, where a gate opening from which the channel stack is exposed is formed in the interlayer dielectric layer; removing the second channel layer of the first region in the gate opening; removing the first channel layer of the second region in the gate opening; and forming a gate structure surrounding a remainder of the first channel layer and the second channel layer. In some implementations of the present disclosure, channel regions of transistors in the first region and the second region are made of different materials to meet performance requirements of different transistors, thereby optimizing electrical performance of the semiconductor structure. |
| US11424164B2 |
Enhanced etch resistance for insulator layers implanted with low energy ions
In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted. |
| US11424163B2 |
Three-dimensional electronic device through organic solvent plasticization process of polymer frame, and method for manufacturing same
Provided are a three-dimensional electronic device manufactured through a polymer frame solvent-plasticizing process and a method for manufacturing the three-dimensional electronic device including a polymer frame configured to have a planar figure-like shape so as to have a polygonal bottom and adjacent surfaces which are formed to be extended from respective edges of the bottom; and a flexible electronic device which is transferred to the polymer frame. The polymer frame is exposed to organic solvent vapor and has a change in Young's modulus. |
| US11424158B2 |
Metal liner passivation and adhesion enhancement by zinc doping
A method comprises depositing a barrier layer on a dielectric layer to prevent oxidation of a metal layer to be deposited by electroplating due to an oxide present in the dielectric layer and depositing a doped liner layer on the barrier layer to bond with the metal layer to be deposited on the liner layer by the electroplating. The dopant forms a protective passivation layer on a surface of the liner layer and dissolves during the electroplating so that the metal layer deposited on the liner layer by the electroplating bonds with the liner layer. The dopant reacts with the dielectric layer and forms a layer of a compound between the barrier layer and the dielectric layer. The compound layer prevents oxidation of the barrier layer and the liner layer due to the oxide present in the dielectric layer and adheres the barrier layer to the dielectric layer. |
| US11424155B2 |
Semiconductor device package and manufacturing method thereof
Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. Methods and systems for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die. |
| US11424147B2 |
Deposition apparatus having particular arrangement of raw material supply port, partition plate, and opening for measuring a temperature
According to an aspect of the present invention, there is provided a deposition apparatus including: a reaction space which is a reaction chamber; a front chamber for deposition; a raw material supply port that is configured to supply a raw material to the reaction space; an opening for measuring a temperature of a wafer mounted on a wafer mounting surface of a mounting stage disposed in the reaction space; and a partition plate that partitions the reaction space and the front chamber for deposition, in which the raw material supply port is positioned on the same plane as the partition plate or on the reaction space side from the partition plate, and the opening is positioned in the front chamber for deposition side from the partition plate. |
| US11424146B2 |
Substrate processing apparatus and temperature measurement unit
There is provided a technique capable of easily improving accuracy of temperature measurement of a substrate, regardless of a film formation state of the substrate. There is provided a substrate processing apparatus including a substrate mounting table having a mounting surface on which a substrate is mounted, a heater configured to heat the substrate mounted on the mounting surface, and an elastically deformable temperature sensor whose leading end portion constitutes a temperature detection part. The temperature sensor is configured to extend from below the mounting surface to above the mounting surface, and the leading end portion protrudes from the mounting surface. |
| US11424140B2 |
Member, method of manufacturing the same, apparatus for manufacturing the same, and semiconductor manufacturing apparatus
A member includes a base material structure and a surface layer on the base material structure. The surface layer includes a particle that includes Y—O—F. The base material structure includes interface layers in contact with the surface layer. The interface layers of the base material structure include fluorine. |
| US11424138B2 |
Substrate cleaning tool, substrate cleaning apparatus, substrate processing apparatus, substrate processing method, and method of manufacturing substrate cleaning tool
A substrate cleaning apparatus comprises a substrate holding roller and an edge cleaner. The substrate holding roller is configured to hold and rotate a substrate to be processed. The edge cleaner is in contact with an edge portion of the substrate to be processed and includes resin material containing fluororesin particles at least in a portion in contact with the substrate to be processed. |
| US11424137B2 |
Drying process for high aspect ratio features
Embodiments described herein generally relate to a processing chamber incorporating a small thermal mass which enable efficient temperature cycling for supercritical drying processes. The chamber generally includes a body, a liner, and an insulation element which enables the liner to exhibit a small thermal mass relative to the body. The chamber is also configured with suitable apparatus for generating and/or maintaining supercritical fluid within a processing volume of the chamber. |
| US11424136B2 |
Rare-earth oxide based coatings based on ion assisted deposition
A component for a processing chamber includes a ceramic body having at least one surface with a first average surface roughness. The component further includes a conformal protective layer on at least one surface of the ceramic body, wherein the conformal protective layer is a plasma resistant rare earth oxide film having a substantially uniform thickness of less than 300 μm over the at least one surface and having a second average surface roughness that is less than the first average surface roughness. |
| US11424128B2 |
Apparatus and method for etching substrate
A substrate etching apparatus for etching a substrate, the substrate etching apparatus includes a treatment container configured to accommodate a substrate, a stage on which the substrate is placed, the stage being disposed in the treatment container, a gas supply configured to supply a treatment gas from an upper space above the stage toward the stage, and a gas exhauster configured to evacuate an interior of the treatment container. The gas supply includes a central region facing a central part of the stage and an outer peripheral region having a same central axis as the central region and configured to surround the central region. The gas supply is capable of supplying the treatment gas to each of the central region and the outer peripheral region. |
| US11424124B2 |
Method of forming a patterned hard mask and method of forming conductive lines
A method of forming a patterned hard mask includes: forming first photoresist features on a hard mask layer; forming at least one sacrificial feature between immediately-adjacent two of the first photoresist features on the hard mask layer; performing a trimming process to the first photoresist features to form second photoresist features; and using the at least one sacrificial feature and the second photoresist features as etching mask, and performing a first etching process to the hard mask layer, in which a plurality of trenches are formed in the hard mask layer to obtain the patterned hard mask. |
| US11424122B2 |
Mask pattern, semiconductor structure and fabrication method thereof
A mask pattern, a semiconductor structure and a method for forming the semiconductor structure are provided. The mask pattern includes a first mask pattern and a second mask pattern. The first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction. The second mask pattern includes a plurality of second target patterns, and the plurality of second target patterns are arranged along the first direction. When the first mask pattern overlaps the second mask pattern, one of the plurality of first target patterns partially overlaps a corresponding one of the plurality of second target patterns. |
| US11424119B2 |
Method for selective deposition of silicon nitride layer and structure including selectively-deposited silicon nitride layer
A method for selectively depositing silicon nitride on a first material relative to a second material is disclosed. An exemplary method includes treating the first material, and then selectively depositing a layer comprising silicon nitride on the second material relative to the first material. Exemplary methods can further include treating the deposited silicon nitride. |
| US11424118B2 |
Electronic devices comprising silicon carbide materials
An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device. |
| US11424117B2 |
Broadband ultraviolet illumination sources
A broadband ultraviolet illumination source for a characterization system is disclosed. The broadband ultraviolet illumination source includes an enclosure having one or more walls, the enclosure configured to contain a gas, and a plasma discharge device based on a graphene-dielectric-semiconductor (GOS) planar-type structure. The GOS structure includes a silicon substrate having a top surface, a dielectric layer disposed on the top surface of the silicon substrate, and at least one layer of graphene disposed on a top surface of the dielectric layer. A metal contact may be formed on the top surface of the graphene layer. The GOS structure has several advantages for use in an illumination source, such as low operating voltage (below 50 V), planar surface electron emission, and compatibility with standard semiconductor processes. The broadband ultraviolet illumination source further includes electrodes placed inside the enclosure or magnets placed outside the enclosure to increase the current density. |
| US11424113B2 |
Two dimensional MS/MS acquisition modes
A method of mass spectrometry is disclosed comprising performing a plurality of experimental runs, wherein each experimental run comprises: periodically mass analysing fragment or product ions at a plurality of time intervals, wherein a delay time is provided between the start of the experimental run and the first time interval at which the fragment or product ions are mass analysed. Different delay times are provided in different ones of the experimental runs and fragment or product ions that have been analysed in the same time interval in at least one of said experimental runs and that have been analysed in different time intervals in at least one other of said experimental runs are identified as fragment or product ions of interest. These fragment or product ions are thus determined to relate to different precursor ions and are used to identify their respective precursor ions. |
| US11424111B2 |
Sputtering target assembly to prevent overetch of backing plate and methods of using the same
A sputtering target assembly, sputtering apparatus, and method, the target assembly including a backing plate having an aperture formed therein; and a target bonded to a front surface of the backing plate. The aperture is disposed on the backing plate such that a first end of the aperture is sealed by a portion of the target that is predicted by a sputtering target erosion profile to have the highest etching rate during a corresponding sputtering process. |
| US11424110B2 |
Plasma processing apparatus and operational method thereof
A plasma processing apparatus includes: a detector configured to detect a change in an intensity of light emission from plasma formed inside a processing chamber; and a unit configured to adjust conditions for forming the plasma or processing a wafer arranged inside the processing chamber using an output from the detector, wherein the detector detects a signal of the intensity of light emission at plural time instants before an arbitrary time instant during processing, and wherein the adjusting unit removes the component of a temporal change of a long cycle of the intensity of light emission from this detected signal and detects the component of a short temporal change of the intensity of light emission, and adjusts the conditions for forming the plasma or processing a wafer arranged inside the processing chamber based on the short temporal change of the detected intensity of light emission. |
| US11424108B2 |
Plasma processing apparatus
Provided is a plasma processing apparatus capable of obtaining desired etch profiles and preventing the degradation of yield rates due to the adhesion of particles, and equipped with a processing chamber in which a sample is plasma-treated; a radio-frequency power source for supplying radio-frequency power used to generate plasma; a sample stage which is provided with electrodes for electrostatically adsorbing the sample and on which the sample is mounted; and a DC power supply for applying DC voltages to the electrodes, the apparatus being further equipped with a control apparatus for controlling the DC power supply so as to apply such DC voltages as to decrease the absolute value of the potential of the sample in the absence of the plasma. |
| US11424104B2 |
Plasma reactor with electrode filaments extending from ceiling
A plasma reactor includes a chamber body having an interior space that provides a plasma chamber and having a ceiling, a gas distributor to deliver a processing gas to the plasma chamber, a pump coupled to the plasma chamber to evacuate the chamber, a workpiece support to hold a workpiece, and an intra-chamber electrode assembly. The intra-chamber electrode assembly includes an insulating frame, a first plurality of coplanar filaments that extend laterally through the plasma chamber between the ceiling and the workpiece support along a first direction, and a second plurality of coplanar filaments that extend in parallel through the plasma chamber along a second direction perpendicular to the first direction. Each filament of the first and second plurality of filaments includes a conductor at least partially surrounded by an insulating shell. A first RF power source supplies a first RF power to the conductor of the intra-chamber electrode assembly. |
| US11424101B2 |
Machine learning on wafer defect review
This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques. |
| US11424096B2 |
Temperature controlled secondary electrode for ion control at substrate edge
Embodiments of process kits for use in substrate processing chambers are provided herein. In some embodiments, a process kit for use in a substrate processing chamber includes an annular electrode configured to surround an electrostatic chuck, wherein the annular electrode includes an upper portion bonded to a lower portion and an annular channel disposed at an interface between the upper portion and the lower portion; wherein the annular electrode includes a first channel extending from a lower surface of the lower portion to the annular channel and a second channel extending from the lower surface of the lower portion to the annular channel; wherein the annular electrode is configured to flow a coolant from the first channel to the second channel via the annular channel to cool the annular electrode; and wherein the annular electrode includes at least one of a dielectric coating or a ceramic cap to reduce or prevent arcing between the annular electrode and the electrostatic chuck. |
| US11424093B2 |
Direct current hybrid circuit breaker with reverse biased voltage source
Within a direct current hybrid circuit breaker (DC HCB), a commutation unit (CU) is provided in a semiconductor switch path in series with a semiconductor switch to facilitate opening the DC HCB. The semiconductor switch path is connected in parallel with a mechanical switch path that includes a mechanical switch. The CU is a controlled voltage source which applies a reverse biased voltage on the semiconductor switch path. The CU causes the current through the mechanical switch to ramp down while the current through the semiconductor switch ramps up to a supply current. The CU maintains the current through the mechanical switch to remain at a zero vale by compensating for the voltage drop across the semiconductor switch and the self-inductance of the semiconductor switch path. The mechanical switch can open without current and against no recovery voltage. |
| US11424092B2 |
Rolling elements-based pivoting supports for keyboards
In one example, a keyboard device may include a base plate, a pivoting support fixedly disposed on the base plate and having a recess portion, a key cap support having a shaft portion rotatably received in the recess portion, a rolling element disposed between the shaft portion and the pivoting support, and a key cap assembled to the key cap support. |
| US11424089B2 |
Heat-absorbing-and-dissipating jacket for a terminal of an electrical device
The present disclosure envisages a heat-absorbing-and-dissipating jacket (80) for a terminal (100) of an electrical device (1000). The jacket has a body (81) configured to at least partially contour walls of the housing (10) of the terminal (100) and the jacket is made of a heat-absorbing-and-dissipating material. The body (81) of the jacket has a lower portion (86) extending operatively below the housing (10) of the terminal (100). The body (81) of the jacket also has an upper portion (88) extending operatively above the housing (10) of the terminal (100). The jacket (80) of the present disclosure is a cost-effective means which allows maximum heat absorption and dissipation from an enclosed electrical device and can be incorporated in an existing design of an electrical device. |
| US11424087B2 |
Electrical switching device
An electrical switching device includes a kinematic chain, a first encapsulation housing, a movable switching contact piece and a fixed switching contact piece. The movable switching contact piece is movable by the kinematic chain which penetrates the first encapsulation housing in a fluid-tight manner. The kinematic chain penetrates the first encapsulation housing in a linearly movable manner. |
| US11424083B2 |
Metal-organic frameworks for supercapacitor electrodes
Metal-organic frameworks, supercapacitor electrodes, and supercapacitors are generally provided. Some metal-organic frameworks described herein may be suitable for use in supercapacitor electrodes, some supercapacitor electrodes described herein may comprise a metal-organic framework described herein, and some supercapacitors described herein may comprise the supercapacitor electrodes described herein. |
| US11424081B2 |
Electrical energy storage apparatus and a method of preparing the same
An electrical energy storage apparatus and a method of preparing the same. The electrical energy storage apparatus includes a first energy storage device arranged to supply electrical energy to an external electrical load; a second energy storage device arranged to recharge the first energy storage when at least a portion of the second energy storage device is exposed to air. The second energy storage device includes an encapsulation arranged to selectively block an air exposure to the second energy storage device, so as to maintain the second energy storage device in an idle state. |
| US11424074B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor that includes a ceramic body including a stack of a plurality of dielectric layers and a plurality of internal electrodes; a first external electrode on a first end surface of the ceramic body and electrically connected to a first set of the plurality of internal electrodes; and a second external electrode on a second end surface of the ceramic body and electrically connected to a second set of the plurality of internal electrodes. The dielectric layer includes a plurality of dielectric grains including Ca, Zr, Ti and a rare earth element, P is present between the plurality of dielectric grains, and where at least a portion of the rare earth element is in a solid solution in the dielectric grains. |
| US11424068B2 |
Inductor
An inductor includes a main body having a bottom surface, a top surface positioned opposite to the bottom surface, four side surfaces connected to the bottom surface and the top surface, a metal body that includes a first metal portion buried in the main body and second metal portions extending outward from respective opposite longitudinal ends of the first metal portion. The second metal portions are exposed from respective opposite side surfaces of the main body. In the inductor, each second metal portion is formed into a tabular shape having a first surface with a plating layer and a second surface positioned opposite to the first surface. Each second metal portion is formed into an external terminal and includes a first bend and a second bend that are formed by bending the second metal portion. |
| US11424065B2 |
Coil electronic component
A coil electronic component includes first and second coil portions magnetically coupled to each other, an intermediate layer disposed between the first and second coil portions and including first magnetic particles, and an encapsulant encapsulating the first and second coil portions and including second magnetic particles. The intermediate layer and the encapsulant have permeabilities different from each other. |
| US11424064B2 |
Multilayer coil component
A multilayer coil component includes a body including laminated ferrite layers, a coil conductor including conductive layers laminated in the body, and a pair of outer electrodes disposed on the lower surface of the body. Each of the pair of outer electrodes is electrically connected to a corresponding one of the end portions of the coil conductor. The lower surface of the multilayer coil component includes a recessed section between the pair of outer electrodes. |
| US11424060B2 |
Superconducting coil and superconducting device
A superconducting coil of an embodiment includes a winding frame; a superconducting wire wound around the winding frame, the superconducting wire including a first region and a second region facing the first region; and a first layer placed between the first region and the second region, the first layer including a first particle and a thermosetting resin, the first particle including crystal having volume resistivity equal to or higher than 10−2 Ω·m and having cleavage, and the thermosetting resin surrounding the first particle. |
| US11424057B2 |
Power inductor
Provided is a power inductor. The power inductor includes a body including metal powder and a polymer, at least one base provided in the body, and at least one coil pattern disposed on at least one surface of the base. The metal powder includes at least three metal powder of which middle values of grain-size distribution are different from each other. |
| US11424056B2 |
Method for producing sintered R-T-B based magnet
A method for producing a sintered R-T-B based magnet includes: a step of providing a sintered R-T-B based magnet work; a step of providing an RL-RH-M based alloy; and a diffusion step. In the diffusion step, an adhering amount of the RL-RH-M based alloy to the magnet work is 4 to 15 mass %, and an adhering amount of RH is 0.1 to 0.6 mass %; in the magnet work, the R content accounts for 27 to 35 mass %, the Fe content in the entire T accounting for 80 mass % or more; and, in the RL-RH-M based alloy, the RL content accounts for 60 to 97 mass %; the RH content accounting for 1 to 8 mass %; and the M content accounts for 2 to 39 mass %. |
| US11424055B2 |
Magnetic powder and preparation method thereof
Provided are a SmFeN magnetic powder which is superior not only in water resistance and corrosion resistance but also in hot water resistance, and a method of preparing the powder. The present invention relates to a method of preparing a magnetic powder, comprising: plasma-treating a gas; surface-treating a SmFeN magnetic powder with the plasma-treated gas; and forming a coat layer on the surface of the surface-treated SmFeN magnetic powder. |
| US11424054B2 |
Thin-film resistors with flexible terminal placement for area saving
An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance. |
| US11424053B1 |
Ceramic feedthrough assemblies for electronic devices with metal housings
A ceramic feedthrough assembly has a feedthrough interface sleeve brazed to a ceramic feedthrough body and a housing interface sleeve brazed to the feedthrough interface sleeve. The housing interface sleeve is configured to be integrated within an electronic device and welded to a metal housing to form a hermetically sealed electronic device. The ceramic feedthrough has at least one embedded electrical conductor extending from a first location on the ceramic feedthrough body to a second location on the ceramic feedthrough body. The feedthrough interface sleeve is positioned around the ceramic feedthrough body between the first location and the second location and brazed to the wrap-around metallization. When the metal housing is welded to the housing interface sleeve, the ceramic feedthrough assembly facilitates connection to an electronic circuit hermetically sealed in the electronic device with the metal housing. |
| US11424048B2 |
Coaxial cable utilizing plated carbon nanotube elements and method of manufacturing same
A cable includes at least one inner conductor and an insulation layer surrounding the inner conductor. An outer conductive layer surrounds the insulation layer and center conductor and includes a carbon nanotube substrate having opposing face surfaces and edges. One or more metals are applied as layer(s) to the opposing face surfaces and edges of the carbon nanotube substrate for forming a metallized carbon nanotube substrate. The metallized carbon nanotube substrate is wrapped to surround the insulation layer and center conductor for forming the outer conductive layer. Embodiments of the invention include a braid layer positioned over the outer conductive layer. The braid layer is woven from of plurality of carbon nanotube yarn elements made of a plurality of carbon nanotube filaments. The carbon nanotube filaments include a carbon nanotube core and metal applied as a layer on the carbon nanotube core for forming a metallized carbon nanotube filaments and yarns woven to form the braid layer. |
| US11424046B2 |
Electronic enclosure with neutron shield for nuclear in-core applications
An enclosure for non-organic electronic components is provided which includes an inner cavity for housing non-organic electronic components and a neutron shielding barrier surrounding the inner cavity and the electronic components housed within the cavity. The barrier is formed from a neutron reflecting material in solid or powdered form and a neutron absorbing material in solid or powdered form. An optional structural support is provided in certain aspects of the enclosure design. |
| US11424044B2 |
While a nuclear reactor element extends into a cask, cutting the element to a length equivalent to internal height of the cask
A method of fragmentation of elements of a nuclear reactor includes placement of elements inside a cask and subsequent cutting, the cask being perforated. Each element is lowered into the cask by a full internal height of the cask using a gripper having clamping jaws. The element is intercepted at an upper edge of the cask, lifted, and positioned using video surveillance and artificial lighting so that a hydraulic cutter is directly under the clamping jaws. The element is cut at a point corresponding to a level of the upper edge of the cask, separating from the element a fragment equal to the internal height of the cask. Then the upper part of the element remaining after cutting is lowered inside the cask by the full internal height of the cask and the cutting of the element into fragments is repeated until the element is fully cut to fragments. |
| US11424038B2 |
Systems and methods for anatomical modeling using information obtained from a medical procedure
Systems and methods are disclosed herein for anatomical modeling using information obtained during a medical procedure, whereby an initial anatomical model is generated or obtained, a correspondence is determined between the initial model and additional data and/or measurements from an invasive or noninvasive procedure, and, if a discrepancy is found between the initial model and the additional data, the anatomical model is updated to incorporate the additional data and reduce the discrepancy. |
| US11424033B2 |
Information processing apparatus, control method therefor, and non-transitory computer-readable storage medium
An information processing apparatus 100 comprising: first inference unit configured to perform a first inference to medical image data and obtain information related to a diagnostic name identified from the medical image data as a first inference result; and second inference unit configured to perform a second inference to the medical image data and the information related to the diagnostic name and obtain information related to an image finding as a second inference result. |
| US11424029B2 |
System, method and apparatus for electronic patient care
A system for electronic patient care includes a gateway and a medical device. The gateway is configured to provide at least one of a routing functionality, a medical device software update, and a web service. The medical device is configured to operatively communicate with the gateway using the web service. |
| US11424022B2 |
Method for processing brain images
The present invention relates to a novel methodology for the field of brain images from Positron Emission Tomography (PET), likewise applicable to brain images from Single-Photon Emission Computer Tomography (SPECT) or another technique that makes it possible to generate images of brain metabolism, function or blood flow. This methodology arises from the need to improve the medical diagnosis of neurological disorders and from the need for objective, unbiased quantification of brain metabolism. The method is based on the spatial symmetry of the metabolism of the healthy human brain. Under this assumption, the entire healthy brain metabolism can be deduced from the metabolism of a single hemisphere of the brain. |
| US11424021B2 |
Medical image analyzing system and method thereof
Provided are a medical image analyzing system and a method thereof, which mainly crop a plurality of image patches from a processed image including a segmentation label corresponding to a location of an organ, train a deep learning model with the image patches to obtain prediction values, and plot a receiver operating characteristic curve to determine a threshold which determines whether the image patches are cancerous, thereby effectively improving the detection rate of cancer. |
| US11424017B2 |
Respiratory system and method that monitors medication flow
A respiratory system and method comprise a tracker module adaptable to be secured to a variety of inhalers, the tracker module sensing activation of the medication canister of the inhaler for delivery of medication to a user. The tracker module also senses the rate of inhalation air flow of the user when inhaling medication for determination of proper inhaler use. Upstream and downstream sensors provide flow information to determine quality of the inhalation. A flow sensor is an integral part of the tracking module and can be used on multiple inhalers. Other sensors are provided that monitor user presence at the inhaler, user technique in using the inhaler, and the attitude of the inhaler when it was used. Low power devices are used to conserve battery power. A spirometer provides user lung function data. |
| US11424015B2 |
Devices, systems, and methods for analyte monitoring having a selectable or variable response rate
Methods, devices, and systems are provided that determine analyte trends according to different methods depending on whether a change-resistant state is active or not active. The method used when the change-resistant state is activated provides for different requirements for a resulting analyte trend to transition between states (e.g., level to non-level). Furthermore, in some aspects, methods, devices, and systems of selecting or modifying a response rate of an analyte monitoring device for an individual user are provided. User instructions for selecting or modifying a response rate of the device or system is received externally via a user interface or communication channel. The response rate of the analyte monitoring device or system is then selected or modified to the first response rate, and the device or system operated with the first response rate. |
| US11424013B2 |
Systems and methods for sorting findings to medical coders
A sorter of medical findings for assessment by a medical coder is provided. In some embodiments, the sorter receives information about a user (coder), including identification, a role, and historical activity. The sorter determines whether to run in exploration or exploitation modes. Exploration is used to explore the scope of the findings and also identify variables that impact a finding. Exploitation is designed to maximize a goal (such as throughput or profitability). Lastly a finding is selected and provided to the user. The selection is based upon computing internal parameters when in exploration, or based upon optimizing for criteria when in exploitation. The sorter may also determine competency for the user, and cut them off from performing additional coding if they are found incompetent. |
| US11424012B1 |
Sectionalizing clinical documents
Techniques for sectionalizing clinical documents are provided. In one set of embodiments, a computer system can, for each page of a clinical document: identify one or more section header candidates in the page and, for each section header candidate, attempt to classify the section header candidate as corresponding to one of a plurality of section types using a first classifier or a second classifier. The computer system can further partition the page into one or more sections based on corresponding section header candidates that have been successfully classified using either the first classifier or the second classifier, where the partitioning includes associating each section with a section type in the plurality of section types in accordance with the classification of the section's corresponding section header candidate. The computer system can then validate, for each section, the section's section type via an analysis of the body of the section. |
| US11424007B2 |
Selection and monitoring methods for xenotransplantation
A method for predictive engineering of a sample derived from a genetically optimized non-human donor suitable for xenotransplantation into a human having improved quality or performance is provided. The method includes constructing a training data set from a series of libraries, wherein at least one library in the series of libraries comprises genomic, proteomic, and research data specific to non-humans. The method includes developing a predictive machine learning model based on the constructed training data set. The method includes utilizing the predictive machine learning model to obtain a predicted quality or performance of a plurality of sequences for a candidate sample from the non-human donor specific to a human patient or patient population. The method includes selecting a subset of sequences for evaluation from the plurality of sequences based on the predicted quality or performance. The method includes designing candidate samples derived from the non-human donor using the selected subset of sequences. The method includes measuring a respective in silico performance of each designed candidate sample. The method includes selecting a designed candidate sample for manufacture based on the respective in silico performance of each designed candidate sample. |
| US11424005B2 |
Apparatuses and methods for adjusting victim data
Addresses of accessed word lines are stored. Data related to victim word lines associated with the accessed word line are also stored. The victim word lines may have data stored in relation to multiple accessed word lines. The data related to the victim word lines is adjusted when the victim word line is refreshed during a targeted refresh operation or an auto-refresh operation. The data related to the victim word lines is adjusted when the victim word line is accessed during a memory access operation. |
| US11424001B2 |
Apparatuses, systems, and methods for error correction
Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree. |
| US11423999B2 |
Memory and its addressing method including redundant decoding and normal decoding
A memory device and its addressing method are disclosed. The memory device includes: an input module for receiving an input signal including an access address, a command, and a decoding selection instruction; a memory array including memory blocks, each having memory units arranged in an array; and a control module including memory block local control units, which respectively connected to one of the memory blocks in one-to-one correspondence. The memory block local control unit includes: at least one decoding unit, which performs redundant decoding or normal decoding to the input signal. The input of the decoding unit is coupled to the input module and the output is coupled to one of the memory units. The device further includes a selection module; the input of the selection module is coupled to the input module, and the output is coupled to the decoding unit. The addressing efficiency of the memory device is improved. |
| US11423994B2 |
Timing controller for controlling memory device, operating method thereof, and electronic device including the timing controller
An electronic device includes a memory device and a timing controller configured to output control signals, which are generated using a first clock signal, to the memory device, generate first captured data by capturing data, which is output from the memory device, using the first clock signal in response to the control signals, and generate control signals using a second clock signal and output the control signals to the memory device when the first captured data is not valid data. |
| US11423991B2 |
Method and apparatus for data erase in memory devices
Aspects of the disclosure provide a method for data erase in a memory device. The method includes providing first erase carriers from a body portion for the memory cell string, during an erase operation in a memory cell string. The first erase carriers flow in a first direction from a source side of the memory cell string to a drain side of the memory cell string. Further, the method includes providing second erase carriers from a junction at the drain side of the memory cell string. The second erase carriers flow in a second direction from the drain side of the memory cell string to the source side of the memory cell string. Then, the method includes injecting the first erase carriers and the second erase carriers to charge storage portions of the memory cells in the memory cell string. |
| US11423987B2 |
Memory device and programming method thereof
A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed. |
| US11423986B2 |
Semiconductor memory device and method of operating the semiconductor memory device
Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array comprising a plurality of memory cells to be programmed to a plurality of programmed states; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a current sensing circuit configured to perform an individual state current sensing operation and an overall state current sensing operation on selected memory cells among the memory cells and determine a result of the program operation on each for the plurality of programmed states; and control logic configured to control the peripheral circuit and the current sensing circuit such that an operation period of the overall state current sensing operation at least partially overlaps with an operation period of a bit line set-up operation of the program operation. |
| US11423980B2 |
Semiconductor storage device
A semiconductor storage device includes a first plane storing user data and system information, a second plane storing the user data and the system information, a first latch circuit storing even-numbered bit data of the system information read from the first plane, a second latch circuit storing odd-numbered bit data of the system information read from the second plane, and a sequencer. The sequencer executes in parallel a first process of reading out the even-numbered bit data of the system information from the first plane and storing the read data in the first latch circuit and a second process of reading out the odd-numbered bit data of the system information from the second plane and storing the read data in the second latch circuit. |
| US11423977B2 |
Static random access memory with write assist circuit
The disclosed write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage. |
| US11423973B2 |
Contemporaneous sense amplifier timings for operations at internal and edge memory array mats
A memory hank has banks of sense amplifiers positioned in edge memory array mats that are coupled to digit lines with different lengths than banks of sense amplifiers coupled between inner memory array mats. During a main sense phase of a sense operation, a first sense amplifier bank positioned between an edge memory array mat and an inner memory array mat is activated at a first time prior to activation of a second sense amplifier bank positioned in the edge memory array mat at a second time. |
| US11423968B2 |
Detecting location within a network
Systems and methods for detecting the presence of a body in a network without fiducial elements, using signal absorption, and signal forward and reflected backscatter of radio frequency (RF) waves caused by the presence of a biological mass in a communications network. |
| US11423963B2 |
Integrated circuit and memory
An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator. |
| US11423953B2 |
Command triggered power gating for a memory device
Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The error correction circuitry may be on during an access portion of an access sequence but may otherwise be off. |
| US11423950B2 |
Solid state drive device and method for fabricating solid state drive device
A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire. |
| US11423949B2 |
Data storage library with media acclimation device and methods of acclimating data storage media
A system, method and apparatus to acclimate a data storage component from a first environmental setting to a second environmental setting is disclosed. In one embodiment a system having a data storage library with a plurality of data storage cartridges and at least one media acclimation device having one or more storage locations which are sized to accept one or more data storage cartridges therein is disclosed. The at least one media acclimation device is configured to gradually acclimate the one or more storage locations from an external environmental condition to an internal environmental condition. In another embodiment, a method of acclimating a data storage library component is disclosed. The system, method and apparatus may optionally further include at least one environmental conditioning unit for conditioning the internal environment within the library. |
| US11423948B2 |
Storage chassis and electronic apparatus comprising the same
The present disclosure provides a storage chassis and an electronic device including the storage chassis. The storage chassis has a first receiving space at an upper portion of a rear end, the first receiving space is configured to be shared by a plurality of functional modules, and each functional module includes cable management supports, CPU computation control modules or storage hard disks. In the present disclosure, more modules can be arranged in a limited chassis space flexibly and reasonably, thereby improving the utilization of the chassis space and implementing configuration of various functions. |
| US11423943B2 |
Method and apparatus for generating a video based on a process
A method and apparatus for generating a video using a process diagram and using a process documentation guide storing screenshots and user inputs associates each node of a process diagram with a respective screenshot stored in the process documentation guide. A video is generated displaying each respective screenshot associated with each node of the process diagram in a sequence identified by the process diagram. The process diagram is generated by a user or by the process video server based on information in the process documentation guide. |
| US11423941B2 |
Write-a-movie: unifying writing and shooting
A method and device for implementing Write-A-Movie technology. The method includes: obtaining a screenplay of a movie; generating, according to the screenplay, an action list by performing natural language processing (NLP) on the screenplay, the action list comprising a plurality of actions with attributes, the attributes of each action including a subject, a predicate, and a location of the action; rendering, according to the action list, three-dimensional (3D) data in 3D scenes of the movie, the 3D data reflecting, for each action, the subject performing the action at the location in a corresponding 3D scene; determining camera sequence of cameras for shooting two-dimensional (2D) frames in the 3D scenes by performing an auto-cinematography optimization process; and generating a 2D video of the movie by combining the 2D frames shot by the cameras based on the determined camera sequence. |
| US11423938B2 |
Detecting errors in sensor data
A method includes receiving a first signal from a first sensor, the first signal including data representing an environment. The method also includes receiving a second signal from a second sensor, the second signal including data representing the environment. The method further includes determining a group of objects based at least in part on the received data, and identifying an error associated with data included in the first signal and/or the second signal. |
| US11423937B2 |
Aluminum alloy substrate for magnetic disk, method for producing the same, and magnetic disk using aluminum alloy substrate for magnetic disk
There are provided: an aluminum alloy substrate for a magnetic disk, the aluminum alloy substrate including an aluminum alloy including 0.4 to 3.0 mass % (hereinafter, “%”) of Fe, less than 0.10% of Si, less than 0.10% of Mg, and the balance of Al and unavoidable impurities, in which an Al—Fe-based intermetallic compound having a longest diameter of 2 μm or more and less than 3 μm is dispersed at a distribution density of 1000 particles/mm2 or more, and a Mg—Si-based intermetallic compound having a longest diameter of 1 μm or more is dispersed at a distribution density of 1 particle/mm2 or less; a method for producing the same; and a magnetic disk in which an electroless Ni—P plating treatment layer and a magnetic layer thereon are disposed on a surface of the aluminum alloy substrate for a magnetic disk. |
| US11423933B2 |
Magnetic recording medium having characterized magnetic layer and magnetic recording and reproducing device
The magnetic recording medium includes a non-magnetic support; and a magnetic layer including a ferromagnetic powder, in which one or more kinds of component selected from the group consisting of a fatty acid and a fatty acid amide are included in a portion of the magnetic layer side on the non-magnetic support, and a C—H derived C concentration calculated from a C—H peak surface area ratio in C1s spectra obtained by X-ray photoelectron spectroscopic analysis performed on a surface of the magnetic layer at a photoelectron take-off angle of 10 degrees, after pressing the magnetic layer at a pressure of 70 atm is 45 atom % or more. |
| US11423931B2 |
Data storage device interleave driving secondary actuators
A data storage device is disclosed comprising a plurality of disks each comprising a top disk surface and a bottom disk surface, and a plurality of actuator arms each comprising a first fine actuator configured to actuate a top head over one of the top disk surfaces and a second fine actuator configured to actuate a bottom head over one of the bottom disk surfaces. A first fine driver controls the fine actuators of an even interleave of the actuator arms, and a second fine driver controls the fine actuators of an odd interleave of the actuator arms. |
| US11423929B1 |
Reader with wide synthetic antiferromagnetic structure optimized for high stability and low noise
A reader includes a bearing surface and a free layer having a front surface that forms a portion of the bearing surface. The reader also includes a synthetic antiferromagnetic (SAF) structure below the free layer, the SAF structure has a narrow portion with a front surface that forms a portion of the bearing surface and a wide portion behind the narrow portion. The reader further includes an antiferromagnetic (AFM) layer in contact with the wide portion of the SAF structure. The SAF structure is configured to prevent switching from one magnetic state to another magnetic state in the wide portion under thermal fluctuations. |
| US11423927B2 |
Assembly that enables reduction in disk to disk spacing
A data storage system includes a data storage foil mounted within the data storage system, the data storage foil has at least one data storage surface. The data storage system also includes a head configured to interact with the at least one data storage surface to carry out at least one of data read or data write operations. |
| US11423924B2 |
Signal analysis device for modeling spatial characteristics of source signals, signal analysis method, and recording medium
A signal analysis device includes a memory and processing circuitry coupled to the memory and configured to obtain, for a spatial covariance matrix Rj (j is an integral number equal to or larger than 1 and equal to or smaller than J) for modeling spatial characteristics of J (J is an integral number equal to or larger than 2) source signals that are present in a mixed manner, a simultaneous decorrelation matrix P as a matrix in which all PHRjP are diagonal matrices, or/and Hermitian transposition PH thereof, as a parameter for decorrelating components corresponding to the J source signals for observation signal vectors based on observation signals acquired at I (I is an integral number equal to or larger than 2) different positions. |
| US11423920B2 |
Methods and systems for suppressing vocal tracks
The methods and systems described herein aid users by modifying the presentation of content to users. For example, the methods and systems suppress the dialogue track of a movie when the user engages with the content by reciting a line of the movie as it is presented to the user. Words spoken by the user are detected and compared with the words in the movie. When the user is not engaging with the movie by reciting the lines or humming tunes while watching the movie, the audio track of the movie is not modified. Content can be modified in response to engagement by a single user or by multiple users (e.g., each reciting lines of a different character in a movie). Accordingly, the methods and systems described herein provide increased interest in and engagement with content. |
| US11423917B2 |
Audio decoder and decoding method
A method for representing a second presentation of audio channels or objects as a data stream, the method comprising the steps of: (a) providing a set of base signals, the base signals representing a first presentation of the audio channels or objects; (b) providing a set of transformation parameters, the transformation parameters intended to transform the first presentation into the second presentation; the transformation parameters further being specified for at least two frequency bands and including a set of multi-tap convolution matrix parameters for at least one of the frequency bands. |