| Document | Document Title |
|---|---|
| US11336522B2 |
Information handling system physical component inventory to aid operational management through near field communication device interaction
NFC communications from a mobile phone to an information handling system initiates an inventory by a management controller of the information handling system. The inventory is provided to the mobile telephone with a second NFC communication so that an end user can see a visual depiction of the interior of the information handling system before opening the chassis of the system. |
| US11336520B2 |
Network design device, network design method, and network design processing program
With a network design apparatus, a network design method, and a network design processing program, a network configuration is designed for a network in which a transfer apparatus is disposed at each of a plurality of communication hubs and the communication hubs are connected via a link by a link portion apparatus in the transfer apparatus. In design of a network configuration, an optimal combination candidate of a link portion apparatus for each link for minimizing a total cost value in an overall network is calculated on the basis of a combination candidate set of link portion apparatuses. The combination candidate set of the link portion apparatuses is configured using only combination candidates with a cost-effectiveness indicating a ratio of a total capacity to a total cost value of the link portion apparatus higher than a predetermined reference. |
| US11336519B1 |
Evaluating placement configurations for distributed resource placement
A distributed system may implement evaluating placement configurations for distributed resource placement. Placement requests for a partition of a distributed resource may be received. An evaluation of prospective placement configurations of the distributed resource is performed that locates the partition at different resource hosts. In some embodiments, placement configurations may be analyzed with respect to infrastructure zone locality. Multiple infrastructure zone localities may be analyzed and combined to evaluate prospective placement configurations. Prospective placement configurations may be analyzed with respect to other criteria, such as resource host utilization data. Based, at least in part, on the evaluation of the prospective placement, a resource host is identified for placing the partition. |
| US11336518B2 |
Staging configuration changes with deployment freeze options
Techniques for a configuration change service to transition a network controller into a frozen state, causing network users submitting configuration changes associated with the network to refrain from deploying the configuration changes for a period of time are disclosed. A first user configured as a stager role may submit data representing a proposed change to the configuration change service, where the proposed change may be stored in association with a list of proposed changes. A second user configured as an approver role may submit data representing an approval or disapproval of the proposed changes to the configuration change service, where a modified list of proposed changes may be generated. A third user configured as an administrator role may submit data configured to transition the controller to an unfrozen state and/or deploy the changes included in the list of proposed changes to the network controller, subsequent to the period of time. |
| US11336515B1 |
Simultaneous interoperability with policy-aware and policy-unaware data center sites
Presented herein are systems and methods to enable simultaneous interoperability with policy-aware and policy-unaware data center sites. A multi-site orchestrator (MSO) device can be configured to obtain configuration information for each of a plurality of different data center sites. The data center sites may include one or more on-premises sites and one or more off-premises sites, each of which may include one or more policy-aware sites and/or one or more policy-unaware sites. The MSO can selectively use namespace translations to create a unified fabric across the different data center sites, enabling one or more hosts and/or applications at a first of the data center sites to communicate with one or more hosts and/or applications at a second of the data center sites, regardless of the sites' respective configurations. |
| US11336506B1 |
Automatic diagnostics alerts for streaming content encoded by multiple entities
Automatic diagnostics alerts for streaming multiple types of content is disclosed. At a first time, a set of metrics for a plurality of groups of streaming sessions is computed. A streaming session in a group is associated with streaming of a piece of content encoded by an entity. The streaming of the piece of content encoded by the entity is associated with streaming of another piece of content. An anomaly is identified at least in part by performing anomaly detection using the set of metrics. A cause of the identified anomaly is diagnosed. An alert is generated based at least in part on the diagnosis. |
| US11336502B2 |
Deriving network device and host connection
This disclosure describes techniques that determine device connectivity in the absence of a network layer 2 discovery protocol such as Link Layer Discovery Protocol (LLDP). In one example, this disclosure describes a method that includes retrieving, from a bridge data store of a bridge device on a network having one or more host devices, a plurality of first interface indexes, wherein each first interface index corresponds to a network interface of network interfaces of the bridge device; retrieving, from the bridge data store, remote network addresses corresponding to the network interfaces of the bridge device, each remote network address of the remote network addresses corresponding to a second interface index; selecting a remote network address having a second interface index that matches the first interface index; determining a host device having the selected remote network address; and outputting an indication that the bridge device is coupled to the host device. |
| US11336499B2 |
Automatic OFDM profile selection
Assigning an appropriate modulation profile for an orthogonal frequency-division multiplexing (OFDM) channel. The current modulation profile assigned to a specific OFDM modem for communicating over a specific OFDM channel is examined to determine whether to consider reassigning the specific OFDM modem to a different modulation profile. Only upon determining consideration should be given, an assessment is made as to which modulation profile, of a set of candidate modulation profiles available to that OFDM modem for communicating over the specific OFDM channel, should be assigned to the specific OFDM modem using linear domain averaging over the OFDM subcarriers of the ratios between a Mean Error Rate (MER) threshold per subcarrier for the specific OFDM modem and the MER reported by the specific OFDM modem per subcarrier. A new modulation profile is assigned to the specific modem based on the assessment. |
| US11336493B1 |
Dynamic transmission impairment correction for satellite systems
A system includes a processor and a memory. The memory stores instructions executable by the processor to identify an equalization response for equalizing an output signal of a modulator of a satellite gateway, generate a compensation response based on the equalization response and a sample rate of a pre-distorter of the modulator, and send the equalization response to the pre-distorter. |
| US11336489B1 |
Method of configuring decision feedback equalizer and related decision feedback equalizer thereof
A decision feedback equalizer includes: a feedforward equalizer, a feedback equalizer, a slicer and a decision adjustment unit. The feedforward equalizer is arranged to generate a feedforward output signal based on an input signal. The feedback equalizer is coupled to the feedforward equalizer and arranged to generate a feedback output signal according to a decision output signal. The slicer is coupled to the feedforward equalizer and the feedback equalizer, and is controllable by a decision adjustment parameter, wherein the slicer is arranged to perform a slicer decision on a sum of the feedforward output signal and the feedback output signal, thereby generating the decision output signal. The decision adjustment unit is coupled to the slicer, and is arranged to adjust the decision adjustment parameter according to a sleep state of a communication device in which the decision feedback equalizer is disposed. |
| US11336488B2 |
Method and apparatus for uplink transmission and reception in a wireless communication system
Disclosed are a method for transmitting and receiving an uplink in a wireless communication system and an apparatus therefore. Specifically, a method for uplink transmission by a User Equipment (UE) in a wireless communication system may include: receiving, from a base station, Sounding Reference Signal (SRS) configuration information, wherein the SRS configuration information includes a parameter set for power control of SRS for each SRS resource set and the SRS resource set includes one or more SRS resources; determining a transmission power of the SRS, based on the parameter set for power control of the SRS; and transmitting the SRS to the base station. |
| US11336487B1 |
Optimized high-efficiency (HE) sounding for multi-link device networks
A system and method for optimizing a channel sounding procedure of a multi-link device (MLD) is disclosed. The improved channel sounding procedure disclosed herein involves an MLD requesting channel sounding information from a group of receivers on a first channel representing a first physical frequency, but receiving channel sounding information from a subgroup of the receivers on one or more other channels representing different physical frequencies. In this manner, the channel sounding procedure on a specific link of an MLD is optimized by offloading some of the sounding process to a different radio link that is also operational for the MLD as part of the same association context. |
| US11336486B2 |
Selection of managed forwarding element for bridge spanning multiple datacenters
Some embodiments provide a method for a set of central controllers that manages forwarding elements operating in a plurality of datacenters. The method receives a configuration for a bridge between (i) a logical L2 network that spans at least two datacenters and (ii) a physical L2 network. The configuration specifies a particular one of the datacenters for implementation of the bridge. The method identifies multiple managed forwarding elements that implement the logical L2 network and are operating in the particular datacenter. The method selects one of the identified managed forwarding elements to implement the bridge. The method distributes bridge configuration data to the selected managed forwarding element. |
| US11336483B2 |
Directional wireless drop systems for broadband networks and related methods
Directional wireless drop systems are provided. These systems include a tap unit that is connected to a communications line of the broadband network; a cable modem unit connected to the tap unit; a plurality of wireless routers connected to the cable modem unit; and a directional antenna unit that is connected to at least a first of the wireless routers. Each wireless router is associated with a respective one of a plurality of subscriber premises that are served by the directional wireless drop system and is configured to communicate with at least one device that is located at the respective one of plurality of subscriber premises. |
| US11336481B2 |
Wireless communication system, communication apparatus, setting information providing method, setting information obtaining method, and computer program
A wireless communication system includes an access point, a master communication apparatus, and a slave communication apparatus, and the master communication apparatus and the slave communication apparatus perform wireless communication through the access point. The master communication apparatus stores setting information necessary for accessing the access point; performs wireless communication through the access point using the stored setting information; and performs near field communication with the slave communication apparatus to transmit the stored setting information to the slave communication apparatus in response to a setting information request received from the slave communication apparatus via near field communication. The slave communication apparatus performs near field communication with the master communication apparatus to transmit the setting information request to the master communication apparatus; receives the setting information from the master communication apparatus via near field communication; stores the setting information; and performs wireless communication through the access point using the setting information. |
| US11336479B2 |
Information processing apparatus, information processing method, and non-transitory computer readable medium
An information processing apparatus includes an acquisition unit and a transmitter. The acquisition unit acquires input information including information on a user and information that the user conveys to an interaction partner. The transmitter transmits the input information to a device having superiority over other candidate devices as a device for processing response information, to the input information, from the interaction partner. |
| US11336477B2 |
Load control system having audio output devices
A control system may comprise a plurality of audio output devices (e.g., controllable speakers), and a remote control device having at least one button for selecting a preset, where the preset defines different commands for at least two of the audio output devices. The at least two audio output devices may be configured to be controlled according to the different commands (e.g., starting, pausing, or stopping playback, adjusting volume, etc.) in response to an actuation of the button of the remote control device. The control system may also comprise a load control device, such as a dimmer configured to control an intensity of a lighting load to a predetermined intensity in response to the actuation of the button of the remote control device to select the preset. The audio output device may be configured to play a feedback signal indicating an operational characteristic of the dimmer. |
| US11336473B2 |
Network and method for delivering content while minimizing congestion costs by jointly optimizing forwarding and caching strategies
Embodiments include a unified framework for minimizing congestion-dependent network cost by jointly optimizing forwarding and caching strategies that account for link congestion between neighboring nodes. As caching variables are integer-constrained, the resulting optimization problem is a non-deterministic polynomial time (NP)-hard problem. Embodiments relax the optimization problem, where caching variables are real-valued. Embodiments include optimality conditions for the relaxed problem. Embodiments include an adaptive and distributed joint forwarding and caching method, based on a conditional gradient method. Embodiments elegantly yield feasible routing variables and integer caching variables at each iteration, and can be implemented in a distributed manner with low complexity and overhead. Over a wide range of network topologies, simulation results show that embodiments have significantly better delay performance in the low to moderate request rate regions. Furthermore, embodiments complement each other in delivering superior delay performance across the range of request arrival rates, compared to existing methods. |
| US11336472B2 |
Data packet processing method and apparatus
A data packet processing method and apparatus, where a storage apparatus disposed on a network side stores a correspondence between an identifier and data flow characteristic information. When configuring a policy for a data packet including a first identifier, a network-side device requests the storage apparatus for data flow characteristic information corresponding to the first identifier. A policy and charging enforcement function (PCEF) receives a data packet that is sent by a user equipment (UE), matches the data packet against the data flow characteristic information, and when the data packet matches the data flow characteristic information, executes a policy on the data packet according to policy information corresponding to the first identifier. |
| US11336470B2 |
Method and apparatus for transmitting and receiving wake-up signal in vehicle network
An operation method of a first end node of an Ethernet-based vehicle network is provided. The operation method includes detecting a local event and transitioning an operation state of a physical layer (PHY) of the first end node from a sleep state to a wake-up state. A pseudo PHY identifier (ID) is configured as a PHY ID of the first end node in response to the first end node operating in the wake-up state. A first beacon including the pseudo PHY ID is then transmitted and the first beacon indicates that the first end node operates in the wake-up state. |
| US11336468B2 |
Synthetic physically unclonable function
A circuit for a Synthetic Physically Unclonable Function, acronym SPUF, in a computer device, wherein the circuit is configured to receive data from a plurality of hardware sensors and/or actuators accessible in the computer device; to determine deviations in the data; to determine a multivariate distribution of the deviations and to determine an identifier from the multivariate distribution. In described developments, deviations comprise random errors, statistical moments in data originating from sensors and/or actuators amongst accessible ones in the computer device can be selected, and entropy can be maximized. Computer program product embodiments are described. |
| US11336467B2 |
Bot permissions
Permission control and management for messaging application bots is described. A method can include providing a messaging application, on a first computing device associated with a first user, to enable communication between the first user and another user, and detecting, at the messaging application, a user request. The method can also include programmatically determining that an action in response to the user request requires access to data associated with the first user, and causing a permission interface to be rendered in the messaging application, the permission interface enabling the first user to approve or prohibit access to the data associated with the first user. The method can include accessing the data associated with the first user and performing the action in response to the user request, upon receiving user input from the first user indicating approval of the access to the data associated with the first user. |
| US11336464B2 |
Identity authentication method and system, as well as computing device and storage medium
The method of identity authentication at the user is provided to prove to the certificate authority that a key is owned by a user. The method can comprise selecting a certain number of keys from a set of keys of the user, obtaining a hash value of a correspondence between each key in the certain number of keys and a user identifier of the user respectively, and transmitting the obtained hash values to the certificate authority, and after receiving from the certificate authority a notification regarding a first subset of hash values, sending keys corresponding to the first subset of hash values as a first subset of keys to the certificate authority. The first subset of hash values can be selected by the certificate authority from the obtained hash values. Zero know ledge proof can be achieved with this technical solution. |
| US11336462B1 |
Systems and methods for post-quantum cryptography optimization
Systems, apparatuses, methods, and computer program products are disclosed for quantum computing (QC) detection. An example method includes generating QC detection data. The example method further includes generating a pair of asymmetric cryptographic keys comprising a public cryptographic key and a private cryptographic key, generating encrypted QC detection data based on the pair of asymmetric cryptographic keys, and destroying the private cryptographic key. The example method further includes monitoring a set of data environments for electronic information related to the encrypted QC detection data. Subsequently, the example method may include generating a QC detection alert control signal in response to detection of the electronic information related to the encrypted QC detection data. |
| US11336461B2 |
Method for controlling by a server the use of at least one data element of a data owner
The invention relates to a method for controlling by a server called secure server the use of a first set of at least one data element of a data owner and provided by a communication device, the method comprising the steps of: receiving at least one digital signature representative of a process authorized by the data owner and adapted to carry out a series of at least one instructions using the first set of at least one data element; receiving from a process entity the series of at least one instruction, and a ciphered version of the first set of at least one data element which is communicated to the process entity by the communication device; verifying that the series of at least one instruction correspond to a process authorized by the data owner of the communication device by comparing the at least one digital signature received by the secure server with a digital signature obtained by the secure server using as an input the series of at least one instruction received by the secure server; and if the series of at least one instruction correspond to an authorized process: deciphering the first set of at least one data element; generating a result data by executing the series of at least one instruction using the first set of at least one data element as an input; transmitting the result data to the process entity. |
| US11336455B2 |
Consensus protocol for blockchain DAG structure
An example operation may include one or more of receiving a chain of blocks from a blockchain comprising a directed acyclic graph (DAG) format in which blocks are independently hash-linked to multiple blocks, identifying temporal relationships between blocks in the chain of blocks based on a structure of the chain of blocks in the DAG format, determining a sequential linear order of the chain of blocks in the DAG format based on the identified temporal relationships, and storing the sequential linear order of the chain of blocks. |
| US11336453B2 |
Transactions between services in a multi-tenant architecture
A method for facilitating transactions between tenants in a multi-tenant architecture system is discussed. The method includes receiving a request, at a multi-tenant platform, from a first service of a first tenant of the multi-tenant platform to access a second service of a second tenant of the multi-tenant platform to perform a transaction, in which the request includes a first access token usable to authenticate the transaction with the first tenant. The method includes generating, by the multi-tenant platform using the first access token, a universal access token. The method includes generating, by the multi-tenant platform using the universal access token, a second access token useable to authenticate the transaction with the second tenant. The method includes using, by the multi-tenant platform, the second access token to communicate with the second service to perform the transaction. |
| US11336452B2 |
Methods for registering data from an individual's identity document and for authenticating an identity document
The invention proposes a method for registering data from an individual's identity document (1), the method being characterized in that it comprises implementing by data processing means (21) of a server (2) the following steps:(A) Receipt of a photograph of said individual visible on said identity document (1), an optical reading data element of the identity document (1), and at least one personal data element of said individual;(B) Extraction by analysis of said photograph from reference information representative of the appearance of said photograph;(C) Generation of a random string, calculation of an encoded data element by applying an encoding procedure to said reference information representative of the appearance of said photograph and said random string;(D) Storage on the server (2) data storage means (22) of: Said encoded data element; A cryptographic imprint of a first concatenation of the optical reading data element of the identity document (1) and the random string; An encryption with a cryptographic imprint of a second concatenation of the optical reading data element of the identity document (1) and the random string, different from the first concatenation, of at least one personal data element of said individual. The invention also relates to an authentication method and a server for this purpose. |
| US11336451B2 |
Cross-blockchain resource transmission
Examples of a method and apparatus for cross-chain resource transmission are described. The cross-chain resource transmission includes sending from a first account of a first blockchain to another blockchain. One example of the method is executed by the first blockchain and includes: initiating, by the first account, a first transaction used for cross-chain resource transmission, to decrement a first resource balance of the first account by a first quantity and save first data obtained through a consensus into the first blockchain based on execution of the first transaction, where the first data includes an authenticable message; and sending the first data and first location information to the relay end, which is used to send the authenticable message to the second blockchain, where a second resource balance of the second account is incremented by a second quantity. |
| US11336445B2 |
Method for updating a one-time secret key
This invention relates to a method for updating a one-time secret key Kn maintained in a subscription module implemented in a communication apparatus, a wireless communication network maintaining an identical version of said one-time secret key Kn and configured to determine a result XRES expected from the communication apparatus when an authentication function is applied by the subscription module using a random challenge and said one-time secret key Kn as an input, the method comprising the following steps: receiving from the communication network an authentication request message containing at least a random challenge RANDn; determining by the subscription module a result RES by applying the authentication function using the random number RANDn and the one-time secret key Kn as inputs; transmitting said result RES to the communication network for it to be compared with the expected result XRES determined by the communication network using the random number RANDn and the corresponding version of the one-time secret key Kn, the subscriber being authenticated if said first and second results are matching; updating the one-time secret key Kn by replacing its current version with a new version obtained by applying a first key derivation function using the random challenge RANDn as an input, the updated version of the one-time secret key Kn being used by the subscription module for processing a subsequent authentication request, the same update being carried out by a server accessible or part of the wireless communication network in order to maintain an identical version of the one-time secret key Kn. |
| US11336441B2 |
Communication terminal, server apparatus, and program
A communication terminal which is capable of reducing load of a server apparatus by reutilizing a message key to be used for encrypting a message is provided. The communication terminal includes a session key storage part which stores a session key which is shared with another communication terminal and which is not shared with the server apparatus, a message key generating part which generates a message key, a message key storage part which stores the message key to be reutilized in association with a message key identifier, a message encrypting part which generates a message encrypted text based on a common key cryptosystem using the message and the message key, a message key encrypting part which generates a message key encrypted text based on a common key cryptosystem which can perform re-encryption using the session key and the message key, and an encrypted text transmitting part which transmits a group identifier which is an identifier of a group to which an own terminal belongs, the message key encrypted text or the message key identifier, and the message encrypted text to the server apparatus. |
| US11336439B2 |
Information processing device, information processing method, and recording medium
An information processing device which includes: a secure storage accessible by only trusted software, in which a first encryption key keeping unit keeping a first encryption key is configured inside a access limit area; a second encryption key keeping unit keeping as a second encryption key; a setup processing activation unit acquiring the second encryption key from the second encryption key keeping unit in response to activation of a local device, and outputting the acquired second encryption key; and a software execution unit being executed as the trusted software, acquiring the second encryption key from the setup processing activation unit, acquiring the first encryption key from the first encryption key keeping unit together with acquisition of the second encryption key, constructing a common encryption key by using the first encryption key and second encryption key, and setting up an encrypted file system by using the constructed common encryption key. |
| US11336436B2 |
Key distribution system and method, key generation apparatus, representative user terminal, server apparatus, user terminal, and program
A key distribution system includes a representative user terminal 2p, a server apparatus 3, and an (n+1)-th user terminal 2n+1. The representative user terminal 2p uses a public key for the (n+1)-th user terminal 2n+1 and information for identifying the (n+1)-th user terminal 2n+1 to encrypt key information with a predetermined encryption function in Certificate-less Encryption to obtain ciphertext. The server apparatus 3 sends the ciphertext to the (n+1)-th user terminal 2n+1 when the (n+1)-th user terminal 2n+1 is added. The (n+1)-th user terminal 2n+1 uses a complete secret key for the (n+1)-th user terminal 2n+1 and the information for identifying the (n+1)-th user terminal 2n+1 to decrypt the ciphertext with a predetermined decryption function to obtain the key information. |
| US11336435B2 |
Method, apparatus, and system for processing two-dimensional barcodes
This specification describes techniques for processing service requests. An electronic credential request including a user identifier is received from a client. An electronic credential that corresponds to the user identifier and a user public key that corresponds to the user are retrieved. A hash operation is performed on the user public key and the electronic credential by using a hash algorithm to obtain a hash value that is signed within a predetermined time period. Server signature information is generated using the hashed credential, and transmitted with the electronic credential to the client. The server signature information is cryptographically verifiable by the client and enables the client to generate a two-dimensional barcode based on the electronic credential. |
| US11336431B2 |
Verification system and method for cooperating with blockchain and off-chain devices
A verification system and method for cooperating with a blockchain and off-chain devices is provided. The system includes a security protocol device, a blockchain device, and a database device. The security protocol device receives and integrates the record data into a binary tree according to a hash function. Hash values of the record data are stored in the leaf nodes. The blockchain device is at the blockchain and communicates with the security protocol device. The security protocol device transmits the root hash to the blockchain device. The database device communicates with the security protocol device in an off-chain manner. The security protocol device stores the binary tree to the database device. The security protocol device compares the root hash from the blockchain device with the root hash of the binary tree stored in the database device to verify the correctness of the binary tree stored in the database device. |
| US11336430B2 |
Blockchain-incorporating distributed authentication system
Disclosed herein are system, method, and device embodiments for an authentication workflow incorporating blockchain technology. An embodiment operates by requesting, from a distributed authentication service, transmission of a time-based one-time password to a communication endpoint associated with an end-user, receiving a time-based one-time password submission from a user device associated with the end-user, retrieving a plurality of distributed ledger entries (e.g., a plurality of blocks of a blockchain), and validating the time-based one-time password submission based on the plurality of distributed ledger entries as a part of a two factor authentication workflow. |
| US11336428B1 |
Blinded passwords for a distributed storage system
A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by performing a key derivation function on a password and issuing a set of blinded passwords to a set of storage units. The method continues by receiving at least a decode threshold number of confidential information responses, regenerating a set of keys using the associated passkeys of the confidential information, decrypting a set of encrypted slices of the confidential information using the set of keys to reproduce a set of encoded data slices, and dispersed storage error decoding a decode threshold number of the set of reproduced encoded data slices to produce recovered data. |
| US11336426B2 |
Authenticated confirmation and activation message
A data transmitter for transmitting data to a data receiver is provided, wherein individual communication information is known to the data transmitter and the data receiver, the data transmitter being configured to generate an individual synchronization sequence while using the individual communication information. |
| US11336423B2 |
Timing synchronization for downlink (DL) transmissions in coordinated multipoint (CoMP) systems
Technology for a user equipment (UE) operable to adjust a receiver timing is disclosed. The UE can decode a plurality of channel-state information reference signals (CSI-RSs) received from a plurality of cooperating nodes, wherein the plurality of cooperating nodes are included in a coordination set of a Coordinated MultiPoint (CoMP) system. The UE can generate a plurality of received RS timings from the plurality of CSI-RSs, wherein the received RS timings represent timings from the plurality of cooperating nodes. The UE can determine a composite received RS timing from the plurality of received RS timings. The UE can adjust the receiver timing based on the composite received RS timing. |
| US11336422B2 |
Methods and devices for data transmission with reference signals
Embodiments of the present disclosure relate to methods and devices for data transmission. In example embodiments, a method implemented in a network device is provided. According to the method, a target RS port group is determined from a plurality of RS ports for transmitting a RS. The RS ports are associated with at least one network device. Then, a configuration of the target RS port group is transmitted to the terminal device. |
| US11336421B2 |
Method and apparatus for transmitting control information in wireless communication system
The present invention pertains to a wireless communication system, and more particularly, to a method of receiving a downlink (DL) control channel in a wireless communication system and an apparatus therefor, and the method comprises the following steps: receiving a radio resource control (RRC) message including resource block (RB) allocation information; receiving a subframe having a plurality of physical RBs; and monitoring a plurality of downlink control channel candidates in a physical RB set corresponding to the RB allocation information from the plurality of physical RBs to detect a downlink control channel allocated to a communication device, wherein the plurality of downlink control channel candidates do not continuously exist in a virtual RB set corresponding to the physical RB set. |
| US11336419B2 |
Reference signal measurement method, reference signal sending method, and related device
A reference signal measurement method, a reference signal sending method, a user equipment, and a base station are provided. According to the embodiments of the present application, a user equipment determines reference signal resource configuration, which includes reference signal port configuration, reference signal subframe configuration, and reference signal configuration, and a quantity of ports configured in the reference signal port configuration is N; receives a reference signal according to the reference signal resource configuration; and performs measurement based on the received reference signal to obtain channel state information and/or signal quality information. In the embodiments of the present invention, a quantity of ports configured in the reference signal port configuration is N; and a quantity of supported ports may vary with different values of N. |
| US11336418B2 |
Method and device for avoiding uplink collisions with overlapping TTI
The present invention discloses a data transmission method and apparatus. The method comprises: determining on a terminal side whether there is an overlap between a transmission time of an uplink channel which transmits using a first transmission time interval length and a transmission time of an uplink channel which transmits using a second transmission time interval length; when there is an overlap, then selecting a part of the uplink channel for transmission according to a predetermined rule, and abandoning the remaining uplink channel for transmission or puncturing the transmission of the remaining uplink channel. On a network side, determining that the terminal selects one type of uplink channel for transmission according to the predetermined rule, and abandons another type of uplink channel for transmission or punctures the transmission of another type of uplink channel. With the present invention, correct transmission of the terminal can be achieved even when channels with different transmission time intervals overlap. |
| US11336414B2 |
Downlink hybrid automatic repeat request feedback for narrowband Internet of Things devices
Techniques for transmitting hybrid automatic repeat request (HARQ) feedback by narrowband Internet-of-Things (NB-IoT) devices are provided. NB-IoT user equipment (UE) can transmit HARQ feedback in response to a narrowband physical downlink shared channel (NPDSCH) received over a downlink (DL). NB-IoT UEs can transmit the responsive HARQ feedback over a narrowband physical uplink shared channel (NPUSCH) or a narrowband physical uplink control channel (NPUCCH). Options for defining the physical structures of the NPUCCH and NPUSCH and user multiplexing on the uplink (UL) are provided. Determination of an UL resource allocation by determining resources in time, frequency, and the code domain for the HARQ feedback transmissions are also provided. Higher level signaling and/or indications provided in downlink control information (DCI) can be used to determine the time, frequency, or code domain resources. |
| US11336413B2 |
Method for transmitting/receiving reference signal in wireless communication system, and device therefor
A method and a device, which: receive, from a base station through a demodulation reference signal (DMRS) symbol, a DMRS set according to a specific pattern by the base station, wherein the DMRS is transmitted in a specific antenna port and positioned on one or two time axis symbols, which are the same as at least one other DMRS transmitted in another antenna port; and decode data by using the DMRS. |
| US11336412B2 |
Synchronization signal configuration method and apparatus
Examples synchronization signal configuration methods and apparatus are described. One example method is applied to a relay network including a first node and a second node, and the first node is a parent node of the second node. The example method includes sending synchronization signal configuration information by the first node to the second node, where the synchronization signal configuration information is used to indicate M first synchronization signal time-frequency positions and N second synchronization signal time-frequency positions in a candidate synchronization signal time-frequency position set. The first synchronization signal time-frequency position is used by the second node to send a first synchronization signal, the second synchronization signal time-frequency position is used by the second node to receive or detect a second synchronization signal, the candidate synchronization signal time-frequency position set includes W synchronization signal time-frequency positions, and W≥(M+N). |
| US11336410B2 |
Zone-based signaling in new radio
Methods, systems, and devices for wireless communications are described. According to one or more aspects, a device, such as a user equipment (UE), may receive a signal including one or more channel transmission parts associated with one or more zones. The UE may identify, based on receiving the signal, at least one zone of the one or more zones that is associated with the UE. Additionally or alternatively, the UE may identify multiple zones of the one or more zones that are associated with the UE. The UE may select a channel transmission part of the one or more channel transmission parts based on receiving the signal and the identified zone associated with the UE. The UE may decode the one or more selected channel transmission parts, and may communicate based on the decoded channel transmission part or the decoded channel transmission parts. |
| US11336408B2 |
Transmission resource allocation method and apparatus, and data sending method and apparatus
This application provides a transmission resource allocation method and apparatus, and a data sending method and apparatus. The method includes: determining, by a network device, at least one basic resource element, where each of the at least one basic resource element corresponds to at least one pilot, a first basic resource element in the at least one basic resource element corresponds to at least two pilots, and the at least two pilots are different; and indicating, by the network device to a terminal device, at least one pilot corresponding to one or more of the at least one basic resource element. |
| US11336407B2 |
Reusing long-term evolution (LTE) reference signals for new radio (NR) system operations
Wireless communications systems and methods related to reusing long-term evolution (LTE) resources for new radio (NR) system operations are provided. A UE receives, from a base station, a reference signal configuration of a first network of a long-term evolution (LTE) radio access technology (RAT). The UE and the base station are associated with a second network of another RAT. The reference signal configuration indicates at least a number of antenna ports associated with a reference signal of the first network. The UE determines a location of the reference signal associated with the reference signal configuration and receives, from the base station, a data signal of the second network based at least on the location of the reference signal of the first network. |
| US11336405B2 |
Wireless communication device and corresponding apparatus, method and computer program
Embodiments of the present disclosure relate to wireless communication devices, systems comprising wireless communication devices, and to an apparatus, a method and a computer program for a wireless communication device. The apparatus comprises a transceiver module for transmitting and receiving wireless transmissions. The apparatus comprises a processing module that is configured to control the transceiver module. The processing module is configured to communicate with a further wireless communication device via the transceiver module. The communication with the further wireless communication device is based on a transmission of data frames between the wireless communication device and the further wireless communication device. Each data frame is based on a two-dimensional grid in a time-frequency plane having a time dimension resolution and a frequency dimension resolution. The processing module is configured to select a communication mode from a plurality of communication modes for the communication between the wireless communication device and the wireless communication device. The communication mode defines a combination of a frequency dimension resolution and a time dimension resolution of the two-dimensional grid in the time-frequency plane. The communication mode is selected from the plurality of communication modes based on an estimated self-interference of the plurality of communication modes. |
| US11336401B2 |
Method of retransmission for downlink transmission in wireless communication system and apparatus for the same
Disclosed herein are a method of retransmission for downlink transmission of a wireless communication system and an apparatus for the same. The method includes receiving multiple feedback signals corresponding to a transmission failure from multiple terminals corresponding to point-to-multipoint transmission, generating retransmission data in response to the multiple feedback signals, and transmitting the retransmission data to the multiple terminals. |
| US11336399B2 |
Code block reordering for retransmissions
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter device may transmit a hybrid automatic repeat request (HARQ) communication using a first code block order for code blocks of the HARQ communication; detect a trigger to retransmit the HARQ communication based at least in part on transmitting the HARQ communication; reorder the code blocks of the HARQ communication based at least in part on detecting the trigger to retransmit the HARQ communication; and retransmit the HARQ communication using a second code block order based at least in part on reordering the code blocks of the HARQ communication. Numerous other aspects are provided. |
| US11336393B2 |
Apparatus for generating broadcast signal frame for signaling time interleaving mode and method using the same
An apparatus and method for generating a broadcast signal frame for signaling a time interleaving mode are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to perform power-normalizing for reducing the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time interleaving after performing the power-normalizing; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling a time interleaving mode corresponding to the time interleaver for each of physical layer pipes (PLPs). |
| US11336389B2 |
Transmitting device which generates a physical layer packet by inserting padding and transmitting method thereof
A transmission device is disclosed. The transmitting device comprises a processor for generating a packet comprising a header and a payload, on the basis of an input packet, and generating a frame comprising the generated packet, and a transmission unit for transmitting a signal generated on the basis of the frame. The processor inserts padding into at least one packet from among a plurality of packets included in the frame, on the basis of the number of packets included in the frame, the length of each input packet included in the frame, and the lengths of the packets. Here, the boundary of an input packet may be included in a packet into which padding is inserted. |
| US11336388B2 |
System and method for setting link parameters in a WiFi link
A method for operating a link method includes estimating a plurality of throughputs, each throughput corresponding to one of a plurality of modulation and coding schemes, each one of the plurality of modulation and coding schemes corresponding to one of a plurality of combinations of spatial stream numbers and bandwidths, selecting a maximum throughput from the plurality of throughputs, and transmitting data according to a modulation and coding scheme, a spatial stream number, and a bandwidth corresponding to the maximum throughput. |
| US11336386B2 |
Submarine branching apparatus, optical submarine cable system, and optical communication method
In order to provide a submarine optical transmission system that utilizes multiple wavelength bands, the submarine branching apparatus is provided with: a first demultiplexing part for demultiplexing a wavelength-multiplex optical signal input from a first terminal station into a first wavelength-multiplex optical signal and a second wavelength-multiplex optical signal; an optical add-drop part for outputting at least a third wavelength-multiplex optical signal included in the first wavelength-multiplex optical signal to a second terminal station, and for outputting a fifth wavelength-multiplex optical signal by multiplexing at least a fourth wavelength-multiplex optical signal included in the first wavelength-multiplex optical signal with a wavelength-multiplex optical signal input from the second terminal station; and a first multiplex part for multiplex the second wavelength-multiplex optical signal with the fifth wavelength-multiplex optical signal input from the optical add-drop part and outputting the resulting signal to a third terminal station. |
| US11336384B2 |
Synchronization signal measurement method and related device
Transmitting, by the network device, the configuration information to a user equipment, wherein the configuration information is used to instruct the user equipment to use a measurement set to measure a synchronization signal, wherein the measurement set is used by a user equipment in a connected state to measure a synchronization signal, the measurement set is a first synchronization signal block (SS block) set, and the first SS block set includes a number of SS blocks smaller than a number of SS blocks included in a second SS block set which includes an SS block used by the user equipment in an idle state to measure the synchronization signal; or the measurement set is a signal set, and the signal set includes a part of signals in Y SS blocks, and Y is a positive integer. |
| US11336377B1 |
Millimeter-wave frequency synthesizer based on microcomb photomixing, and associated methods
A millimeter-wave frequency synthesizer generates a millimeter wave by photomixing two Kerr-soliton microcombs. A single-frequency laser beam is modulated to create first and second pump components having first and second pump frequencies. The first pump component excites a first microresonator to create a first microcomb while the second pump component excites a second microresonator to generate a second microcomb. A pair of comb lines from the two microcombs is detected to generate a low-frequency beat note that is phase-locked by identically tuning the pump frequencies. Another pair of comb lines is detected with a high-speed photodiode to generate the millimeter wave. The frequency of the millimeter wave is based on (i) the difference between the pump frequencies, (ii) the difference between the repetition rates, and (iii) the index of the comb lines that are photomixed to generate the millimeter wave. |
| US11336375B2 |
Optical transmission apparatus, optical communication system, and optical signal transmission method
An object is to perform wavelength filtering of an optical signal while preventing filter narrowing in an optical transmission apparatus. A branching unit branches a wavelength-multiplexed optical signal including an optical signal of a first wavelength into two optical signals. A wavelength selection unit blocks an optical signal of a first wavelength band including the first wavelength in the optical signal. A filter unit allows passage of an optical signal of a second wavelength band including the first wavelength in the optical signal. A multiplexing unit multiplexes and the optical signal and an optical signal of a second wavelength. The second wavelength band is wider than the first wavelength band. |
| US11336372B2 |
Hybrid data transport for a virtualized distributed antenna system
A system for data transport in a Distributed Antenna System (DAS) includes a plurality of remote Digital Access Units (DAUs) located at a Remote location. The plurality of remote DAUs are coupled to each other and operable to transport digital signals between the plurality of remote DAUs. The system also includes a plurality of central hubs. Each of the plurality of central hubs is in communication with one of the remote DAUs using an electrical communications path. The system further includes a plurality of transmit/receive cells. Each of the plurality of transmit/receive cells includes a plurality of remote hubs. Each of the remote hubs in one of the plurality of transmit/receive cells is in communication with one of the plurality of central hubs using an optical communications path. |
| US11336371B2 |
Defocuser for compact free space communication
Methods, devices, and systems are described for free space optical communication. An example device can comprise a defocuser configured to receive an optical signal from a laser and control a beam divergence of the optical signal. The optical signal can comprise a data signal and a beacon signal. The device can comprise a controller configured to cause the defocuser to adjust the beam divergence based on an operational mode of the laser. |
| US11336370B1 |
Integrated multi-channel photonics transmitter chip having variable power dividers
An integrated transmitter chip comprising: at least one input port disposed at a first end; a first variable power divider optically connected to a first input port of the at least one input port, the first variable power divider being tunable to a first splitting ratio; a second and a third variable power dividers each optically connected to the first variable power divider, the second and the third variable power dividers being tunable to a second and a third splitting ratios; and a first and a second optical channels being optically branched from the second variable power divider, and a third and a fourth optical channels being optically branched from the third variable power divider; wherein an optical signal being launched into the first input port and having an input power is caused to be split by the first variable power divider into a first and a second optical signals. |
| US11336365B2 |
Method for managing the telecommunication data traffic of a very high throughput satellite communication system
A method for managing the telecommunication data traffic of a very high throughput satellite communication system wherein, for each satellite, the management of a so-called n+p site diversity and/or of a load diversity is implemented in a digital transparent processor in the satellite to guarantee the availability of the very high throughput communication system. |
| US11336362B2 |
Repeater system and method for high-performance communication
A repeater system includes a first repeater device to receive a first beam of radio frequency (RF) signal from a first network node, and a second repeater device to receive a second beam of RF signal from the first network node. The first repeater device synchronizes and controls the second repeater device to concurrently provide the first beam and the second beam of RF signal to a second network node. A plurality of measurements associated with network nodes and repeater devices is acquired. A plurality of signal parameters is selected at the first and second repeater devices for a first beam and a second beam of RF signal, respectively, such that a cross-leakage of first beam on the second beam of RF signal and vice-versa at the second network node is reduced and the gain and a phase of first beam and the second beam of RF signal is adjusted. |
| US11336361B2 |
Millimeter-wave non-line of sight analysis
Reducing the effects of path loss in millimeter wave (mmWave) directional communications by performing channel measurements estimating non-line of sight (NLOS) blockages, to determine angle-of-departure (AoD) and angle-of-arrival (AoA) and gain of identified paths so that directional antennas can be reconfigured to overcome unfavorable propagation conditions and reduce path losses. |
| US11336358B2 |
Transmission control method
A transmission control method includes sending, by a terminal, uplink control information (UCI) in a first format of the UCI to a radio access network device, where the UCI includes at least one of measurement result information of beam groups or information of the beam groups. The measurement result information of the beam groups includes a measurement result of a first beam group and an offset of a measurement result of a second beam group relative to the measurement result of the first beam group. The measurement result of the first beam group is a reference measurement result, and the information of the beam groups indicates a beam group corresponding to at least one of the measurement result of the first beam group or the measurement result of the second beam group. |
| US11336356B2 |
Uplink control information
Embodiments of the present disclosure relate to methods, devices, apparatuses and computer readable storage media for Uplink Control Information (UCI) design. The method comprises determining, at a terminal device, a matrix comprising a set of non-zero linear combination coefficients for quantizing a channel between the terminal device and a network device, the matrix having spatial components and frequency components; shifting the frequency components of the matrix circularly, such that a target coefficient of the set of non-zero linear combination coefficients is located in a frequency component with a predetermined index of the frequency components in a shifted matrix; generating a first indication indicating the spatial component associated with the target coefficient in the matrix; and transmitting, to the network device, uplink control information comprising the first indication. In this way, a new solution for designing the UCI may reduce the overhead for reporting the parameters in the UCI. |
| US11336351B2 |
Method and apparatus for higher rank CSI reporting in advanced wireless communication systems
The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method of operating a user equipment (UE) for CSI feedback is provided. The method comprises receiving configuration information for the CSI feedback from a base station (BS) and identifying a number of antenna ports for the CSI feedback. The method comprises, if the number of antenna ports is <16, identifying a first codebook for the CSI feedback corresponding to a rank value of 3 or 4, and, if otherwise, identifying a second codebook for the CSI feedback corresponding to the rank value of 3 or 4. The method comprises generating the CSI feedback using the identified codebook and transmitting the generated CSI feedback to the BS. The first codebook has a structure that partitions the antenna ports into two equal partitions. The second codebook has a structure that partitions the antenna ports into four equal partitions by partitioning each partition into two equal sub-partitions. |
| US11336345B2 |
Signal transmission device
A signal transmission device includes a first antenna, a second antenna, a demodulation device, and a fixing member. The first antenna transmits radio waves containing a signal modulated at a first frequency. The second antenna receives the radio waves containing the signal via a medium. The demodulation device demodulates the signal and connected to the second antenna. The fixing member fixes the first antenna and the second antenna to the medium. |
| US11336343B2 |
Method and device for performing communication using orthogonal or nonorthogonal code multiple access scheme in wireless communication system
Provided are a method and a device for transmitting uplink data by using a non-orthogonal code multiple access scheme in a wireless communication system. Specifically, a terminal receives information on a terminal-specific codebook from a base station. The terminal-specific codebook is included in a codebook for a predefined multi-dimensional modulation. The terminal performs multi-dimensional modulation-based encoding on an information bit on the basis of the terminal-specific codebook so as to generate a complex vector. The terminal performs DFT on the complex vector on the basis of the terminal-specific codebook so as to generate a frequency signal. The terminal transmits uplink data generated by performing IFFT on the frequency signal. |
| US11336339B2 |
Precoding matrix indication method, terminal, and network side device
Provided in the present disclosure are a precoding matrix indication method, a terminal, and a network device, the method includes: receiving, by a terminal, a control signaling transmitted from a network side device, wherein the control signaling includes N bits of precoding information, and the N is a positive integer; determining, by the terminal, a quantity of precoding granules according to a scheduling resource, and determining, by the terminal, bits of the precoding information of each of the precoding granules in the N bits of precoding information according to the quantity of the precoding granules, wherein each of the precoding granules includes at least one subband, and each of the at least one subband includes at least one PRB; and acquiring, by the terminal, a precoding matrix indicated by the bits of the precoding information of each of the precoding granules. |
| US11336336B2 |
Methods and apparatuses for dynamic transmit diversity fallback
Systems, methods, apparatuses, and computer program products for dynamic transmit diversity fallback are provided. One method may include configuring a user equipment with a maximum number of multiple-input multiple-output (MIMO) layers used for transmission mode 9 or transmission mode 10 scheduling, and performing, by a network node, at least one of transmission mode 9 or transmission mode 10 scheduling. The configuring may include indicating to the user equipment to use a modified mapping table providing transmit diversity fallback for the at least one of transmission mode 9 or transmission mode 10 scheduling. |
| US11336333B2 |
NFC device, reader/writer device and methods for authorizing and performing an update
An NFC device comprises a function unit configured to execute a function based on related command code, a storage unit configured to store the command code, a communication unit configured to communicate with another NFC device, and a processing unit configured, if an update of the command code shall be made by the another NFC device, to calculate a checksum over at least part of the command code, to compare the calculated checksum with a checksum received from the another NFC device and to authorize the update if the received checksum matches the calculated checksum. |
| US11336330B2 |
Radio frequency circuit and communication device
A radio frequency circuit includes a first acoustic wave filter that is connected to a common terminal and includes a first acoustic wave resonator, a first LC filter that is connected to the common terminal via the first acoustic wave filter and includes at least one of an inductor or a capacitor, a second acoustic wave filter that is connected to the common terminal and includes a second acoustic wave resonator, and a second LC filter that is connected to the common terminal via the second acoustic wave filter and includes at least one of an inductor or a capacitor. |
| US11336327B2 |
Base station coordination for cross-link interference cancelation
Techniques and apparatuses are described for enabling base stations (121, 122) to coordinate for canceling cross-link interference (380). The techniques and apparatuses described herein overcome challenges that a single base station (121) might otherwise face in trying to compensate a reception (131) by the base station (121) for cross-link interference (382) from a transmission (132) by another base station (122). The techniques and apparatuses described herein enable the base stations (121, 122) to form coordination sets to exchange information to enable the base stations (121, 122) to accurately reconstruct cross-link interference (380) and ultimately cancel the cross-link interference (380) to improve link quality. |
| US11336323B2 |
Front-end module and communication device
A front-end module includes: a switch module that performs CA for bands A and C and performs non-CA for band B, which is located between these two bands, and that has a common terminal and selection terminals; a duplexer that is connected to the selection terminal and allows band A to pass therethrough; a duplexer that is connected to the selection terminal and allows band C to pass therethrough; an impedance matching network that is connected to the selection terminal; and a reception filter that is connected to the impedance matching network and allows band B to pass therethrough. During CA for bands A and C, a first circuit, which includes the impedance matching network and the reception filter, forms an attenuation pole in the frequency band of band C in the transmission characteristic of a path connecting the duplexer, the common terminal, and the duplexer to each other. |
| US11336321B1 |
Transmitter / receiver device
A transmitter/receiver device include an antenna, a voltage source, a radio frequency receiver connected to the antenna and powered by the voltage source, a radio frequency transmitter connected to the antenna and powered by the voltage source, and a switch coupled to the antenna, the receiver and the transmitter and configured to couple/decouple the antenna from the transmitter or from the receiver. The antenna is shared between the transmitter and the receiver. The receiver includes a radio frequency stage that includes an amplifier device having an input coupled to the antenna. The amplifier device includes an amplifier switch configured to connect or disconnect the amplifier device from the voltage source. |
| US11336319B2 |
Radiation exposure control for beamforming technologies
A circuit arrangement including one or more processors configured to: detect a presence of one or more human object proximities based on sensor data; identify one or more coverage sectors of one or more antenna arrays, operably coupled to the one or more processors, in response to the detected presence of the one or more human object proximities; determine whether radio waves within the one or more identified coverage sectors satisfy a transmit power criteria; select one or more candidate coverage sectors of the one or more antenna arrays based the one or more identified coverage sectors; and determine at least one radio link quality for the radio waves of the one or more candidate coverage sectors. |
| US11336316B2 |
Transmission and/or reception of radio frequency signals
An apparatus comprising: a sampler for over-sampling an input signal to produce a sampled input signal; a delta-sigma modulator for modulating the sampled input signal to produce a modulated signal; and a filter for filtering the modulated signal, the filter comprising: a conductive patch and a ground plane separated by a dielectric wherein the ground plane comprises a band-gap periodic structure. |
| US11336315B2 |
Radio-frequency module and communication device
A radio frequency module includes a module board including a first principal surface and a second principal surface on opposite sides of the module board, a transmission power amplifier connected to a transmission path, a first circuit component connected to a reception path, and a control circuit that controls the transmission power amplifier. The control circuit is disposed on the first principal surface, and the first circuit component is disposed on the second principal surface. |
| US11336312B2 |
Radio frequency module and communication device
A radio frequency module includes: a switch that includes: a common terminal connected to a first common transmission path; a first selection terminal connected to a first transmission path; and a second selection terminal connected to a second transmission path, and switches between connecting the common terminal to the first selection terminal and to the second selection terminal; a transmission power amplifier disposed on the module board and on first common transmission path; and first circuit components disposed on a reception path. The first transmission path is a path through which a transmission signal of a first communication band is transferred, the second transmission path is a path through which a transmission signal of a second communication band is transferred, the switch is disposed on a first principal surface, and at least one of the first circuit components is disposed on a second principal surface. |
| US11336308B2 |
Apparatus and method for determining reflection coefficient of antenna
Disclosed is an electronic device. Other various embodiments as understood from the specification are also possible. The electronic device may include an antenna, a communication module including a transceiver, and a control circuit. The control circuit may be configured to radiate a first signal generated from the transceiver through the antenna, to obtain at least part of a second signal obtained by combining a forward signal delivered from the communication module to the antenna and a reverse signal reflected from the antenna, and to determine a reflection coefficient for the antenna based on at least part of the first signal and at least part of the second signal. |
| US11336307B2 |
Memory system that carries out soft bit decoding
A memory system includes a nonvolatile semiconductor memory, and a controller configured to maintain a plurality of log likelihood ratio (LLR) tables for correcting data read from the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on a physical location of a target unit storage region of a read operation, and carry out correcting of data read from the target unit storage region, using one of the LLR tables selected according to the determined order. |
| US11336306B2 |
Decoding apparatus, decoding method, and non-transitory computer readable medium
A decoding apparatus includes a multi-input branch metric calculation unit configured to calculate, by using a branch label corresponding to a path extending toward a state S at a time point N in a trellis diagram and a plurality of reception signal sequences, a branch metric in the state S, a path metric calculation unit configured to calculate a path metric in the state S at the time point N, and a surviving path list memory configured to store path labels corresponding to L path metrics among a plurality of calculated path metrics. The path metric calculation unit generates a path label in the state S at the time point N by combining the branch label with a path label in each of the states at the time point N−1 and the surviving path list memory outputs path labels corresponding to L path metrics. |
| US11336305B2 |
Memory system
A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region. |
| US11336302B2 |
Pipelined forward error correction for vector signaling code channel
Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values. |
| US11336297B2 |
DMA transfer apparatus, method of controlling the same, communication apparatus, method of controlling the same, and non-transitory computer-readable storage medium
A DMA (Direct Memory Access) transfer apparatus acquires information including a transfer source address and a transfer destination address based on a received transfer instruction, selects whether to perform first checksum calculation for data from an area of a memory corresponding to the transfer source address or perform second checksum calculation different from the first checksum calculation, and transfers data obtained via the checksum calculation selected in the selecting to an area of the memory corresponding to the transfer destination address. |
| US11336286B2 |
Scalable micro bumps indexing and redundancy scheme for homogeneous configurable integrated circuit dies
A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs. |
| US11336281B2 |
Output module for industrial control system
An output module for a PLC includes an output circuit. This output circuit is open or closed selectively between a power supply terminal (to which a power supply voltage is supplied) and an output terminal (connected to a solenoid). The output module includes a control apparatus which controls the operation of the output circuit. The output circuit includes switches connected in series to each other between the power supply terminal and the output terminal, and a current output section which performs an operation of short-circuiting terminals of the switch to pass a predetermined current through a path formed due to the short-circuiting. The control apparatus includes on/off control sections which controls on/off states of the respective switches, and diagnosis sections which perform a diagnosis on presence of a short-circuit fault in the respective switches based on diagnostic signals output from a low-potential terminal of the switches. |
| US11336273B1 |
Protection against attacks on integrated circuits using voltage monitoring
An Integrated Circuit (IC) includes functional circuitry and attack-protection circuitry (APC). The functional circuitry is to receive a supply voltage from a power-supply input. The APC is coupled to the power-supply input and includes a front-end circuit and an averaging circuit. The front-end circuit is to compare the supply voltage to a plurality of voltage thresholds, and to output a respective plurality of indications that indicate whether the supply voltage violates the respective voltage thresholds. The averaging circuit is to estimate, for a selected subset of the indications, respective duty-cycles at which the indications in the subset exceed the respective voltage thresholds. The APC is to trigger one or more attack detection events in response to the indications and the duty-cycles. |
| US11336272B2 |
Low power single retention pin flip-flop with balloon latch
Systems, apparatuses, and methods for implementing a low-power, single-pin retention flip-flop with a balloon latch are described. A flip-flop is connected to a retention latch to store a value of the flip-flop during a reduced power state. A single retention pin is used to turn on the retention latch. During normal mode, the retention latch is pre-charged and a change in the value stored by the flip-flop does not cause the retention latch to toggle. This helps to reduce the power consumed by the circuit during normal mode (i.e., non-retention mode). When the retention signal becomes active, the retention latch gets triggered and the value stored by the flip-flop is written into the retention latch. Later, if the flip-flop is powered down and then powered back up while the circuit is in retention mode, the value in the retention latch gets written back into the flip-flop. |
| US11336268B2 |
Integrated circuit comprising at least one ring oscillator and method for controlling an operation of the oscillator
Integrated circuit, comprising at least one ring oscillator including a succession of inverters looped back to form the ring, the at least one oscillator being intended to operate at a desired output frequency and configured so that the inverter transistors operate in or near their temperature inversion zone. |
| US11336264B1 |
Systems and methods for varying an impedance of a cable
A system may include a transmitter, a receiver, a cable coupled between the transmitter and the receiver and having two wires for communicating a differential signal from the transmitter to the receiver, and a direct-current (DC) voltage source coupled to a first wire of the two wires of the cable and configured to apply a variable DC offset voltage to the first wire in order to vary an impedance of the cable as a function of the variable DC offset voltage. |
| US11336263B2 |
Negative-resistance circuit and active filter for millimetre wave frequencies
The invention relates to a tunable, silicon-based negative-resistance circuit (10, 30) and to an active filter (50) for E-band frequencies (60 to 90 GHz). A base of a transistor (11) is connected to an on-chip inductive transmission line (13) which has a length of approximately a quarter-wavelength at a frequency of 83.5 GHz. The transmission line connects a DC voltage source (14) to the base terminal of the transistor (11) in order to bias the base. Another DC voltage source (15) is connected to the collector of the transistor (11) to bias the transistor. A capacitor (16) operatively bypasses or decouples the voltage source (15) in order to shunt high frequencies or alternating current (AC) signals to ground. The emitter terminal of the transistor (11) is connected to ground through a resistor (18) to limit the collector current (le). The circuit gives rise to improved quality factor of resonators. |
| US11336261B2 |
Multiplexer, high-frequency front end circuit, and communication device
A multiplexer (1) includes a plurality of filters connected to a common terminal (110). The multiplexer (1) includes: a low-frequency filter (11L) that is formed of at least one surface acoustic wave resonator arranged between the common terminal (110) and the input/output terminal (120) and has a first pass band; a high-frequency filter (12H) that is connected between the common terminal (110) and the input/output terminal (130) and has a second pass band located at a higher frequency than the first pass band; and a capacitor (CB1) that is serially arranged in a connection path between the common terminal (110) and the low-frequency filter (11L). The Q value of the capacitor (CB1) in the second pass band is higher than the Q value in the second pass band of a capacitance obtained by treating the at least one surface acoustic wave resonator of the low-frequency filter (11L) as a capacitance. |
| US11336260B2 |
Filter module
A filter module includes a filter provided on a path connecting an input/output terminal and an input/output terminal, a filter provided on a path connecting an input/output terminal and an input/output terminal, a switch that switches between electrical connection and electrical disconnection between a wire connected to the input/output terminal and a ground, and a switch that switches between electrical connection and electrical disconnection between a wire connected to the input/output terminal and the ground. When the wire and the ground are electrically connected by the switch, the wire and the ground are electrically disconnected by the switch, and when the wire and the ground are electrically connected by the switch, the wire and the ground are electrically disconnected by the switch. |
| US11336255B2 |
Acoustic wave element and method for manufacturing same
An acoustic wave element which can be reduced in size and produced relatively easily, practically used without using harmful substances, and can suppress a surface acoustic wave propagation loss, which has an excellent temperature coefficient of frequency and a velocity dispersion characteristic, and with which an increase in the reflection coefficient of interdigital transducers can be suppressed, and a method for manufacturing the acoustic wave element are provided. The acoustic wave element includes a pair of electrodes provided on both surfaces of a piezoelectric substrate, and a dielectric film provided on a first surface of the piezoelectric substrate so as to cover the electrode. The acoustic wave element alternatively includes interdigital transducers provided on a first surface of the piezoelectric substrate, and a dielectric film provided on the interdigital transducers, a gap between the interdigital transducers, and/or a second surface of the piezoelectric substrate. |
| US11336254B2 |
Composite substrate and acoustic wave element using same
A composite substrate 10 includes a first substrate 10 comprised of a piezoelectric single crystal and a second substrate 20 comprised of a silicon single crystal bonded to the first substrate 10. In the second substrate, a planar orientation is (111), and ψ of Euler angles (φ, θ, ψ) is offset from 0°. Due to this, a bulk wave spurious is reduced in a specific frequency band. |
| US11336252B2 |
Radio frequency filter, multiplexer, radio frequency front end circuit, and communication apparatus
A filter (10) includes two capacitors (C1a and C1b) that are connected in series on a path connecting an input terminal (101a) and an output terminal (102a), an inductor (L2) that is connected in parallel with a series circuit including the two capacitors (C1a and C1b), and a parallel-arm resonator (P1) that is connected between the ground and a node (N) between the two capacitors (C1a and C1b) on the path. |
| US11336244B2 |
Fully differential rail-to-rail output amplifier with inverter-based input pair
A fully differential rail-to-rail-output amplifier includes a differential input inverter pair, folded cascode pair, class AB control pair, and class AB output rail-to-rail pair. A drain associated with the folded cascode pair is operatively coupled to the class AB control pair, and the drain associated with the folded cascode pair is unconnected to the current source associated with the class AB control pair. A method of providing fully differential rail-to-rail-output amplification includes coupling a folded cascode pair operatively to a differential input inverter pair, coupling a drain associated with the folded cascode pair operatively to a class AB control pair, and coupling a class AB output rail-to-rail pair operatively to the class AB control pair. |
| US11336240B2 |
Uplink multiple input-multiple output (MIMO) transmitter apparatus using transmit diversity
An uplink multiple input-multiple output (MIMO) transmitter apparatus using transmit diversity uses transmit diversity signals that are modified to create intermediate orthogonal signals. A transceiver circuit in the transmitter apparatus includes a sigma-delta circuit that creates a summed (sigma) signal and a difference (delta) signal from the intermediate orthogonal signals. These new sigma and delta signals are amplified by power amplifiers to a desired output level before having two signals reconstructed from the amplified sigma and amplified delta signals by a second circuit. These reconstructed signals correspond to the two original transmit diversity signals but are at a desired amplified level relative to the two original signals. The reconstructed signals are then transmitted through respective antennas as uplink signals. |
| US11336237B2 |
Vector modulator for millimeter wave applications
Examples disclosed herein relate to a vector modulator architecture, having an input splitter network configured to receive a radio frequency (RF) input signal and generate a plurality of quadrature signals at different phases, a variable gain amplifier (VGA) stage coupled to the input splitter network and configured to apply a first gain to one or more of the plurality of quadrature signals, a power combiner coupled to the VGA stage and configured to combine the plurality of quadrature signals into a combined RF signal, and a power amplifier (PA) stage coupled to the power combiner and configured to apply a second gain to the combined RF signal and generate an output RF signal. Other examples disclosed herein relate to an antenna system for autonomous vehicles and a radar system for use in an autonomous driving vehicle. |
| US11336235B2 |
Amplifier
An amplifier is configured in such a way that a first capacitor resonates at the frequency of a second harmonic wave included in a signal outputted from an amplifying element, a circuit including a second transmission line, the first capacitor, and a second capacitor resonates at the frequency of a third harmonic wave included in the signal outputted from the amplifying element, and also matches the impedance for a fundamental wave together with an impedance matching circuit. |
| US11336234B2 |
Power amplifier circuit
A power amplifier circuit includes a power amplifier that amplifies an input signal and outputs the amplified signal from an output terminal thereof, a first filter circuit that has a frequency characteristic that attenuates an Nth-order harmonic of the amplified signal, N that is an integer greater than or equal to 2, and a second filter circuit that has a frequency characteristic that attenuates the Nth-order harmonic of the amplified signal. The first filter circuit includes a first capacitor and a first inductor. The first capacitor and the first inductor are connected in series between the output terminal and ground. The second filter circuit includes a second capacitor and a second inductor. The second capacitor and the second inductor are connected in series between the output terminal and ground. |
| US11336230B2 |
Oscillator circuit with two current supplies
An oscillator circuit comprises a crystal oscillator and an inverter. The input of the inverter is connected to the first terminal of the crystal oscillator and the output of the inverter is connected to the second terminal of the crystal oscillator, oscillator circuit is arranged to operate the inverter in its linear operating region. An amplitude regulator has an input connected to the input of the inverter, arranged to provide a first supply current IAREG to the inverter, where the magnitude of the first supply current is inversely dependent on a magnitude of a voltage at the inverter input. A digital-to-analogue converter is arranged to provide a second supply current IDAC to the inverter having a magnitude determined by a digital signal applied to a digital input of the digital-to-analogue converter. |
| US11336228B2 |
High frequency push-push oscillator
A high frequency push-push oscillator is disclosed. The high frequency push-push oscillator includes a resonant circuit, including tank transmission lines or an inductor capacitor (LC) tank circuit, for generating a differential signal having a resonant frequency, and a Gm-core circuit for converting the differential signal to an output signal having an output frequency that is higher than the resonant frequency. The Gm-core circuit includes cross-coupled first and second transistors having first and second gates, drains, and sources, respectively, and first and second gate transmission lines. The first and second drains are in electrical communication with the resonant circuit. The first gate transmission line is joined with the first gate and the resonant circuit and the second gate transmission line is joined with the second gate and the resonant circuit. The Gm-core circuit includes a differential transmission line positioned between the first and second gates of the first and second transistors. |
| US11336226B2 |
Compensating temperature null characteristics of self-compensated oscillators
Techniques are described that enables controlling the TNULL characteristic of a self-compensated oscillator by controlling the magnitude and direction of the frequency deviation versus temperature, and thus, compensating the frequency deviation. |
| US11336223B2 |
Electrical connection device for a photovoltaic system
The present invention provides a building exterior cladding. The panel includes an upper overlap area, a lower overlap area and a central part, covered by at least one photovoltaic module. A perforation is located in the lower overlap area and traversed by an electrical cable connecting one of two electrical poles of the photovoltaic module to an electrical plug located on the reverse side of the panel in the lower overlap area. An opening is located in the upper overlap area, into which is inserted an electrical junction box connected to another electrical pole of the photovoltaic module by an electrical cable. The junction box includes: a base, a lateral wall, including on its external surface, a peripheral shoulder to hold the box in place in the opening, an access door located on the lateral wall of the junction box, a cable outlet, an internal cavity delimited by the base and the wall, including an electrical terminal with an axis perpendicular to the base, and an electrical switch connecting the electrical terminal to the cable outlet and located facing the access door. The invention further provides an associated electrical junction box and the associated electrical connection assembly. |
| US11336220B2 |
Mounting assembly for mounting a solar panel
A mounting assembly for mounting a solar panel to a surface includes a mounting base that is supported on the surface. The mounting base defines an elongated opening that extends along an axis. A module mount can be coupled to the mounting base. The module mount includes a first mount portion that is received within the elongated opening of the mounting base such that the module mount is movable with respect to the mounting base along the axis. A second mount portion is coupled to the solar panel for mounting the solar panel to the surface through the mounting base. |
| US11336219B2 |
Monitoring an electrical machine for the presence of a fault
The disclosure relates to an electric machine and in particular to the monitoring of the electric machine for the presence of a fault, (e.g., in the stator windings). A monitoring unit is provided, wherein the monitoring unit measures the multiphase electrical time signals transmitted from or to the machine and with the aid of a Hilbert filter determines substantially in real time the envelopes and the phase positions of the individual phases of the time signal. The envelopes corresponding to the different phases or the corresponding phase positions are compared with one another by way of forming differences and, in the event that one or more of the differences deviate(s) from a specified expectation value, the presence of a fault is inferred. The approach allows significantly increased operational reliability of the electric machine to be achieved in particular. |
| US11336215B2 |
Display and rotating method thereof
A display including a supporting stand and a display panel is provided. The supporting stand has a rotating assembly, a drive motor, and a microcontroller. The display panel has a computing device. The drive motor is connected to the rotating assembly for driving the rotating assembly to rotate. The microcontroller is coupled to the drive motor for controlling the drive motor. The display panel is disposed on the rotating assembly. The computing device is coupled to the microcontroller. The computing device is configured to read an image. The computing device transmits a signal to the microcontroller based on an orientation of the image being portrait or landscape so that the microcontroller switches on the drive motor and the rotating assembly drives the display panel to rotate relative to the supporting stand for switching a rotating position of the display panel to a portrait mode or a landscape mode. |
| US11336211B2 |
Vibration wave motor and driving apparatus using vibration wave motor
A vibration wave motor includes a vibrator; a first holding member configured to hold the vibrator; a second holding member; an elastic coupling member configured to couple the first holding member and the second holding member to each other; a friction member; and a pressurizing unit, wherein the vibrator and the friction member relatively move due to vibration of the vibrator, wherein the elastic coupling member includes a first coupling portion and a second coupling portion, and wherein one of the first coupling portion and the second coupling portion is arranged on a straight line that is parallel to a direction of the relative movement and passes through a pressurizing gravity center and another of the first coupling portion and the second coupling portion is arranged on a straight line that is orthogonal to the direction of the relative movement and passes through the pressurizing gravity center. |
| US11336205B1 |
Inverter for a low frequency amplifier with high drive voltage, high power density, high efficiency, and wide bandwidth operation
A low frequency direct drive amplifier is disclosed which can simultaneously achieve high drive voltages, high power density, high efficiency, and wide bandwidth operation is disclosed. The power circuit structure includes an input DC-DC converter and an output multi-level DC-AC inverter. The input DC-DC converter's circuit topology is commonly referred to as the phase shifted full bridge, which includes input capacitors, a Gallium Nitride (GaN) based full bridge, an isolation transformer, two rectifying diodes, and two series stacked output capacitors. The output DC-AC inverter includes two series stacked input capacitors (same as the input DC-DC converter's output capacitors), four Silicon Carbide (SiC) semiconductors, four Silicon IGBTs, and an output filter. The disclosure's features the combination of the output multi-level DC-AC inverter circuit topology paired with 1.7 kV SiC semiconductors, allowing for a high voltage direct drive design without a low frequency boost transformer. |
| US11336202B1 |
Over voltage protection for wireless power receiver circuits
Methods and apparatuses for controlling a rectified voltage outputted by a rectifier circuit is described. In response to an occurrence of an overvoltage condition, an apparatus can regulate a gate-source voltage of a low-side switching element of the rectifier circuit to control the rectified voltage. The apparatus can include an operational amplifier that can compare a reference voltage and with a scaled voltage measured at a node between the low-side switching element and a high-side switching element of the rectifier circuit. The operational amplifier can output a voltage to regulate a gate-source voltage of a low-side switching element. The apparatus can further include a current sensor configured to sense current flowing through the low-side switching element. A power dissipation of the low-side switching element can be controlled based on the current being sensed by the current sensor. |
| US11336199B2 |
Load identifying AC power supply with control and methods
An improved AC power supply is described. The supply identifies the load through monitoring the current and voltage wave forms and phase relations with the AC Mains. The comparison is done in conditions where the power to the load is programmably varied through use of a control switch located in the line and neutral between the AC mains and the load. The program of controlling the switch is varied to optimize the ability to distinguish similar load types. The switch can be further used to control power to the load that varies according to a set of rules based upon the identity of the load. In a preferred embodiment, the design enables high efficiency with minimal components that may be fully integrated onto silicon. |
| US11336198B2 |
System for generating a power output and corresponding use
The present invention relates to a system for generating a direct current power output from an alternating current (103) in a primary wire (3), wherein the system comprises: at least one core (104) configured to be located around the primary wire (3); at least one secondary winding (22, 24) arranged around the at least one core (104), wherein each winding (22, 24), together with the at least one core (104) and the primary wire (3), forms a current transformer unit, and wherein each secondary winding (22, 24) has a first end and a second end; for each secondary winding (22, 24), a rectifier (10), wherein each rectifier (10) is configured to convert an alternating current to a direct current, and wherein each rectifier (10) comprises two AC connections for alternating current and two DC connections for direct current, wherein the first end and the second end of the secondary winding (22, 24) are connected to the AC connections of the rectifier (10); for each secondary winding (22, 24), a shunting unit arranged and configured to short the ends of the secondary winding (22, 24); and a load element (6), wherein the load element (6) is connected to a DC connection of each rectifier (10). The present invention also relates to a corresponding use. |
| US11336195B2 |
Power conversion apparatus that determines, based on a set of data, whether it is operable to perform an output
A power conversion apparatus includes a rectifier to convert AC power into constant-current DC power, a resonant inverter to convert the DC power into AC power to be output to a load, and a control unit to receive settings of an output current value of the inverter, a current-supplying time of the inverter, an operation rate defined by dividing the current-supplying time by a sum of the current-supplying time and a non-current-supplying time, and a resonance frequency of the load. The control unit operates the rectifier and the inverter only when it determines that it is operable to perform an output in accordance with the set conditions, based on data in which the output frequency, the current-supplying time and the operation rate are associated with an allowable output current value of the inverter at a temperature equal to or lower than a maximum operable temperature of a switching device. |
| US11336192B2 |
Three-phase power apparatus with bidirectional power conversion
A three-phase power apparatus with bidirectional power conversion applied to charge a battery of an electric vehicle. The three-phase charging apparatus includes an AC-to-DC conversion unit, a first DC bus, a first DC-to-DC conversion unit, a second DC bus, and a second DC-to-DC conversion unit. The first DC bus is coupled to the AC-to-DC conversion unit. The first DC-to-DC conversion unit includes an isolated transformer, a resonant tank, a first bridge arm assembly, and a second bridge arm assembly. The first bridge arm assembly is coupled to the first DC bus and a primary side of the isolated transformer. The second bridge arm assembly is coupled a secondary side of the isolated transformer. The second DC bus is coupled to the second bridge arm assembly. The second DC-to-DC conversion unit is coupled to the second DC bus and the battery. |
| US11336186B2 |
Resonant DC-DC voltage converter
The subject matter of the invention is a resonant DC-DC voltage converter, notably for an electric or hybrid vehicle, said converter including n interleaved main resonant circuits, n being a natural integer greater than or equal to two, and in which: the main resonant circuits are connected together at least one neutral point different from a ground of the converter, said neutral point being connected to a ground of the converter by an impedance configured to store energy and to enable zero voltage switching of the switches of the resonant DC-DC converter. |
| US11336175B2 |
Charge balanced charge pump control
Operating a charge pump in which switches from a first set of switches couple capacitor terminals to permit charge transfer between them and in which switches from a second set of switches couple capacitor terminals of capacitors to either a high-voltage or a low-voltage terminal includes cycling the switches through a sequence of states, each state defining a corresponding configuration of the switches. At least three of the states define different configurations of the switches. During each of the configurations, charge transfer is permitted between a pair of elements, one of which is a first capacitor and another of which is either a second capacitor or the first terminal. |
| US11336173B1 |
Power converter device and driving method
The present disclosure relates to a power converter device including a power factor correction circuit, a resonance converter circuit, and a zero voltage switching circuit. The power factor correction circuit is coupled to the primary side rectifier circuit, and includes a first switching circuit, a first control circuit and a first output circuit. The resonance converter circuit includes a second switching circuit and a second control circuit. The second switching circuit is coupled to the first output circuit, and the second control circuit is coupled to the secondary side rectifier circuit. The zero voltage switching circuit is coupled between the first control circuit and the second control circuit. The zero voltage switching circuit is configured to obtain a switching voltage of a switch element in the second switching circuit, and output an adjustment signal to the first control circuit according to the switching voltage. |
| US11336169B2 |
Power conversion device
A power converter includes an arm in which a plurality of converter cells are connected in series, each of the converter cells including at least two switching elements, a power storage element and a pair of output terminals. A control device controls the power converter. The converter cell includes a switch to have the converter cell bypassed. When the control device senses failure of the converter cell, it has the failed converter cell bypassed, estimates an output voltage lost by bypassing the failed converter cell, and has a normal converter cell supply the estimated output voltage of the failed converter cell. |
| US11336162B2 |
Spherical brushless direct current machine
A spherical brushless direct current (BLDC) machine includes a first stator, a second stator, and a spherical rotor. The first stator is symmetrically disposed about a first axis and includes a first multi-pole stator core having a first multi-phase winding wound thereon. The second stator is symmetrically disposed about a second axis and includes a second multi-pole stator core having a second multi-phase winding wound thereon. The second stator core is coupled to the first stator core, and the second axis intersects the first axis. The spherical rotor is disposed adjacent to, and is moveable relative to, the first and second stators. The spherical rotor includes a plurality of magnets that emanate a magnetic field, and each magnet has at least one of its magnetic poles facing the first and second stators. |
| US11336161B2 |
Rotating electric machine and method of manufacturing same
A rotating electric machine includes a stator core, a stator coil formed of electrical conductors and insulating coats respectively covering the electrical conductors, and an encapsulating resin body. The stator coil has a coil end part protruding from the stator core. The coil end part includes exposed portions of the electrical conductors, which are exposed from the insulating coats, joints formed at the exposed portions, and covered portions of the electrical conductors which are covered with the respective insulating coats and respectively adjoin the exposed portions. The encapsulating resin body has a first part in which the exposed portions of the electrical conductors and the joints are encapsulated, and a second part in which at least part of each of the covered portions of the electrical conductors is encapsulated. A coefficient of linear expansion of the first part is lower than a coefficient of linear expansion of the second part. |
| US11336160B2 |
Methods for forming woven undulated coil assemblies
Methods and apparatuses for forming a woven coil assembly (100), the coil assembly having adjacent superimposed linear portions (LI-L6, AL7-ALI2) extending parallel to each other in a first area (Al) of the coil assembly, and adjacent superimposed linear portions (L7-L12, AL13-AL18) extending parallel to each other in a second area (A2) of the coil assembly, wherein a plurality of head portions (T) connect the linear portions of the first area (AI) to the linear portions of the second area (A2). |
| US11336158B2 |
Manufacturing method of core of rotating electrical machine, and core of rotating electrical machine
A manufacturing method of a core of a rotating electrical machine includes: a preparation step of preparing a press device; a fixing step of fixing a steel sheet to a shaft member held by the press device by passing the shaft member through a hole provided in the steel sheet and extending in a stacking direction; and a processing step of performing press-working on the steel sheet by the press device in a state where the steel sheet is fixed to the shaft member. |
| US11336156B2 |
Power control unit
A power control unit includes a power module, a support block configured to support the power module, an upper case configured to cover the power module from above, and a connection conductor configured to connect an internal power feeding passage on the side of the power module and an external power feeding passage on the side of the motor unit, wherein the connection conductor vertically passes through the support block and includes a connecting fixing section that protrudes upward than the support block and that is connected to the internal power feeding passage by a fastening member, an inclination wall inclined downward toward a side end portion of the upper wall of the upper case is provided on the upper wall of the upper case, and an opening section facing the connecting fixing section of the connection conductor is provided in the inclination wall. |
| US11336154B2 |
Stator for an electric motor or generator
A stator for an electric motor or generator, the stator comprising a circumferential support having a plurality of first engagement elements distributed about the circumferential support, a first resiliently deformable element having a first temperature sensing element mounted on the circumferential support, a plurality of teeth for receiving coil windings, wherein each tooth includes a second engagement element to allow engagement with a first engagement element on the circumferential support for allowing each tooth to be mounted on the circumferential support, wherein coil windings on a tooth are arranged to engage with the first temperature sensing element when the tooth is being mounted to the circumferential support with the first resiliently deformable element being arranged to deform upon the coil windings on the tooth engaging with the first temperature sensing element to move the temperature sensing element from a first position to a second position. |
| US11336153B2 |
Motor
The present invention may provide a motor including a housing; a stator disposed in the housing; a rotor disposed in the stator; a shaft coupled to the rotor; and a wire assembly connected to the stator, wherein the wire assembly includes a first ground part, the housing includes a body and a bracket including a first fastening hole and disposed on an upper portion of the body, and the bracket includes a third ground part, which is inserted into the first fastening hole and thereby contacts the body, and a second ground part, which is connected to the third ground part and is disposed so as to be exposed to the bottom surface of the bracket and thereby contacts the first ground part. |
| US11336147B2 |
Speed reducing device having power source
A speed reducing device includes a motor and a speed reducing mechanism. The speed reducing mechanism includes at least one roller assembly, a cycloid disc, at least one fixing disc and a positioning assembly. The roller assembly is disposed within a rotor portion of the motor. While the roller assembly is rotated with the rotor portion, the roller assembly is eccentrically revolved. The roller assembly includes a wheel disc and at least one roller. The cycloid disc includes a main body and at least one cycloid tooth structure. The cycloid tooth structure is protruded from an outer periphery of the main body and in contact with the corresponding roller. While the roller assembly is eccentrically revolved, the at least one cycloid tooth structure is pushed against the corresponding roller, so that the cycloid disc is correspondingly rotated. |
| US11336146B2 |
Motor
A motor includes a rotor including a shaft centered on a vertically extending center axis, a stator radially opposite to the rotor and including coils, a bearing supporting the shaft, and a bus bar assembly on an upper side in an axial direction of the stator. The bus bar assembly includes bus bars including a terminal portion connected to a lead wire drawn out from the coil and a bus bar holder holding the bus bars. The terminal portion includes a slit which extends axially downward and into which the lead wire is fitted. The width of the slit is narrower than the diameter of the lead wire. |
| US11336145B2 |
Motor
A motor includes a rotor, a stator, and first bus bars electrically connected to the stator on one axial direction side of the stator. The stator includes a stator core including a core back extending in a circumferential direction, teeth extending radially from the core back, and coils defined by winding a conducting wire, each of which is mounted on the teeth. A first conducting wire and a second conducting wire which are two respective ends of the conducting wire extend to one axial direction side from each of the coils. The first bus bars are neutral point bus bars connecting two or more first conducting wires as neutral points. The second conducting wire is connected to a power supply that supplies power to the stator. |
| US11336144B2 |
Motor having terminals with unified shapes for positioning
The present invention may provide a motor including a shaft, a rotor coupled to the shaft, a stator disposed outside the rotor, and a bus bar disposed on the stator, wherein the bus bar includes a terminal connected to a coil of the stator, the terminal includes a first terminal and a second terminal which are separated from each other in a circuit manner, the first terminal includes a first neutral terminal and a plurality of first phase terminals, the second terminal includes a second neutral terminal and a plurality of second phase terminals, first curvature centers of the plurality of first phase terminals are disposed to be different, second curvature centers of the plurality of second phase terminals are disposed to be different, and a position of a curvature center of the first neutral terminal is the same as a position of a curvature center of the second neutral terminal. |
| US11336141B2 |
Insulator
Guide portions that guide a winding include a plurality of guide grooves which is provided at each boundary between adjacent wind surfaces, and which is extended in a winding direction of the winding. The plurality of guide grooves is arranged side by side in a radial direction of a stator at an equal pitch. The guide groove provided at an arbitrary boundary among the boundaries is offset in the radial direction relative to the guide groove provided at the adjacent boundary at the opposite side to the winding direction with reference to an orthogonal direction to the radial direction of the motor stator. Respective offset directions and offset amounts of the guide grooves are consistent. |
| US11336138B2 |
Hybrid rotor module cooling
An electric machine including a housing, and a stator mounted to the housing. The stator includes a plurality of laminations, a first end turn and a second end turn. A rotor shaft extends through the housing. A hybrid rotor module is coupled to the rotor shaft. The hybrid rotor module includes a clutch basket having a rotor carrier. The clutch basket houses one or more clutch assemblies. A rotor is mounted to the rotor carrier, and one or more openings are formed in the rotor carrier. The one or more openings direct coolant onto at least one of the stator, the first end turn, and the second end turn. |
| US11336135B2 |
Motor rotor structure and permanent magnet motor
Disclosed is a motor rotor structure including a rotor core. A plurality of radial slots each are in the rotor core along a circumferential direction, and a first flux barrier slot is provided between every two adjacent radial slots. Two kinds of permanent magnets having different coercivities mounted in each radial slot. The two kinds of permanent magnets having different coercivities are distributed along a radial direction of the rotor core. The two kinds of permanent magnets having different coercivities are both magnetized along a tangential direction of the rotor core. A second flux barrier slot is provided between the two kinds of permanent magnets having different coercivities. |
| US11336133B2 |
Stator for an electric motor
A stator (1) for an electric motor has a modular stator body (2) with at least two stator cores (10, 20) arranged axially in series. Each core (10, 20) is form from a plurality of stacked electrical laminations (11, 21). This forms winding poles (16, 26) with radially extending winding webs (17, 27). The stator cores (10, 20) each have a separate overmolding (U1, U2). |
| US11336132B2 |
Electric machine with liquid cooled coils and stator core
An electric machine includes a rotor configured to rotate about an axis of rotation, a stator having a stator core and a plurality of teeth annularly arranged on the stator core about the axis of rotation, a plurality of electromagnetic coils, and a base plate. Each coil of the plurality of electromagnetic coils may be mounted on a separate tooth of the plurality of teeth. The base plate may be located adjacent to the plurality of electromagnetic coils and the stator core. The base plate may have a first side and an opposing second side. The first side may be in thermal contact with the plurality of electromagnetic coils and the stator core. A liquid-coolant channel may be defined on the second side of the base plate such that as the coils and the stator core heats during operation, the base plate is configured to transfer the heat to a liquid coolant in the liquid-coolant channel to dissipate heat from the plurality of electromagnetic coils and the stator core. |
| US11336128B2 |
System for providing power to a stationary underwater control station
Ultrasonic transmitting elements in an electroacoustical transceiver transmit acoustic energy to an electroacoustical transponder, which includes ultrasonic receiving elements to convert the acoustic energy into electrical power for the purposes of powering one or more sensors that are electrically coupled to the electroacoustical transponder. The electroacoustical transponder transmits data collected by the sensor(s) back to the electroacoustical transceiver wirelessly, such as through impedance modulation or electromagnetic waves. A feedback control loop can be used to adjust system parameters so that the electroacoustical transponder operates at an impedance minimum. An implementation of the system can be used to collect data in a vehicle, such as the tire air pressure. Another implementation of the system can be used to collect data in remote locations, such as in pipes, enclosures, in wells, or in bodies of water. |
| US11336122B2 |
Wireless power transmission device and wireless power transmission system
A wireless power transmission device capable of reducing an output power of wireless power receiving device receiving power transmitted from a wireless power transmission device. The wireless power transmission device including: a DC (Direct Current)/DC converter; an inverter configured to convert output voltage of the DC/DC converter into AC voltage having driving frequency; a power transmission coil configured for the AC voltage to be supplied to from the inverter and configured to generate the AC magnetic field; a transmission-side resonance circuit including the power transmission coil; and control circuit configured to increase difference between a driving frequency of the inverter and a resonance frequency of the transmission-side resonance circuit when a predetermined condition is satisfied. |
| US11336120B2 |
Wireless power transfer system for elevators with extended range
A wireless power transfer system for wirelessly powering a conveyance apparatus of a conveyance system including: a wireless electrical power transmitter located along a side of the conveyance system in a first location, the side being stationary; and a wireless electrical power receiver located along a surface of the conveyance apparatus opposite the side, the wireless electrical power receiver and the wireless electrical power transmitter being in a facing spaced relationship defining a gap therebetween when the wireless electrical power receiver is located at the first location. |
| US11336116B2 |
High precision signal measurement in wireless charging system
A wireless charging system is configured to charge one or more receiver devices simultaneously. The wireless charging system includes multiple coils that may be driven independently based on a feedback system with one or more feedback channels. One of the feedback channels may be a voltage and/or current measurement of coil driving signals from the coils that are indicative of receiver device presences on the wireless charging system. A coil driving signal may be sampled and processed using discrete Fourier transform to determine amplitude and phase information of the signal. |
| US11336107B2 |
Information processing device, information processing system, and charging method
[Object] To achieve both prevention of overcharging of the battery and convenience of the user.[Solution] An information processing device includes: a charged capacity detection unit configured to detect a charged capacity of a battery; a charging control unit configured to control a charging circuit; and a specification unit configured to specify when discharge of the battery starts. The charging control unit performs charging suppression control on the charging circuit such that the battery is charged to a preparatorily charged capacity that is lower than a fully charged capacity of the battery, on the basis of the charged capacity detected by the charged capacity detection unit, the charging of the battery stops when the charged capacity of the battery reaches the preparatorily charged capacity, and the charging of the battery restarts from the preparatorily charged capacity before discharge of the battery starts. |
| US11336104B2 |
Method of performing a state of health estimation for a rechargeable battery energy storage system
A method can be used to perform a state of health (SoH) estimation for a rechargeable battery energy storage system during operation of the rechargeable battery energy storage system. The rechargeable battery energy storage system includes a plurality of parallel strings that are individually controllable. The method includes selecting at least one string from the plurality of parallel strings, placing the selected at least one string into a SoH calibration mode for performing a SoH calibration while concurrently maintaining at least one other string of the plurality of parallel strings in operative mode, and causing the selected at least one string to return to the operative mode after the SoH calibration has been completed for the selected at least one string. |
| US11336102B2 |
Battery supply circuits, devices to be charged, and charging control methods
The present disclosure provides a battery supply circuit, a device to be charged, and a charging control method. The battery supply circuit includes a first cell, a second cell, a switch, a first switching unit and a second switching unit. A first end of the second cell is coupled to a first end of the second switching unit, and a second end of the second cell is coupled to a first end of the switch, a second end of the second switching unit is coupled to a second end of the switch; a first end of the first cell is coupled to the second end of the switch, a second end of the first cell is coupled to a first end of the first switching unit, and a second end of the first switching unit is coupled to the first end of the switch. |
| US11336101B2 |
Adaptive fast-charging of multi-pack battery system in a mobile platform having dual charge ports
A system for use with a direct current fast-charging (DCFC) station includes a controller and battery system. The battery system includes first and second battery packs, and first, second, and third switches. The switches have ON/OFF conductive states commanded by the controller to connect the battery packs in a parallel-connected (P-connected) or series-connected (S-connected) configuration. An electric powertrain with one or more electric machines is powered via the battery system. First and second charge ports of the system are connectable to the station via a corresponding charging cable. The first charge port receives a low or high charging voltage from the station. The second charge port receives a low charging voltage. When the station can supply the high charging voltage to the first charge port, the controller establishes the S-connected configuration via the switches, and thereafter charges the battery system solely via the first charge port. |
| US11336100B2 |
System and method for balancing state of charge of battery
A system and method for balancing a battery having a plurality of cells connected in series. The system includes a plurality of reactive charge transfer units connected with the plurality of cells, a first control unit and a second control unit. The first control unit is configured to determine a state of charge of the plurality of cells, determine a reference value associated with the battery, identify an overcharged cell or a discharged cell in the battery, and determine a charge differential between state of charge of the overcharged cell or the discharged cell and the reference value associated with the battery. The second control unit is configured to arrange charge transfer between the overcharged cell or the discharged cell, and remaining pack of cells in the battery. The first and the second control units are configured to function iteratively until cell balancing is attained. |
| US11336099B2 |
Photovoltaic system and control method therefor
A photovoltaic system and a control method therefor are disclosed. A photovoltaic system according to an embodiment of the present disclosure comprises: a solar cell array for converting solar energy into electric power; a power management device for monitoring the power generation amount of the solar cell array and the reverse power from an external power grid; an energy storage device charged by receiving the electric power produced by the solar cell array or the power of the external power grid; and a power control device for supplying, to the energy storage device, the electric power generated by the solar cell array or the power of the external power grid in response to a valid power command, wherein the power management device generates the valid power command which has different values according to whether the reverse power is generated by the external power grid. |
| US11336097B2 |
Wind power generation system with power storage device
A wind power generation system with a power storage device includes a wind power generation system, a power storage device system, and a reactive power controller. The wind power generation system includes a wind power generator, a first power conversion circuit, a first control circuit, a first filter capacitor, and a circuit breaker interposed between the first filter capacitor and a grid connection point. The wind power generation system is configured to output the electric power converted by the first power conversion circuit to an electric power grid via the grid connection point. The power storage device system includes a power storage device, a second power conversion circuit, and a second control circuit that controls the second power conversion circuit to perform load leveling operation. The reactive power controller causes the second power conversion circuit to perform reactive power compensation operation. |
| US11336094B2 |
Inverter, power generating system, and method for suppressing harmonic distortion of alternating current system
An inverter includes an inverter circuit; an alternating current filter, where an input port of the alternating current filter is connected to an output port of the inverter circuit; an alternating current electromagnetic interference (EMI) filter; and a first alternating current switch, connected between an output port of the alternating current filter and an input port of the alternating current EMI filter. The first split capacitor is disposed between the first alternating current switch and the input port of the alternating current EMI filter; and when the first alternating current switch is turned off, the first split capacitor is disconnected from the output port of the alternating current filter, and the first split capacitor is connected to a circuit in which an alternating current system connected to the output port of the alternating current EMI filter is located, to suppress harmonic distortion of the alternating current system. |
| US11336092B2 |
Multi-objective real-time power flow control method using soft actor-critic
Systems and methods are disclosed for control voltage profiles, line flows and transmission losses of a power grid by forming an autonomous multi-objective control model with one or more neural networks as a Deep Reinforcement Learning (DRL) agent; training the DRL agent to provide data-driven, real-time and autonomous grid control strategies; and coordinating and optimizing power controllers to regulate voltage profiles, line flows and transmission losses in the power grid with a Markov decision process (MDP) operating with reinforcement learning to control problems in dynamic and stochastic environments. |
| US11336086B2 |
Current limiting circuit for limiting the magnitude of an alternating current
A current-limiting circuit for limiting the magnitude of an alternating current. The circuit includes a coil unit and a capacitor unit, which are connected electrically in series, and a bypass device for electrically bridging the capacitor unit on occasion of an overcurrent. The bypass device has a first bypass branch and a second bypass branch connected electrically in parallel with the first bypass branch. A third bypass branch is connected electrically in parallel with a second bypass element of the second bypass branch. |
| US11336083B2 |
Power converter monitor and method of use
A power converter monitor having built-in fault tolerance and containment including a plurality of voltage inputs operatively connected to a pulse timing device, a respective comparator electrically connected to each of the voltage inputs, an and-gate electrically connected in series to each of the comparators and wherein the pulse timing device is operatively connected by the and-gate and a-not gate to each of the voltage inputs configured to reset a detected voltage output fault and provide a converter inhibit pulse if the voltage output fault is detected. |
| US11336081B2 |
Protection circuit for a medium voltage or high voltage transformer
A protection circuit is for a medium voltage or high voltage transformer and includes a sensing device, a measurement device, and a switching device. The sensing device is configured to be connected between a primary winding of a voltage transformer and ground potential. The measurement device is connected to the sensing device and the measurement device is configured to measure at least one parameter sensed by the sensing device. The protection circuit is configured to analyse the measured at least one parameter sensed by the sensing device. The protection circuit is configured to generate a trip signal based on the analysis of the measured at least one parameter sensed by the sensing device. The switching device is configured to receive the generated trip signal and disconnect the voltage transformer from a high voltage potential. |
| US11336080B1 |
Slotted grommet
Embodiments of a slotted grommet configured to manage a cable in an electrical cavity are provided. The slotted grommet includes a body structure having a first surface, a second surface opposite to the first surface, and a peripheral surface extending between the first and second surfaces. A first slot is formed in the first surface and extends through the body structure towards the second surface. The first slot defines a chamber having sidewalls in the body structure configured to hold a loop of the cable. The first slot has a first width that is less than a cross-sectional dimension of the cable such that the cable is pinched within the chamber between the first sidewalls to prevent vibration-related chafing of the cable. |
| US11336078B2 |
Semiconductor laser diode
A semiconductor laser diode is specified, the semiconductor laser diode includes a semiconductor layer sequence having an active layer which has a main extension plane and which, in operation, is adapted to generate light in an active region and to emit light via a light-outcoupling surface, the active region extending from a rear surface opposite the light-outcoupling surface to the light-outcoupling surface along a longitudinal direction in the main extension plane, the semiconductor layer sequence having a surface region on which a first cladding layer is applied in direct contact, the first cladding layer having a transparent material from a material system different from the semiconductor layer sequence, and the first cladding layer being structured and having a first structure. |
| US11336076B2 |
Apparatus for compensating parasitic impedance for integrated circuits
A laser diode driver circuit includes a first pair of contacts and connectors coupled to an anode of the laser diode. An inductance of each of the first pair of contacts and connectors is the same. A second pair of contacts and connectors are coupled to a cathode of the laser diode. An inductance of each of the second pair of contacts and connectors is the same. The laser diode driver circuit also includes current driving circuitry. |
| US11336075B2 |
Light emitting device and method of manufacturing light emitting device
A light emitting device comprises: a semiconductor laser element; a base portion comprising: a bottom portion on which the semiconductor laser element is located, and a frame portion comprising a step and surrounding the semiconductor laser element; and a light reflecting member disposed on the bottom portion of the base portion so as to lean against the step, the light reflecting member being configured to reflect light from the semiconductor laser element. |
| US11336073B2 |
Brillouin dynamic grating generation using dual-Brillouin-peak optical fiber
Disclosed herein is a method comprising injecting light of a first wavelength λ1 into a wavelength division multiplexer; injecting light of a second wavelength λ2 into the wavelength division multiplexer; combining the light of the first wavelength λ1 and the light of the second wavelength λ2 in the wavelength division multiplexer to produce light of a third wavelength λ3; and reflecting the light of the third wavelength λ3 in a dual-Brillouin peak optical fiber that is in communication with the wavelength divisional multiplexer; wherein the dual-Brillouin peak optical fiber has at least two Brillouin peaks, such that an amplitude A1 of at least one of said Brillouin peaks is within 50% to 150% of an amplitude A2 of another Brillouin peak 0.5A2≤A1≤1.5A2; wherein the dual-Brillouin peak optical fiber generates a Brillouin dynamic grating that reflects an improved back-reflected Brillouin signal of the combined light. |
| US11336072B2 |
Semiconductor optical device
A semiconductor optical device includes: a laser for emitting light; a modulator for modulating the light using an electroabsorption effect; a chip capacitor that is electrically connected in parallel to the laser; a chip inductor that is electrically connected in series to the chip capacitor, is electrically connected in series to the laser and the chip capacitor as a whole, and includes a first terminal and a second terminal; a solder or a conductive adhesive that directly bonds the first terminal of the chip inductor and the chip capacitor to each other; an electrical wiring group in which the laser, the modulator, the chip capacitor, and the chip inductor are electrically connected to each other; and a substrate on which the laser, the modulator, the chip capacitor, and the chip inductor are mounted. |
| US11336068B2 |
Crimping die device, crimping press and method for creating a crimp connection
A crimping die device (15) for a crimping press which includes a first movable pressing die (20), which is preferably essentially vertically movable, a first drive device (22), and the first drive device (22) comprises a first drive (23) as well as a base structure (17). Furthermore, a wedge flange (30) is present, which is movable and is connected to the first drive (23) of the first drive device (22). The invention furthermore relates to a crimping press with a crimping die device as well as a method for making a crimp connection with a crimping die device in a crimping press. |
| US11336063B2 |
Insert for connecting an electric connection to a wall, and protective cap for an insert
The invention relates to an insert for connecting an electric connection to a wall (10), having a pin (1) with a shaft (4), which has a first connection means (5), and an electrically conductive ring (2) with a through-opening (6) for receiving the pin (1), wherein the shaft (4) of the received pin (1) protrudes out of a contact surface (11) of the ring (2). For protection purposes while working, for example while painting, the insert comprises a protective cap (20, 20′) with a holding portion (21, 21′) comprising a second connection means (26), which can be connected to the first connection means (5) of the pin (1), and a flange section (22, 22′) which rests against the contact surface (11) of the ring (2) when the protective cap (20, 20′) is connected. |
| US11336062B2 |
Illuminated power strip assembly
An illuminated power strip assembly includes a housing with a top wall having opaque areas and translucent areas. A plurality of power outlets is mounted in the housing. A power cord extends outwardly from the housing and terminates with a male power plug. A power switch is mounted on the housing and is in electrical communication with the power outlets. A plurality of light emitters is mounted in the interior space and is in electrical communication with the power switch. The light emitters selectively emit different colors to be emitted through the translucent areas. A control circuit is electrically coupled to the light emitters and is actuated to select a color emitted by the light emitters. |
| US11336061B2 |
Switch construction
A switch assembly includes a switch and a connector. The switch and the connector are configured to interlock, wherein the switch includes a connection extending at least partially along a center axis of the switch, and the connection is configured to receive at least a part of the connector. The connection may include at least one slot and at least one wedge-shaped groove which is extending from the at least one slot and tapered in a direction of the center axis. The connector may include at least one corresponding wedge-shaped protrusion. The at least one corresponding wedge-shaped protrusion may include a resilient contact blade which can interlock with the at least one wedge-shaped groove. |
| US11336057B2 |
Electrical connector and electronic device
An electrical connector contains a first contact group arranged on a first contact plane, a second contact group arranged on a second contact plane and a ground plate located on a ground plane. The ground plate is located between horizontally extending portions of the contacts of the first contact group and horizontally extending portions, downwardly extending portions and terminal portions of the contacts of the second contact group in addition to between contacting portions and the horizontally extending portions of the contacts of the first contact group and contacting portions and the horizontally extending portions of the contacts of the second contact group. |
| US11336055B2 |
Locking clip for an electrical connector housing
An electrical connector housing is provided with at least one locking clip, which is mounted pivotably via a bearing pin and has a locking region and an actuation region. In order to reversibly lock the electrical connector housing to a mating electrical connector housing, the locking region engages overbearing journals integrally moulded on the mating electrical connector housing. The locking clip has a locking device or means for blocking the pivot movement of the locking clip. In this manner, an accidental release of the plug-in connection can be prevented. |
| US11336054B2 |
First housing with two connector ports selectively connected to electrical connector on second housing
A connector device is provided, including a first housing, a circuit assembly, a second housing, and a connector. The circuit assembly is disposed on the first housing, and has a first connecting port and a second connecting port. The second housing is detachably engaged with the first housing. The connector is disposed on the second housing, and has an opening and a terminal. When the first housing is engaged with the second housing and the opening faces the first direction, the terminal is electrically connected to the first connecting port. When the first housing is engaged with the second housing and the opening faces the second direction, the terminal is electrically connected to the second connecting port. The first direction is different from the second direction. |
| US11336051B1 |
Header seal for header connector of power connector system
A header connector includes a header housing having a mating end and a mounting end. The mounting end is configured to be mounted to a supporting structure. The header housing has shroud walls forming a header chamber configured to receive a plug connector. The header connector includes a header seal coupled to the header housing having an upper portion with an upper sealing surface and a lower portion with a lower sealing surface. The upper portion extends into the header chamber and the upper sealing surface is configured to interface with the plug connector to form a seal between the header housing and the plug connector. The lower portion extends to the mounting end and the lower sealing surface is configured to interface with the supporting structure to form a seal between the header housing and the supporting structure. |
| US11336039B2 |
Connector for printed circuit board and battery system comprising printed circuit board and connector
The present invention relates to a battery system including a battery module configured to include a plurality of rechargeable battery cells, a housing configured to house the battery module, a printed circuit board disposed on the battery module to include a first surface that faces the battery module and a second surface that is opposite to the first surface, and a connector configured to connect the printed circuit board and an external electrical component, wherein the printed circuit board includes a plurality of bent terminal portions disposed on the second surface, and the connector includes a plurality of metal clamps that are respectively connected to the plurality of bent terminal portions of the printed circuit board. In the battery system of the present invention, the connection between the connector and the printed circuit board can be realized without soldering wires. |
| US11336035B2 |
Clamping spring for a screwless connection terminal
A clamping spring for a screwless connection terminal for clamping a conductor, has a clamping limb, a contact limb, and a tensioning limb, the tensioning limb being connected to the clamping limb and the contact limb, and the clamping limb and the contact limb being designed as intersecting limbs. In the clamping limb, a clamping opening is provided, through which the contact limb extends, such that the contact limb is in contact with an edge of the clamping opening remote from the tensioning limb in a pretensioned manner and an exposed wire end of a conductor can be clamped with the contact limb onto a contact surface of a contact element of a screwless connection terminal. Furthermore, the clamping limb has a clamping extension having a clamping surface. The clamping extension, starting from the free end of the clamping limb remote from the tensioning limb, initially extends away from the tensioning limb, then extends back in the direction of the tensioning limb in a substantially curved form, and finally is oriented in the direction of the contact limb. |
| US11336033B2 |
Socket for shielded connector
The invention concerns a connector-type socket comprising: —a body suitable for being connected via a front face to a complementary plug comprising a plurality of insulation-displacement contacts oriented in the same direction; —a separate connection module comprising a plurality of positions each intended to receive one end of a strand of a cable comprising shielding, the module being arranged in such a way as to be inserted into the body so as to bring each strand against the corresponding insulation-displacement contact; the socket being characterised in that the body comprises two separate parallel plates, each plate comprising a row of contacts, each row of contacts being arranged in a plane (P), the planes (P) containing the rows being separate from and parallel to each other such that all the strands of the cable can be connected in a single movement. |
| US11336032B2 |
Reactive array
Methods and apparatus for providing a radiator having an antenna comprising a patch antenna layer and a first ground plane layer, wherein the antenna has a reactive field region of the radiator between the patch antenna layer and the first ground plane layer, and an integrated circuit located in the active region. |
| US11336018B2 |
Antenna
An antenna includes: a dielectric layer including a first and second surface placed in layering; a ring-shaped conductor layer formed on the first surface; a first and second feedline that are closer to the first surface than the second, and are formed at positions different from those of the surfaces; a reference potential conductor layer formed on the second surface; and a conductor pin located in the inner diameter of the ring-shaped conductor layer in planar view from the direction of the layering, that is connected to the reference potential conductor layer. In the planar view, the first and second feedlines include portions overlapping with the ring-shaped conductor layer, and the extending directions of the feedlines intersect with each other. The ring-shaped conductor layer is connected to neither the reference potential conductor layer nor the conductor pin, and neither the first nor second feedline is connected to the conductor pin. |
| US11336016B2 |
Cavity supported patch antenna
An antenna (100) comprises a cavity (120) formed by a conductive plate (121) in a first horizontal conductive layer (221) of a multi-layer circuit board and a vertical sidewall formed by conductive vias (222) extending from the conductive plate (121). Further, the antenna (100) comprises an antenna patch (130) arranged in the cavity. The antenna patch (130) is formed in a second conductive layer (223) of the multi-layer circuit board and is peripherally surrounded by the vertical sidewall of the cavity (120). |
| US11336015B2 |
Antenna boards and communication devices
Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna board may include: a substrate including an antenna feed structure; an antenna patch, wherein the antenna patch is a millimeter wave antenna patch; and an air cavity between the antenna patch and the substrate. |
| US11336009B2 |
Array antenna device and communication device
An array antenna device includes a classifying unit that classifies rotating devices into a plurality of groups with different priorities under the condition that the number of rotating devices included in one group is equal to or less than the number of rotating devices that is calculated by a number-of-drivable-devices calculating unit; and a rotation instructing unit that selects groups in descending order of priority from among the plurality of groups and drives, each time one group is selected, all rotating devices included in the group, and the classifying unit performs the classification in such a manner that, among the rotating devices, a rotating device that rotates an element antenna with a higher importance level is classified into a group with a higher priority. |
| US11336007B1 |
Multi-band integrated antenna arrays for vertical lift aircraft
A system of antennas, each having disparity operating frequencies, are incorporated into the same aircraft body panels. HF antennas define loops with large internal areas; additional higher frequency antennas are disposed within that large internal area. The higher frequency antennas are sufficiently different so as to prevent coupling. Antennas operating in the same frequency range, disposed on different parallel surfaces are operated in concert as a steerable array. |
| US11336006B2 |
Isolating antenna array component
A communication device includes two antennas operational within a first frequency range in the communication device. An integrated isolating antenna array component is positioned between the two antennas in the communication device to reduce radiofrequency coupling between the two antennas. The integrated isolating antenna array component includes an interconnection substrate and an antenna array adjacent to the interconnection substrate and including one or more radiating elements. The antenna array is configured to drive the one or more radiating elements within a second frequency range in the communication device. The second frequency range is higher than the first frequency range. The integrated isolating antenna array component also includes an isolator affixed to the interconnection substrate and configured to be connected to electrical ground. The isolator is configured to reduce the radiofrequency coupling between the two antennas within the first frequency range. |
| US11336002B2 |
Antenna and electronic device including the same
An electronic device is provided. The electronic device includes a housing having an inner space. The electronic device may further include an antenna structure disposed in the inner space of the housing and including a printed circuit board (PCB) having a first board surface facing a first direction, a second board surface facing a second direction opposite to the first direction, and a lateral board surface surrounding a space between the first and second board surfaces, a first antenna array disposed in the space between the first and second board surfaces and forming a beam pattern in a third direction that the lateral board surface faces, and a second antenna array disposed at a position spaced apart from the first antenna array and forming a beam pattern in the first direction. |
| US11336000B2 |
Filter antenna
The present invention provides a filter antenna including a first resonant cavity and a second resonant cavity which are stacked from top to bottom and in coupling communication with each other, an antenna unit provided on a side of the first resonant cavity facing away from the second resonant cavity, and a feed structure provided in the second resonant cavity. The present invention integrates a filter with an antenna to ensure the performance of the filter antenna by using a SIW cavity filter, thereby effectively suppressing interference from out-of-band spurious signals. In addition, the stacking structure of the antenna and the filter effectively reduces a volume to achieve miniaturization, and the antenna structure is optimized in a compact environment. |
| US11335994B2 |
System and method for dynamic multi-transmit antenna and proximity sensor reconfiguration for a multi-radio-access-technology multi-mode device
An information handling system (IHS) may include a configuration sensor for sensing a physical configuration of the IHS, a first proximity sensor probe for sensing whether a first biological entity element is proximate to a first antenna, a second proximity sensor probe for sensing whether a second biological entity element is proximate to a second antenna, and a third proximity sensor probe for sensing whether a third biological entity element is proximate to a third antenna. The IHS is adapted to reconfigure use of at least two of the first antenna, the second antenna, and the third antenna in response to the sensing of at least one of the first proximity sensor probe, the second proximity sensor probe, and the third proximity sensor. |
| US11335991B2 |
Electronic device with radio-frequency module
A radio-frequency device includes a radio-frequency module. The radio-frequency module includes a first substrate, a second substrate, a radio-frequency integrated circuit (RFIC), a front-end integrated circuit (FEIC), and a flexible substrate. The RFIC has at least a portion surrounded by a first core member and is configured to input or output a base signal and a first radio-frequency (RF) signal having a frequency higher than a frequency of the base signal. The FEIC has at least a portion surrounded by a second core member and is configured to input or output the first RF signal and a second RF signal having a power different from a power of the first RF signal. The flexible substrate is configured to connect the first and second substrates to each other, provide a transmission path for the first RF signal, and being more flexible than the first and second substrates. |
| US11335988B2 |
Automated feed source changer for a compact test range
A mechanical means for deploying one of two or more feed sources within a test range is presented. The feed source selected for testing is properly positioned for use within the range by rotating one of two or more arms to an upright and locked position. An arm may further include a rotatable antenna wheel with two or more feed sources thereon whereby a selected feed source is rotated into position via the antenna wheel. The antenna wheel includes a center body, feed sources attached to the center body and aligned along a rotational plane, and a shroud disposed about the center body and feed sources. The antenna wheel may include a cooling system for managing heat generated by the feed sources and electronics therefore. In preferred embodiments, the feed source changer is mounted within the range so that a selected feed source communicates an emitted beam onto a reflector which is redirected as a reflected beam toward a device under test. Concealment panel(s) may be positioned adjacent to the feed source changer to minimize electromagnetic reflections therefrom. |
| US11335984B2 |
Dielectric waveguide filter
Provided is a dielectric waveguide filter that includes a dielectric main body. A plurality of isolation slots and frequency tuning blind holes are provided in the dielectric main body. At least two port signal transmission holes are further provided in the dielectric main body. The at least two port signal transmission holes and at least part of the plurality of frequency tuning blind holes are disposed on two opposite sides of the dielectric main body. In a thickness direction of the dielectric main body, the at least two port signal transmission holes do not overlap with the at least part of the plurality of frequency tuning blind holes. The dielectric waveguide filter according to embodiments of this disclosure achieves miniaturization while improving out-of-band rejection capability. |
| US11335980B2 |
Flexible battery
A flexible battery may include: an electrode assembly having one or more unit cells each of the unit cells including a pair of electrode plates having different polarities, a separator interposed between the respective electrode plates and electrode tabs that protrude from the respective electrode plates; a pair of electrode leads connected to electrode tabs; and a strengthening tab fixed on any one electrode lead connection tab among the electrode tabs. |
| US11335978B2 |
Secondary battery and battery module
The disclosure relates to a secondary battery and a battery module. The secondary battery comprises: a case comprising a receiving hole having an opening; a cap assembly sealingly connected with the case to close the opening; an electrode assembly disposed in the receiving hole, wherein the electrode assembly comprises two end surfaces opposite to each other in a first direction perpendicular to an axial direction of the receiving hole and tabs extending from respective end surfaces, and the electrode assembly comprises two or more electrode units which are stacked in the axial direction; and a current collecting unit comprising a first sheet and a first current collecting sheet connected to the first sheet, wherein both the first sheet and the first current collecting sheet extend in the axial direction, and the tab is bent with respect to the first direction and is electrically connected to the first current collecting sheet. |
| US11335977B1 |
Inter-cell connection materials
Batteries according to embodiments of the present technology may include a first battery cell including a first current collector. The batteries may include a second battery cell including a second current collector. The second battery cell may be vertically aligned with the first battery cell, and the second current collector may be positioned adjacent the first current collector. The first battery cell and the second battery cell may be electrically coupled together so the first battery cell and the second battery cell transfer current through the cells between the first current collector and the second current collector. The batteries may also include a patterned coupling material disposed between the first battery cell and the second battery cell and joining the first current collector with the second current collector. |
| US11335975B1 |
Proton selective membranes based on two dimensional materials
Proton conductive membrane includes a proton selective layer of 80-100% carbon with sp2 hybridization having a thickness of 0.3-100 nm, with 0-20% of hydrogen, oxygen, nitrogen and sp3 carbon; wherein the sp2 carbon is in a form of graphene-like material; the proton selective layer having a plurality of pores formed by any of 7, 8, 9 or 10 sp2 carbon cycles or a combination thereof, with the pores having an effective diameter of up to 0.6 nm; an ionomeric polymer layer on the proton selective layer. Total thickness of the proton conductive membrane is less than 50 microns. The ionomeric polymer is PFSA (perfluorinated sulfonic acid), PVP (polyvinylpyrrolidone) or PVA (poly vinyl alcohol) with iodide or bromide counterion dissolved inside. The graphene-like material is CVD graphene or reduced graphene oxide (rGO). A D to G Raman band ratio of the membrane is more than 0.1. |
| US11335970B2 |
Battery pack provided with degassing flow channel
A battery pack includes a pack case configured to accommodate a cell module assembly in an inner space thereof and having an opening formed at one side, and a pack cover having a degassing port communicating with the inner space and configured to cover the opening of the pack case. The cell module assembly includes a cell fixing frame having an upper plate and a lower plate respectively disposed at an upper portion and a lower portion of the cell stack and in surface contact with an upper wall and a lower wall of the pack case. At least one of the upper plate and the lower plate includes at least one gas moving route formed by concavely depressing one surface in contact with the upper wall or the lower wall of the pack case along a path toward the degassing port, and at least one hole. |
| US11335965B2 |
Heating device for a prismatic battery cell of a high-voltage battery of a motor vehicle, battery cell, battery module, high-voltage battery and motor vehicle
A heating device for a prismatic battery cell of a high-voltage battery of a motor vehicle includes two sheet-shaped heating elements to be arranged on two opposite lateral outer sides of a cell housing of the battery cell, and two connecting elements to be arranged on a housing cover of the cell housing. The connecting elements are electrically connected to terminals of the two heating elements. The connecting elements are flexibly formed, at least in certain regions, and as a result the heating elements are connected in a hinge-like manner. The heating device can be arranged by arranging the first heating element on the first lateral outer side of the cell housing, swinging the second heating element over the housing cover, and arranging the second heating element on the second lateral outer side on the cell housing. |
| US11335963B2 |
Traction battery packs with second tier integrated supporting, thermal, and sealing structures
This disclosure details exemplary battery pack designs, such as those designed for use within electrified vehicles. Exemplary battery packs may include an enclosure assembly and a plurality of battery arrays housed inside the enclosure assembly. The enclosure assembly may include a mid-tray that is configured for supporting, cooling/heating, and sealing second tier battery arrays. The configuration of the mid-tray allows coolant joints to be eliminated inside of the battery pack. |
| US11335962B2 |
Electrodes and process for reconditioning contaminated electrode materials for use in batteries
A polymer derived ceramic precursor is selected and mixed with a contaminated recycled electrode material or materials. The mixture is pyrolyzed to form a ceramic or ceramic-carbon composite, reduced to a powder and formed into an electrode of a battery, such as a lithium ion battery. |
| US11335955B2 |
Non-aqueous electrolyte for lithium ion secondary battery and lithium ion secondary battery using same
A non-aqueous electrolyte for a lithium ion secondary battery capable of improving rate characteristics, and the lithium ion secondary battery using the same. The non-aqueous electrolyte for the lithium ion secondary battery includes a carboxylic acid ester and 2.0×10−6 to 3.0×10−3 mol/L of halide ion other than fluoride ion. |
| US11335953B2 |
Electrolyte for lithium secondary battery and lithium secondary battery including the same
Provided are an electrolyte for a secondary battery including a lithium salt, a nonaqueous organic solvent, and a difluorophosphite olefin compound, and a lithium secondary battery including the same. |
| US11335952B2 |
Lithium battery
A lithium battery includes a cathode including a cathode active material, an anode including an anode active material, and an organic electrolytic solution between the cathode and the anode, wherein the organic electrolytic solution includes a first lithium salt, a second lithium salt, an organic solvent, and a bicyclic sulfate-based compound represented by Formula 1 below: wherein, in Formula 1, each of A1, A2, A3, and A4 is independently a covalent bond, a substituted or unsubstituted C1-C5 alkylene group, a carbonyl group, or a sulfinyl group, in which both A1 and A2 are not a covalent bond and both A3 and A4 are not a covalent bond. The second lithium salt includes at least one selected from LiCF3SO3, Li(CF3SO2)2N, LiC4F9SO3, Li(FSO2)2N, and LiN(CxF2x+1SO2)(CyF2y+1SO2) where 2≤x≤20 and 2≤y≤20. |
| US11335949B2 |
Battery including a sulfide barrier coating
Provided is a lithium-conductive solid-state electrolyte material that comprises a sulfide compound of a composition that does not deviate substantially from a formula of Li9S3N. The compound's conductivity is greater than about 1×10−7 S/cm at about 25° C. and is in contact with a negative electroactive material. Also provided is an electrochemical cell that includes an anode layer, a cathode layer, and the electrolyte layer between the anode and cathode layers. In an example, the material's activation energy can be no greater than about 0.52 eV at about 25° C. |
| US11335947B2 |
Polymer electrolyte composition including perfluorinated ionomer and inorganic additive and lithium secondary battery including the same
The present invention relates to a composition for a polymer electrolyte and a lithium secondary battery using the same, and particularly, to a composition for a polymer electrolyte which includes a single ion-conductive polymer including a unit represented by Chemical Formula 1; and at least one additive selected from the group consisting of a ceramic electrolyte and inorganic particles, wherein a weight ratio of the single ion-conductive polymer:the additive(s) is 1:0.1 to 1:9, and a lithium secondary battery which exhibits an improvement in cell performance by including the same. |
| US11335946B2 |
Shape-conformable alkali metal-sulfur battery
Provided is an alkali metal-sulfur cell comprising: (a) a quasi-solid cathode containing about 30% to about 95% by volume of a cathode active material (a sulfur-containing material), about 5% to about 40% by volume of a first electrolyte containing an alkali salt dissolved in a solvent and an ion-conducting polymer dissolved, dispersed in or impregnated by a solvent, and about 0.01% to about 30% by volume of a conductive additive wherein the conductive additive, containing conductive filaments, forms a 3D network of electron-conducting pathways such that the quasi-solid electrode has an electrical conductivity from about 10−6 S/cm to about 300 S/cm; (b) an anode; and (c) an ion-conducting membrane or porous separator disposed between the anode and the quasi-solid cathode; wherein the quasi-solid cathode has a thickness from 200 μm to 100 cm and a cathode active material having an active material mass loading greater than 10 mg/cm2. |
| US11335944B2 |
Secondary battery charging/discharging device
A charging and discharging apparatus for performing an activation process of a secondary battery including a plurality of compression plates spaced apart from each other by a predetermined distance to form a cell insert space into which a secondary battery cell is inserted, the plurality of compression plates moving to reduce the separated distance to press a body of the secondary battery cell; a slip sheet having a sheet shape and formed to include attachment portions attached to top ends of the compression plates and a folding portion formed by folding a region between the attachment portions to be interposed in the cell insert space; and a slip sheet fixing unit provided to be attached to and detached from the top end of the compression plate in a fitting and releasing manner in a state where the attachment portions of the slip sheet are interposed therein is provided. |
| US11335940B2 |
Fuel cell stack
A fuel cell stack includes an endplate assembly having a structural endplate. An insulator plate has a second exterior surface contacting a first interior surface of the structural endplate and a second interior surface on an opposite side of the insulator plate. A third plate has a third exterior surface contacting the second interior surface and a third interior surface on an opposite side of the third plate relative to the insulator plate. The third interior surface and third exterior surface are substantially flat. The second interior surface and the third exterior surface contact each other substantially continuously in a longitudinal direction and a lateral direction, and are flat and substantially parallel to each other. The second exterior surface is contoured such that the second exterior surface is not flat and is substantially non-parallel relative to the third interior surface. |
| US11335934B2 |
Assembly comprising a SOEC/SOFC-type solid oxide stack and a clamping system with an integrated gas superheating system
An assembly comprising a SOEC/SOFC-type solid oxide stack, and a clamping system for the stack. The assembly further comprises a system for superheating the gases at the inlet of the stack, comprising: a heating plate integrated within the thickness of at least one of the upper and lower clamping plates of the clamping system; an upper or lower end plate for superheating the gases, comprising a circuit through which the gases to be heated flow; and an inlet duct for the gases to be heated. |
| US11335931B2 |
Highly ion-selective composite polymer electrolyte membranes comprising metal-ion blocking layer, redox flow batteries comprising the same, and electrochemical devices comprising the same
Disclosed is a composite polymer electrolyte membrane comprising: a support membrane; a metal ion-blocking layer stacked on the support membrane; a stabilization layer; and a protecting layer, wherein the support membrane includes a cation conductive polymer. |
| US11335930B2 |
Fuel cell system and method for operating the same
A fuel cell system includes a fuel feeder that supplies fuel, a fuel cell stack that generates power through an electrochemical reaction using air and a hydrogen-containing gas generated from the fuel, a first temperature sensor that senses the temperature of the fuel cell stack, and a controller. The fuel cell stack has a membrane electrode assembly including an electrolyte membrane through which protons can pass, a cathode on one side of the electrolyte membrane, and an anode on the other side of the electrolyte membrane. The controller defines an upper limit of current output from the fuel cell stack on the basis of the temperature of the fuel cell stack, the supply of the fuel, and the hydrogen consumption of the fuel cell stack associated with internal leakage current and keeps the current output from the fuel cell stack at or below the upper limit. |
| US11335919B2 |
Selectively rotated flow field for thermal management in a fuel cell stack
An electrochemical cell stack comprises a plurality of electrochemical cell units, each comprising a cathode, an anode, and an electrolyte, and also comprises a plurality of interconnects. An interconnect is disposed between adjacent electrochemical cell units and defines a longitudinal channel having circumferential corrugations defined therearound. A fuel channel is defined between each anode and a respective adjacent interconnect, the fuel channel having fuel inlet and outlet. An oxidant channel is defined between each cathode and a respective adjacent interconnect, the oxidant channel having an oxidant inlet and outlet. The plurality of electrochemical cell units and interconnects include a first electrochemical cell unit, a first interconnect adjacent the first electrochemical cell unit, a second electrochemical cell unit adjacent the first interconnect, and a second interconnect adjacent the second electrochemical cell unit. The second interconnect is rotationally offset from the first interconnect about a longitudinal axis of the fuel cell stack. |
| US11335916B2 |
Liquid reserve batteries for low temperature activation and performance in munitions
A liquid reserve battery including: a collapsible storage unit having a collapsible cavity for storing a liquid electrolyte therein; and a battery cell in communication with an outlet of the collapsible storage unit, the battery cell having gaps dispersed therein. Wherein the collapsible storage unit includes: a top plate having three or more first sides; a bottom plate having three or more second sides, each of the three or more first sides being angularly offset from a corresponding one of the three or more second sides about a central axis, the top plate being linearly offset from the bottom plate in a longitudinal direction along the central axis; and for each of the three of more first sides, first and second triangular sidewalls connecting the top plate bottom plate and each other. |
| US11335913B2 |
Method for manufacturing solid oxide cell having three-dimensional ceramic composite interface structure
The present invention presents a method for manufacturing a negative electrode of a solid oxide cell in a three-dimensional structure by using a pressurization process. In addition, the present invention proposes a structure in which the entire interface of a solid oxide cell is manufactured on the manufactured three-dimensional negative electrode substrate, through various deposition methods, in a three-dimensional structure so as to maximize a reaction area. |
| US11335912B2 |
Decorative ring
A decorative ring includes a body having a hollow tubular structure and defining a body space. A plurality of electrical energy generating elements is located in the body space and spaced apart from each other. The body space is divided into a plurality of sub-body spaces separated from each other. Each of plurality of electrical energy generating elements includes a first porous electrode, an eggshell membrane, and a second porous electrode stacked on each other in that order. A light emitting element is located on the body and electrically connected to one of the plurality of electrical energy generating elements. A liquid having positive ions and negative ions in the body space. |
| US11335909B2 |
Negative electrode active material for electrochemical device, negative electrode including the negative electrode active material and electrochemical device including the same
A negative electrode active material for an electrochemical device which has improved quick charging characteristics. The negative electrode active material includes two types of graphite particles having a different particle diameter and shows a bimodal distribution, wherein the ratio of the average particle diameter (D50) of the first graphite particles to the average particle diameter (D50) of the second graphite particles is larger than 1.7. |
| US11335907B2 |
Positive electrode materials having a superior hardness strength
A powderous positive electrode material for a lithium secondary battery has the general formula Li1+x[Ni1−a−b−cMaM′bM″c]1−xO2−z. M is one or more elements of the group Mn, Zr and Ti. M′ is one or more elements of the group Al, B and Co. M″ is a dopant different from M and M′, and x, a, b and c are expressed in mol with −0.02≤x≤0.02, 0≤c≤0.05, 0.10≤(a+b)≤0.65 and 0≤z≤0.05. The material has an unconstrained cumulative volume particle size distribution value (Γ0(D10P=0)), a cumulative volume particle size distribution value after having been pressed at a pressure of 200 MPa (ΓP(D10P=200)) and a cumulative volume particle size distribution value after having been pressed at a pressure of 300 MPa (ΓP(D10P=300)). When ΓP(D10P=200) is compared to Γ0(D10P=0), the relative increase in value is less than 100%. When ΓP(D10P=300) is compared to Γ0(D10P=0), the relative increase in value is less than 120%. |
| US11335905B2 |
Negative electrode active material, mixed negative electrode active material, and method of producing negative electrode active material
A negative electrode active material particle including: a silicon compound particle containing a silicon compound that contains oxygen, wherein the silicon compound particle contains a Li compound; and the negative electrode active material particle including aluminum phosphorous composite oxide attached to at least part of the surface, wherein the aluminum phosphorous composite oxide is a composite of P2O5 and Al2O3, and the P2O5 and the Al2O3 are in a mass ratio in a range of 1.2 |
| US11335903B2 |
Highly efficient manufacturing of silicon-carbon composites materials comprising ultra low z
Silicon-carbon composite materials and related processes are disclosed that overcome the challenges for providing amorphous nano-sized silicon entrained within porous carbon. Compared to other, inferior materials and processes described in the prior art, the materials and processes disclosed herein find superior utility in various applications, including energy storage devices such as lithium ion batteries. |
| US11335901B2 |
Negative active material for lithium secondary battery, manufacturing method thereof and lithium secondary battery including the same
Provided are a negative active material for a lithium secondary battery, a manufacturing method thereof, and a lithium secondary battery including the same, and the present invention may provide a negative active material for a lithium secondary battery including a secondary particle in which a plurality of silicon nanoparticles are aggregated; and a plurality of metal particles distributed in pores in the secondary particle, a manufacturing method thereof, and a lithium secondary battery including the same. |
| US11335895B2 |
Micro-capsule type silicon-carbon composite negative electrode material and preparing method and use thereof
The present invention discloses a micro-capsule type silicon-carbon composite negative electrode material, and the negative electrode material comprises a current collector and a silicon-carbon coating layer formed by drying silicon-carbon paste coating the current collector; the silicon-carbon slurry comprises a carbonaceous paste and silicon capsule powder dispersed in the carbonaceous paste; the carbonaceous paste comprises a dispersing agent, and a carbon material, a first conductive agent and a first binder dispersed in the dispersing agent; the silicon capsule powder has micro-capsule structures comprising silicon powder and a second binder coating the surface of the silicon powder and in which the silicon powder is a core and the second binder is an outer shell; and the first binder is different from the second binder. The improved silicon-carbon composite negative electrode material of the present disclosure has excellent effects in cycle performance, coulombic efficiency and rate capability. |
| US11335892B2 |
Organic layer deposition apparatus and method of manufacturing organic light-emitting display apparatus using the same
An organic layer deposition apparatus and a method of manufacturing an organic light-emitting display device by using the apparatus. In particular, an organic layer deposition apparatus that is more easily manufactured and is suitable for use in mass production of large substrates while performing high-definition patterning thereon, as well as a method of manufacturing an organic light-emitting display device by using such an apparatus. |
| US11335889B2 |
Organic light emitting diode display and method for manufacturing the same
An organic light emitting diode (OLED) display including: a substrate; an organic light emitting diode formed on the substrate; a metal oxide layer formed on the substrate and covering the organic light emitting diode; a first inorganic layer formed on the substrate and covering the organic light emitting diode; a second inorganic layer formed on the first inorganic layer and contacting the first inorganic layer at an edge of the second inorganic layer; an organic layer formed on the second inorganic layer and covering a relatively smaller area than the second inorganic layer; and a third inorganic layer formed on the organic layer, covering a relatively larger area than the organic layer, and contacting the first inorganic layer and the second inorganic layer at an edge of the third inorganic layer. |
| US11335886B2 |
Display device and method of manufacturing display device
A display device includes a display panel including a display region, a terminal region provided with a terminal, and a bending region located between the display region and the terminal region and capable of bending, the terminal region being located on a rear surface side opposite to a display surface side with respect to the display region based on the bending region bent and a protective coating provided on the display surface side of the bending region. When a direction in which the display region, the bending region, and the terminal region are arranged is defined as a first direction and a direction crossing the first direction is defined as a second direction, the bending region includes a bank portion located in the second direction with respect to the protective coating, projecting to the display surface side, and extending in the first direction. |
| US11335884B2 |
Method for manufacturing display device having flexibility
A display device comprises an organic EL substrate including an organic EL layer formed on a flexible substrate and a first main surface of the flexible substrate; a film covering a display region of the organic EL substrate; and a terminal region arranged at an end portion of the organic EL substrate, and arranged adjacent to and apart from an end portion of the film. The end portion of the film may have a taper region. A thickness of the taper region increases with distance from the terminal region in a cross-sectional view. A width of the taper region may be 0.5 times or more and 1.5 times or less of the film thickness in a plan view. |
| US11335878B2 |
Window member for display device, display device, and manufacturing method for display device
A display device includes a display module and a window member disposed on the display module, where the window member includes a base layer and a hard coating layer disposed on the base layer. A moisture absorption ratio of the window member is about 2.2% or greater under a first condition including a first temperature and a first humidity. The first temperature is about 60° C. or greater, and the first humidity is about 70% or greater. |
| US11335874B2 |
Quantum dot color filter substrate, fabricating method thereof, and display panel
A quantum dot color filter substrate, a manufacturing method thereof, and a display panel are provided. The quantum dot color filter substrate includes a quantum dot layer and a light-guiding encapsulation film. The quantum dot layer includes a plurality of light-guiding films arranged in an array and a black matrix disposed among the light-guiding films. A plurality of light-guiding grooves are defined on an illuminated surface of each of the light-guiding films. A light-guiding encapsulation film includes a package body disposed on a side of the quantum dot layer adjacent to the light-guiding grooves and a plurality of light-guiding protrusions extending from the package body and filled into the light-guiding grooves. |
| US11335869B2 |
Display device and method of manufacturing the display device
A method of manufacturing a display device includes providing an inorganic layer on a carrier substrate, providing a first flexible substrate on the inorganic layer, providing a first shielding layer including a metal on the first flexible substrate, providing a first barrier layer on the first shielding layer, and providing a thin film transistor layer on the first barrier layer. The inorganic layer includes at least one material selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy), and a thickness of the inorganic layer is in a range from about 10 Å to about 6000 Å. |
| US11335863B2 |
Compound, display panel and display apparatus
A compound, having a structure represented by Formula (I), in which L is selected from the group consisting of a substituted or unsubstituted phenyl, a substituted or unsubstituted naphthyl, a substituted or unsubstituted pyridyl, a substituted or unsubstituted pyrimidinyl, and a substituted or unsubstituted pyrazinyl; and D is an electron donor and is selected from the group consisting of a substituted or unsubstituted phenyl, biphenyl, naphthyl, anthryl, phenanthryl, acenaphthylenyl, pyrenyl, perylenyl, fluorenyl, spirobifluorenyl, chrysenyl, benzophenanthrenyl, benzanthracenyl, fluoranthenyl, picenyl, furyl, benzofuryl, dibenzofuryl, thienyl, benzothienyl, dibenzothiophenyl, phenoxazinyl, phenazinyl, phenothiazinyl, thianthrenyl, carbazolyl, acridinyl, and diarylamino. The compound according to the present disclosure has the TADF property, and the triplet excitons, which are blocked in molecular transition of the conventional fluorescent material, can be used to emit light, thereby improving the efficiency of device. |
| US11335860B2 |
Organic electroluminescence device and condensed cyclic compound for organic electroluminescence device
An organic electroluminescence device of an embodiment includes a first electrode and a second electrode facing each other, and at least one organic layer disposed between the first electrode and the second electrode, wherein at least one organic layer includes a condensed cyclic compound represented by Formula 1, thereby showing improved device efficiency and life. |
| US11335856B2 |
Display device and fabricating method of the same
A display device includes a display area, a test pad, a plurality of first test transistors, and at least one outline. The display area includes pixels coupled to data lines and scan lines. The test pad receives a test signal. The first test transistors are coupled between the data lines of the display area and the test pad. The at least one outline is coupled between one of the first test transistors and the test pad. The at least one outline is located in a non-display area outside the display area. |
| US11335855B2 |
Method for patterning a coating on a surface and device including a patterned coating
An opto-electronic device includes: a first electrode; an organic layer disposed over the first electrode; a nucleation promoting coating disposed over the organic layer; a nucleation inhibiting coating covering a first region of the opto-electronic device; and a conductive coating covering a second region of the opto-electronic device. |
| US11335853B2 |
Method of manufacturing OTS device, and OTS device
A method of manufacturing an OTS device of the invention is a method of manufacturing OTS device including a first conductor, an OTS portion made of chalcogenide, and a second conductor which are layered in order and disposed on an insulating substrate. The manufacturing method includes: a step D of forming a resist so as to coat part of an upper surface of the second conductor; a step E of dry etching a region which is not coated with the resist; and a step F of ashing the resist. In the step E, the second conductor, all of the OTS portion, and an upper portion of the first conductor are removed by an etching treatment once in a depth direction of the region. |
| US11335852B2 |
Resistive random access memory devices
The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a dielectric layer having an opening, sidewalls along the opening, a first electrode in the opening, a resistive layer disposed upon the first electrode, an oxygen scavenging layer disposed upon the resistive layer, and a second electrode in contact with the oxygen scavenging layer. The oxygen scavenging layer includes a material that is different from the resistive layer and partially covers the resistive layer. The first electrode is electrically linked to the second electrode by the oxygen scavenging layer and the resistive layer. |
| US11335850B2 |
Magnetoresistive random-access memory device including magnetic tunnel junctions
A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first free layer, forming a first tunnel barrier layer on the free layer, forming a reference layer on the first tunnel barrier layer, forming a second tunnel barrier layer on the reference layer, and forming a second free layer on the second tunnel barrier layer. An area of the second free layer is less than an area of the first free layer. Also, the first free layer, the first tunnel barrier layer and the reference layer are a first magnetic tunnel junction, and the reference layer, the second tunnel barrier layer and the second free layer are a second magnetic tunnel junction. |
| US11335849B2 |
Magnetic domain wall displacement type magnetic recording element and magnetic recording array
A magnetic domain wall displacement type magnetic recording element which comprises: a first magnetization fixed part which is stacked in a first direction, a magnetic recording layer which includes a magnetic domain wall and extends in a second direction which crosses with the first direction, a non-magnetic layer which is provided between the first magnetization fixed part and the magnetic recording layer, and a first via part which is electrically connected to the magnetic recording layer, wherein at least a part of the first via part is located at a position which is apart from the first magnetization fixed part in the second direction in planar view observed from the first direction, the magnetic recording layer includes a first part which has a position where the first magnetization fixed part overlaps with the magnetic recording layer in planar view observed from the first direction, and a width of the first via part in a third direction which is orthogonal to the second direction is larger than a width of said position of the first part of the magnetic recording layer. |
| US11335848B2 |
Production of lead-free piezoceramics in aqueous surroundings
The invention relates to a method for producing ceramics having piezoelectric properties in predominantly aqueous suspending agents. |
| US11335843B2 |
Semiconductor device package
A semiconductor device package includes a resin unit having a first through hole and a second through hole, a conductive body disposed on the resin unit and having a cavity that is concave in a first direction from a top surface of the conductive body toward a bottom surface thereof, and a light-emitting device disposed in the cavity, wherein the conductive body includes a first protrusion and a second protrusion, which protrude in the first direction from the bottom surface of the conductive body, and the first protrusion is disposed inside the first through hole, the second protrusion is disposed inside the second through hole, and a top surface of the resin unit is in contact with the bottom surface of the conductive body. |
| US11335842B2 |
Chip-scale packaging light-emitting device with electrode polarity identifier and method of manufacturing the same
A chip-scale packaging (CSP) light-emitting device (LED) is provided with an electrode polarity identifier, and includes a light-emitting semiconductor chip and a packaging structure. A first horizontal direction and a perpendicular second horizontal direction are specified on a semiconductor-chip-upper surface. The packaging structure covers the semiconductor-chip-upper surface, a first semiconductor-chip-side surface and a second semiconductor-chip-side surface of the light-emitting semiconductor chip, and includes a first package-side surface and a second package-side surface. A first region is between the first package-side surface and the first semiconductor-chip-side surface, and a second region is between the second package-side surface and the second semiconductor-chip-side surface, wherein an area of the first region is different from an area of the second region. An orientation of the electrode polarity of the CSP LED can be visually identified by recognizing the area difference of the first region and the second region. |
| US11335838B2 |
Light emitting apparatus
A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer. |
| US11335836B2 |
Micro LED structure and method of manufacturing same
The present invention relates to a micro LED structure and a method of manufacturing the same that facilitate realizing of pixels of the micro LED structure. |
| US11335835B2 |
Converter fill for LED array
An optical isolation material may be applied to walls of a first cavity and a second cavity in a wafer mesh. A wavelength converting layer may be deposited into the first cavity to create a first segment and into the second cavity to create a second segment. The first segment may be attached to a first light emitting device to create a first pixel and the second segment to a second light emitting device to create a second pixel. The wafer mesh may be removed. |
| US11335834B2 |
Quantum dot films utilizing multi-phase resins
Multi-phase polymer films containing quantum dots (QDs) are described herein. The films have domains of primarily hydrophobic polymer and domains of primarily hydrophilic polymer. QDs, being generally more stable within a hydrophobic matrix, are dispersed primarily within the hydrophobic domains of the films. The hydrophilic domains tend to be effective at excluding oxygen. |
| US11335833B2 |
Light-emitting diodes, light-emitting diode arrays and related devices
Light-emitting diodes (LEDs), LED arrays, and related devices are disclosed. An LED device includes a first LED chip and a second LED chip mounted on a submount with a light-altering material in between. The light-altering material may include at least one of a light-reflective material and/or a light-absorbing material. Individual wavelength conversion elements may be arranged on each of the first and second LED chips. The light-altering material may improve the contrast between the first and second LED chips as well as between the individual wavelength conversion elements. LED devices may include submounts in modular configurations where LED chips may be mounted on adjacent submounts to form an LED array. Each LED chip of the LED array may be laterally separated from at least one other LED chip by a same distance and a light-altering material may be arranged around the LED array. |
| US11335832B2 |
LED package structure and carrier thereof
An LED package structure and a carrier thereof are provided. The LED package structure includes a carrier, a plurality of LED chips, and an encapsulating colloid. The carrier includes a substrate, a ring-shaped first wall disposed on the substrate, and a ring-shaped second wall stacked on the first wall. A portion of the substrate surrounded by the first wall is defined as a die-bonding region, and the first wall, the second wall, and the die-bonding region jointly define an accommodating space. The LED chips are mounted on the die-bonding region and are arranged in the accommodating space. The encapsulating colloid is filled within the accommodating space, and the LED chips are embedded in the encapsulating colloid. |
| US11335831B2 |
Optical device case and optical device
An optical device case (100A) of an embodiment includes: a light-transmitting window member (20A); and a housing (10) which has a space for accommodating a light-receiving element and/or a light-emitting element (OE), wherein the window member (20A) includes a light-transmitting member (22), a polymer film (50) provided on an outer surface of the light-transmitting member (22), the polymer film (50) having a moth-eye structure at its surface, a contact angle of the surface with respect to water being not less than 140°, and a resistance heater (24) provided on an inner surface of the light-transmitting member (22). |
| US11335830B2 |
Photo-emission semiconductor device and method of manufacturing same
A photo-emission semiconductor device superior in reliability is provided. The photo-emission semiconductor device includes a semiconductor layer, a light reflection layer provided on the semiconductor layer, and a protective layer formed by electroless plating to cover the light reflection layer. Therefore, even if the whole structure is reduced in size, the protective layer reliably covers the light reflection layer without gap. |
| US11335826B2 |
Semiconductor photo-detecting device
A photo-detecting device includes a substrate, a first semiconductor layer, a light-absorbing layer, a second semiconductor layer, a semiconductor contact layer, an insulating layer, and an electrode structure. The second semiconductor layer includes a first region and a second region. The semiconductor contact layer is on the first region. The insulating layer covers the semiconductor contact layer, the first region, and the second region. The electrode structure covers the semiconductor contact layer, the insulating layer, the first region, and the second region. |
| US11335824B2 |
Near-infrared photodetector semiconductor device
The near-infrared photodetector semiconductor device comprises a semiconductor layer (1) of a first type of conductivity with a main surface (10), a trench or a plurality of trenches (2) in the semiconductor layer at the main surface, a SiGe alloy layer (3) in the trench or the plurality of trenches, and an electrically conductive filling material of a second type of conductivity in the trench or the plurality of trenches, the second type of conductivity being opposite to the first type of conductivity. |
| US11335821B2 |
Low noise silicon germanium image sensor
Low noise silicon-germanium (SiGe) image sensor. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor substrate. The photodiodes of an individual pixel are configured to receive an incoming light through an illuminated surface of the semiconductor substrate. The semiconductor substrate includes a first layer of semiconductor material having silicon (Si); and a second layer of semiconductor material having silicon germanium (Si1-xGex). A concentration x of Ge changes gradually through at least a portion of thickness of the second layer. Each photodiode includes a first doped region extending through the first layer of semiconductor material and the second layer of semiconductor material; and a second doped region extending through the first layer of semiconductor material and the second layer of semiconductor material. |
| US11335818B2 |
Solar cell and production method therefor, and solar cell module
A solar cell includes a semiconductor substrate, a first conductive layer, a second conductive layer, a first electrode, a second electrode, and an island-shaped conductive layer. The first conductive layer and the second conductive layer are disposed on one principal surface of the semiconductor substrate. The first electrode is disposed on the first conductive layer and the second electrode is disposed on the second conductive layer. The first electrode and the second electrode are electrically separated, and the island-shaped conductive layer is disposed between the first electrode and the second electrode. |
| US11335817B2 |
Composite etch stop layers for sensor devices
A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer. |
| US11335814B2 |
Semiconductor chip
Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2. |
| US11335811B2 |
Semiconductor arrangement comprising buffer layer and semiconductor columns over the buffer layer and formation thereof
A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the drain or source of the transistor. |
| US11335809B2 |
Stacked Gate-All-Around FinFET and method forming the same
A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics. |
| US11335805B2 |
High voltage switch device
A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure. |
| US11335803B2 |
Source-down transistor with vertical field plate
The structure of a field-effect transistor with a source-down configuration and process of making the transistor are described in this paper. The transistor is built in a semiconductor chip with a trench extending from top chip surface towards the bottom surface. The trench contains a conductive gate material embedded in a dielectric material in the trench. A conductive field plate is also embedded in the trench and extends from the top surface of the chip towards the bottom surface of the chip and splits the conductive gate electrode into two halves. The conductive field plate penetrates the trench and makes electrical contact with the heavily doped substrate near the bottom surface of the chip. |
| US11335799B2 |
Group-III nitride semiconductor device and method for fabricating the same
The present application discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride. |
| US11335793B2 |
Vertical tunneling field-effect transistors
Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs. |
| US11335792B2 |
Semiconductor processing system with in-situ electrical bias and methods thereof
A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage. |
| US11335790B2 |
Ferroelectric memory devices with dual dielectric confinement and methods of forming the same
A semiconductor structure contains a semiconductor channel extending between a source region and a drain region, at least one gate electrode, a ferroelectric material portion located between the semiconductor channel and the at least one gate electrode, a front-side gate dielectric located between the ferroelectric material portion and the semiconductor channel, and a backside gate dielectric located between the ferroelectric material portion and the at least one gate electrode. The front-side gate dielectric and the backside gate dielectric have a dielectric constant greater than 7.9 and a band gap greater than a band gap of the ferroelectric material portion. |
| US11335786B2 |
Gate structure in high-κ metal gate technology
Various embodiments of the present disclosure are directed towards a semiconductor device including a gate structure. The semiconductor device further includes a pair of spacer segments on a semiconductor substrate. A high-κ gate dielectric structure overlies the semiconductor substrate. The high-κ gate dielectric structure is laterally between and borders the spacer segments. The gate structure overlies the high-k gate dielectric structure and has a top surface about even with a top surface of the spacer segments. The gate structure includes a metal structure and a gate body layer. The gate body layer has a top surface that is vertically offset from a top surface of the metal structure and further has a lower portion cupped by the metal structure. |
| US11335784B2 |
Field plate structure for high voltage device
Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening. |
| US11335781B2 |
Vanadium dioxide heterostructures having an isostructural metal-insulator transition
Heterostructures that include a bilayer composed of epitaxial layers of vanadium dioxide having different rutile-to-monoclinic phase transition temperatures are provided. Also provided are electrical switches that incorporate the heterostructures. The bilayers are characterized in that they undergo a single-step, collective, metal-insulator transition at an electronic transition temperature. At temperatures below the electronic transition temperature, the layer of vanadium dioxide having the higher rutile-to-monoclinic phase transition temperature has an insulating monoclinic crystalline phase, which is converted to a metallic monoclinic crystalline phase at temperatures above the electronic transition temperature. |
| US11335772B2 |
Semiconductor device and method of manufacturing semiconductor device
Provided is a semiconductor device including a semiconductor substrate doped with impurities, a front surface-side electrode provided on a front surface side of the semiconductor substrate, a back surface-side electrode provided on a back surface side of the semiconductor substrate, wherein the semiconductor substrate has a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration, a high concentration region arranged closer to the front surface than the peak region and having a gentler impurity concentration than the one or more peaks, and a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region. |
| US11335771B2 |
Semiconductor device
A semiconductor device includes first and second electrodes, a semiconductor part therebetween; first and second control electrodes each in a trench at the frontside of the semiconductor part. The semiconductor part includes first to sixth layers. The first and third layers are of a first conductivity type. Other layers are of a second conductivity type. The first layer extends between the first electrode at the backside and the second electrode at the frontside. The second layer is provided between the first layer and the second electrode. The third and fourth layers each are selectively provided between the second layer and the second electrode. The fifth layer is provided between the first layer and the first electrode. The sixth layer is provided between the first layer and the second control electrode. The sixth layer extends along an insulating film between the semiconductor part and the second control electrode. |
| US11335770B2 |
Semiconductor isolation structures having different configurations in different device regions and method of forming the same
Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure. |
| US11335768B2 |
Integrated high voltage capacitor
A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates. |
| US11335765B2 |
Display panels, display screens, and display terminals
A display panel, a display screen, and a display terminal are provided. The display panel includes a substrate and a plurality of wavy first electrodes disposed on the substrate. The plurality of first electrodes extend in parallel in the same direction and have an interval between adjacent first electrodes. In an extending direction of the first electrode, a width of the first electrode changes continuously or intermittently, and the interval changes continuously or intermittently. |
| US11335761B2 |
Display apparatus
A display apparatus includes a substrate, a display unit disposed on the substrate, an insulating layer disposed on the substrate, a power supply wire disposed on the insulating layer outside the display unit, and a cladding layer. The display unit includes a pixel circuit and a display element electrically connected to the pixel circuit. The insulating layer extends from the display unit to an edge of the substrate. The power supply wire is electrically connected to the display element and includes an alignment pattern that exposes at least a portion of the insulating layer. The cladding layer covers an inner surface of the alignment pattern and contacts the at least a portion of the insulating layer. |
| US11335760B2 |
Display panel having portion of encapsulation layer located in hollow region that is direct contact with first inorganic layer, manufacturing method thereof, and display device having the same
Display panel, manufacturing method thereof, and display device are provided. As an example, the display panel includes a substrate, a TFT layer formed on the substrate, and an encapsulation layer formed on the TFT layer. The TFT layer includes a thin film transistor with a source electrode, a drain electrode and a gate electrode, and further includes a first metal layer, a first inorganic layer on the first metal layer, and a second metal layer on the first inorganic layer. The second metal layer includes a first region and a second region, a hollowed-out region is formed between the first region and the second region, and the first region and the second region are electrically connected via the first metal layer. A portion of the encapsulation layer that is located in the hollowed-out region is in contact with the first inorganic layer. |
| US11335756B2 |
OLED display device and manufacturing method of TFT array substrate
An OLED display device including an OLED pixel driving circuit is provided. A driving thin film transistor in the OLED pixel driving circuit is configured as a double gate oxide thin film transistor, and a switch thin film transistor is configured as a top gate self-aligned oxide thin film transistor. A manufacturing method of a TFT array substrate is also provided, and the TFT array substrate is used for preparing the OLED display device. |
| US11335755B2 |
Display apparatus and method of manufacturing the same
A display apparatus includes a pixel electrode and a opposite electrode facing each other; a thin-film transistor connected to the pixel electrode; a contact electrode connected to the opposite electrode and spaced apart from the pixel electrode; an auxiliary electrode connected to the contact electrode and spaced apart from the thin-film transistor; an intermediate layer with which light is emitted, the intermediate layer including: an emission layer, and a first functional layer corresponding to the pixel electrode and the contact electrode, the first functional layer defining an opening portion at which the contact electrode is exposed; and a multi-insulating layer between the thin-film transistor and the pixel electrode, between the auxiliary electrode and the contact electrode, and defining a contact opening at which the auxiliary electrode is connected to the contact electrode, the contact opening corresponding to the opening portion of the intermediate layer. |
| US11335754B2 |
Display panel and display device including camera area with light transmission hole
A display panel and a display device thereof are provided. Pixel units of camera areas are removed to form a light transmission hole, and after that, the camera component is disposed below the display panel of the camera area. External light can be incident on the camera component directly, so purpose of photographing is achieved, and the screen-to-body ratio is further increased. |
| US11335753B2 |
Display panel and display device having discontinuous organic light-emitting layer
A display panel and a display device are disclosed. The display panel includes an array substrate, an organic light-emitting layer, a thin-film encapsulation layer, and a polarizing film. The array substrate includes at least two inorganic layers disposed on an underlay substrate. In a transparent display region, at least two inorganic layers include at least one first hole. The organic light-emitting layer has faults in a position of the first hole. A transparent sealant is used to cover edges of the faults of the organic light-emitting layer. |
| US11335752B2 |
Organic-EL display device with alternately lined source drain electrodes and manufacturing method thereof
This organic-EL display apparatus comprises: a substrate with a drive circuit comprising a thin-film transistor (TFT), a planarizing layer to cover the drive circuit, and an organic light-emitting element formed upon the surface of the planarizing layer facing the opposite direction from the drive circuit. The surface of the planarizing layer has an arithmetic average roughness of 50 nm or less. The TFT comprises a drain electrode, a source electrode, and a semiconductor layer that includes regions to be a channel of TFT and partially overlaps with the source and drain electrodes. Respective parts of a first conductor layer forming the drain electrode and a second conductor layer forming the source electrode are arranged in an alternating manner along a prescribed direction, and the region to be the channel is sandwiched between the part of the first conductor layer and the part of the second conductor layer. |
| US11335751B2 |
Display device
A display device includes: a substrate; a data line disposed on the substrate; an another data line disposed on the substrate and adjacent to the data line; a first light emitting diode including a first electrode; and a second light emitting diode including an another first electrode, wherein the first electrode partially overlaps the data line and the another first electrode partially overlaps the another data line. |
| US11335750B2 |
Organic light emitting diode (OLED) display panel and OLED display device
The present invention provides an organic light-emitting diode (OLED) display panel and an OLED display device. The OLED display panel comprises a light transmission area and a display area surrounding a periphery of the light transmission area; a concave groove is disposed in the OLED display panel corresponding to the light transmission area, and the concave groove penetrates through at least an encapsulation layer, a light emitting function layer and a part of a thin film transistor (TFT) structure layer; and at least a part of a touch function layer extends from the display area toward the concave groove and covers the concave groove. |
| US11335748B2 |
Transparent OLED substrate, display panel and OLED substrate
The present disclosure provides a transparent OLED substrate, a display panel, and an OLED substrate. The transparent OLED substrate includes: a base substrate; a first electrode layer formed over the base substrate; a pixel defining layer formed over the first electrode layer, the pixel defining layer including a plurality of pixel defining holes penetrating the pixel defining layer to the first electrode layer, and an exposed area of the first electrode layer is equal to an area of the pixel defining hole; a light emitting layer formed over the pixel defining layer and including organic light emitting blocks; a second electrode layer formed over the light emitting layer; wherein each of the pixel defining holes corresponds to a plurality of the organic light emitting blocks. |
| US11335745B2 |
Display panel comprising blocking structure disposed between display region and bending region
The present invention provides a display panel, and the display panel includes an array substrate, a drain metal layer disposed on the array substrate, a flat layer disposed on the drain metal layer, and a pixel defining layer and light-emitting device layer disposed on the flat layer. The pixel defining layer includes a first pixel defining layer located in a display region of the display panel, and a second pixel defining layer located in an edge region of a side portion of the display region. A packaging layer is disposed on the first pixel defining layer, and a blocking structure is disposed on the second pixel defining layer. |
| US11335739B2 |
Display panel and display device
The present disclosure provides a display panel and a display device, comprising: a flexible base substrate comprising a first flexible substrate, a second flexible substrate, and metal signal lines located between the first flexible substrate and the second flexible substrate; a display unit disposed on the flexible base substrate; a touch unit disposed on a light-exiting side of the display unit and covering the display unit; and a processing chip connected to the flexible base substrate for receiving and feeding back signals from the display unit and/or the touch unit. The metal signal lines are electrically connected to the processing chip and the touch unit transmits a touch signal to the metal signal lines through a conductive adhesive. By transmitting the touch signal to the processing chip through the conductive adhesive, the touch unit and the display unit can share one processing chip. |
| US11335734B2 |
Organic light emitting diode display device
An organic light emitting diode display device includes a substrate, first and second active patterns, and first and second sub-pixel structures. The substrate has a first sub-pixel circuit region including a first driving transistor region and a second sub-pixel circuit region including a second driving transistor region. The first active pattern is disposed in the first sub-pixel circuit region and has a first bent portion in the first driving transistor region. The second active pattern is disposed in the second sub-pixel circuit region and has a second bent portion in the second driving transistor region. In a direction in a plan surface, the first active pattern has a first recess formed by the first bent portion, and the second active pattern has a second recess formed by the second bent portion. An area of the second recess is less than that of the first recess. |
| US11335731B1 |
3D semiconductor device and structure with transistors
A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step. |
| US11335727B2 |
Image sensing device
The image sensing device includes a pixel array including a plurality of unit pixels is arranged in rows and columns. Each of the plurality of unit pixels includes a photoelectric conversion element to generate charge carriers by converting light incident upon the photoelectric conversion element, a plurality of floating diffusion regions spaced apart from the photoelectric conversion element to hold the charge carriers, a plurality of circulation gates located at sides of the photoelectric conversion element in each of a first direction and a second direction perpendicular to the first direction, configured to create an electric field in different regions of the photoelectric conversion element based on circulation control signals, and configured to induce movement of the charge carriers, and a plurality of transfer gates located between the circulation gates, and configured to transfer the charge carriers generated by the photoelectric conversion element to a corresponding floating diffusion region. |
| US11335715B2 |
Solid-state imaging unit, method of producing the same, and electronic apparatus
The present technology relates to a solid-state imaging unit that makes it possible to increase the number of terminals, a method of producing the same, and an electronic apparatus. A solid-state imaging unit includes: an image sensor substrate including a light receiving region in which pixels that convert incoming light to an electric signal are arranged in a matrix; a solder ball; a glass substrate opposite the image sensor substrate and the solder ball; and a through electrode that couples a wiring line pattern and the solder ball to each other by penetrating a glass adhesive resin interposed between the wiring line pattern and the solder ball. The solder ball is disposed outside the image sensor substrate in a plane direction. The wiring line pattern being formed on the glass substrate. The present disclosure is applicable, for example, to a package and the like including the image sensor substrate. |
| US11335713B2 |
Display device
A display device includes a substrate including a display area and a non-display area, a reference voltage supply line disposed in the non-display area and transmitting a reference voltage, and a driving voltage supply line disposed in the non-display area and transmitting a driving voltage. The reference voltage supply line includes a straight line part extending in a first direction and a curved line part extending from the straight line part to be bent, and the curved line part of the reference voltage supply line is disposed along a periphery of the display area. |
| US11335711B2 |
Array substrate, manufacturing method thereof, and display panel
An array substrate, a manufacturing method thereof, and display panel are provided. Gate scanning lines and Light-shielding conductive layer are electrically connected, so that a width of the gate scanning line is substantially unchanged from the conventional technology to ensure an aperture ratio of a display panel. Therefore, an impedance of the wire used to transmit the scanning electrical signal is reduced, so that the display panel driving power consumption is reduced to increase the corresponding speed of pixel charging and discharging. |
| US11335710B2 |
Thin film transistor, display panel and preparation method thereof, and display apparatus
A thin film transistor, a display panel and a preparation method thereof and a display apparatus are provided. The thin film transistor includes: a substrate; a gate metal located on a side of the substrate; a gate insulating layer located on a side of the gate metal away from the substrate; an active layer located on a side of the gate insulating layer away from the substrate; a first metal oxide and a second metal oxide which are located on a side of the active layer away from the substrate and are arranged on a same layer; and a source metal and a drain metal which are located on sides of the first metal oxide and the second metal oxide away from the substrate and are arranged in a same layer. |
| US11335708B2 |
Display device having a plurality of thin film transistors per pixel
A display device capable of improving image quality is provided. A storage node is provided in each pixel and first data can be held in the storage node. Second data is added to the first data by capacitive coupling, which can be supplied to a display element. Thus, the display device can display a corrected image. A reference potential for the capacitive coupling operation is supplied from a power supply line or the like, and thus the first data and the second data can be supplied from a common signal line. |
| US11335704B2 |
Low parasitic capacitance RF transistors
Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects. |
| US11335703B2 |
Display panel, method for manufacturing the same, and display device
The present disclosure provides a display panel, a method for manufacturing the same, and a display device. The insulation layer is provided above the first conductive electrodes in the bonding area of the display panel, the insulation layer covers the first conductive electrodes, and the insulation layer is capable of being pierced by ACF particles. When the display panel is bound to an FPC by an ACF, second conductive electrodes on the FPC can be electrically coupled to the first conductive electrodes on the display panel through the ACF particles, thereby achieving the bonding connection between the display panel and the FPC, even if a conductive foreign object falls into the area where the first conductive electrodes are located, short circuit cannot be caused, thereby improving the product yield. |
| US11335700B2 |
Block-on-block memory array architecture using bi-directional staircases
A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions. |
| US11335699B2 |
Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator. |
| US11335697B2 |
Vertical memory devices having contact plugs vertically extending through plurality of gate electrodes and contacting lower circuit pattern
A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction. |
| US11335695B2 |
Integrated circuit device
An integrated circuit device including a substrate having a cell and interconnection region; and a first stacked structure and a second stacked structure on the first stacked structure, each of the first and second stacked structures including insulating layers and word line structures that are alternately stacked one by one on the substrate in the cell region and the interconnection region, wherein, in the interconnection region the first stacked structure includes a first dummy channel hole penetrating through the first stacked structure, the second stacked structure includes a second dummy channel hole communicatively connected to the first dummy channel hole, the second dummy channel hole penetrating through the second stacked structure, respectively, and a first dummy upper width of an uppermost end of the first dummy channel hole is greater than a second dummy upper width of an uppermost end of the second dummy channel hole. |
| US11335692B2 |
Non-volatile flash memory device and a manufacturing method thereof
The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist. |
| US11335690B2 |
Multicolor approach to DRAM STI active cut patterning
Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures. |
| US11335688B1 |
Semiconductor structures and preparation methods thereof
In a semiconductor structure preparation method, the trench runs through a well region of a first conductivity type and extends to the substrate below the well region. A heavily doped first electrode layer is formed on the sidewall of the trench. The first electrode layer covers the bottom of the trench and extends into the well region. A capacitor dielectric layer is formed on the surface of the first electrode layer and the sidewall of the trench, and a second electrode layer is formed on the surface of the capacitor dielectric layer to fill the trench. A dielectric layer is formed on the sidewall of the through silicon via, and an interconnect structure is formed on the surface of the dielectric layer to fill the through silicon via. |
| US11335685B2 |
Semiconductor memory device
Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern. |
| US11335680B2 |
Integrated circuits and method of manufacturing the same
An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions. |
| US11335674B2 |
Diode triggered silicon controlled rectifier (SCR) with hybrid diodes
The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes. |
| US11335673B2 |
Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits
An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions. |
| US11335672B2 |
Semiconductor structure and manufacturing method thereof
A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test. |
| US11335668B2 |
Semiconductor package and method of fabricating the same
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad. |
| US11335667B2 |
Stacked semiconductor die assemblies with die substrate extensions
Stacked semiconductor die assemblies with die substrate extensions are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first die mounted to the package substrate, and a second die mounted to the first die. The first die includes a first die substrate, and the second die includes a second die substrate attached to the first die substrate. At least one of the first and second dies includes a semiconductor substrate and a die substrate extension adjacent the semiconductor substrate. The die substrate extension comprises a mold material that at least partially defines a planform. |
| US11335665B2 |
Microelectronic assemblies
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects. |
| US11335663B2 |
Microelectronic assemblies
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects. |
| US11335660B2 |
Semiconductor module
A semiconductor module includes a first semiconductor element and a second semiconductor element each having an upper-surface electrode and a lower-surface electrode, and being connected in parallel to configure an upper arm, a first conductive layer having a U-shape in planar view, having two end portions, and having an upper surface on which the first semiconductor element and the second semiconductor element are disposed in a mirror image arrangement, a positive electrode terminal having a body part and at least two positive electrode ends branched from the body part, and a negative electrode terminal having a negative electrode end disposed between the positive electrode ends. The positive electrode ends are respectively connected to one of the two end portions of the first conductive layer. |
| US11335659B2 |
Semiconductor chip with patterned underbump metallization and polymer film
Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion. |
| US11335654B2 |
Devices and methods for enhancing insertion loss-performance of an antenna switch
Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device. |
| US11335653B2 |
Terahertz device
The task of the present invention is to achieve gain enhancement.A terahertz device (10) of the present invention includes a terahertz element (20) generating an electromagnetic wave, a dielectric (50) including a dielectric material and surrounding the terahertz element (20), a gas space (92) including a gas, and a reflecting film (82) serving as a reflecting portion. The reflecting film (82) includes a portion opposing the terahertz element (20) through the dielectric (50) and the gas space (92) and reflecting the electromagnetic wave toward a direction, wherein the electromagnetic wave is generated from the terahertz element (20) and transmitted through the dielectric (50) and the gas space (92). In addition, the refractive index of the dielectric (50) is lower than the refractive index of the terahertz element (20) and is higher than the refractive index of the gas in the gas space (92). |
| US11335649B2 |
Low impedance multi-conductor layered bus structure with shielding
Various embodiments of laminated planar bus structures that minimize electromagnetic interference (EMI) and parasitic inductance are described. In one embodiment, a laminated planar bus structure may include a plurality of stacked conductive layers and a plurality of stacked insulation layers. The plurality of stacked conductive layers may include positive and negative conductive layers, and conductive ground layers stacked as outer layers as to enclose vertically the positive and the negative conductive layers. In another embodiment, the laminated planar bus structure may include a middle ground layer stacked in between the positive and the negative conductive layers to provide additional reduction in electric field strength. A laminated planar bus structure that is integrated with other power electronics components is also presented. |
| US11335648B2 |
Semiconductor chip fabrication and packaging methods thereof
A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions. |
| US11335646B2 |
Substrate structure including embedded semiconductor device and method of manufacturing the same
The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed. |
| US11335645B2 |
High-frequency module and manufacturing method thereof
A high-frequency module 1 includes: a substrate 2; a first component 4 mounted on an upper surface 2a of the substrate 2; a second component 5 mounted on a lower surface 2b of the substrate 2; an upper sealing resin layer 6 and a lower sealing resin layer 7; a conductor pin 8; and a shield layer 9. The conductor pin 8 includes a terminal portion 8a exposed from a lower surface 7a of the lower sealing resin layer 7 and connected to a ground electrode of an outer substrate, and a shield connection portion 8b exposed from a side surface 7b of the lower sealing resin layer 7 and connected to the shield layer 9. As a result of the terminal portion 8a of the conductor pin 8 being connected to the ground electrode, the shield layer 9 is connected to a ground potential with the shortest distance therebetween. |
| US11335643B2 |
Embedded ball land substrate, semiconductor package, and manufacturing methods
A electronic device includes an embedded ball land substrate and a semiconductor die. The embedded ball land substrate includes a top surface, a bottom surface opposite the top surface, and one or more side surfaces adjacent the top surface and the bottom surface. The embedded ball land substrate further includes a mold layer on the bottom surface, contact pads on the top surface, and ball lands embedded in the mold layer and electrically connected to the contact pads. The semiconductor die includes a first surface, a second surface opposite the first surface, one or more side surfaces adjacent the first surface and the second surface, and attachment structures along the second surface. The semiconductor die is operatively coupled to the contact pads via the attachment structures. |
| US11335642B2 |
Microelectronic assemblies
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die. |
| US11335639B2 |
Method of forming stacked trench contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate. |
| US11335634B2 |
Chip package structure and method for forming the same
A method for forming a chip package structure is provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer over the first pad. The method includes forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer. The method includes bonding a chip to the wiring substrate through a conductive bump and a flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the flux layer while the conductive protection layer covers the nickel-containing layer. |
| US11335633B2 |
Circuit module and power supply chip module
Provided is a circuit module including a power supply chip module, a load chip module, and a system board. A power supply output terminal group of the power supply chip module is arranged side by side in a row along a side of the power supply chip module board, the power supply input terminal group of a load chip module includes a specific terminal group arranged in a specific row that is a row along a side of the load chip module board, and a wiring width along an arrangement direction of the power supply output terminal group of a wiring pattern in which the power supply output terminal group is connected to the system board is equal to or more than a wiring width W31 along an arrangement direction of the specific terminal group of the wiring pattern in which the specific terminal group is connected to the system board. |
| US11335624B2 |
Print head and liquid discharge apparatus
A liquid discharge apparatus includes a print head discharging a liquid and a control circuit controlling an operation of the print head. the print head includes a connector having a first terminal, a second terminal, a third terminal, and a fourth terminal, a first integrated circuit, a circuit substrate on which the connector and the first integrated circuit are provided and which has first wiring, second wiring, third wiring, fourth wiring, fifth wiring, and sixth wiring, and a first wiring substrate, in which the first wiring electrically couples the first terminal and the first integrated circuit to each other, the fifth wiring electrically couples the first terminal and the first integrated circuit to each other, and the sixth wiring electrically couples the first integrated circuit and the first wiring substrate to each other. |
| US11335623B2 |
Method of producing heat-dissipating unit
[Purpose] To provide is a method capable of producing a heat-dissipating unit easily and at low cost.[Solution] The method of producing a heat-dissipating unit 12 includes: inserting pins 17 punched out of a second plate member 22 for pins into a plurality of through-holes 16 formed in a first plate member 20 for a substrate. In the first plate member 20, a plurality of substrate forming portions 25 is provided side by side in the longitudinal direction of the first plate member 20. In the second plate member 22, a plurality of pin punch-out portions 26 is provided side by side in the longitudinal direction of the second plate member 22. The method includes: a step A of forming the through-holes 16 in the substrate forming portion 25 of the first plate member 20; a step B of subjecting the pin punch-out portion 26 of the second plate member 22 to a half-punch out process to form half-punched-out pin forming portions 27 protruding from one surface side of the second plate member 22; a step C of forming the pins 17 by punching out the pin forming portions 27 from the second plate member 22 and simultaneously inserting the pins 17 into the through-holes 16 in the first plate member 20; and a step D of forming a substrate by cutting the substrate forming portion 25 with the pins 17 inserted in the through-holes 16 from the first plate member 20. |
| US11335619B2 |
Semiconductor device
A semiconductor device, including: a heat sink which has a mounting surface, a heat radiation surface, a side surface and an engagement part, a semiconductor chip which is mounted on the mounting surface of the heat sink, a lead frame which is engaged with the engagement part of the heat sink, and a mold resin which seals the heat sink, the semiconductor chip and the lead frame, wherein the engagement part of the heat sink is disposed at a place which avoids the mounting surface of the heat sink. The engagement part of the heat sink is a dowel formed in the heat radiation surface of the heat sink. Further, the engagement part of the heat sink is a dowel formed in the side surface of the heat sink. |
| US11335618B2 |
Thermals for packages with inductors
An apparatus is provided which comprises: one or more pads comprising metal on a first substrate surface, the one or more pads to couple with contacts of an integrated circuit die, one or more substrate layers comprising dielectric material, one or more conductive contacts on a second substrate surface, opposite the first substrate surface, the one or more conductive contacts to couple with contacts of a printed circuit board, one or more inductors on the one or more substrate layers, the one or more inductors coupled with the one or more conductive contacts and the one or more pads, and highly thermally conductive material between the second substrate surface and a printed circuit board surface, the highly thermally conductive material contacting the one or more inductors. Other embodiments are also disclosed and claimed. |
| US11335616B2 |
Substrate integrated inductor with composite magnetic resin layer
A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. A semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package. |
| US11335615B2 |
Wafer accommodation container
Described herein are wafer accommodation containers. A wafer accommodation container (1) includes: a container body having one end that is provided with an opening (11) and another end that is provided with a mount element (12) on which wafers are stacked, the mount element (12) facing the opening (11); a cover (20) to cover the opening (11); and a connection mechanism (30) to detachably connect the container body (10) and the cover (20). |
| US11335611B2 |
Semiconductor structure and fabrication method thereof
The embodiments relate to a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a wafer, in the wafer there being provided with a scribe line, in the scribe line there being provided with a test pad, a first test structure, and a second test structure; the second test structure being positioned below the first test structure, and a transverse pitch between the second test structure and the first test structure being at least equal to a width of the test pad; forming a protective layer on the wafer, the protective layer at least covering the scribe line; and performing exposure and development on the protective layer, such that a thickness of the protective layer remained above the first test structure is greater than that of the protective layer remained above the second test structure. |
| US11335609B2 |
Micro detector
A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate. |
| US11335608B2 |
Electron beam system for inspection and review of 3D devices
An electron beam system for wafer inspection and review of 3D devices provides a depth of focus up to 20 microns. To inspect and review wafer surfaces or sub-micron-below surface defects with low landing energies in hundreds to thousands of electron Volts, a Wien-filter-free beam splitting optics with three magnetic deflectors can be used with an energy-boosting upper Wehnelt electrode to reduce spherical and chromatic aberration coefficients of the objective lens. |
| US11335607B2 |
Apparatus and methods for wafer to wafer bonding
A method includes having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based on the physical parameter of the first wafer; obtaining measurements of the first wafer to obtain the physical parameter of the first wafer; generating, by the model, the first wafer bonding recipe based on the physical parameter of the first wafer; and bonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer. |
| US11335606B2 |
Power rails for stacked semiconductor device
The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening. |
| US11335603B2 |
Multi-layered insulating film stack
A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material. |
| US11335600B2 |
Integration method for finfet with tightly controlled multiple fin heights
A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin. |
| US11335593B2 |
Interconnect structure of semiconductor device including barrier layer located entirely in via
Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature. |
| US11335590B2 |
Methods for forming elongated contact hole ends
Disclosed is a semiconductor processing approach wherein a wafer twist is employed to increase etch rate, at select locations, along a hole or space end arc. By doing so, a finished hole may more closely resemble the shape of the incoming hole end. In some embodiments, a method may include providing an elongated contact hole formed in a semiconductor device, and etching the elongated contact hole while rotating the semiconductor device, wherein the etching is performed by an ion beam delivered at a non-zero angle relative to a plane defined by the semiconductor device. The elongated contact hole may be defined by a set of sidewalls opposite one another, and a first end and a second end connected to the set of sidewalls, wherein etching the elongated contact hole causes the elongated contact hole to change from an oval shape to a rectangular shape. |
| US11335587B2 |
Substrate processing apparatus and substrate processing meihod
A substrate processing apparatus includes a substrate holding unit which holds and rotates a substrate in a horizontal orientation, a substrate heating unit which has a heating surface which faces the substrate, held by the substrate holding unit, from below and overlaps with an outermost periphery of the substrate in top view, and heats the substrate in a state of contacting a lower surface of the substrate, a transferring unit which transfers the substrate between the substrate holding unit and the substrate heating unit, and a processing fluid supplying unit which supplies a processing fluid toward the substrate held by the substrate holding unit. |
| US11335585B2 |
Vacuum wafer chuck for manufacturing semiconductor devices
Disclosed is a substrate displacing assembly so as to improve its durability during a semiconductor processing. In one embodiment, a semiconductor manufacturing system, includes, a substrate holder, wherein the substrate holder is configured with a plurality of pins; and a substrate displacing assembly for displacing a substrate on the substrate holder in a first direction perpendicular to the top surface of the substrate holder through the plurality of pins, wherein the substrate displacing assembly comprises a pair of load forks, a coupler and a driving shaft, wherein the pair of load forks comprises a fork region and a base region, wherein the coupler is mechanically coupled to the base region through at least one first joining screw extending in the first direction, wherein the coupler is further mechanically coupled to the driving shaft through a second joining screw extending in the first direction. |
| US11335583B2 |
Mass transfer method and device for micro light emitting diode chips
The disclosure provides a mass transfer method and device for micro light emitting diode chips. The method includes the following steps: performing magnetic pole electroplating on the micro light emitting diode chips obtained by peeling off the sapphire substrate to enable corresponding magnetic poles to be generated at corresponding positions of the micro light emitting diode chips; peeling off the transfer substrate, and placing the micro light emitting diode chips obtained by peeling off the transfer substrate in a dispersion liquid to form a solution in which micro light emitting diode chips are dispersed; and the display substrate picks up the micro light emitting diode chips dispersed under the action of the magnetic field force. |
| US11335582B2 |
Micro LED display substrate and manufacturing method thereof
The present disclosure relates to a method for manufacturing a micro LED display substrate. The method may include forming an array of micro LEDs on an epitaxial wafer; transferring the array of micro LEDs on the epitaxial wafer to an adhesive layer on a surface of a transfer substrate assembly; and transferring the array of micro LEDs on the surface of the transfer substrate assembly onto corresponding pads on a driving substrate respectively. |
| US11335581B2 |
System and method for adhering a semiconductive wafer to an electrostatic carrier by adjusting relative permittivity
A mobile electrostatic carrier (MESC) provides a structural platform to temporarily bond a semiconductive wafer and can be used to transport the semiconductive wafer or be used to perform manufacturing processes on the semiconductive wafer. The MESC uses a plurality of electrostatic field generating (EFG) circuits to generate electrostatic fields across the MESC that allow the MESC to bond to compositional impurities within the semiconductive wafer. A dielectric thin film is superimposed across the bonding surface of MESC in order to adjust the relative permittivity between the semiconductive wafer to the MESC. This adjustment in the relative permittivity allows the MESC to further adhere the semiconductive wafer to the MESC. |
| US11335580B2 |
Error measurement device of linear stage and error measurement method of linear stage
An error measurement device and an error measurement method are provided. The optical measurement assembly of the error measurement device includes a light source, an optical lens, and a photoelectric sensor. The light beam emitted by the light source is transmitted to a sensing area on the photoelectric sensor to form a first optical path illuminating on a first light-spot position of the sensing area. The moving stage is moved by a linear displacement, so that the light beam is transmitted to the photoelectric sensor to form a second optical path illuminating on a second light-spot position of the sensing area. The processor calculates a movement error of the moving stage and controls the actuator to drive one or more of the light source, the optical lens, and the photoelectric sensor to perform a relative motion, so that the light beam illuminates on the first light-spot position again. |
| US11335579B2 |
Method for manufacturing a semiconductor package and method for testing bonding strength of composite specimen
A method for manufacturing a semiconductor package includes the following steps. A semiconductor process is performed to form an encapsulated semiconductor device, wherein the encapsulated semiconductor device comprises an encapsulating material and a semiconductor device encapsulated by the encapsulating material. A testing apparatus including a holder body, a positioning mechanism and a force applying bar is provided. The encapsulated semiconductor device is clamed by the holder body. A clamping position of the encapsulated semiconductor device is adjusted by the positioning mechanism. The positioning mechanism is removed. A predetermined force is applied to a part of the encapsulated semiconductor device exposed by the holder body by the force applying bar. If the encapsulated semiconductor device is failed by the predetermined force, a process parameter of the semiconductor process is modified to form a modified encapsulated semiconductor device. |
| US11335578B2 |
Substrate transfer apparatus and method of measuring positional deviation of substrate
A substrate transfer apparatus of the present invention includes: a robot including a hand configured to hold a substrate, and an arm configured to move the hand; a robot control device configured to set a moving path for the hand and control the arm such that the hand moves on the moving path toward a target position; and a camera disposed so as to be able to capture an image of the substrate held by the hand located at a predetermined confirmation position. The robot control device sets the moving path so as to pass through the confirmation position, obtains an image captured by the camera when the hand is located at the confirmation position, calculates a distance between a predetermined environment and the substrate which are taken in the image, and calculates a positional deviation amount from a reference position of the substrate on the basis of the distance. |
| US11335577B2 |
Methods and apparatus to prevent interference between processing chambers
Methods and apparatus to minimize electromagnetic interference between adjacent process chambers of a cluster tool are described. The start time of the subject recipe is controlled based on the electromagnetic process window of the subject process chamber, the electromagnetic window of the first adjacent process chamber and of an optional second adjacent process chamber. The start time of the subject process chamber is controlled to prevent temporal overlap of the electromagnetic window of the subject chamber with the electromagnetic window of an adjacent chamber. |
| US11335576B2 |
Method for molding substrate storing container, mold, and substrate storing container
There is provided a method for molding a substrate storing container 1 including a container main body molding step of molding a container main body 2 in a state where a direction P2 perpendicular to a plane P1 passing through the entire periphery of an end edge of an opening circumferential portion 28 of the container main body 2 is inclined in a direction forming a predetermined angle a2, with respect to a horizontal direction L1 which is a movement direction of the movable die M1 with respect to the fixed die M2, and a pullout step of pulling the container main body 2 molded in the mold space M0 out from the movable die M1 by moving the movable die M1 so as to retreat from the fixed die M2. |
| US11335574B2 |
Light-irradiation type thermal processing method and thermal processing apparatus
From a stage of preheating by a halogen lamp to irradiation with a flash by a flash lamp, a radiation thermometer is used for measuring the temperature of a back surface of a semiconductor wafer. A increased temperature ΔT is determined by which the back surface of the semiconductor wafer is increased in temperature from the preheating temperature by irradiation with a flash. The specific heat of the semiconductor wafer has a known value. Further, the increased temperature ΔT is proportionate to the magnitude of energy applied to a front surface of the semiconductor wafer by irradiation with a flash. Thus, a front surface attained temperature of the semiconductor wafer can be determined using the increased temperature ΔT of the back surface of the semiconductor wafer during irradiation with a flash. |
| US11335573B2 |
Dry etching method and β-diketone-filled container
Disclosed is a dry etching method for etching a metal film on a substrate with an etching gas containing a β-diketone and an additive gas, wherein the metal film contains a metal element capable of forming a complex with the β-diketone; and wherein the amount of water contained in the etching gas is 30 mass ppm or less relative to the amount of the β-diketone. It is preferable that the β-diketone used for the dry etching method is supplied from a β-diketone filled container, wherein the β-diketone filled container has a sealed container body filled with a β-diketone whose water content is 15 mass ppm or less relative to the β-diketone. This etching method enables etching of the metal film while suppressing etching rate variations from the initial stage to the later stage of use of the filled container. |
| US11335569B2 |
Conductive wire structure and manufacturing method thereof
A method of manufacturing a conductive wire structure including following steps is provided. A conductive layer is formed on a substrate. A rectangular ring spacer is formed on the conductive layer by a self-aligned double patterning process. A patterned photoresist layer is formed. The patterned photoresist layer exposes a first portion and a second portion of the rectangular ring spacer. The first and second portions are located at two corners on a diagonal of the rectangular ring spacer. The first and second portions are removed by using the patterned photoresist layer as a mask to form a first spacer and a second spacer. The first spacer and the second spacer are L-shaped. The patterned photoresist layer is removed. A pattern of the first spacer and a pattern of the second spacer are transferred to the conductive layer to form an L-shaped first conductive wire and an L-shaped second conductive wire. |
| US11335564B2 |
Element chip smoothing method and element chip manufacturing method
An element chip smoothing method including: an element chip preparation step of preparing at least one element chip including a first surface covered with a resin film, a second surface opposite the first surface, and a sidewall connecting the first surface to the second surface and having ruggedness; a sidewall cleaning step of exposing the element chip to a first plasma, to remove deposits adhering to the sidewall, with the resin film allowed to continue to exist; a sidewall oxidation step of exposing the element chip to a second plasma, after the sidewall cleaning step, to oxidize a surface of the sidewall, with the resin film allowed to continue to exist; and a sidewall etching step of exposing the element chip to a third plasma, after the sidewall oxidation step, to etch the sidewall, with the resin film allowed to continue to exist. |
| US11335561B2 |
Apparatus for laser irradiation and method for laser irradiation
A laser irradiation apparatus includes: a laser module configured to emit a laser beam; a first optical system configured to scan the laser beam emitted from the laser module along a first direction; an optical element configured to refract the laser beam emitted from the first optical system; and a substrate supporter on which a base substrate to which the laser beam refracted through the optical element reaches is arranged. |
| US11335547B2 |
Top down analysis of antibodies in mass spectrometry
A separation device separates an unknown intact mAb or reduced mAb subunits of a known mAb class from a sample. An ion source device ionizes the mAb. A mass spectrometer fragments the ionized mAb using an ECD device and mass analyzes resulting product ions using a mass analyzer, producing one or more product ion spectra. Theoretical product ion peaks are calculated for one or more constant portions of the mAb class. The theoretical product ion peaks are removed from the one or more product ion spectra, producing one or more difference product ion spectra. De novo sequencing is applied to the one or more difference product ion spectra, producing one or more candidate sequences for one or more variable portions of the mAb. A genome database is searched for matches to the one or more candidate sequences, producing one or more matched sequences for the one or more variable portions. |
| US11335545B2 |
Ambient ionization mass spectrometry imaging platform for direct mapping from bulk tissue
A method of ion imaging is disclosed that includes automatically sampling a plurality of different locations on a sample using a front device which is arranged and adapted to generate aerosol, smoke or vapour from the sample. Mass spectral data and/or ion mobility data corresponding to each location is obtained and the obtained mass spectral data and/or ion mobility data is used to construct, train or improved a sample classification model. |
| US11335544B2 |
Plasma processing apparatus
A plasma processing apparatus includes a balun having a first unbalanced terminal, a second unbalanced terminal, a first balanced terminal, and a second balanced terminal, a grounded vacuum container, a first electrode electrically connected to the first balanced terminal, and a second electrode electrically connected to the second balanced terminal. When Rp represents a resistance component between the first balanced terminal and the second balanced terminal when viewing a side of the first electrode and the second electrode from a side of the first balanced terminal and the second balanced terminal, and X represents an inductance between the first unbalanced terminal and the first balanced terminal, 1.5≤X/Rp≤5000 is satisfied. |
| US11335542B2 |
Plasma processing apparatus
A plasma processing apparatus includes: a processing container; a stage provided in the processing container and configured to place a substrate on the stage; a gas introduction part provided in an upper portion of the processing container to face the stage and configured to introduce a processing gas into the processing container; and an annular exhaust path which is provided in an upper portion of a side wall of the processing container, and in which an opening toward a center of the processing container is formed at an inner circumferential side of the exhaust path, wherein the stage and the gas introduction part are respectively connected to high-frequency power supplies for generating plasma of the processing gas, wherein the exhaust path is grounded, wherein the plasma processing apparatus further comprises a grounded plasma distribution adjuster covering the opening, and wherein through-holes are formed in the plasma distribution adjuster. |
| US11335540B2 |
Impedance matching network and method
In one embodiment, an impedance matching network includes a mechanically variable capacitor (MVC), a second variable capacitor, and a control circuit. The control circuit carries out a first process of determining a second variable capacitor configuration for reducing a reflected power at the RF source output, and altering the second variable capacitor to the second variable capacitor configuration. The control circuit also carries out a second process of determining an RF source frequency, and, upon determining that the RF source frequency is outside, at a minimum, or at a maximum of a predetermined frequency range, determining a new MVC configuration to cause the RF source frequency, according to an RF source frequency tuning process, to be altered to be within or closer to the predetermined frequency range. The determination of the new MVC configuration is based on the RF source frequency and the predetermined frequency range. |
| US11335539B2 |
Systems and methods for optimizing power delivery to an electrode of a plasma chamber
A method for optimizing delivery of power to a plasma chamber is described. The method includes dividing each cycle of a low frequency (LF) radio frequency generator (RFG) into multiple time intervals. During each of the time intervals, a frequency offset of a high frequency (HF) RFG is generated for which the delivery of power is maximized. The frequency offsets provide a substantially inverse relationship compared to a voltage signal of the LF RFG for each cycle of the voltage signal. The frequency offsets for the time intervals are multiples of the low frequency. The substantially inverse relationship facilitates an increase in the delivery of power to the electrode. A total range of the frequency offsets from a reference HF frequency over the LF RF cycle depends on a power ratio of power that is supplied by the LF RFG and power that is supplied by the HF RFG. |
| US11335535B2 |
Charged particle beam apparatus
Provided is a charged particle beam apparatus capable of estimating an internal device structure of a sample. The charged particle beam apparatus includes an electron beam optical system, a detector, and a calculator. The electron beam optical system irradiates a plurality of irradiation points on a sample, which are different in position or time, with an electron beam. The detector detects electrons emitted from the sample in response to irradiation of the electron beam by the electron beam optical system. The calculator calculates a dependence relationship between the irradiation points based on the electrons detected by the detector at the plurality of irradiation points. |
| US11335533B2 |
Charged particle beam device
The purpose of the present invention is to provide a charged particle beam device which suppresses sample deformation caused by placing a sample on a suctioning surface of an electrostatic chuck mechanism, the sample having a temperature different from the suctioning surface. Proposed is a charged particle beam device which has an electrostatic chuck mechanism, the charged particle beam device being provided with: a stage (200) which moves a sample, which is to be irradiated with a charged particle beam, relative to an irradiation position of the charged particle beam; an insulating body (203) which is disposed on the stage and constitutes a dielectric layer of the electrostatic chuck; a first support member (402) which supports the insulating body on the stage; a ring-shaped electrode (400) which encloses the surroundings of the sample and is installed on the insulating body in a contactless manner, and to which a predetermined voltage is applied; and a second support member (405) which supports the ring-shaped electrode. |
| US11335529B2 |
Thermally enhanced compound field emitter
A compound field emitter (CFE) includes a first surface possessing a field enhancement factor >1, and a second surface possessing one or both of a field enhancement factor >1, or a low work function, wherein the second surface is coated, formed or applied upon the first surface. The second surface has a characteristic size at least 3 times smaller than the first surface, and the outer surface includes a coating of calcium aluminate 12CaO-7Al2O3. |
| US11335525B2 |
Electromagnetic relay
An electromagnetic relay includes: a coil; a housing that supports the coil; a non-movable portion supported by the housing and including a fixed core and a fixed magnetic path defining member; and a movable portion provided to be reciprocally movable along a center axis line of the coil according to an energization state of the coil. The movable portion includes a movable core disposed to face the fixed core along the center axis line. The movable portion integrally has a flange portion protruding in a coil radial direction perpendicular to the center axis line to define a separation distance and/or a facing area in a magnetic gap between the fixed magnetic path defining member and the movable core by abutting against the non-movable portion. |
| US11335524B2 |
Electrical switching system
An electrical switching device includes: a main contact arrangement including a fixed contact and a movable contact, a plurality of splitter plates, each having a loop structure, the splitter plates being coaxially stacked with respect to their loop structure to form a stack, wherein one splitter plate is a first outermost plate and another splitter plate is a second outermost plate, a first arc runner electrically connected to the second outermost plate and a second arc runner electrically connected to the first outermost plate, the first and second arc runners being configured to direct a main arc from the main contact arrangement to the stack to thereby split the main arc into a plurality of secondary arcs between the splitter plates, and a first drive coil electrically connected to the second arc runner and to the movable contact or to the first arc runner and to the fixed contact. |
| US11335521B2 |
Input apparatus
An input apparatus includes a base member, an operating member provided so as to be vertically movable with respect to the base member, the operating member being to be pushed down, a circuit board fixed to the base member and provided under the operating member, a push switch provided on a lower surface of the circuit board, and a link mechanism including a rotational member disposed under the circuit board such that a rotation center shaft is rotatably held by the base member, the rotational member pushing the push switch upward by rotating in response to a push-down operation of the operating member. |
| US11335519B2 |
Electrical current switching unit
A switching unit for switching an electrical current, the unit comprising separable fix and mobile electrical contacts and a mechanism capable of switching over the contacts between a closed state and an open state. The mechanism comprises a switching shaft coupled to a mobile electrical contact, a trip hook mounted to be pivoted on a fixed support of the mechanism and comprising a bore in which is housed an abutment and a link system coupling the switching shaft to the trip hook. The link system comprises an articulated linkage, which is rotationally linked with respect to the trip hook and which comprises a main bearing surface, which bears on the abutment when the switching mechanism is in the closed state. The abutment is configured to be elastically deformed when the switching mechanism passes from the open state to the closed state and the linkage exerts an effect on the abutment, so as to damp the impact of the linkage on the abutment. |
| US11335518B2 |
Switching element guide
An improved switching device includes a guide configured to reduce undesired movement of the switching element. The guide includes an upper portion configured to receive the switching element and a lower portion configured to receive a spring. The upper portion defines a seat to receive the switching element and includes at least one resilient tab to retain the switching element within the guide. The lower portion defines an opening in which the spring is positioned, where the spring is seated, in part, against the switching element and against the guide. The guide includes guide portions configured to engage a housing on the switching device to prevent rotation of the switching element within the switching device. The switching element further includes protrusions configured to engage each side of the guide and to prevent longitudinal movement of the switching element within the housing. |
| US11335516B2 |
High-capacity micro-supercapacitor, method of manufacturing high-capacity micro-supercapacitor, and method of forming current collector for micro-supercapacitor
Disclosed herein is a method of manufacturing a micro-supercapacitor with an increased storage capacity of electrical energy. The method is a method of manufacturing a high-capacity micro-supercapacitor including an anode and a cathode separated from each other, which includes forming a pair of current collectors by discharging conductive ink on a substrate surface with a 3D printer, and forming an electrode consisting of an anode and a cathode by stacking an electrode constituting material in the form of a plurality of layers on each of the pair of current collectors using the 3D printer. |
| US11335515B2 |
Capacitive energy storage device and method of producing the same
The invention provides a capacitive energy storage device comprising: at least one porous film infiltrated with an electrolyte; and one or more pairs of separated electrodes disposed on top of a first surface of the porous film, each electrode comprising a capacitive electrode material in ionic communication with the underlying porous film, wherein the electrolyte provides ionic communication between the separated electrodes via the internal porosity of the porous film. |
| US11335514B2 |
Solar cell
The present invention aims to provide a solar cell that includes a photoelectric conversion layer containing an organic-inorganic perovskite compound and that can exhibit high photoelectric conversion efficiency and high heat resistance. Provided is a solar cell including, in the stated order: a cathode; a photoelectric conversion layer; and an anode, the photoelectric conversion layer containing an organic-inorganic perovskite compound represented by the formula R-M-X3 where R is an organic molecule, M is a metal atom, and X is a halogen atom or a chalcogen atom, and a polymer having an acid dissociation constant pKa of 3 or less. |
| US11335507B2 |
Multi-layer ceramic capacitor and method of producing the same
A multi-layer ceramic capacitor includes a multi-layer unit and a side margin. The multi-layer unit includes a capacitance forming unit and a cover. The capacitance forming unit includes ceramic layers laminated in a first direction and internal electrodes disposed between the ceramic layers and mainly containing nickel. The cover covers the capacitance forming unit from the first direction. The side margin covers the multi-layer unit from a second direction orthogonal to the first direction. The internal electrodes each include an oxidized area adjacent to the side margin and intensively including a metal element that forms an oxide together with nickel. The capacitance forming unit includes a first portion adjacent to the cover and a second portion adjacent to the first portion in the first direction and including the oxidized area having a smaller dimension in the second direction than that of the oxidized area of the first portion. |
| US11335506B2 |
Ceramic electronic component
A ceramic electronic component includes a body including a capacitance formation portion including a dielectric layer and a plurality of internal electrodes disposed to face each other with the dielectric layer interposed therebetween and forming capacitance and protective portions disposed on upper and lower surfaces of the capacitance formation portion and external electrodes including electrode layers disposed on the body and connected to the plurality of internal electrodes and conductive resin layers respectively disposed on the electrode layers, wherein ta2/ta1 is 0.05 or greater, where ta1 is the thickness of the electrode layer at a central portion of the capacitance formation portion and ta2 is the thickness of the electrode layer at a boundary between the capacitance formation portion and the protective portion. |
| US11335504B2 |
Film capacitor, combination type capacitor, inverter, and electric vehicle
A film capacitor includes a main body portion. A dielectric film of the main body portion includes an insulation margin in a first direction. A first metal film and a second metal film are each separated by first slits which each includes a first end which is at an angle of θ1 to the second side face, and second slits. The second slit is connected at a contact point to the first slit, and includes a second end which is located on a negative side in the first direction relative to the contact point. The second end is positioned in alignment with a first end of a first slit which is continuous with the second slit adjacent thereto on the negative side in the first direction. A value of tan (θ1) is in a range of 0.15 or more and 0.35 or less. |
| US11335499B2 |
Reactor
A small size reactor that effectively utilizes a space is provided. This reactor includes: a reactor body which includes a core and a coil attached to the core, a casing which houses therein the reactor body and which has an opening where a part of the reactor body protrudes outwardly, a bus bar which is a conductive component electrically connected to the coil and which covers a part of a side of the reactor body protruding from the opening, and a terminal stage which includes an extended portion formed of a resin material where a part of the bus bar is embedded and provided along an edge of the opening, and which supports an electrical connection portion between the bus bar and an exterior. |
| US11335496B2 |
Coil component
A coil component includes a body having a bottom surface and a top surface opposing each other in one direction, and a plurality of walls each connecting the bottom surface to the top surface of the body; recesses respectively formed in both front and rear surfaces of the body opposing each other among the plurality of walls of the body and extending up to the bottom surface of the body; a coil portion buried in the body and including first and second lead-out portions exposed to internal walls and lower ledge surfaces of the recesses; first and second external electrodes respectively including connection portions disposed in the recesses and extended portions disposed on the bottom surface of the body, and connected to the coil portion; a shielding layer including a cap portion disposed on the top surface of the body and side wall portions respectively disposed on the plurality of walls of the body; and an insulating layer disposed between the body and the shielding layer and extending onto lower ledge surfaces and internal walls of the recesses to cover the connection portions. |
| US11335495B1 |
System to optimize voltage distribution along high voltage resistor string in ICT high voltage power supply
An Insulated Core Transformer (ICT) high voltage DC power supply is disclosed. The power supply comprises a plurality of printed circuit boards, each comprising a secondary winding and a voltage doubler circuit. These voltage doubler circuits are arranged in series. The stacked printed circuit boards are surrounded by a plurality of grading rings. The last grading ring is electrically connected to the output voltage. High voltage resistors are then disposed between adjacent grading rings to form a voltage divider. The voltage of the first grading ring may be used as part of a feedback system to regulate the output of the AC power supply. By disposing the high voltage resistors on the grading rings, a more uniform voltage gradient may be created. |
| US11335493B2 |
Integrated transformer
An integrated transformer arrangement for combining output signals of multiple differential power amplifiers to a single-ended load. The integrated transformer arrangement comprises a first transformer branch comprising an inductor loop. The inductor loop comprises a set of N windings connected in series. The first transformer branch further comprises a number of primary inductors. Each primary inductor comprises a winding placed concentrically to one winding of the inductor loop, and each primary inductor is configured to couple to a differential output of one of the multiple differential power amplifiers. The integrated transformer arrangement further comprises a secondary inductor comprising a winding placed concentrically to a winding of the inductor loop, and the secondary inductor is configured to couple to the single-ended load. |
| US11335492B2 |
Solenoid plunger movement detection system
A solenoid plunger movement detection system and method can include: detecting current supplied to a solenoid with a current sensor; converting the current supplied to the solenoid into a digital signal with a counter coupled to a first comparator; detecting a peak within the digital signal with a peak detector; comparing the peak to the digital signal with a second comparator coupled to the peak detector; measuring a dip from the peak and measuring a trough with the second comparator; generating a fault when the peak and the trough indicate a smooth current ramp to the solenoid; receiving configurable parameters for processing the digital signal with a signal processor; and providing configurable parameters to the counter, the second comparator, the signal processor, or a combination thereof with an interface. |
| US11335491B2 |
Fluid servo valve and fluid servo apparatus
The present invention controls the pressure and flow rate of fluid, in order to obtain uniform performance, configure a closed loop magnetic circuit so as to include an electromagnet, a flapper, and a yoke material, and elastically deform the flapper itself by Maxwell attractive force generated between a magnetic pole of the electromagnet and the flapper to make the separation distance between the nozzle and the flapper variable. As opposed to a rigid flapper structure that swingably moves around a supporting point, like a conventional servo valve, the electromagnet, the magnetic pole, the nozzle, the flapper, and the like are arranged such that a change in magnetic gap directly leads to a change in air gap. |
| US11335483B2 |
Magnet structure
The present invention provides a magnet structure comprising a first magnet, a second magnet, and an intermediate layer joining the first magnet and the second magnet. In the magnet structure, each of the first magnet and the second magnet is a permanent magnet comprising a rare earth element R, a transition metal element T, and boron B. In addition, the rare earth element R comprises: a light rare earth element RL comprising at least Nd; and a heavy rare earth element RH, and the transition metal element T comprises Fe, Co, and Cu. Further, the intermediate layer comprises: an RL oxide phase comprising an oxide of the light rare earth element RL; and an RL—Co—Cu phase comprising the light rare element RL, Co, and Cu. |
| US11335478B2 |
Compression and stretch resistant components and cables for oilfield applications
An opto-electrical cable may include an opto-electrical cable core and a polymer layer surrounding the opto-electrical cable core. The opto-electrical cable core may include a wire, one or more channels extending longitudinally along the wire, and one or more optical fibers extending within each channel. The opto-electrical cable may be made by a method that includes providing a wire having a channel, providing optical fibers within the channel to form an opto-electrical cable core, and applying a polymer layer around the opto-electrical cable core. A multi-component cable may include one or more electrical conductor cables and one or more opto-electrical cables arranged in a coax, triad, quad configuration, or hepta configuration. Deformable polymer may surround the opto-electrical cables and electrical conductor cables. |
| US11335477B2 |
High voltage power cable with fatigue-resistant water barrier
A power cable has an insulated conductor; a copper water barrier, in form of a tube with a welding line, surrounding each insulated conductor; and a polymeric sheath surrounding each copper water barrier. The copper water barrier has a thickness and the polymeric sheath has a thickness such that a ratio between the thickness of the copper water barrier and the thickness of the polymeric sheath is 0.15 at most. |
| US11335468B2 |
Fuel pellet
A uranium oxide fuel pellet having an inner region and an outer rim region about the inner region, and that the fuel pellet is cylindrical and the inner region and outer rim region are coaxial cylindrical regions. The outer rim region has an excess of oxygen in comparison to the inner region, wherein high burnup structure (HBS) formation will be suppressed or delayed. Preferably, the excess oxygen is obtained by a chemical treatment by immersing the pellet in hydrogen peroxide (H2O2) or potassium permanganate (KMnO4) in solution. |
| US11335467B2 |
Systems and methods for improved sustainment of a high performance FRC and high harmonic fast wave electron heating in a high performance FRC
Systems and methods that facilitate forming and maintaining FRCs with superior stability as well as particle, energy and flux confinement and, more particularly, systems and methods that facilitate forming and maintaining FRCs with elevated system energies and improved sustainment utilizing neutral beam injection and high harmonic fast wave electron heating. |
| US11335464B2 |
Integrated precision medicine by combining quantitative imaging techniques with quantitative genomics for improved decision making
Disclosed herein is a combined multi-modality biomarker method for identification and treatment of a disease comprising performing quantitative and/or semi-quantitative molecular imaging on a patient; where the semi-quantitative imaging includes a cut-off; measuring a first plurality of parameters from the quantitative and/or semi-quantitative molecular imaging; simultaneously or sequentially performing a liquid biopsy on the patient; measuring a second plurality of quantitative and/or semi-quantitative molecular parameters from the liquid biopsy; developing an algorithm that combines one or more of the first plurality of parameters and one or more of the second plurality of parameters; where the algorithm is operative to identify a disease and/or predict a course of treatment and/or monitoring the patient; and treating the patient with the course of treatment generated by the algorithm. |
| US11335463B2 |
Cancer evolution detection and diagnostic
The present disclosure provides methods for determining a probability that after any of a number of therapeutic interventions, an initial state of a subject, such as somatic cell mutational status of a subject with cancer, will develop a subsequent state. Such probabilities can be used to inform a health care provider as to particular courses of treatment to maximize probability of a desired outcome for the subject. |
| US11335456B2 |
Sensing device for medical facilities
A medical system may utilize a modular and extensible sensing device to derive a two-dimensional (2D) or three-dimensional (3D) human model for a patient in real-time based on images of the patient captured by a sensor such as a digital camera. The 2D or 3D human model may be visually presented on one or more devices of the medical system and used to facilitate a healthcare service provided to the patient. In examples, the 2D or 3D human model may be used to improve the speed, accuracy and consistency of patient positioning for a medical procedure. In examples, the 2D or 3D human model may be used to enable unified analysis of the patient's medical conditions by linking different scan images of the patient through the 2D or 3D human model. In examples, the 2D or 3D human model may be used to facilitate surgical navigation, patient monitoring, process automation, and/or the like. |
| US11335455B2 |
Method for managing annotation job, apparatus and system supporting the same
A computing device obtains information about a medical slide image, and determines a dataset type of the medical slide image and a panel of the medical slide image. The computing device assigns to an annotator account, an annotation job defined by at least the medical slide image, the determined dataset type, an annotation task, and a patch that is a partial area of the medical slide image. The annotation task includes the determined panel, and the panel is designated as one of a plurality of panels including a cell panel, a tissue panel, and a structure panel. The dataset type indicates a use of the medical slide image and is designated as one of a plurality of uses including a training use of a medical learning model and a validation use of the machine learning model. |
| US11335454B2 |
Biopsy device for digital pathology and artificial intelligent analytics
An in vivo of insitu bio-matter sample magnified digital image creating device for realtime biopsy determinations having a sharp edged window pocket coupled to housing having an optical and digital magnification path coupled to image detecting sensor logic. The device has an optical two blade window pocket rotatably coupled to a stem mechanically controlled and extendable from mechanism within the housing, the stem having source for at least one fiber optical channel for selected frequency and wavelength light various light sources, an optical two blade window pocket slide component optically coupled to the two blade window pocket fiber optic channel stem distal end, providing light through the two blade window pocket slide normal axis surface for illumination penetrating a bio matter assay or sample for imaging through an optical microscopy magnification path axis to a micrograph image sensor. The resulting image micrographs for digital pathology realtime result determination. |
| US11335453B1 |
Systems and methods for displaying hubs in brain data
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for displaying hubs in brain data. One of the methods includes receiving hub data, the hub data comprising anatomical data and connectivity data of at least part of a brain, the connectivity data comprising a first plurality of nodes and a second plurality of edges, each edge of the second plurality of edges connecting a pair of nodes among the first plurality of nodes; forwarding the hub data to a user computer for display; receiving a first user indication requesting a display of unexpected hub data; determining, in response to the first user indication, unexpected hub data comprising nodes that have connectivity outside of a specified threshold; and forwarding the unexpected hub data to the user computer for display. |
| US11335452B2 |
Enabling the use of multiple picture archiving communication systems by one or more facilities on a shared domain
Methods, systems, and computer-storage media are provided for utilizing multiple Picture Archiving Communication Systems (PACS) to view one more medical images by storing one or more PACS at a database within the system. Requests are received from one or more users at one or more facilities to utilize one or more PACS to view one or more medical images. After accessing the database to determine one or more PACS authorized for each facility from which a request is received, one or more users are provided with one or more PACS to view medical images associated with radiological exams and provide the necessary assessments and reports for treatment. |
| US11335451B2 |
Method and system for improving wellbeing of a person using a digital character
Efforts have been made in the past to improve the wellbeing of a person. Various methods involve use of virtual pet character which can interact with the person. But these methods are mainly for entertainment purpose, people get bored quickly. Moreover, the present application doesn't take into the input of the present state of user. A method and system for improving wellbeing of person using a digital character such as virtual pet has been provided. The system maintains a wellbeing index for both the user and digital character. A set of activities are provided which is performed by the digital character and the user. Further, a response of the user is also captured depending on the current wellbeing index using a set of questionnaire. And a second set of activities are recommended based on the response to further improve the wellbeing index of the person. |
| US11335448B2 |
Systems and methods for medication management
A method for managing medication, comprising the steps of: providing a server having databases, including a drug-to-drug interaction database, a drug-to-allergy interaction database, and a database of user profiles; detecting a current time of a first user, the first user being associated with a first user's profile within the database of user profiles, wherein the first user's profile comprises a medication list; providing a medication dispenser adapted to store and dispense medication associated with a first medication prescription of the medication list, the first medication prescription having a set of instructions for consumption by the first user; adding the first medication prescription to the first user's profile; implementing a reminder schedule according to the set of instructions and the current time detected; sending consumption reminder notifications to the first user according to the reminder schedule; and tracking adherence by the first user to the set of instructions. |
| US11335446B2 |
Method of optimizing healthcare services consumption
A method of optimizing healthcare services consumption according to the invention includes the steps of assessing the healthcare situation of an employer providing healthcare benefits to a population, identifying a first group of patients from the population likely to generate expensive healthcare claims based on data representing past claims, periodically determining whether patients in the first group have satisfied certain predetermined healthcare requirements, identifying a first group of providers who provide high quality, cost efficient healthcare services based on the practice patterns of the providers, prompting patients who have not satisfied the predetermined healthcare requirements to obtain services from providers in the first group, and responding to healthcare requests from patients by determining whether the requesting patient is seeking services from a provider in the first group, and, if not, urging the patient to obtain such services from a provider in the first group. |
| US11335445B2 |
Method, apparatus, and system to manage patient treatment
A care plan risk rating (CPR2) system and method enables physicians and other clinicians to manage patient health care plans remotely in response to patient input to generate CPR2 values. In one aspect, patients under care for a particular condition respond to a series of questions related to that condition. The questions may be weighted according to predetermined criteria which a physician or clinician may set. Based on the CPR2 values, the physician or clinician may alter a care plan for a patient or a group of patients. In one aspect, patients with CPR2 values in a predetermined range may be grouped into a cohort, and their care plans managed as a group. |
| US11335439B2 |
Systems and methods for generating, visualizing and classifying molecular functional profiles
Various methods, systems, computer readable media, and graphical user interfaces (GUIs) are presented and described that enable a subject, doctor, or user to characterize or classify various types of cancer precisely. Additionally, described herein are methods, systems, computer readable media, and GUIs that enable more effective specification of treatment and improved outcomes for patients with identified types of cancer. Some embodiments of the methods, systems, computer readable media, and GUIs described herein comprise obtaining RNA expression data and/or whole exome sequencing (WES) data for a biological sample from a subject; determining a molecular-functional (MF) profile for the subject; identifying an MF profile cluster with which to associate the MF profile for the subject; and clustering the plurality of MF profiles to obtain the MF profile clusters. |
| US11335438B1 |
Detecting false positive variant calls in next-generation sequencing
A method for detecting false positive variant calls in a next generation sequencing analysis pipeline involves obtaining a plurality of read pileup windows associated with a first sample genome. The method also involves obtaining, for each reference nucleotide position represented in the plurality of read pileup windows, a label indicating that the reference nucleotide position is either (i) a known variant or (ii) a non-variant. The method further involves training a neural network based on data indicative of the plurality of read pileup windows and the labels. Additionally, the method involves receiving a read pileup window associated with a second sample genome. Further, the method involves determining, using the trained neural network, a likelihood that the read pileup window associated with the second sample genome represents a variant. |
| US11335435B2 |
Identifying ancestral relationships using a continuous stream of input
Identification of inheritance-by-descent haplotype matches between individuals is described. A set of tables including word match, haplotypes and segment match tables are populated. DNA samples are received and stored. A word identification module extracts haplotype values from each sample. The word match table is indexed according to the unique combination of position and haplotype. Each column represents a different sample, and each cell indicates whether that sample includes that haplotype at that position. The haplotypes table includes the raw haplotype data for each sample. The segment match table is indexed by sample identifier, and columns represent other samples. Each cell is populated to indicate for each identified sample pair which position range(s) include matching haplotypes for both samples. The tables are persistently stored in databases of the matching system. As new sample data is received, each table is updated to include the newly received samples, and additional matching takes place. |
| US11335434B2 |
Feature selection for efficient epistasis modeling for phenotype prediction
Various embodiments select markers for modeling epistasis effects. In one embodiment, a processor receives a set of genetic markers and a phenotype. A relevance score is determined with respect to the phenotype for each of the set of genetic markers. A threshold is set based on the relevance score of a genetic marker with a highest relevancy score. A relevance score is determined for at least one genetic marker in the set of genetic markers for at least one interaction between the at least one genetic marker and at least one other genetic marker in the set of genetic markers. The at least one interaction is added to a top-k feature set based on the relevance score of the at least one interaction satisfying the threshold. |
| US11335430B2 |
Error remapping
Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses. |
| US11335428B2 |
Methods, systems and apparatus for in-field testing for generic diagnostic components
The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing. |
| US11335425B2 |
Memory system quality integral analysis and configuration
A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system health threshold. Formulating the comparison to these metrics can include determining an area between a baseline frequency and a curve specified by the CDF-based data. In some implementations, this area can further be defined by a lowest frequency bound and/or can be compared as a ratio to an area of a rectangle that contains the CDF curve. |
| US11335422B2 |
Semiconductor memory device and memory system
A semiconductor memory device includes: a first memory cell and switching element coupled in series between a first and second interconnect; a second memory cell and switching element coupled in series between the first and a third interconnect; a third memory cell and switching element coupled in series between the first and a fourth interconnect; and a control circuit. The control circuit is configured to: in a first operation on the first memory cell, upon receipt of a first command, apply a third voltage between the first and second voltage to the third and fourth interconnect; and upon receipt of a second command, apply the first and third voltage to the fourth and third interconnect, respectively. |
| US11335418B2 |
Memory device including dynamic programming voltage
Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells. |
| US11335416B1 |
Operational modes for reduced power consumption in a memory system
Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor. |
| US11335415B2 |
Memories having multiple voltage generation systems connected to a voltage regulator
Memories having an array of memory cells might include a plurality of voltage generation systems each having a respective output selectively connected to a respective access line, and a voltage regulator having an input connected to the output of each of the voltage generation systems, and having an output selectively connected to the respective access line for each of the voltage generation systems. |
| US11335411B1 |
Erase operation for memory device with staircase word line voltage during erase pulse
Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation applies a staircase or multi-level word line voltage concurrent with a fixed level erase pulse to provide multiple channel-to-gate voltages. Current consumption and time are saved compared to applying a multi-level erase voltage to a high capacitance substrate, for example. In one approach, the word line voltage is changed from a positive erase-enable voltage to a negative erase-enable voltage during the multi-level erase pulse. A step size of a next erase pulse can be set to achieve an approximately constant step increase in channel-to-gate voltages of the memory cells. |
| US11335410B2 |
Memory device and method of operating the same
A memory device that controls a floating time point of word lines connected to a sub block adjacent to a sub block on which an erase operation is performed includes a plurality of memory blocks each including a plurality of sub blocks, a voltage generator configured to generate a plurality of voltages to perform an erase operation on any of the plurality of sub blocks, and control logic configured to divide a plurality of word lines connected to an adjacent sub block neighboring a sub block on which the erase operation is performed into a plurality of groups, and configured to control the voltage generator to differently set a floating time point of word lines included in each group for each of the plurality of groups, during the erase operation. |
| US11335399B2 |
Electronic device for configuring neural network
Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line. |
| US11335395B2 |
Applying chip select for memory device identification and power management control
A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line. |
| US11335394B2 |
Temperature informed memory refresh
Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element. |
| US11335390B1 |
Negative word line biasing for high temperature read margin improvement in MRAM
An electronic biasing circuit for memory operating in a high temperature environment, comprising a first memory cell and a second memory cell, a first MOSFET transistor electrically coupled in series with the first memory cell, wherein the first MOSFET transistor is configured as a switch, a second MOSFET transistor electrically coupled in series with the second memory cell, wherein the second MOSFET transistor is configured as a switch, a DC bias current source configured to generate a negative DC bias voltage signal, a first read/word line electrically coupled to a gate of the first MOSFET transistor, and a second read/word line electrically coupled to a gate of the second MOSFET transistor, wherein in response to a read operation of the first memory cell, the second read/word line is configured to deliver the negative DC bias voltage signal to the gate of the second MOSFET transistor. |
| US11335386B1 |
Calibration circuit and semiconductor device including the same
A semiconductor device which includes a termination circuit coupled to a first pad and suitable for providing a termination resistance according to a first control code and a second control code during a normal operation in which data are input and output through the first pad; a stress replica circuit suitable for replicating a stress applied to the termination circuit during the normal operation and for generating a detection code during a second calibration mode; a first calibration circuit suitable for adjusting the first control code to match an impedance of a resistor part coupled to a second pad to an external resistor during a first calibration mode; and a second calibration circuit suitable for generating the second control code by adjusting the first control code according to the detection code during the second calibration mode. |
| US11335385B2 |
Apparatuses including temperature-based threshold voltage compensated sense amplifiers and methods for compensating same
Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder. |
| US11335383B2 |
Memory component for a system-on-chip device
The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure. |
| US11335376B1 |
Drive controller-override mechanism
A data storage device includes a primary storage media, a drive storage controller electrically coupled to media recording electronics and a controller-override mechanism. The controller-override mechanism is selectively controllable by a user to override control actions of the drive storage controller to prevent the drive storage controller from altering the primary storage media at a time when the storage device is otherwise configured for nominal data storage operations. |
| US11335375B2 |
Magnetic disk device and error correction method
According to one embodiment, a magnetic disk device includes a disk, a head that writes data to the disk and reads data from the disk, and a controller that executes error correction on a first sector which is unreadable in a first track from an initial reading time of initially one-round reading the first track of the disk based on first parity data corresponding to the first track. |
| US11335371B2 |
Reproduction apparatus and reproduction method
A reproduction apparatus dividing a cross section of superposed light into a plurality of regions in a tangential and/or radial direction includes: an optical system configured to generate each of a first set of signal light and reference light having a phase difference of approximately 0°, a second set of signal light and reference light having a phase difference of approximately 180°, a third set of signal light and reference light having a phase difference of approximately 90°, and a fourth set of signal light and reference light having a phase difference of approximately 270°, using a plurality of superposed light beams corresponding to the divided regions; an optical receiver configured to output signals corresponding to the sets of the signal light and the reference light; and a circuit configured to compute signals as differences between the signals, and obtain a reproduction signal by computation from the computed signals. |
| US11335368B2 |
Recording tape cartridge
Provided is a recording tape cartridge including: a case that is configured by causing a peripheral wall of an upper case and a peripheral wall of a lower case to abut against each other and accommodates a reel on which a recording tape is wound; a reference surface that is formed on the lower case and serves as a reference in an axial direction of the reel in a case where the case is loaded into a drive device; a noncontact communication medium on which individual information is recorded, the noncontact communication medium being accommodated in the lower case and having a plate shape; a supporting portion that is formed on the lower case and supports the noncontact communication medium such that the noncontact communication medium is disposed while being inclined with respect to the reference surface at an angle of approximately 45 degrees; a position restricting portion that is formed on the lower case and restricts a position of a lower end portion of the noncontact communication medium; and a retaining portion that is formed on the lower case and retains an upper end portion of the noncontact communication medium. |
| US11335366B2 |
Magnetic disk device and read processing method
According to one embodiment, a magnetic disk device includes a disk including a first sector arranged at a first radial position deviated from a target position in a radial direction by a first offset amount larger than a first threshold value, a head that writes data to the disk and reads data from the disk, and a controller that reads the first sector by arranging the head at a second radial position deviated from the target position by a second offset amount different from the first offset amount. |
| US11335356B2 |
Digital audio processing device, digital audio processing method, and digital audio processing program
A local extremum calculator detects a local maximum sample and a local minimum sample of a digital audio signal. A number-of-sample detector detects a sample interval between the local maximum sample and the local minimum sample. A difference value calculator calculates difference values between adjacent samples. A correction value calculator calculates a first correction value by multiplying the difference value between the local maximum sample and a first adjacent sample by a coefficient and calculates a second correction value by multiplying the difference value between the local minimum sample and a second adjacent sample by the coefficient. When a periodic signal detector detects that the digital audio signal is a single sine wave, an adder/subtractor does not add the first correction value to the first adjacent sample, and does not subtract the second correction value from the second adjacent sample. |
| US11335352B2 |
Voice identity feature extractor and classifier training
A voice identity feature extractor training method includes extracting a voice feature vector of training voice, The method may include determining a corresponding I-vector according to the voice feature vector of the training voice. The method may include adjusting a weight of a neural network model by using the I-vector as a first target output of the neural network model, to obtain a first neural network model, The method may include obtaining a voice feature vector of target detecting voice and determining an output result of the first neural network model for the voice feature vector of the target detecting voice. The method may include determining an I-vector latent variable. The method may include estimating a posterior mean of the I-vector latent variable, and adjusting a weight of the first neural network model using the posterior mean as a second target output, to obtain a voice identity feature extractor. |
| US11335350B2 |
Dual use of audio noise level in speech-to-text framework
An apparatus includes processor(s) to: perform pre-processing operations including derive an audio noise level of speech audio of a speech data set, derive a first relative weighting for first and second segmentation techniques for identifying likely sentence pauses in the speech audio based on the audio noise level, and select likely sentence pauses for a converged set of likely sentence pauses from likely sentence pauses identified by the first and/or second segmentation techniques based on the first relative weighting; and perform speech-to-text processing operations including divide the speech data set into data segments representing speech segments of the speech audio based on the converged set of likely sentence pauses, and derive a second relative weighting based on the audio noise level for selecting words indicated by an acoustic model or by a language model as being most likely spoken in the speech audio for inclusion in a transcript. |
| US11335349B1 |
Machine-learning conversation listening, capturing, and analyzing system and process for determining classroom instructional effectiveness
A machine-learning conversation listening, capturing, and analyzing system that determines instructional effectiveness is a classroom setting and a machine-learning conversation listening, capturing, and analyzing process for determining classroom instructional effectiveness are disclosed. The machine-learning conversation listening, capturing, and analyzing system and process for determining classroom instructional effectiveness relies on predetermined objective criteria and uses big data, deep learning, and redundancy to validate results. |
| US11335347B2 |
Multiple classifications of audio data
Described herein is a system for sentiment detection in audio data. The system is trained using acoustic information and lexical information to determine a sentiment corresponding to an utterance. In some cases when lexical information is not available, the system (trained on acoustic and lexical information) is configured to determine a sentiment using only acoustic information. |
| US11335346B1 |
Natural language understanding processing
Techniques for processing a user input are described. Text data representing a user input is processed with respect to at least one finite state transducer (FST) to generate at least one FST hypothesis. Context information may be required to traverse one or more paths of the at least one FST. The text data is also processed using at least one statistical model (e.g., perform intent classification, named entity recognition, and/or domain classification processing) to generate at least one statistical model hypothesis. The at least one FST hypothesis and the at least one statistical model hypothesis are input to a reranker that determines a most likely interpretation of the user input. |
| US11335345B2 |
Method for voice control, terminal, and non-transitory computer-readable storage medium
A method for voice control includes: a voice is acquired to obtain a voice signal; image information is obtained; whether a pose attribute of a target object that utters the voice satisfies a preset condition is determined based on the image information; and responsive to that the pose attribute of the target object satisfies the preset condition, an operation indicated by the voice signal is performed. |
| US11335344B2 |
System and method for multi-microphone automated clinical documentation
A method, computer program product, and computing system for receiving a plurality of predefined beams associated with a microphone array. A plurality of predefined nulls associated with the microphone array may be received. One or more predefined beams from the plurality of predefined beams or one or more predefined nulls from the plurality of predefined nulls may be selected. A microphone array may obtain audio encounter information, via the microphone array, using at least one of the one or more selected beams and the one or more selected nulls. |
| US11335343B2 |
Adding audio and video context to smart speaker and voice assistant interaction
The present invention provides automated methods, apparatus, and systems for improving engagement with a voice assistant or smart speaker. Media content playback is detected at a media content detection application and the media content is identified. Upon receiving a voice command from a user at a smart speaker or voice assistant relating to the identified media content, the context of the voice command in relation to the identified media content is determined. The voice command is processed and executed based on the determined context. |
| US11335342B2 |
Voice assistance system
An approach is provided in which the approach captures a voice command spoken by a user along with a set of data generated from a smart contact lens worn by the user. The approach matches the set of data to a command augmentation indicator that identifies an augmentation to the voice command. The approach aggregates the command augmentation indicator with the voice command into an aggregated command and executes the aggregated command accordingly. |
| US11335337B2 |
Information processing apparatus and learning method
An information processing apparatus includes a memory; and a processor coupled to the memory and the processor configured to: generate phoneme string information in which a plurality of phonemes included in voice information is arranged in time series, based on a recognition result of the phonemes for the voice information; and learn parameters of a network such that when the phoneme string information is input to the network, output information that is output from the network approaches correct answer information that indicates whether a predetermined conversation situation is included in the voice information that corresponds to the phoneme string information. |
| US11335336B2 |
Cognitive analysis of public communications
Disclosed herein are system, method, and computer program product embodiments for categorizing customer complaints on social media using a model trained on customer voice calls or chats with agents. Additionally, users interested in monitoring regulatory compliance issues based on customer complaints can receive notifications regarding complaints that are linked to regulatory topic areas, without the need to manually scan vast numbers of social media postings. |
| US11335335B2 |
Disambiguation of generic commands for controlling objects
A computer system performs an action on an object identified from a command. A command is analyzed to perform an action on a target object, wherein the command includes a term for the target object that refers to a plurality of different candidate objects. The target object is identified from the plurality of different candidate objects based on historical associations of the term with specific ones of the candidate objects, recent interactions with the different candidate objects, and a state of the candidate objects provided by network devices. The action is performed on the identified target object. Embodiments of the present invention further include a method and program product for performing an action on an object identified from a command in substantially the same manner described above. |
| US11335331B2 |
Multibeam keyword detection system and method
A system and method provides for multibeam keyword detection. A composite audio signal may include sound components. The system and method groups the sound components into subsets based on the angles of arrival of sound components. Keyword detectors evaluate each subset and determine whether a keyword is present. |
| US11335329B2 |
Method and system for generating synthetic multi-conditioned data sets for robust automatic speech recognition
Performance of Automatic Speech Recognition (ASR) for robustness against real world noises and channel distortions is critical. Embodiments herein provide method and system for generating synthetic multi-conditioned data sets for additive noise and channel distortion for training multi-conditioned acoustic models for robust ASR. The method provides a generative noise model generating plurality of types of noise signals for additive noise based on weighted linear combination of plurality of noise basis signals and channel distortion based on estimated channel responses. The generative noise model is a parametric model, wherein basis function selection, number of basis functions to be combined linearly and weightages to be applied to the combinations is tunable, thereby enabling generation of wide variety of noise signals. Further, the noise signals are added to set of training speech utterances under set of constraints providing the multi-conditioned data sets, imitating real world effects. |
| US11335324B2 |
Synthesized data augmentation using voice conversion and speech recognition models
A method for training a speech conversion model personalized for a target speaker with atypical speech includes obtaining a plurality of transcriptions in a set of spoken training utterances and obtaining a plurality of unspoken training text utterances. Each spoken training utterance is spoken by a target speaker associated with atypical speech and includes a corresponding transcription paired with a corresponding non-synthetic speech representation. The method also includes adapting, using the set of spoken training utterances, a text-to-speech (TTS) model to synthesize speech in a voice of the target speaker and that captures the atypical speech. For each unspoken training text utterance, the method also includes generating, as output from the adapted TTS model, a synthetic speech representation that includes the voice of the target speaker and that captures the atypical speech. The method also includes training the speech conversion model based on the synthetic speech representations. |
| US11335321B2 |
Building a text-to-speech system from a small amount of speech data
A method of building a text-to-speech (TTS) system from a small amount of speech data includes receiving a first plurality of recorded speech samples from an assortment of speakers and a second plurality of recorded speech samples from a target speaker where the assortment of speakers does not include the target speaker. The method further includes training a TTS model using the first plurality of recorded speech samples from the assortment of speakers. Here, the trained TTS model is configured to output synthetic speech as an audible representation of a text input. The method also includes re-training the trained TTS model using the second plurality of recorded speech samples from the target speaker combined with the first plurality of recorded speech samples from the assortment of speakers. Here, the re-trained TTS model is configured to output synthetic speech resembling speaking characteristics of the target speaker. |
| US11335317B2 |
Road and engine noise control
Exemplary road and engine noise control systems and methods include directly picking up road noise from a structural element of a vehicle to generate a first sense signal representative of the road noise, directly picking up engine noise from an engine of the vehicle to generate a second sense signal representative of the engine noise, and combining the first sense signal and the second sense signal to provide a combination signal representing the combination of the first sense signal and the second sense signal. The systems and methods further include broadband active noise control filtering to generate a filtered combination signal from the combination signal, converting the filtered combination signal provided by the active noise control filtering into anti-noise and radiating the anti-noise to a listening position in an interior of the vehicle. The filtered combination signal is configured so that the anti-noise reduces the noise at the listening position. |
| US11335315B2 |
Wearable electronic device with low frequency noise reduction
A method at a wearable electronic device with: a first electro-acoustic input transducer and a second electro-acoustic input transducer arranged to pick up a first acoustic signal and convert the first acoustic signal to a first microphone signal and second microphone signal; and a third electro-acoustic input transducer arranged to pick up a second acoustic signal and convert the second acoustic signal to a third microphone signal; and a processor (140). The method comprises: generating a beamformed signal based on the first microphone signal (x1) and the second microphone signal; estimating a first frequency value representing a fundamental frequency in one or more of: the first microphone signal, the second microphone signal and the third microphone signal; configuring a first filter with one or more passbands at one or more integer multiples of the first frequency value and one or more stop bands adjacent the one or more stop bands; and filtering, using the first filter, one or more of: the first microphone signal, the second microphone signal and the beamformed signal. |
| US11335313B2 |
Noise-canceling headphones including multiple vibration members and related methods
Noise-canceling headphones may include a headband, an audio input, and earcups supported proximate ends of the headband. A first vibration member operatively connected to the audio input, a second vibration member operatively connected to the audio input, and a microphone may be supported by a housing of at least one of the earcups. A feedback, noise-cancelation circuit configured to reduce a user's perception of a portion of an audible response of the second vibration member may be operatively connected to the microphone. The feedback, noise-cancelation circuit may be configured to modify an audio signal from the audio input at least in part based on a signal from the microphone and send the modified audio signal to the first vibration member. |
| US11335309B2 |
Connector device for electronic musical instruments comprising vibration transducer
A connector device for electronic musical instruments. The connector device comprising input electrical connector means that receives electrical signals generated by pickup means for an instrument. The instrument being played and a vibration transducer mechanically attached to the input electrical connector means or provided as an integral part of the input electrical connector means, such that vibrations from the instrument are transferred to the vibration transducer. The vibration transducer generates an electrical output signal based on the vibrations. The connector device comprises electrical output connector means that receives the electrical signals generated by the pickup means and the electrical output signal from the vibration transducer and provides these signals to equipment. The connector device further comprises a mixer that combines the signals vg(t) from the pickup means and the signal vvib(t) from the vibration transducer. The mixer provides output signal vo(t) that is a weighted combination of the input signals. |
| US11335305B2 |
String tensioner for musical instrument
A string tensioner is configured to apply a substantially constant tension to a string over an operational range even if such string stretches and contracts over time. Tension is provided by a spring. Flexers can attach the spring to a force modulation member and a frame. The flexers preferentially bend out-of-axis so that the spring does not bend out-of-axis when the force modulation member rotates. A dampening system can slow the force modulation member's response to vibrational forces. A flexible stop can prevent rotation of the force modulation member beyond a desired point, but flexes to remain in contact with the force modulation member over a small range of movement. |
| US11335303B2 |
Gaze dependent foveated rendering apparatus, method, computer program and system
Certain examples of the present invention relate to an apparatus, method, computer program and system for use in gaze dependent foveated rendering. Certain examples provide an apparatus including at least one processor; and at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform adapting a gaze dependent foveated rendering process in response to a determination of a sub-optimal operational condition of the gaze dependent foveated rendering process. |
| US11335300B2 |
Projector and projection method
A projector and a projection method that effectively protect a to-be-protected object existing in a sensing area are provided. The projector includes a first sensor, a second sensor, an optical engine and a processor. The optical engine includes a light source. The first sensor receives a first sensed signal, generates a first signal corresponding to the first sensed signal and transmits the first signal to the processor. The second sensor receives a second sensed signal different from the first sensed signal, generates a second signal corresponding to the second sensed signal and transmits the second signal to the processor. The processor determines whether the first signal and the second signal fall into their respective pre-determined ranges. The processor transmits a light adjusting signal to control a light source. |
| US11335297B2 |
Method for displaying projection picture and method for rotating projection picture
Disclosed are a method for displaying projection picture and a method for rotating projection picture, comprising following steps: A: using a main control chip of a display to receive a picture signal parameter of a handheld terminal; B: the main control chip determining the black edge and calculating the starting position of a display picture by detecting the intensity of display signal inputted from the handheld terminal; C: obtaining the width of the display picture by calculation, and at the same time, directly obtaining the height of the display signal by signal detection of the main control chip; and D: using the function calculation provided by a control unit to enlarge the picture to a proportional or full-screen output with the handheld terminal. After adopting the above method, the display provides a picture with “full screen without having black edges” or “small black edges” to enhance the visual experience. |
| US11335296B2 |
Low-latency context switch systems and methods
An electronic device includes a display panel and image processing circuitry. The image processing circuitry receives input image data corresponding to an image to display on the display panel, modifies the input image data by executing a first context task (e.g., lower priority task), and receives a context switch request. The image processing circuitry also pauses modification of the input image data by pausing execution of the first context task and then switches to modifying the input image data by executing a second context task (e.g., higher priority task). |
| US11335295B1 |
Device and method for driving a display panel
A processing system includes a timing controller and source driver circuitry. The timing controller is configured to stop scanning of a plurality of gate lines of a display panel in response to a detection of a communication failure between the processing system and a controller. The source driver circuitry is configured to update a plurality of display elements of the display panel to cause a black display in response to expiration of a time limit after the detection of the communication failure. The timing controller may be further configured to resume the scanning of the plurality of gate lines in response to the expiration of the time limit. |
| US11335292B2 |
Display panel, display device and driving method
A display panel, a display device and a driving method are provided. In the display panel, subpixels input with a first voltage data signal and subpixels input with a second voltage data signal are alternately arranged, and among the subpixels with a same color in a same row; the number of the subpixels input with the first voltage data signal with a positive polarity is equal to the number of the subpixels input with the first voltage data signal with a negative polarity; two adjacent pixel groups in a same column adopt contrary polarity driving manners. |
| US11335291B2 |
Display controller with multiple common voltages corresponding to multiple refresh rates
A display controller for a display may include a frame rate circuit to change a frame rate of the display from a first frame rate to a second frame rate, and a reference voltage circuit to adjust a reference voltage of the display from a first reference voltage corresponding to the first frame rate to a second reference voltage corresponding to the second frame rate. The display may be a thin film transistor liquid crystal display. The reference voltage may correspond to a common voltage (Vcom) for the display. |
| US11335289B2 |
Blur eliminating circuit
A blur eliminating circuit and a display device are provided. The blur eliminating circuit includes a detection unit and a control unit. The detection unit generates a control signal after detecting and determining that the display device is shut down. The control unit controls a gate low voltage level outputted from a gate driving unit of the display device to be a predetermined voltage level according to the control signal, and thus turns on an active switch of the display device, thereby speeding up a discharging of a liquid crystal capacitor and a storage capacitor of the display device, and eliminating a shutdown blur phenomenon. |
| US11335283B2 |
Display device and display method thereof, display equipment
A display device and a display method thereof, and a display equipment are disclosed. The display device includes a display panel and a light transmittance adjusting layer, the display panel includes a plurality of pixel regions, the light transmittance adjusting layer is stacked with the display panel, and the light transmittance adjusting layer is configured to adjust display brightness of the plurality of pixel regions. |
| US11335279B2 |
Display optimization method and a display apparatus
The present application discloses a display optimization method. The method includes setting a light-emitting substrate including a first plurality of unit regions. Each unit region is associated with a luminance produced by one or more light-emitting diodes. The method further includes determining a sensitive area having a second plurality of unit regions in part of the light-emitting substrate in association with eyeball position of viewer relative to the light-emitting substrate and a non-sensitive area having a plurality of combined-regions in remaining part of the light-emitting substrate. Additionally, the method includes transferring local variables including information about the sensitive area and the combining factor k to a processor. Furthermore, the method includes operating the processor based on the local variables to individually control a first luminance of the one unit region in the sensitive area and to commonly control a second luminance of one combined-region in the non-sensitive area. |
| US11335275B2 |
Source driver
The present disclosure discloses a source driver capable of accurately sensing characteristics of a display panel by minimizing the influence of a floating channel. The source driver may include normal channels connected to pixels of a display panel, a floating channel under no-load; and a sampling circuit configured to sample signals of the normal channels and the floating channel. The source driver may provide a first reference voltage to the floating channel in a first period in which characteristics of the pixels are sensed. |
| US11335271B2 |
Pixel circuit, driving method, and display device
A pixel circuit, a driving method and a display device are provided. The pixel circuit includes: a data writing unit, a driving unit, a light emitting unit and an initialization unit. The initialization unit is configured to initialize a second node with an initialization voltage. The data writing unit is configured to set voltage of a first node to the voltage of a data signal and update voltage of the second node. The driving unit is configured to drive the light emitting unit to emit light according to a control signal. Due to the second node being initialized and compensated by the initialization unit, the storage capacitor leakage paths and the electric leakage of the storage capacitor during the light emitting stage are reduced, thus improving the quality of the displayed image. |
| US11335267B2 |
Display device and related operating method
An organic light emitting display device may include a display panel, a power supply, and a display driver. The display panel may comprise a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the scan lines and to the data lines. The power supply may supply a first pixel voltage and a second pixel voltage to the pixels. The display driver may control the display panel. The display panel may display a first image in a first frame frequency during a first driving mode, and display a second image in a second frame frequency that is lower than the first frame frequency during a second driving mode, according to a control by the display driver. |
| US11335263B2 |
Pixel driving method, display driving method and display substrate
Pixel driving method for driving pixel unit, display driving method and display substrate are provided. The pixel unit includes pixel driving circuit, including driving transistor, storage capacitor, and data writing circuit, the driving transistor has control electrode coupled to first terminal of the data writing circuit and the storage capacitor, and first electrode coupled to second terminal of the storage capacitor, and second terminal of the data writing circuit is coupled to data line. The pixel driving method includes: loading a data voltage into the data line, and controlling the first and second terminals of the data writing circuit to be connected; controlling the data line to be floating, and maintaining connection between the first and second terminals of the data writing circuit to reduce gate-source voltage of the driving transistor; and controlling the first and second terminals of the data writing circuit to be disconnected. |
| US11335261B2 |
Display panel and driving method thereof, and display apparatus
A display panel and a driving method thereof, and a display apparatus are provided. In the present disclosure, external compensation circuits electrically connected to pixel circuits are added. The external compensation circuits are configured to adjust anode voltages of light emitting devices to cause the anode voltages of the light emitting devices to be consistent with voltages of data voltage ends. |
| US11335255B2 |
Signal processing device and image display apparatus including the same
A signal processing device and an image display apparatus including the same are disclosed. The image display apparatus includes a display including an organic light emitting diode panel and a signal processor configured to control the display, wherein the signal processor is configured to perform luminance conversion based on a first luminance conversion pattern in the case in which the luminance level of an input image is greater a first level and to perform luminance conversion based on a second luminance conversion pattern having a higher luminance level than the first luminance conversion pattern in the case in which the luminance level of the input image is equal to or less than the first level, whereby low gray level expression of the organic light emitting diode panel is improved. |
| US11335254B2 |
Display-driving apparatus, method, and display apparatus
A display-driving apparatus for driving a display panel having at least two display areas is provided. The apparatus includes a storage device configured to receive and store a group of source data signals corresponding to a frame of image. The apparatus further includes a demultiplexer configured to split the group of source data signals into at least two sub-groups of data signals. Additionally, the apparatus includes a converter configured to convert a signal format of a respective one of the at least two sub-groups of data signals to a displayable format corresponding to the display panel. Furthermore, the apparatus includes a controller configured to transfer the at least two sub-groups of data signals in the displayable format to respective at least two display areas of the display panel to display a frame of image. |
| US11335253B2 |
Optical compensation method for display panel and optical compensation device
An optical compensation method for a display panel and an optical compensation device are provided. The optical compensation method for the display panel includes selecting a pixel block to be compensated in an edge region; and acquiring a pixel compensation parameter of at least one pixel block in a main body region as a pixel compensation parameter of the pixel block to be compensated. |
| US11335252B2 |
Display device and driving method thereof
A display is disclosed where in an optimization mode, the controller transmits a first lock signal having a pulse waveforms to a first source driver circuit among source driver circuits, receives a second lock signal having pulse waveforms from a last source driver circuit that receives the first lock signal, and transmits phase loop fixed data for recovering a frequency and a phase of a clock to each of the source driver circuits when the second lock signal is received, and in the display mode, the controller transmits a first lock signal having a preset voltage level to the first source driver circuit, receives a second lock signal having a plurality of preset voltage levels from a last source driver circuit, and supplies an image signal and control data to each of the source driver circuits when the second lock signal is received. |
| US11335251B2 |
LED driving apparatus having mitigated common impedance effect
An LED driving apparatus includes a driving circuit and multiple pixel circuits, each including: a pixel line connecting pixel power sources; an LED in series to the pixel line; two pixel MOSFETs connected in series to the pixel line, wherein the first MOSFET is turned on by the driving circuit and the second MOSFET is connected to the first MOSFET source; and a capacitor connected between the two MOSFET gates. The driving circuit includes: a driving line connecting driving power sources; a current source in series to the driving line; two driving MOSFETs connected in series to the driving line, wherein the first driving MOSFET is connected to the first pixel MOSFET gate and the second driving MOSFET is connected to the second pixel MOSFET gate and the first driving MOSFET source; and a switch connected between the gates of the first pixel and the first driving MOSFETs. |
| US11335243B2 |
Display panel and display device
Disclosed are a display panel and a display device. The display panel includes M rows and N columns of pixel units. The display panel is divided into R regions along a column direction, and an i-th region includes: (1+M(i−1)/R)-th row to a (Mi/R)-th row of pixel units. The display panel further includes M shift registers, M light emitting drivers, R light emitting control scan staring signal terminals, R scan start signal terminals for controlling time length and R scan start signal terminals for controlling current. An i-th row of pixel units is connected with an i-th shift register and an i-th light emitting driver, a light emitting driver connected to a first row of pixel units in the i-th region is connected with an i-th scan start signal terminal for controlling light emission. |
| US11335242B2 |
Display substrate and display device
The present disclosure provides a display substrate, including: a substrate; a plurality of pixel units on the substrate, each of the pixel units having a light-emitting device therein; a power supply electrode configured to supply a power supply voltage to the light-emitting device, wherein the power supply electrode includes a first electrode layer and a second electrode layer, the second electrode layer has a mesh-shaped structure and is coupled to the first electrode layer through a via hole, and the first electrode layer includes a plurality of first electrode parts spaced apart from each other and each having a block shape, each of the first electrode parts being electrically coupled to a plurality of light-emitting devices for supplying the power supply voltage to the plurality of light-emitting devices. |
| US11335241B2 |
Sub pixel circuit, pixel circuit, driving method thereof, display module and display device
What is described above are optional embodiments of the present disclosure. It should be noted that, for those of ordinary skills in the art, several modifications and refinements may be made without departing from the principle of the present disclosure. These modifications and refinements should also be considered to be within the scope of the present disclosure. What is described above are optional embodiments of the present disclosure. It should be noted that, for those of ordinary skills in the art, several modifications and refinements may be made without departing from the principle of the present disclosure. These modifications and refinements should also be considered to be within the scope of the present disclosure. |
| US11335237B2 |
Display device
A pixel circuit including a drive transistor and a capacitor electrically connected to a control terminal of the drive transistor, a light-emitting element, a first power supply voltage line intersecting a data signal line, and a second power supply voltage line electrically connected to the control terminal via the capacitor are provided, and in a writing period in which a scanning signal line becomes active, the first power supply voltage line and a second conduction terminal of the drive transistor are not conductive with each other, and in a light emission period of the light-emitting element, the first power supply voltage line and the second conduction terminal of the drive transistor are conductive with each other. |
| US11335236B2 |
Image processing method and display device
The present disclosure provides an image processing method and a display device including rows of actual pixels each including actual sub-pixels, and starting positions of actual sub-pixels in odd-numbered and even-numbered rows are staggered by a distance of half of an actual sub-pixel. The method includes: determining rows of theoretical pixels corresponding to a to-be-displayed image, each theoretical pixel including theoretical sub-pixels, each actual pixel corresponding to at least two theoretical pixels; calculating grayscale data of each actual sub-pixel in a manner of: for a target actual pixel, determining a rendering mode for calculating grayscale data of each actual sub-pixel of the target actual pixel according to whether there is a specified detail feature in a pixel area where target theoretical pixels corresponding to the target actual pixel are located, different rendering modes are employed when there is or there is not a specified detail feature in the pixel area. |
| US11335235B2 |
Display driving method and display driving device
A display driving method and a display driving device are disclosed. The display driving method includes the steps of: setting an image signal to be inputted, so that when the image signal is driven on a display panel, a first sub-pixel showing a positive polarity is displayed, and other sub-pixels are not displayed; copying the set image signal by the logic board and inputting the set image signal to the display panel; and finally inputting a gate drive signal. |
| US11335231B2 |
Data conversion circuit for converting black-and-white or grayscale frames for color display panel/ module, and electronic device and color display device using the same
A data conversion circuit for converting black-and-white or grayscale frames for a color display panel/module, and an electronic device and a color display device using the data conversion circuit are disclosed. The data conversion circuit includes a data conversion unit for receiving an input data of the black-and-white or grayscale frame provided by a controller/MCU. The data conversion unit converts the input data into a color frame data for the color display panel/module, and no input clock or reference clock for adjusting an output rate of the color frame data is received or generated by the data conversion circuit. |
| US11335230B2 |
Display panel
The present application provides a display panel. The display panel includes multiple sub-pixels, multiple data lines, multiple scan lines, and multiple gate fan-out lines. Each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and any two adjacent gate fan-out lines are spaced by at least one sub-pixel group. A width of the gate fan-out line is not less than a sum of widths of the two data lines in the sub-pixel group. |
| US11335229B2 |
Display for controlling operation of gamma block on basis of indication of content, and electronic device comprising said display
According to various embodiments of the disclosure, a display may include a display panel including a first region in which first group subpixels are disposed and a second region in which second group subpixels are disposed, a converter group including converters respectively connected to subpixels included in the first group subpixels and the second group subpixels to transfer image data for output of specified content to the subpixels, a first group gamma circuit selectively connected to the converters to output a first grayscale voltage whose intensity is determined based on a plurality of binary bits, a second group gamma circuit selectively connected to the subpixels to output a second grayscale voltage whose intensity is determined based on a single binary bit, and a controller that controls selective connections between the first group gamma circuit and the converters and selective connections between the second group gamma circuit and the subpixels. According to an embodiment, the controller may receive the image data from an external processor and transfer the image data to the converter group, connect the first group gamma circuit with at least some converters such that the first group gamma circuit applies the first grayscale voltage to the at least some converters of the converter group, connect the second group gamma circuit with the second group subpixels such that the second group gamma circuit applies the second grayscale voltage to the second group subpixels, and output the specified content to at least a portion of the first region. In addition, various embodiments understood from the specification are possible. |
| US11335227B2 |
Display system with variable resolution
Device for displaying images comprising: a line selector, the line selector and/or the column controller comprising a selection circuit comprising a succession of output channels corresponding to various rows of the matrix, said selection circuit further comprising a succession of shift registers and a succession of switches controlled by at least one configuration word for controlling the respective configurations of the succession of switches of said selection circuit and for placing the switches of said succession of switches respectively in one of said first configuration or second configuration according to the respective states of configuration bits of this configuration word, the first configuration allowing to propagate a signal in the succession of registers, the second configuration allowing to duplicate a signal emitted on the preceding output channel on the given output channel in order to consequently duplicate on a row corresponding to the given output channel a piece of data intended for a row corresponding to the preceding output channel. |
| US11335224B2 |
Pixel circuit, driving method thereof, and display device
A pixel circuit, a driving method thereof, and a display device are provided. The pixel circuit includes: a light-emitting assembly including a plurality of light-emitting elements; a driving sub-circuit electrically coupled to the light-emitting assembly and configured to generate driving current for driving the light-emitting assembly; and a repair sub-circuit electrically coupled to the light-emitting assembly and configured to: receive a repair scanning signal (Gate_R, Gate_Ri) and a repair data signal (Data_R, Data_Ri), and provide the driving current to at least one light-emitting element capable of emitting light normally among the plurality of light-emitting elements under the control of the repair scanning signal (Gate_R, Gate_Ri) and the repair data signal (Data_R, Data_Ri). |
| US11335222B2 |
Method for detecting defects in ultra-high resolution panels
A system for inspection of electrical circuits, which electrical circuits include a multiplicity of conductors which are mutually spaced from each other, the system including a voltage driver operative to apply different electrical voltages to a plurality of conductors from among the multiplicity of conductors, which plurality of conductors are in spatial propinquity to each other, a sensor operative to sense at least one characteristic of a test region defined thereby with respect to the electrical circuits, the sensor lacking sufficient spatial resolution to distinguish between the locations of individual ones of the plurality of conductors and a defect indicator responsive to at least one output of the sensor for ascertaining whether a defect exists in the plurality of conductors. |
| US11335221B2 |
Method, device and system for detecting display panel
A method, device and system for detecting a display panel are disclosed. The display panel includes a plurality of groups of pixels, and the method includes: controlling the plurality of groups of pixels to be successively displayed with a first gray scale, and in condition that an ith group of pixels are displayed with the first gray scale, controlling other groups of pixels in the plurality of groups of pixels except the ith group of pixels to be displayed with a second gray scale, the ith group of pixels being any group of pixels in the plurality of groups of pixels; detecting a first current output by the display panel, in a process of displaying the ith group of pixels with the first gray scale; determining that a display abnormality occurs to the ith group of pixels, in condition that the first current is not within a first current range. |
| US11335219B2 |
Display module fastening assembly and multi-display device including the same
Display module fastening assemblies are provided which facilitate installment of multi-display devices in small or limited spaces and without needing access to a rear side of the devices. A display module fastening assembly includes a back cover. A fastener receptacle includes a groove formed in a sidewall of the back cover. A fastener is detachably securable to the fastener receptacle. A support protrusions may extend outwardly from a contact portion of the fastener, and the support protrusion is configured to fit into the groove of the fastener receptacle when the contact portion is inserted into the back cover. |
| US11335211B2 |
Modular building block easy to assemble
A modular building block easy to assemble comprises a base plate, basic parts, and electronic individual components. First protrusions are disposed on the base plate and the basic parts, and slots are formed in the basic parts and the electronic individual components. First conductive pins and conductive metal sheets are disposed inside the basic parts. Control panels, electronic devices and conductive contacts are disposed inside the electronic individual components. The invention designs the base plate, basic parts and electronic individual components of original electronic building blocks as individual modules. |
| US11335210B2 |
Apparatus and method for analyzing images
Devices and a method are provided for providing feedback to a user. In one implementation, the method comprises obtaining a plurality of images from an image sensor. The image sensor is configured to be positioned for movement with the user's head. The method further comprises monitoring the images, and determining whether relative motion occurs between a first portion of a scene captured in the plurality of images and other portions of the scene captured in the plurality of images. If the first portion of the scene moves less than at least one other portion of the scene, the method comprises obtaining contextual information from the first portion of the scene. The method further comprises providing the feedback to the user based on at least part of the contextual information. |
| US11335201B2 |
Passage possibility determination apparatus, passage possibility determination method, and computer program
An apparatus according to one aspect of the present invention determines whether or not platoon vehicles can pass through an intersection, and includes: a calculation unit that calculates a first distance, a second distance, and a third distance described below; and a determination unit that determines whether or not the platoon vehicles can pass through the intersection, based on a result of comparison of the first distance with the second and third distances. First distance: a distance from a stop line of the intersection to a position of a leading vehicle at the present time. Second distance: a distance obtained by subtracting a platoon length from a distance of traveling for a remaining green interval at a vehicle speed at the present time. Third distance: a distance required for the leading vehicle to safely stop before the stop line of the intersection, with the vehicle speed at the present time. |
| US11335200B2 |
Method and system for providing artificial intelligence analytic (AIA) services using operator fingerprints and cloud data
One embodiment of the present invention discloses a process of providing a report predicting potential risks relating to an operator driving a vehicle using information obtained from various interior and exterior sensors, vehicle onboard computer (“VOC”), and cloud network. After activating interior and exterior sensors mounted on a vehicle operated by a driver for obtaining data relating to external surroundings and internal environment, the data is forwarded to VOC for generating a current fingerprint associated with the driver. The current fingerprint represents current driving status in accordance with the collected real-time data. Upon uploading the current fingerprint to the cloud via a communications network, a historical fingerprint which represents historical driving information associated with the driver is retrieved. In one aspect, the process is capable of generating a driving analysis report which predicts potential risks associated with the driver according to the current and historical fingerprints. |
| US11335198B2 |
Notification system, notification device, and notification method
A notification system includes a notification unit configured to notify a second person of position information relating to a parking position of a vehicle and auxiliary information to help the second person to find the vehicle after the vehicle is moved and parked by a first person. |
| US11335197B2 |
Teleoperated driving of a vehicle
A method for teleoperated driving of a transportation vehicle wherein sensor data concerning an environment of the transportation vehicle are received and a computation system determines a probability for an incident affecting a control of the transportation vehicle based on the sensor data. The computation system receives quality information concerning a predicted quality of the communication network and defines at least one parameter for a teleoperation of the transportation vehicle based on the probability for the incident and on the quality information. |
| US11335190B2 |
Storage system for vehicle
An acquisition unit acquires vehicle information related to a vehicle. An in-vehicle storage unit is provided in the vehicle and stores therein the vehicle information acquired by the acquisition unit. A transmission unit transmits the vehicle information acquired by the acquisition unit to an off-vehicle server located at an outside of the vehicle. A classification unit classifies the vehicle information acquired by the acquisition unit into information for transmission to be transmitted to the off-vehicle server or information for storage to be stored in the in-vehicle storage unit. |
| US11335188B2 |
Method for automatically producing and updating a data set for an autonomous vehicle
A method for the automatic production and updating of a data set for an autonomous vehicle, in which at least one traffic light and a switching state of the at least one traffic light are registered; at least one road marking is ascertained; a trajectory of at least one vehicle traveling ahead is registered; and the collected data are used for producing and updating a data set, and based on the at least one detected trajectory, the at least one switching state of the at least one traffic light and the at least one ascertained road marking, at least one traffic lane is allocated to at least one traffic light. In addition, an autonomous or partially autonomous vehicle is described for carrying out the method. |
| US11335186B2 |
Communication system
A communication system includes an information acquisition unit that acquires information (road information), a type identifying unit that identifies the type of the information acquired by the information acquisition unit, a storage unit (vehicle storage unit, server storage unit) that stores relationship information that associates the type of the information with the transmission direction of the information, and a direction identifying unit that identifies the transmission direction of the information acquired by the information acquisition unit based on the identification result by the type identifying unit and the relationship information stored in the storage unit (vehicle storage unit, server storage unit). |
| US11335184B2 |
System and method for rapid configuration of a universal controlling device
A universal controlling device is provided with one or more buttons which, when activated in a set up mode, serves to initiate a rapid configuration of the universal controlling device to adapt the universal controlling device to communicate with an intended target appliance. |
| US11335183B2 |
System and method for testing networked alarm units
Disclosed is an alarm unit having an alarm controller, the alarm controller being operatively connected to a plurality of implements within the alarm unit having a mechanical actuator and a magnetic sensor and at least one of a visual source and an audible source, wherein the alarm unit: monitors for input to initiate one of a plurality of self-tests including: a first test, initiated by actuation of the mechanical actuator without actuation of the magnetic sensor, and a second test, initiated by actuation of the mechanical actuator with actuation of the magnetic sensor, and wherein the first test differs from the second test. |
| US11335180B1 |
Apparatus and systems for flood/moisture detection and notification
A monitoring apparatus includes a rigid structure, at least one sensor supported by the structure that is configured to detect a level of liquid or a presence of moisture in a vicinity of the structure, and a housing supported by the structure. A transmitter and a controller are located within the housing. The controller is in electrical communication with the at least one sensor and the wireless transmitter, and the controller is configured to cause the transmitter to transmit measurement data received from the at least one sensor to a remote device. |
| US11335174B2 |
Security cameras with thermal imaging sensors
The disclosed techniques include systems and methods for implementing security cameras with thermal imaging sensors. The disclosed techniques can utilize a thermal imaging sensor (TIS) and a less robust passive infrared (PIR) sensor of a security camera system to monitor a field of view. |
| US11335172B1 |
Sharing video footage from audio/video recording and communication devices for parcel theft deterrence
Systems and methods for communicating in a network using parcel theft share signals in accordance with various embodiments of the present disclosure are provided. In one embodiment, an audio/video (A/V) recording and communication device comprises: a camera configured to capture first image data of a drop-off zone; a communication module; and a processing module comprising: a processor; and a parcel theft deterrence application that configures the processor to: monitor a parcel in the drop-off zone, wherein the parcel is associated with parcel tracking data; determine that the parcel has been removed from the drop-off zone; generate a parcel theft share signal using the first image data and the parcel tracking data, wherein the parcel theft share signal includes a command to share the first image data with a network of users; and transmit the parcel theft share signal to the backend server using the communication module. |
| US11335168B2 |
Gaming machine, control method for machine, and program for gaming machine having a bonus feature event
A gaming machine is described herein. The gaming machine includes a control unit programmed to initiate an instance of a primary game and spin and stop virtual reel strips to display an outcome of the primary game. The control unit detects an appearance of a winning combination of game symbols in the outcome and provides an initial award based on the winning combination, and detects an appearance of the collect symbol and a credit prize symbol in the outcome, determines an amount of credits associated with the credit prize symbol, and a bonus award including the determined amount of credits. |
| US11335167B2 |
System and method for post-play reproduction of game outcomes
A system which makes available game outcome data to a player to enable the player to access a post-play reproduction of a game outcome previously determined utilizing the game outcome data. |
| US11335154B1 |
Apparatus, methods and systems for storing and conveying items within a food delivery apparatus
A cartridge for food delivery apparatus is disclosed. The cartridge is for storing and conveying items. The cartridge includes a housing and an outer looped element affixed at least partially in a main cavity of the housing. A movable inner looped element is mounted on rotatable rollers. A plurality of panels defines a plurality of movable chambers between the outer looped element and the movable inner looped element. Each of the plurality of movable chambers is defined by a space between a first panel and an adjacent panel of the plurality of panels. A first movable door partially defining the outer looped element covers a first opening providing access to at one of the chambers. A second movable door is on the outer looped element and allows items to exit the cartridge. Generally, the cartridge enables the on-demand delivery of food items having a generally planar shape or surface. |
| US11335151B2 |
Reader and a method for controlling the reader
A method for controlling a reader communicating with a user terminal using Bluetooth Low Energy (BLE), comprising: transmitting a first advertising packet to the user terminal; performing a first authentication with the user terminal that has received the first advertising packet; discovering service of the user terminal by the reader that has transmitted the first advertising packet after the first authentication is performed; obtaining a first service data from the user terminal in response to the discovering service; discovering characteristic of the user terminal based on the first service data; and obtaining a first characteristic data from the user terminal in response to the discovering characteristic. |
| US11335148B2 |
Power-saving door lock systems and methods
An electronic door lock system that saves power by putting some electronic devices, such as transceivers, in sleep mode and by executing instructions only in response to ambient trigger scenarios. Instructions sent to an electronic door lock from a remote device could be stored on a server before being downloaded to the electronic door lock system once the transceiver is awakened from sleep mode. |
| US11335146B2 |
Method and apparatus for personal pathogen status verification at point of entry into an area of congregation
A system and system for personal pathogen status verifying allows an entity to control access to an area of congregation (AOC) at one or more points of entry (POE) is a configurable manner. In one embodiment, the system may be used for the SARS-CoV-2 virus, but may be similarly used for other pathogens. |
| US11335145B2 |
Access system with at least one gate
The application relates to an access system (100, 200, 500, 600, 700) comprising at least one first gate (102, 602.1, 602.2, 702.1, 702.2) configured to enable an access from a first area (104) to a second area (106), the first gate (102, 602.1, 602.2, 702.1, 702.2) comprising at least one first array antenna arrangement (108, 208, 308, 308.1, 308.2, 508, 608.1, 608.2, 708.1, 708.2) configured to process at least one information signal (234, 446, 564.1, 564.2, 564.3, 562, 662.1, 662.2, 734) including at least one modulated signal part (458) and at least one unmodulated signal part (456), wherein the first array antenna arrangement (108, 208, 308, 308.1, 308.2, 508, 608.1, 608.2, 708.1, 708.2) comprises a plurality of gate antennas (110, 210, 510) arranged adjacent to each other. |
| US11335144B2 |
Method for unlocking intelligent lock, mobile terminal, intelligent lock and server
Provided are a method for unlocking an intelligent lock, a mobile terminal, an intelligent lock and a server. The method includes following steps. A mobile terminal receives an initial key and a communication key from a server. The mobile terminal encrypts the initial key and preset key data by using the communication key to generate an unlocking verification code. The mobile terminal attaches the preset key data to the unlocking verification code, to obtain an unlocking verification code attached with the preset key data. The mobile terminal sends the unlocking verification code attached with the preset key data to the intelligent lock. The intelligent lock performs an unlocking operation based on the unlocking verification code attached with the preset key data. |
| US11335142B1 |
Systems for analyzing vehicle journeys
A traffic analysis system analyzes location data from a plurality of vehicles to determine journeys made by the vehicles. Vehicles may make one or more rest stops during a journey. The traffic analysis system compares rest periods to journey criteria to determine whether a rest period delineates the end of a journey, or whether a rest period is still within the journey. In this way, a plurality of trips can be chained together into a journey to provide more accurate analysis of traffic patterns. |
| US11335141B2 |
Checkpoint-based tracing for monitoring a robotic system
To identify sources of data resulting from an execution flow in a robotic device such as an autonomous vehicle, an operating system receives sensor data from various sensors of the robotic device. For each sensor, the system generates a data log comprising an identifier of a first checkpoint associated with that sensor, as well as a first timestamp. The system performs an execution flow on the sensor data from that sensor. The system updates the data log to include an identifier and timestamp for one or more additional checkpoints during the execution flow. The system then fuses results, uses the fused data as an input for a decision process, and causes a component of the robotic device to take an action in response to an output of the decision process. The system may record the action, an action timestamp and the data logs for each sensor in a memory. |
| US11335139B1 |
System and method for selective vehicle data retrieval
A method of mobile application-based vehicle diagnostics comprises establishing a user profile associated with a user of a mobile communication device, the profile including a vehicle identification number (VIN) associated with a vehicle operated by the user, receiving an instruction to obtain vehicle condition information, determining a geolocation of the device, in response to the instruction, directing the user to a nearby diagnostic service provider having a capability to retrieve diagnostic data including the VIN from the registered vehicle and upload the retrieved diagnostic data to a server or other data processor associated with a diagnostic database for deriving vehicle condition information from retrieved diagnostic data, receiving the vehicle condition information from the server, the vehicle condition information having been derived from the diagnostic data uploaded by the diagnostic service provider and associated with the user based on the VIN included in the diagnostic data, and displaying the received vehicle condition information on the device. |
| US11335138B2 |
System and method for tire embedded object detection
A method of performing a diagnostic test on a vehicle having at least one tire includes providing the vehicle with at least one sensor configured to detect a vehicle operating characteristic, a receiver configured to receive AM signals, a notification system, and a controller in electronic communication with the at least one sensor, the receiver, and the notification system, receiving sensor data from the at least one sensor and AM signal data from the receiver, analyzing the sensor data and the AM signal data, determining whether a first condition is satisfied, and in response to the first condition being satisfied, generating a first control signal to control the notification system to generate a notification. |
| US11335137B2 |
Trained pattern analyzer for roll out decisions
A historical task database relating vehicle rollout decisions, vehicle maintenance states and subsequent deteriorations is created. A pattern analyzer may use an item-set mining algorithm on the task database to recommend whether a vehicle with its current maintenance state should be deployed. A supervisor uses this recommendation to make a rollout decision. These decisions are added to the database. Heuristic rules are defined to determine if the rollout decision was correct. The system to learns when a supervisor continues to make costly rollout errors. The system also discovers combinations of defects that lead to a rapid deterioration and makes recommendations that the vehicle be sent for maintenance rather than being rolled out. |
| US11335132B2 |
Partial sensor data sharing for connected vehicles
A method of partial sensor data sharing is described. The method includes defining an area of interest (AoI) based on a traffic topology and state information of a selected sender vehicle. The method also includes transmitting the area of interest to the selected sender vehicle. The method further includes sharing, by the selected sender vehicle, a sensor data corresponding to the area of interest when the area of interest is within a sensor coverage area of the selected sender vehicle. |
| US11335130B2 |
Method for checking toll transactions and components therefor
The subject matter disclosed herein relates to a method for checking toll transactions, produced from position notifications of a mobile phone connected via a mobile network to a transaction server, with the aid of a network of distributed toll beacons, which can communicate via short-range radio with on-board units of passing vehicles and are connected to the transaction server. To this end, a interoperable multi-functional OBU is created that is formed from a GNSS- and NFC-enabled mobile phone on the one hand and an NFC- and DSRC-enabled OBU on the other hand, which exchange data concerning a session identifier (SID) via their common NFC interface, which session identifier forms a link between the infrastructureless and the infrastructure-bound billing functions of the multi-functional OBU. The disclosed subject matter also relates to a toll beacon and a transaction server for same. |
| US11335128B2 |
Methods and systems for evaluating a face recognition system using a face mountable device
A computer-implemented method is disclosed. The method includes a) accessing a first image, b) accessing a second image, c) from an adversarial pattern generating system, generating a face recognition adversarial pattern for display from a specified region of a face corresponding to the second image, the face recognition adversarial pattern operable to minimize a measure of distance as determined by a face recognition system, between the face and a class of the first image, or to maximize a probability of the misclassification of the second image by the face recognition system, d) providing a face mountable device, that is mounted on the face, access to the face recognition adversarial pattern in real time via a communications component, and e) controlling light patterns on the face mountable device according to the face recognition adversarial pattern. |
| US11335121B2 |
Global configuration interface for default self-images
A method for operating a messaging system is provided. The method is adapted to send and receive modifiable videos and includes receiving, by a computing device, a first authorization from a user to use a self-image of the user in a personalized video. The method also includes receiving, by the computing device, a second authorization from the user to enable use of another self-image of another user in the personalized video. The method further includes sending, by the computing device, after the first and second authorizations have been received, the personalized video including at least part of the self-image of the user, at least part of the other self-image of the other user, and at least part of a stock video. A system and a non-transitory processor-readable medium for operating a messaging system adapted to send and receive modifiable videos are provided. |
| US11335115B2 |
Fake fingerprint identification device and method for driving the same
A fingerprint recognition technology is disclosed. More specifically, embodiments of the present invention provide a fake fingerprint identification device and a method for driving the identification device. According to the device and the method, an alternating voltage is applied to read a fingerprint such that the fingerprint is identified and physical authentication is made whether the fingerprint is live or fake when the frequency of a TX or RX ultrasonic signal generated by the application of the alternating voltage varies. Therefore, the device and the method can be used to accurately identify whether a fingerprint is live or fake and is thus effective in preventing harmful effects caused when a fake fingerprint is authenticated. |
| US11335110B2 |
Systems and methods for processing a table of information in a document
A device may receive document image data that includes an image of a document to be digitized. The device may detect, from the document image data, a table of information that is depicted in the image. The device may determine a data extraction score associated with a table image, wherein the data extraction score is associated with using a data conversion technique to convert the table image to digitized table data. The device may perform, based on the data extraction score not satisfying a threshold, a morphological operation on the table image to generate an enhanced table image that corresponds to an enhanced table of information associated with the table of information. The device may process, using the data conversion technique, the enhanced table image to extract the information from the enhanced table. The device may perform an action associated with the extracted information. |
| US11335108B2 |
System and method to recognise characters from an image
System and method to recognise characters from an image are disclosed. The method includes receiving the at least one image, pre-processing the at least one image, extracting a plurality of characters from the corresponding at least one image, extracting at least one structure from the corresponding at least one image upon applying an edge detection technique to extract a structure, identifying a template based on extracted structure, subjecting the plurality of characters into a plurality of ensemble AI models to extract one of a plurality of texts, a plurality of non-textual data and a combination thereof, comparing a plurality of extracted plurality of texts, a plurality of non-textual data, or a combination thereof from the corresponding plurality of ensemble AI models with each other, generating a confidence score and validating one of the plurality of accurate texts, the plurality of accurate non-textual data, or a combination thereof. |
| US11335107B2 |
Generating file name using machine-learned model that relearns
An information processing device includes a storage section that stores a machine-learned model subjected to machine learning using teaching data in which at least one of an image included in read data of a document read by a scanner, a character string included in the read data, and a layout of the read data that is included in the read data is associated with a file name of the read data, and a controller that generates the file name of the read data using the machine-learned model and at least one of the image, the character string, and the layout that are included in the read data. |