最新美国发明专利
Document Document Title
US11258914B2 Information processing apparatus, recording apparatus, determination method of printing medium, and storage medium
An information processing apparatus includes an acquisition unit, notification control unit, input unit, and extension unit. The acquisition unit acquires a measurement result obtained by measuring a printing medium characteristic and acquires a characteristic reference range of each of printing media types set in advance to identify a type of a measured printing medium. Extracting, as a candidate printing medium and based on the acquired measurement result and the acquired characteristic reference range, a type of printing medium using the characteristic reference range including the measurement result and notifying information indicating the type of the candidate printing medium are performed. The input unit inputs information, wherein a type of printing medium on which recording is to be performed by the recording unit has a first reference range which is the characteristic reference range of the type and corresponds to the input information. The extension unit extends the first reference range.
US11258908B2 Spectral blending with interior microphone
A headphone can include plurality of exterior microphones, that generates corresponding exterior microphone signals, an accelerometer that generates an accelerometer signal; and an interior microphone, not directly exposed to the environment, that generates an interior microphone signal. A processor of the headphone can be configured to generate an audio signal containing voice of a user, based on a) the accelerometer signal, b) the interior microphone signal, and c) the plurality of exterior microphone signals.
US11258906B2 System and method of real-time wiki knowledge resources
A system and method are disclosed for recommending a resource to a customer service representative that includes one or more databases that store data describing electronic communication between one or more customer system communication devices and one or more service center communication devices. Embodiments further include a computer coupled with one or more databases and configured to monitor communication activity to determine whether a customer service ticket has been opened between one or more customer system communication devices and one or more service center communication devices and determine a customer service representative score based on one or more customer service representative ranking factors.
US11258904B2 Communications processing
A system is disclosed. The system comprises a service platform associated with a call center, the service platform comprising an applications server configured to communicatively couple to a softswitch and a database. The applications server is configured to receive an inbound communication, determine a source of the inbound communication, and identify one or more configuration parameters associated with a destination of the inbound communication, the destination of the inbound communication associated with a client of the call center. The applications server is configured to route the inbound communication to an agent associated with the call center to establish a communication session. The applications server is configured to send, to the client based on the one or more configuration parameters associated with the destination of the inbound communication, a notification that the inbound communication was received, the notification identifying the source of the inbound communication.
US11258902B2 Partial automation of text chat conversations
To allow the human customer service agents to specialize in the instances where human service is preferred, but to scale to the volume of large call centers, systems and methods are provided in which human agents and intelligent virtual assistants (IVAs) co-handle a conversation with a customer. IVAs handle simple or moderate tasks, and human agents are used for those tasks that require or would benefit from human compassion or special handling. Instead of starting the conversation with an IVA and then escalating or passing control of the conversation to a human to complete, the IVAs and human agents work together on a conversation.
US11258897B2 Communication device controlling method
A communication device controlling method, for controlling a communication device including a first subscriber identification and a second subscriber identification when a process of a data call established with the first subscriber identification is in a suspension, comprising: (a) receiving, by a processor of the communication device, a request to establish a mobile terminated (MT) call with the second subscriber identification; and (b) resuming, by the processor, the process of the data call from the suspension before an instruction of accepting or rejecting the request is received if the MT call is packet-switch based.
US11258894B2 Profile picture display method and terminal
A method includes: receiving, by a first terminal, first input, where the first input is used to instruct the first terminal to display a first screen that includes a profile picture of a first user, and the first user is an owner of the first terminal or a contact saved on the first terminal; and searching, by the first terminal in response to the first input, for a profile picture of the first user and that corresponds to current scenario information of the first user; and displaying, by the first terminal in response to the first input, the first screen that includes a first profile picture.
US11258890B2 Portable terminal accessory device for holographic projection and user interface
A holographic display system for a portable electronic device. The display system includes a case configured to receive the portable electronic device and a projector coupled to the case by a first hinge element. The projector includes a projector screen for generating images. A reflective element is coupled to the projector by a second hinge element. The reflective element is oriented to reflect light from the images in order to create holographic images perceptible to a user of the portable electronic device. The case may include a connector for receiving, from the portable electronic device, a video signal defining the images. The holographic display system may further include a substantially transparent touch screen attached to the first hinge element.
US11258889B2 Module identification method for expandable gateway applications
A modular wireless communications system (edge device, etc.) that includes a base unit having a base unit processor and one or more additional units that each include a processor, in which the base unit processor is configured with processor-executable software instructions to determine whether the base unit has been combined with the one or more additional units to create a combined unit and/or whether one or more of the additional units have been detached from the combined unit. The processor may automatically perform an edge reconfiguration interrogation and enumeration (ERIE) operation in response to determining that the base unit has been combined with the one or more additional units to create the combined unit or in response to determining that one or more of the additional units have been detached from the combined unit.
US11258888B2 Parallel redundancy protocol (PRP) using non-overlapping resource unit (RU) groupings on a radio
Parallel Redundancy Protocol (PRP) using non-overlapping Resource Unit (RU) groupings may be provided. A first computing device may associate to a first Access Point (AP) at a virtual Media Access Control (MAC) address. Next, the first computing device may associate to a second AP at the virtual MAC address. Then data from a data frame may be replicated to a first one or more RUs in a channel. The first one or more RUs may be assigned to the first AP. Data from the data frame may then be replicated to a second one or more RUs in the channel. The second one or more RUs may be assigned to the second AP and may not overlap the first one or more RUs.
US11258885B2 Flexible parser in a networking device
One embodiment includes a network device, including hardware parsers to receive data of a header section of a packet, the header section including respective headers, parser configuration registers to store a default parsing configuration data set, wherein at least one of the hardware parsers is configured to parse at least one of the headers responsively to the default parsing configuration data set, yielding first parsed data, a packet processing engine to select a selected parsing configuration data set from a selection of parsing configuration data sets responsively to the first parsed data, cause loading of the selected parsing configuration data set into the parser configuration registers, and wherein ones of the hardware parsers are configured to parse respective ones of the headers responsively to the selected parsing configuration data set, yielding second parsed data, and process the packet responsively to the second parsed data.
US11258884B1 Secure remote access based on inspection and validation of remote access protocol traffic
Disclosed embodiments relate to securely inspecting and validating remote access protocol communications. Operations may include accessing remote access protocol communications between a first computing resource and a second computing resource; and validating at least a portion of the remote access protocol communications by at least one of: analyzing a sequence among the at least the portion, analyzing data contents of the at least the portion, analyzing a size field in the at least the portion, or analyzing a data-size correlation of the at least the portion; wherein at least one of the following is conditioned on a result of the validation: an ability of the at least the portion of the remote access protocol communications to pass between the first computing resource and the second computing resource, or an establishment of a remote access session between the first computing resource and the second computing resource.
US11258882B2 Information processing device, method, and storage medium for prioritized content acquisition
A server computer sets a priority order of each of contents based on an attribute of each of the contents designated by HTML data and provides the HTML data including the priority order with a client computer. The client computer acquires the contents from the server computer by using streams with priorities depending on the priority order of each of the contents designated by the HTML data provided from the server computer. The client computer controls display using a part of the contents and caches other contents from among the acquired contents.
US11258878B2 Method for providing QOS differentiation in a multi-tenant network and networking device employing method
A method for providing a differentiation in terms of quality of service (QoS) for multiple tenants in a network, by a networking device receives a data packet from a transmitting tenant, and the networking device identifies the tenant and a priority class of the received packet. The networking device then determines one or more color markers to apply to the received packet according to the sending tenant and the priority to be associated with the packet. The networking device then transmits or does not transmit the packet onwards depending on one or more color markers applied to the packet.
US11258872B1 Techniques for accelerating page rendering
Systems and methods are described herein for accelerating page rending times. In some embodiments, an intermediary proxy device may be utilized to accelerate page rending times experienced at an application operating at a user device. The intermediary proxy device may perform operations such as obtaining, on behalf of the application, first webpage content and second webpage content for a webpage, the first webpage content being obtained from the web server. In some embodiments, the intermediate proxy device may execute third-party code to obtain the second webpage content from a third party. In some embodiments, the intermediary proxy device may modify the second webpage content obtained from the content server from a first format to a second format the first webpage content and the second webpage content as modified to the application. The application may then perform one or more operations to present data at a display of the user device.
US11258871B2 Message push method and terminal
A message push method, where a first push client determines, based on a security level indication mark, whether the first push client needs to process the push message, and when the first push client does not need to process the push message, forwards the push message to a second push client for processing. In this way, a terminal can perform, based on security level indication marks, differentiated processing on push messages of different security levels such that security processing is performed on sensitive information of a relatively high security level. This avoids information leakage in a process of processing, by the terminal, the sensitive information of the relatively high security level, thereby resolving a push message security processing problem.
US11258869B2 Method and system for controlling downloading of a file in a cloud storage service
There are provided a method and a system for controlling downloading of a file in a cloud storage service. The method can be executed at a server. The method comprises appreciating an activity parameter representative of total download activity of a file from a cloud storage service via a communication network, and, responsive to the activity parameter being above a pre-determined threshold, applying a remedial action to the downloading of the file, such that the remedial action is applied only to downloading of the file via a data transmittal path that a user has received from the user who uploaded the file to the cloud storage service, and downloading of the file by the user who uploaded the file is not affected.
US11258865B2 Automated integration with cloud-based services
A computational instance of a remote network management platform may be dedicated to a managed network. The managed network may use computing resources of a cloud-based service provider. One or more processors may be disposed within the computational instance and may cause a provider-neutral cloud discovery software application to: (i) obtain a specification that defines an interface for accessing the cloud-based service provider, a discoverable set of computing resources provided by the cloud-based service provider, and mappings between descriptions of the discoverable set of computing resources and the database tables disposed within the computational instance, (ii) log on to the cloud-based service provider by way of the interface, (iii) request and receive, from the cloud-based service provider, descriptions of the discoverable set of computing resources, and (iv) store, in fields of database tables, the descriptions of the discoverable set of computing resources in accordance with the mappings.
US11258864B2 Communication device capable of interacting with devices on a network
A system and method for seamless exchange and interaction of multimedia content between communication devices in a network are disclosed. The method can include the discovery and identification of devices within proximity of a sending device. The found devices can be authenticated through unique identifiers established during registration. Connection requirements can be determined based on the identifiers associated with the found devices and the sending device. In turn, the sender can establish a connection with the found devices using the connection requirements. The sending device can share or serve as a remote control to redirect and navigate the content, with a simple action or a gesture command, to the found device. The shared multimedia content, can either reside on the sender's mobile device or on a remote server within a connected network.
US11258863B1 Systems, devices, and methods for establishing multiple electronic flight bag sessions with a flight management computer
An onboard system establishes a first-EFB connection between a first electronic flight bag (EFB) and an aircraft interface device (AID), and establishes a first-EFB session between the first EFB and a flight management computer (FMC) based on a session identifier for the first EFB. The first-EFB connection is associated with a first-EFB connection identifier for the first EFB, and the first-EFB session is established over the first-EFB connection in accordance with the first-EFB connection identifier. The onboard system establishes a second-EFB connection between a second EFB and the AID, and establishes a second-EFB session between the second EFB and the FMC based on a session identifier for the second EFB. The second-EFB connection is associated with a second-EFB connection identifier for the second EFB, and the second-EFB session is established over the second-EFB connection in accordance with the second-EFB connection identifier.
US11258861B2 Secure reporting of platform state information to a remote server
Technologies disclosed herein provide a method for receiving at a device from a remote server, a request for state information from a first processor of the device, obtaining the state information from one or more registers of the first processor based on a request structure indicated by a first instruction of a software program executing on the device, and generating a response structure based, at least in part, on the obtained state information. The method further includes using a cryptographic algorithm and a shared key established between the device and the remote server to generate a signature based, at least in part, on the response structure, and communicating the response structure and the signature to the remote server. In more specific embodiments, both the response structure and the request structure each include a same nonce value.
US11258858B1 Multi-device connection management
A connection request is received for an account, the account associated with a set of devices, the connection request comprising a request to establish communication between a sending device and a device associated with the account. By analyzing device usage data for a first device in the set of devices, an availability score of the first device is determined. The first device is presented for connection based on the availability score of the first device. Responsive to the presenting, the sending device and the first device are connected.
US11258854B2 Data sharding for transmission over a high generation cellular network
Aspects of the disclosure relate to data sharding for transmission over a high generation cellular network. A computing platform may detect, via a communication network, transmission of data from a first computing device to a second computing device. Subsequently, the computing platform may intercept, prior to receipt of the transmission by the second computing device, the data. Then, the computing platform may shard the data into a first shard and a second shard. Then, the computing platform may identify, within the communication network, a first communication channel and a second communication channel. Then, the computing platform may send, to the second computing device, the first shard via the first communication channel, and the second shard via the second communication channel. Subsequently, the computing platform may merge, the first shard and the second shard, to reconfigure the data.
US11258852B2 Dynamic topology switch for data replication
The present disclosure involves systems, software, and computer implemented methods for performing dynamic topology switch in a failover operation. In one example, a failover of a first node is determined. The first node includes a first data server and a first replication server. At least one user application connects to the first data server prior to the failover of the first node. In response to the determined failover, the at least one user application is connected to a second data server of a second node. The second node includes the second data server and a second replication server. Prior to the failover of the first node, a data replication topology of the second node is a remote topology. During the failover, if the first replication server on the first node is down, the data replication topology of the second node is switched from the remote topology to a local topology.
US11258850B2 Distributed register intelligent node transfer engine
Embodiments of the invention are directed to an architecture modifier for intelligent node transfer and review processing. The engine collects user activity data from IoT devices and non-IoT applications to identify user activity and stores user workstation availability metrics. Upon receiving a request for review and consensus, the engine develops various user data routing configuration and schema based on live data feed for identification of nodes for transaction consensus and immediate review posting without any delay architectural delay.
US11258847B1 Assignments of incoming requests to servers in computing clusters and other environments
An embodiment may involve persistent storage containing definitions of a set of queues and a set of servers, and wherein the servers are respectively associated with deactivation times. One or more processors may be configured to: (i) identify, by an assignment engine, an incoming request in a particular queue, wherein the incoming request is ready for assignment to one of the servers; (ii) determine, by the assignment engine and based on data associated with the incoming request, an expected duration for servicing of the incoming request; (iii) calculate, by the assignment engine and based on the deactivation times, times remaining in service for each of the servers; (iv) select, by the assignment engine and from the servers, a particular server that has a time remaining that is greater than the expected duration; and (v) assign, by the assignment engine, the incoming request to the particular server.
US11258839B2 Data storage management and resource scaling
Aspects of the present disclosure relate to managing data storage resources. In embodiments, one or more data streams are received. Each data stream can include one or more data portions. Further, one or more storage parameters are monitored. Each storage parameter can include data input load of each data stream, data write rate of each stream, number of events in each stream, and data ingestion rates of one or more storage devices. Data storage resources are elastically scales based on any changes to the at least one monitored storage parameter.
US11258838B2 Method, system, and non-transitory computer readable record medium for processing chatroom based on usage
Disclosed are methods, systems, and non-transitory computer-readable record mediums for processing a chatroom based on a level of use. A chatroom processing method including verifying a level of use by a user with respect to each chatroom of chatrooms included in a chatroom list, selecting at least one chatroom from the chatroom list as a chatroom to be managed based on the level of use, and processing the chatroom to be managed to be distinguished from remaining chatrooms in the chatroom list may be provided.
US11258828B2 Systems and methods for monitoring and correcting computer system security practices
Systems and methods for monitoring and correcting security measures taken for a computer system are disclosed. Exemplary implementations may: determine a set of risk parameters of the computing system; collect sets of values of the security parameters at various times and determine the efficacy adjustments based on a comparison of the sets of values and an elapsed time between collection of the sets of values.
US11258824B1 Method and apparatus for authorizing microservice APIs
Some embodiments of the invention provide a system for defining, distributing and enforcing policies for authorizing API (Application Programming Interface) calls to applications executing on one or more sets of associated machines (e.g., virtual machines, containers, computers, etc.) in one or more datacenters. This system has a set of one or more servers that acts as a logically centralized resource for defining and storing policies and parameters for evaluating these policies. The server set in some embodiments also enforces these API-authorizing policies. Conjunctively, or alternatively, the server set in some embodiments distributes the defined policies and parameters to policy-enforcing local agents that execute near the applications that process the API calls. From an associated application, a local agent receives API-authorization requests to determine whether API calls received by the application are authorized. In response to such a request, the local agent uses one or more parameters associated with the API call to identify a policy stored in its local policy storage to evaluate whether the API call should be authorized. To evaluate this policy, the agent might also retrieve one or more parameters from the local policy storage.
US11258821B2 Application firewall
A firewall uses information about an application that originates a network request to determine whether and how to forward the request over a network. The firewall may more generally rely on the identity of the originating application, the security state of the originating application, the security state of the endpoint, and any other information that might provide an indication of malicious activity, to make routing and forwarding decisions for endpoint-originated network traffic.
US11258817B2 Rule-based assignment of criticality scores to assets and generation of a criticality rules table
In an embodiment, a management system obtains a criticality rules table that includes a plurality of rules mapped to corresponding criticality scores indicative of a level of risk in the event that an associated asset of a managed network is compromised by a third party. The one embodiment, the criticality rules table is updated based upon machine learning and/or feedback from an operator of the managed network. In another embodiment, the criticality rules table is used to assign one or more criticality scores to one or more assets based on one or more attributes of one or more assets, and the criticality rules table.
US11258815B2 AI-based system for accurate detection and identification of L7 threats
Systems and methods for accurate detection and identification of application-level threats in a computer network include one or more nodes instantiated at protected systems and a network-based security platform communicatively coupled to receive data collected by the one or more nodes. Each node is configured to inspect application-level requests in inbound network traffic to a respective protected system. The security platform includes a three-layer machine learning engine to iteratively reconstruct each protected system's application business logic, identify associated application endpoints, data boundaries, and customary user behaviors based on the data collected by the one or mode nodes, and to create customized profiles for the protected systems and make those profiles available to the nodes instantiated at the protected systems. The security platform detects anomalies in the data provided by the nodes through comparisons with the behavior profile for each of the application endpoints.
US11258812B2 Automatic characterization of malicious data flows
A method of identifying malicious activity in a sequence of computer instructions includes monitoring data flows from a public network to one or more networked devices on a private network and to one or more honeypots that appear to the public network to be devices on the private network, representing each such data flow as a word, and the sequence of data flows as comprising an n-gram of two or more words. The data flows are characterized with a likelihood of being malicious based on their statistical association with the one or more honeypots relative to their statistical association with one or more networked devices. Identified malicious activity is used to train a network device to identify malicious data flows and prevent them from reaching devices on the private network.
US11258810B2 Identity authentication method, apparatus, and system
A method may be performed using a server. The method may include receiving an identity authentication request associated with a user, generating authentication information based on the identity authentication request, and generating candidate information based on the authentication information such that the authentication information is a subset of the candidate information. The candidate information may be displayed at a randomly selected location. The user may provide input through a graphic input interface to select the authentication information from among the candidate information.
US11258809B2 Targeted attack detection system
Systems and methods for targeted attack detection. A protection system intercepts traffic destined for a protected system and only traffic identified as non-malicious is allowed to pass thereto. Data collection agents (DCAs) instantiated at protected systems report information concerning protected system resources to the protection system, which creates from that information a set of threat attack detection metrics (TADMs) by which it evaluates payloads of the intercepted traffic. In particular, the intercepted traffic is assessed using conventional threat detection approaches to identify suspect payloads. The suspect payloads are additionally evaluated against the TADMs to determine if they contain any references to specific resources of the protected system. For those of the suspect payloads for which the TADM evaluation reveals positive results, the protection system provides an alert that a targeted attack has been recognized.
US11258808B2 Methods and systems for identification of breach attempts in a client-server communication using access tokens
Embodiments provide a method of using access tokens for identification of breach attempts in a client-server communication. The method includes receiving, by a server system, a token validation request for validation of a token from an Application Programming Interface (API) server sent from a client device to the API server. The method includes accessing one or more token configuration parameters associated with a valid token. The token configuration parameters include one or more of a number of allowable access attempts using the valid token in the API session and a range of frequency of allowable access attempts using the valid token in the API session. The method includes verifying whether the token conforms to the token configuration parameters associated with the valid token. The method further includes determining a breach attempt associated with the token if the token does not conform to the token configuration parameters.
US11258800B2 Managing admin controlled access of external resources to group-based communication interfaces via a group-based communication system
Embodiments of the present disclosure relate to managing admin-controlled access of external resources to group-based communication interfaces associated with an organization, via a group-based communication system including APIs for improved external resource permissioning, provisioning, and access handling. Embodiments include methods, computer program products, apparatuses, and systems configured to receive an external resource access request, determine an organization identifier, obtain an admin response indication, set an external resource permission status for the external resource based on the admin response indication, and cause rendering of the requested group-based communication interface based on the admin response indication. Embodiments further relate to provisioning and handling requests for services associated with an external resource by managing one or more single-interface access tokens linked to a multi-interface access token.
US11258791B2 Linked account system using personal digital key (PDK-LAS)
One embodiment of the invention includes a system comprising: a personal digital key and a computer readable medium that is accessible when authenticated by the personal digital key.
US11258788B2 Protections against security vulnerabilities associated with temporary access tokens
Disclosed embodiments relate to systems and methods for automatically detecting and addressing security risks in code segments. Techniques include identifying a request from a network identity for an action involving a target network resource, wherein the action requires a temporary access token. Techniques further include performing, based on a security policy, at least one of: storing the temporary access token separate from the network identity and providing the network identity with a customized replacement token having an attribute different from the temporary access token; or creating a customized replacement role for the network identity, the customized replacement role having associated permissions that are customized for the network identity based on the request.
US11258787B2 Network request handling based on optically-transmitted codes
A computing device determines whether or not to authorize a network request. In particular, responsive to the computing device receiving the network request from a mobile device, the computing device controls a plurality of light fixtures to each optically transmit a respective challenge code. The computing device approves or rejects the network request based respectively on whether or not a group of the challenge codes is received from the mobile device, each challenge code in the group being optically receivable at a location authorized for approving the network request.
US11258786B2 Generating derived credentials for a multi-tenant identity cloud service
A multi-tenant system that provides cloud-based identity management receives a request to execute a job, where the job has a scheduled start time, or a timeframe to complete, that exceeds the validity time of a request access token. The system generates the request access token corresponding to the job, where the request access token has access privileges. The system schedules the job and persists the request access token. The system triggers the job at the scheduled start time and generates a derived access token based on the request access token, where the derived access token includes the access privileges. The system then injects the derived access token during runtime of the job and calls a service using the derived access token to execute the job.
US11258784B2 Ownership maintenance in a multi-tenant environment
Approaches presented herein enable credentials to be revoked or otherwise modified while limiting the impact of inadvertent or unintended changes in access. In some embodiments, the revocation of a credential can occur over a period of time with the level of access being diminished over that period, in order to prevent an inadvertent denial of access while indicating to the requestor that there is an issue with the credential. When a new policy is created for a new credential, a prior policy can be retained for at least a period of time such that users with inadvertently revoked access can obtain a level of access per the previous policy. Various embodiments trace the calls for a credential throughout the system in order to determine which services, processes, or components might be affected by the revocation, such that an appropriate remedial action can be taken.
US11258783B2 Authentication with random noise symbols and pattern recognition
Disclosed in some examples are methods, systems and machine-readable mediums which allow for more secure authentication attempts by implementing authentication systems with credentials that include interspersed noise symbols in positions determined by the user. These systems secure against eavesdroppers such as shoulder-surfers or man-in-the middle attacks as it is difficult for an eavesdropper to separate the noise symbols from legitimate credential symbols.
US11258781B2 Context and device state driven authorization for devices
In some examples, a target device determines that each device of a plurality of devices (i) includes a certificate that is provided to each device during provisioning, (ii) is within a predetermined distance from the target device, (iii) includes a beacon secret that is broadcast to each device at a predetermined time interval, and (iv) that either: (a) a privilege level associated with at least one device of the plurality of devices satisfies a particular privilege level specified by an access policy or (b) a number of the plurality devices with the determined distance from the target device satisfies a predetermined number specified by the access policy. The target device grants at least one device of the plurality of devices access to the target device, and receives a message from the at least one device. The target device initiates an action based at least in part on the message.
US11258777B2 Method for carrying out a two-factor authentication
The invention relates to a method for carrying out a two-factor authentication between a client and a relying party, wherein, as the second factor, a data carrier is employed which carries out a communication with a token server.
US11258772B2 Secured communication from within non-volatile memory device
An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.
US11258770B2 Methods and devices for delegation of distribution of encrypted content
A method for requesting proof of delegation for delivery of content to a client terminal via an encrypted connection. The content is referenced on a content server, to which the client terminal emitted a request to obtain the content. The content server has delegated the delivery of the content to a primary delivery server. The method is implemented by a secondary delivery server, to which the primary delivery server has delegated the delivery of the content. The method includes: receiving a request to establish an encrypted connection, from the client terminal, including an identifier of the content server; emitting a request for proof of delegation of delivery, addressed to the content server; receiving of a message from the content server, including an encryption key; emitting a response for establishing an encrypted connection, addressed to the client terminal; and establishing the encrypted connection with the client terminal using the encryption key.
US11258766B2 VNF package signing system and VNF package signing method
A VNF package signing system, comprises an orchestration unit sending an acknowledge of receiving a VNF package including the VNF image, in response to the receiving the VNF package from a sender, a storage unit storing the VNF package and generating a certificate for the VNF package using a private key for at least generating a certificate for signing the VNF package and a HISEE (Hardware Isolated Secured Execution Environment) unit providing the private key in response to the request from the storage unit. The orchestration unit sends the acknowledge of receiving a VNF package when the storage unit successes generating the certificate of the VNF package.
US11258760B1 Stateful distributed web application firewall
A method and system are disclosed. A first service engine among a plurality of service engines detects a traffic violation of a web application policy for an instantiation of a virtual service on the first service engine. The service engines maintain corresponding instances of a shared state of policy violations for the web application policy. In response to detecting the traffic violation, a first instance of the shared state on the first service engine is updated. The first service engine broadcasts the updated first instance of the shared state. Remaining service engines, which have instantiations of the virtual service, update their instances of the shared state in response to receiving the updated first instance. The instances of the shared state are aggregated to obtain an aggregated shared state. It is detected whether the aggregated shared state triggers an application policy rule for the web application policy.
US11258759B2 Entity-separated email domain authentication for known and open sign-up domains
An email validation system receives an email validation request from a requestor to validate an email, the email validation request indicating at least a sender domain indicating a domain of the sender of the email. The email validation system determines whether the sender domain is in a whitelist of known domains, wherein a known domain is a domain that is linked to an organization whose provenance is known, such that it can be linked to an identifiable entity in the real world. The email validation system generates, in response to determining that the sender domain is not in the list of known domains, a message indicating that the email is not valid. The email validation system generates, in response to determining that the sender domain is in the list of known domains, the message indicating that the email is valid, and transmits the message to the requestor.
US11258755B2 Method and system for processing coherent data
Methods, systems and computer readable storage medium for processing coherent data are provided. In an embodiment, a method for processing coherent data includes dividing the coherent data into two separate frames. Further, the method includes applying a same coherency number to the two separate frames and transmitting a signal including the two separate frames to a receiving module. The method also includes determining whether the two separate frames match based on the same coherency number. When the two separate frames match, the method outputs the two separate frames to downstream logic. The method may include adding the two separate frames to a buffer populated with a selected number of most recently received frames and, when the two separate frames do not match, identifying a selected frame from the two separate frames and searching the buffer for a matching frame from the most recently received frames.
US11258753B2 Method for detection of DNS spoofing servers using machine-learning techniques
The present disclosure is related to the network communication technology field and relates to a method for the classification and recognition of the Domain Name System (DNS) server, using machine-learning techniques. The classification process assigns a given DNS server as belonging to a preset of classes. For example, it enables to label a DNS server as either benign or malicious. On the other hand, the recognition process seeks the identification of the DNS server behavioral profile, which, consequently, can be used to assess the DNS server trustworthiness before DNS responses can be reliably used, e.g. identification of well-known and trusted DNS servers. Hence, the present patent, by the means of detecting the DNS server RFC adherence improves user security through the classification and recognition of DNS characteristics. Therefore, security solutions can use the DNS server characteristics to assess its trustworthiness before DNS responses can be reliably used.
US11258747B2 Method for controlling notification and electronic device therefor
An operation method of an electronic device, according to various embodiments, comprises the steps of: displaying a notification list; determining a first notification among a plurality of notifications, which are included in the notification list, according to the detection of a first input; and displaying the notification list based on the determination. The first notification is maintained in the notification list even if a second input for initializing the notification list is detected. A second notification among the plurality of notifications is deleted from the notification list according to the detection of the second input.
US11258745B2 Emoji response display method and apparatus, terminal device, and server
The present disclosure provides a method and an apparatus for displaying an emoji reply, a terminal device, and a server. The method includes: popping up an emoji box quickly in response to an operation performed by a user on a target chat message on a chat interface to pop up the emoji box, sending an emoji selected by the user from the emoji box to a server directly as an emoji reply; and displaying the emoji entered by the user and a user label on the target chat message in accordance with instruction information returned by the server.
US11258738B1 Messaging system with circumstance configuration framework
An example method comprises: receiving, at the server from a first client device, a request for access to a client feature on the first client device; determining, by the server, an applicable rule for the access request, the applicable rule having a plurality of nodes; determining, by the server, device capabilities needed for the determined rule; determining, by the server, nodes that can be executed and nodes that cannot be executed, based on the device capabilities; executing, by the server, nodes that can be executed to reach a partial decision for the applicable rule; pruning the rule to remove executed nodes and generate a pruned rule that includes nodes that cannot be executed; transmitting the pruned rule and partial decision to the device. The pruned rule is executed on the first client device with partial decision to generate a final decision. The client feature is configured based on the decision.
US11258736B2 Matching and connection methods and systems requiring video communication
Methods and systems for matching and connecting people are described and comprise a plurality of user profiles and user accounts associated with a plurality of users wherein a user may be presented with user profiles of candidate matches, matched at least in part on criteria specified by the user. Following mutual match interest indications from two users, a match is created therebetween and a connection is possible, however, the connection between the two users is contingent on a qualified video chat therebetween and mutual connection interest indications therefrom. Communication between two users of a match is restricted and controlled towards satisfying the qualified video chat requirement. Upon establishing a connection, the two users are enabled for ongoing communication with each other.
US11258735B2 Intelligent, trackable, and actionable conversational systems and methods
Intelligent, trackable, and actionable conversational systems and methods identify specific items in a stream of messages representing conversational primitives as described below and organize them in a structured and actionable form (referenced as Conversational Primitives Dashboard below), further triggering automated workflows. Advantageously, the structured and actionable form improves collaboration providing a layer of productivity to augment messaging. A method includes, subsequent to identification of messages matching a plurality of conversational primitives, analyzing messages in a conversational service to identify the messages matching any of the conversational primitives; responsive to identifying the messages, converting each of the messages into an associated structured form, wherein each message is identified as a specific conversational primitive of the plurality of conversational primitives and the associated structured form is based on the specific conversation primitive; and maintaining all of the messages in their associated structured form.
US11258730B2 Generating a plurality of selectable responses based on a database indexed by receiver devices storing responses to similar SMS messages
A method is provided to receive an SMS message from a sender device addressed to a receiver device. Similar SMS messages addressed to the receiver device are determined. One or more of the most common responses to the similar SMS messages are determined. One or more of the most common responses are transmitted as selectable responses to the receiver device. A selected response is sent to the sender device. Another method is provided to receive an SMS message from a sender device and transmit the SMS message to a receiver device. A response from the receiver device may be received and transmit to the sender device. The SMS messages and responses collected by repeating this process may be stored in a database so that the most frequently asked questions and their corresponding most frequent answers may be determined. The most frequently asked questions and their corresponding answers may be used to build a webpage of a website.
US11258723B2 Data processing method and apparatus, and switching device using footprint queues
This application discloses a data processing method and apparatus, and a switching device. The data processing method includes: obtaining a destination address of a data packet received by an input port; determining an available output port based on the destination address; determining a busy degree of the available output port, when there is no non-busy available output port in the available output port, determining a quantity of footprint queues on the available output port, and selecting an available output port with a largest quantity of footprint queues as a target output port; determining a busy degree of a queue on the target output port, and when there is no non-busy queue on the target output port, selecting a footprint queue on the target output port as a target output queue. In the foregoing manners, a network resource is properly used, and network blocking can be effectively alleviated.
US11258722B2 Telegram splitting transmission method for bidirectional networks
A data transmitter is provided, having: a generator for generating transmission data packets, configured to split a first data packet into at least three transmission data packets, each of the transmission packets being shorter than the first data packet, the generator being configured to channel-encode the at least three transmission packets such that only a portion thereof is required for decoding the first data packet; a transmission element for transmitting data packets, configured to transmit the at least three transmission packets in a frequency channel via a communications channel with a time gap; a monitor element for monitoring the frequency channel, configured to recognize an interference or transmission of a further data transmitter in the frequency channel; the transmission element being configured not to transmit via the communications channel a packet, waiting for transmission, of the at least three transmission packets if an interference or transmission from a further data transmitter is recognized by the monitor element at the time of transmitting the transmission data packet.
US11258719B1 Methods, systems and computer readable media for network congestion control tuning
The subject matter described herein includes methods, systems, and computer readable media for network congestion control tuning. A method for network congestion control tuning occurs at a network congestion control tuning analyzer. The method includes receiving in-band telemetry (INT) metadata from a system under test (SUT); analyzing network information associated with one or more remote direct memory access (RDMA) transactions for determining a tuning action for adjusting a data center quantized congestion notification (DCQCN) mechanism associated with the SUT, wherein the network information includes the INT metadata and DCQCN information; and performing the tuning action for adjusting the DCQCN mechanism associated with the SUT.
US11258715B2 Stateful packet inspection and classification
Stateful inspection and classification of packets is disclosed. For a first packet associated with a network traffic flow, a differentiated services header value (DSHV) is determined to associate with the first packet. The DSHV is used to perform a lookup of a quality of service treatment associated with the DSHV. The treatment is applied to the first packet. A determination is made, for a second packet associated with the network traffic flow, to associate a second DSHV with the second, where the second DSHV is different from the first DSHV.
US11258713B2 Policy-based proximity routing
In some embodiments, a first network device in a first site sets a first IP address for an interface of the first network device to a value of a second IP address of a second network device in a second site. Policies are added in a policy table to cover IP addresses used in the second site and a specific route for a third IP address associated with a first workload migrated from the second site to the first site is added into a routing table. The first workload is on a stretched network that is coupled via a layer 2 channel. The policy table configures the first network device to send a second packet from the first workload to a third workload in the second site via the layer 2 channel when an IP address for the third workload does not match an eligible route in the routing table.
US11258711B2 Split-brain prevention in a high availability system during workload migration
In some embodiments, a method receives a control message from a second host. The control message includes a first address to use as a next hop to reach an active workload that has migrated to the second host from another host. The method reprograms a local route table to include a policy to send packets to check a liveness of the active workload with the next hop of the first address. A packet is sent from a standby workload to the active workload using the next hop of the first address to check the liveness of the active workload. The packet is encapsulated and sent between the first host and the second host using an overlay channel between a first endpoint of the overlay channel on the first host and a second endpoint of the channel on the second host.
US11258709B2 Detecting communication network insights of alerts
In one embodiment, the system identifies one or more geographic areas covered by a communication network. The system determines, for each identified geographic area, a congestion metric for the identified geographic area based at least on a difference between a first and second reference point on a network speed curve, wherein the network speed curve represents download speeds for a volume of traffic in the identified geographic area. The system identifies one or more network traffic congestions in one or more of the identified geographic areas based on a comparison of the respective congestion metrics of the identified geographic areas to a threshold congestion metric. The system sends, to one or more operators of the communication network, one or more alerts about the identified network traffic congestions.
US11258708B2 Communication method and communications apparatus
A communication method and a communications apparatus, where the method includes: assigning, by a control plane device, an Internet Protocol (IP) address to a user equipment; obtaining, by the control plane device using a routing policy network element, a routing rule corresponding to the IP address; and sending, by the control plane device, the routing rule and the IP address to the user equipment, where the routing rule is used by the user equipment to determine a source IP address when the user equipment initiates a service.
US11258707B1 Systems for building data structures with highly scalable algorithms for a distributed LPM implementation
Described are programmable IO devices configured to perform operations. These operations comprise: determining a set of range-based elements for a network; sorting the set of range-based elements according to a global order among the range-based elements; generating an interval table from the sorted range-based elements; generating an interval binary search tree from the interval table; propagating data stored in subtrees of interior stages of the interval binary search tree to subtrees of a last stage of the interval binary search tree such that the interior stages do not comprise data; converting the interval binary search tree to a Pensando Tree; compressing multiple levels of the Pensando Tree into cache-lines; and assembling the cache-lines in the memory unit such that each stage can compute an address of a next-cache line to be fetched by a next stage.
US11258703B1 Data plane for learning flows, collecting metadata regarding learned flows and exporting metadata regarding learned flows
Some embodiments provide a data-plane forwarding circuit that can be configured to learn about a new message flow and to maintain metadata about the new message flow without first having a control plane first configure the data plane to maintain metadata about the flow. To perform its forwarding operations, the data plane includes several data message processing stages that are configured to process the data tuples associated with the data messages received by the data plane. In some embodiments, parts of the data plane message-processing stages are also configured to operate as a flow-tracking circuit that includes (1) a flow-identifying circuit to identify message flows received by the data plane, and (2) a first set of storages to store metadata about the identified flows.
US11258696B1 Low-latency signaling-link retimer
A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.
US11258689B2 Mobility network slice selection
Core network slices that belong to a given operator community are efficiently tracked at the network control/user plane functions level, with rich data analytics in real-time based on their geographic instantiations. In one aspect, an enhanced vendor agnostic orchestration mechanism is utilized to connect a unified management layer with an integrated slice-components data analytics engine (SDAE), a slice performance engine (SPE), and a network slice selection function (NSSF) in a closed-loop feedback system with the serving network functions of one or more core network slices. The tight-knit orchestration mechanism provides economies of scale to mobile carriers in optimal deployment and utilization of their critical core network resources while serving their customers with superior quality.
US11258685B1 Packet generation-based bidirectional forwarding detection
A method of performing bidirectional forwarding detection (BFD) by a hardware forwarding element that includes a set of ingress pipelines and a set of egress pipelines. Each ingress pipeline includes a packet generator. A packet generator in a first pipeline periodically generates a pair of packets to monitor the health of a particular egress link. The pair includes a BFD transmit packet and a BFD dummy transmit packet. The method forwards each dummy BFD transmit packet to a first egress pipeline and increments a counter at the first egress pipeline. Each BFD packet is transmitted through the particular egress link to a network node. BFD packets received from the network node are forwarded to the first egress pipeline and the value of the counter is rest. The method marks the particular egress link as failed when the value of the counter exceeds a predetermined threshold.
US11258683B2 Web services platform with nested stream generation
A web services platform includes a data collector and a timeseries service. The data collector is configured to collect samples of data points and generate input timeseries including a plurality of the samples. The timeseries service is configured to identify a first timeseries processing workflow that uses the input timeseries as an input and defines processing operations to be applied to the samples of the input timeseries, perform the processing operations defined by the first timeseries processing workflow to generate a first derived timeseries comprising a first set of derived timeseries samples, identify a second timeseries processing workflow that uses the first derived timeseries as an input and defines processing operations to be applied to the samples of the first derived timeseries, and perform the processing operations defined by the second timeseries processing workflow to generate a second derived timeseries comprising a second set of derived timeseries samples.
US11258681B2 Application assessment and visibility for micro-segmentation of a network deployment
A method for visualizing network flows of a network is provided. The method monitors network flows between a group of machines in a network. The method associates identifiers with the monitored network flows. The method aggregates the monitored network flows into a set of groups based on the associated identifiers. The method displays a set of flow records for the each group of the set of groups.
US11258677B1 Data representation generation without access to content
Techniques for generating a data representation without access to content are described. A method for generating a data representation without access to content comprises receiving a request to analyze one or more data items in a protected area of the provider network, sending the request to the protected area of the provider network, wherein the cluster model is used to identify a cluster identifier associated with each of the one or more data items, receiving the cluster identifier associated with each of the one or more data items, and regenerating each of the one or more data items based on the cluster identifier.
US11258674B1 Methods and systems for predicting successful data transmission during mass communications across computer networks featuring disparate entities and imbalanced data sets using machine learning models
Methods and systems for predicting successful data transmission during mass communications across computer networks featuring disparate entities and imbalanced data sets using machine learning models. For example, the methods and systems provide a prediction as to whether or not a communication will be successful prior to the transmission being sent. Moreover, in some embodiments, the methods and systems described herein provide probability of a successful transmission as a function of time. For example, the methods and system provide a probability of how likely a communication will succeed (or fail) if it is sent at various times. Additionally, in some embodiments, the methods and systems may alert a sender prior to the transmission of a communication that the transmission is likely to succeed or fail.
US11258671B1 Functionality management for devices
Systems and methods for functionality management of devices are disclosed. Multiple computing devices may be located in the same environment and/or space and at least two of those computing devices may be configured to perform a given functionality. In these and other examples, one of the devices may be identified as a primary device and the other devices may be identified as secondary devices based on, for example, historical usage data, audio-signal data, computer-vision analysis, and/or one or more other criteria. The functionality may be disabled on the secondary devices until the secondary devices are utilized and/or until a triggering event occurs.
US11258664B2 System for provisioning racks autonomously in data centers
A provisioning system autonomously and asynchronously brings up data center racks. In an embodiment, the provisioning system determines presence of a first and second device connected to a network. The provisioning system generates a first and second thread for validation of the first and second devices, respectively. Responsive to determining by the first thread that the first device is not validated, the provisioning system notifies a detection system that the validation of the first device has not passed. Responsive to determining by the second thread that the second device is validated, the provisioning system provisions the second device for integration with one or more provisioned devices on the network.
US11258662B2 Dedicated virtual computing system servers
A virtual computer system service receives a request from a customer to provision a dedicated server for the exclusive use of the customer. The dedicated server may be used to launch one or more virtual machine instances. The virtual computer system service subsequently selects, from a pool of available servers, a server that can be dedicated to the customer and that does not have capacity allocated to any other customer. The virtual computer system service may update a database to specify, in an entry corresponding to the selected server, that the server has been dedicated for the exclusive use of the customer. Once the database has been updated, the virtual computer system service will enable the customer to launch a virtual machine instance using the dedicated server.
US11258661B2 Initializing server configurations in a data center
A system for configuring a data center includes a fabric management server coupled to a management switch. A provisional Software Defined Networking (SDN) controller executing on the fabric management server can discover physical servers coupled to the management switch, receive network interface configuration information from the physical servers, and use the discovered network interface configuration information to determine a configuration for switches and servers coupled to an IP fabric. The configuration can be migrated to a full functionality SDN controller.
US11258660B2 Configuring the zone served by a base station providing wireless communication
Methods and apparatuses for configuring the zone served by a base station providing wireless communication for a plurality of user equipment located in moving vehicles are disclosed. Motion reports are received from the user equipment, indicating a current location, a current direction of motion, and a current speed of the moving vehicles. The motion reports are received from at least one of: user equipment currently using the base station for wireless communication; user equipment currently within the zone served by the base station, but not using the base station for wireless communication; and/or user equipment currently using at least one neighbouring base station to the base station for wireless communication. A configuration for the zone served by the base station is then determined, based on the motion reports and on locations of the base station and of the at least one neighbouring base station. The configuration for the zone served by the base station is then applied to the base station.
US11258652B2 System and method for placeshifting media playback
Systems and methods of placeshifting media playback between two or more devices are provided. For example, a method for placeshifting media may include downloading onto a first device an index of files accessed or modified on a second device via a data storage server, at least one of the files being a media file played on the second device. The first device may display a user selectable list of the files on the first device before issuing a request for the media file to the data storage server. The data storage server may send the media file to the first device from the data storage server, and the first device may play back the media file where the second device left off.
US11258650B2 Communication method, communications apparatus, and storage medium
A communication method, a communications apparatus, and a storage medium are disclosed, to reduce a probability that consecutive bit errors occur in a communications system. A received to-be-sent signal is modulated to obtain a modulated signal, and N rounds of operations are further performed on the modulated signal to obtain an encoded signal. An output of the 1st-round operation in the N rounds of operations is determined based on the modulated signal and an output that is of the Nth-round operation and that is processed by a first delay circuit, and an output of the ith-round operation in the N rounds of operations is determined based on an output of the (i−1)th-round operation and an output that is of the Nth-round operation and that is processed by a second delay circuit, where i is an integer greater than 1 and less than or equal to N.
US11258645B2 Method and apparatus for sequence generation
A method and apparatus for generating a reference signal sequence for performing channel estimation. In one embodiment, the method includes: determining an initialization value; limiting the initialization value to be less than a predetermined positive integer M to provide a limited initialization value; mapping the limited initialization value into an initialization sequence having a predetermined number L of sequence values; providing the initialization sequence to a pseudo-random number generator to generate a pseudo-random number sequence; and generating the RS sequence based on the PRNS.
US11258643B1 Frequency modulation tracking for band rejection to reduce dynamic range
In at least one embodiment of the invention, a method for reducing a dynamic range of a received radio frequency signal includes receiving digital IQ signals corresponding to an in-phase component of the received radio frequency signal and a quadrature component of the received radio frequency signal. The method includes demodulating the digital IQ signals to generate an instantaneous frequency signal. The method includes selecting a center frequency of a selectable filter according to whether an interfering signal is detected in a target frequency band of the received radio frequency signal. The center frequency is selected from a predetermined frequency and an estimated center frequency determined using the instantaneous frequency signal. The method includes filtering the digital IQ signals using the selectable filter configured using the center frequency to generate output digital IQ signals.
US11258640B2 Feedback control systems for wireless devices
An apparatus for a mobile communication device adapted for digital pre-distortion that includes a memory and a processor operatively coupled to the memory of the processor. The processor receives a first input signal and also receives a first output signal from a power amplifier that is based on the first input signal. The processor additionally varies compression applied to a second input signal based on the first output signal of the power amplifier, generates a distortion compensation vector for the second input signal based on the first output signal of the power amplifier, and also varies an input excitation signal supplied to the power amplifier based on the first output signal of the power amplifier.
US11258639B2 Non-linear equalizer in communication receiver devices
Disclosed are methods, systems, devices, apparatus, media, design structures, and other implementations, including a method is that includes receiving, at a receiver device, a signal transmitted from a remote wireless device, with the signal including a training sequence, and updating, based on the training sequence, one or more adjustable characteristics for a non-linear equalizer of the receiver device, with the one or more adjustable characteristics controlling signal non-linear compensation processing to correct non-linear distortions affecting communication signals transmitted from the remote wireless device. In some embodiments, the method may further include updating, based on the training sequence, additional one or more adjustable characteristics for a linear equalizer of the receiver device, with the additional one or more adjustable characteristics controlling signal linear compensation processing to correct linear distortions affecting the communication signals.
US11258638B2 Gateway device and system and method for use of same
A gateway device and system and method for use of the same are disclosed. In one embodiment, multiple wireless transceivers are located within an in-wall housing, which also interconnectedly includes a processor, memory, various physical ports and wireless transceivers. To improve convenience, the gateway device may establish a pairing with a proximate wireless-enabled interactive programmable device. Virtual remote control functionality for various amenities may then be provided. To improve safety, the gateway device may be incorporated into a geolocation and safety network.
US11258635B2 Overlay network routing using a programmable switch
The techniques discussed herein include storing a fast-path and a slow-path table in a memory associated with a programmable switch, such as a cache of the programmable switch. An offload controller may control the contents of the fast-path and/or slow-path table and may thereby control behavior of the programmable switch. The programmable may route a received packet to a gateway if the packet generates a hit in the slow-path table. If the received packet generates a hit in the fast-path table, the packet may be forwarded directly to a virtual private cloud (VPC), virtual switch thereof, and/or to a virtual machine (VM).
US11258632B2 Unavailable inter-chassis link storage area network access system
A Storage Area Network (SAN) access includes a first aggregated switch device that is coupled to a host device, a Local Area Network (LAN), and a SAN, and a second aggregated switch device that is coupled to the host device, the LAN, and the SAN. The second aggregated switch device is connected to the first aggregated switch device via an Inter-Chassis Link (ICL). The second aggregated switch device detect that the ICL has become unavailable and, in response, prevents Internet Protocol traffic between the host device and the LAN while transmitting storage traffic between the host device and the SAN.
US11258630B2 Controller area network receiver
A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.
US11258626B2 Heating cooking system
A heating cooking system includes a cooking device (100), servers (400, 500) for communicating with the cooking device (100) via a communication network and an information terminal (300) for communicating with the servers (400, 500) via the communication network. The servers (400, 500) have a communication tool manager (400) for managing communication tools of the information terminal (300) for users. The cooking device (100) has posting sections for posting information relating to executed cooking menus to the communication tool manager (400) of the servers (400, 500) via the communication network (N).
US11258624B2 System and method for providing remote site security for information handling systems in a protected network
A network interface card includes a memory configured to store a credential associated with one of a manufacturer of the network interface card, a particular manufacturer of the server that includes the network interface card, or another manufacturer of an enclosure that holds the network interface card. A processor performs network discovery to identify devices in a local area network, performs port configuration, and establishes a secure network connection with a cloud service broker. Subsequent to the establishment of the secure network connection, the processor submits a provisioning request to the cloud service broker, receives a response to the provisioning request, and applies the security policies to the network interface card, wherein the security policies are for the devices of the local area network.
US11258617B1 Device identity using key agreement
A client device may be provisioned with a digital certificate to support various operations. The client may transmit a certificate request to a server. The server may initiate a key agreement process using a short-lived private key generated at the server and a public key of the device to derive a symmetric key. The symmetric key may be used to encrypt a payload that includes the digital certificate and an associated private key. Further, the server initiates a key agreement process using the partial private key that was generated for the client and the short-lived public key. A partial key agreement result, and the encrypted payload may be transmitted to the client. The client may complete the key agreement process using the partial key agreement result and a respective portion of the private key. The client may derive the encryption key and decrypt the payload to access the digital certificate.
US11258616B2 Decentralized key management system and method
A decentralized key management system according to an embodiment of the present disclosure includes a bootstrap for generating a key and obtaining a certificate corresponding to the generated key, a memory for receiving the key and the certificate from the bootstrap and storing the key and the certificate, a container, in response to a mount command of the bootstrap, for reading the key and the certificate from the memory and being mounted with the key and the certificate, and a controller for generating the bootstrap, and deleting the bootstrap after the container mounts the key and the certificate.
US11258615B2 Systems and methods for secure certificate management
A method for managing certificates includes the steps of transmitting, over an electronic network by an electronic device of a client, a certificate request to a certificate management portal separate from the client, establishing an interaction with an electronic interface of a certificate authority by the certificate management portal; generating, by the certificate authority, a certificate package, delivering the generated certificate package to the certificate management portal, and downloading from the certificate management portal, by the client, at least one certificate of the delivered certificate package.
US11258612B2 Method, apparatus, and electronic device for blockchain-based recordkeeping
A method for blockchain-based data verification is provided. The method includes: obtaining target data submitted by a data submitter, wherein a first data digest of the target data is recorded in a blockchain; computing a second data digest of the target data; determining whether the second data digest matches the first data digest of the target data recorded in the blockchain; and determining that the target data submitted by the data submitter is valid in response to determining that the second data digest matches the first data digest of the target data recorded in the blockchain.
US11258608B1 Systems for secure access to protected content in a content management system
A system having a content management system (CMS) and an edge node of a content delivery network is provided. The CMS and edge node are configured to perform a method that includes sharing a server secret between the CMS and the edge node and using, by the CMS, the server secret to generate a signing key. The signing key includes a signing secret generated using the server secret. The signing key is transmitted to a client system, and the client system receives a request for a content asset from a user device and authorizes said user device for access to the content asset. The client system uses the signing key to generate a signed URL for the content asset, and the user device is redirected to the signed URL. Responsive to receiving, by the edge node, the signed URL from the user device, the method proceeds to validating the signed URL by the edge node. Validating the signed URL uses the server secret to rederive the signing secret based on the signed URL. Responsive to successful validation of the signed URL by the edge node, the content asset is provided from the edge node to the user device.
US11258604B2 Rewiring cryptographic key management system service instances
Embodiments are directed to rewiring a key management system (“KMS”) service instance (“SI”) with associated keys. Embodiments, in response to a request, delete a first SI that is mapped to one or more keys. To restore the keys, embodiments create a second SI and map the second SI to the one or more keys.
US11258600B2 Secure communication in accessing a network
Secure communication in accessing a network is described herein. An example apparatus can include a memory and a processor coupled to the memory. The processor can be configured to receive an identity public key from the identity device. The identity public key can be received in response to providing, to the identity device, a request to modify content of the identity device. The processor can be further configured to encrypt data corresponding to subscriber information using the identity public key, provide (to the identity device) the encrypted data to store the subscriber information in the identity device, and access a network operated by a network operator via the data stored in the identity device.
US11258598B2 Smartphones based vehicle access
A symmetric key-based generation and distribution system and method for a vehicle access authentication framework is provided, the framework comprising: a first device operated by a car owner, a second device operated by a delegated user, and a third device residing in a vehicle. The first device is configured to: request for an authentication key from the third device, the request for the authentication key comprising an ID of the first device, idO; receive an authentication key KidO from the third device; and generate a delegated authentication key KidU based on authentication key KidO and an ID of the second device in response to receiving a request for delegated authentication key from the second device, the request for delegated authentication key comprising the ID of the second device.
US11258597B2 Key derivation from PUFs
Some embodiments relate to an electronic cryptographic device (100) arranged to determine a cryptographic key. The cryptographic device is arranged for an enrollment phase and a later reconstruction phase. The cryptographic device comprising a physically unclonable function (PUF) (110) and a processor circuit. The circuit being configured to determine during the enrollment phase debiasing data (142), first noise reduction data (131) and first noise reduction data. The circuit being configured to during the reconstruction phase compute at least one cryptographic key from first corrected bits and second corrected bits.
US11258595B2 Systems and methods for “Machine-to-Machine” (M2M) communications between modules, servers, and an application using public key infrastructure (PKI)
Methods and systems are provided for supporting efficient and secure “Machine-to-Machine” (M2M) communications using a module, a server, and an application. A module can communicate with the server by accessing the Internet, and the module can include a sensor and/or an actuator. The module, server, and application can utilize public key infrastructure (PKI) such as public keys and private keys. The module can internally derive pairs of private/public keys using cryptographic algorithms and a first set of parameters. A server can authenticate the submission of derived public keys and an associated module identity. The server can use a first server private key and a second set of parameters to (i) send module data to the application and (ii) receive module instructions from the application. The server can use a second server private key and the first set of parameters to communicate with the module.
US11258594B2 Quantum key distribution using a thermal source
A passive continuous-variable quantum key distribution scheme, where Alice splits the output of a thermal source into two spatial modes, measures one locally and transmits the other mode to Bob after applying attenuation. A secure key can be established based on measurements of the two modes without the use of a random number generator or an optical modulator.
US11258591B2 Cryptographic key management based on identity information
Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for managing cryptographic keys based on user identity information. One of the methods includes receiving a request to store identity information and a user key pair to a memory on a chip, the request being digitally signed with a digital signature, the identity information uniquely identifying the user, and the user key pair being assigned to the user; determining that the digital signature is authentic based on a public key pre-stored in the memory; encrypting the identity information and the user key pair; and storing the identity information and the user key pair to the memory.
US11258582B2 Distributed system and method for encryption of blockchain payloads
Distributed systems and methods for encrypting data on a blockchain network are disclosed. One system comprises at least one injector coupled to a node on the blockchain, a controller coupled to the injector, and a generator coupled to the controller. The injector intercepts messages bound for the blockchain and encrypts data in the messages using encryption information received from the controller. The controller acquires encryption information from the generator, which generates encryption keys and derives encryption information from those encryption keys. The encryption information may be divided into multiple parts and distributed between a plurality of injectors. As a result, to assemble an encryption key for encrypting or decrypting data, an injector may have to cooperate with other injectors to acquire sufficient encryption information to re-assemble the encryption key. Thereafter, once encryption information has been distributed, the system may function without further involvement of the controller or generator.
US11258577B2 Low power edge and data sampling
An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
US11258576B2 Method, device, transmitter, and receiver for detecting syncwords
The present application provides a method, a device, a transmitter, and a receiver for detecting syncwords. After inserting syncwords in a data frame to be transmitted, a transmitter transmits the data frame to be transmitted inserted with a preset number of syncwords to a receiver. Because the bit-length of information in the data frame to be transmitted inserted with the preset number of syncwords is a specified multiple of the length of the syncwords, and the symbol components of the preset number of the inserted syncwords are different, or the symbol components are the same but the orders of the symbols are different, the receiver correlates each syncword of the preset number of syncwords with the data frame to be transmitted inserted with the preset number of syncwords after receiving the data frame to be transmitted.
US11258570B2 Joint optimization of bandwidth part, search space and connected mode discontinuous reception operation in 5G New Radio
Apparatuses, systems, and methods for a user equipment device (UE) to perform a method using a status change of a timer associated with a connected mode discontinuous reception (CDRX) communication session with a base station to trigger a switch from using a first bandwidth part (BWP) to a second BWP as the active BWP for the CDRX communication session. The timer may be an on-duration timer, an inactivity timer, or a retransmission timer. The UE may also alter a monitoring schedule of a physical downlink control channel (PDCCH) in response to detecting the status change of the timer. The second BWP may have a wider or narrower bandwidth than the first BWP, depending on the type of timer and the type of status change.
US11258563B2 Sounding reference signal sending and receiving method, apparatus, and non-transitory computer-readable medium
A signal sending and receiving method includes: receiving, by a terminal device, at least one piece of resource configuration information for determining N reference signal resource groups, and each of the N reference signal resource groups includes at least one reference signal resource; and sending a reference signal on a resource in an ith reference signal resource group in the N reference signal resource groups by using a jth antenna group corresponding to the ith reference signal resource group, where the jth antenna group includes at least one antenna. The N reference signal resource groups correspond to N antenna groups, and any two of the N antenna groups are different.
US11258558B2 Transmitter, receiver, transmission method, and reception method
In a transmitter, an assignment circuit maps a phase tracking reference signal (PT-RS) onto a subcarrier, and a transmitting circuit transmits a signal containing the phase tracking reference signal. The phase tracking reference signal is mapped onto a different subcarrier for each cell, group, or mobile station.
US11258556B2 Method and apparatus for determining reference signal sequence, computer program product, and computer readable storage medium
This application provides a method for determining a reference signal sequence, a terminal device, and a network device. The method includes: receiving, by a terminal device, first indication information sent by a network device; determining, by the terminal device, a target resource based on the first indication information; determining, by the terminal device, a reference signal sequence based on parameters of a first bandwidth and parameters of a second bandwidth; and sending or receiving, by the terminal device, the reference signal sequence on the target resource. Based on the method for determining a reference signal sequence provided in this application, the reference signal sequence can be determined based on the parameters of the first bandwidth and the parameters of the second bandwidth.
US11258553B2 Carrier load control method, network device and UE
A method for controlling carrier load, a network device and a user equipment (UE) are provided. The method comprises: configuring an uplink bandwidth part set and a downlink bandwidth part set for a UE according to broadcast information, wherein the uplink bandwidth part set comprises at least two uplink bandwidth parts, and the at least two uplink bandwidth parts are a part of all uplink bandwidth parts that the network device can allocate; at least two uplink bandwidth parts comprises at least one first uplink bandwidth part comprising physical random access channel (PRACH) resource configuration information; the downlink bandwidth part set comprises at least two downlink bandwidth parts, and the at least two downlink bandwidth parts are a part of all downlink bandwidth parts that the network device can allocate.
US11258552B2 Method of transmitting sounding reference signal and device utilizing same
The invention provides a method of transmitting a sounding reference signal (SRS) and a device utilizing the same. The method comprises: a user equipment transmits, to a base station, a sounding reference signal (SRS) on a time domain symbol in a special subframe, wherein the time domain symbol comprises one or more time domain symbols of time domain symbols occupying an uplink pilot time slot; and a number of the time domain symbols occupying the uplink pilot time slot is N, N is an integer, and 3≤N≤12. The embodiment resolves a problem of an incomplete scheme of transmitting an SRS on a time domain symbol, and realizes transmission of an SRS on increased time domain symbols.
US11258550B2 Feedback information sending or receiving methods, devices and system
The embodiments of the application provide feedback information sending or receiving methods, devices and a system, and relate to the field of communication. The method includes that: a first bit length is determined, the first bit length being a number of bits for representing Transport Block (TB)-level feedback response information; a second bit length is determined, the second bit length being a number of bits for representing target TB indication information; feedback information is generated according to the first bit length and the second bit length, the feedback information including the TB-level feedback response information, the target TB indication information and code block group-level feedback response information; and the feedback information is sent.
US11258548B2 V2X communication apparatus and geo-networking transmission method
Disclosed is a geo-networking transmission method of a V2X communication apparatus. The geo-networking transmission method according to an embodiment of the present disclosure includes receiving a geo-networking packet; identifying whether the received geo-networking packet is a packet which is prestored in a buffer; determining whether to perform a forwarding progress of the geo-networking packet, when the received geo-networking packet is not a prestored packet; storing the received geo-networking packet in the buffer and starting a timer, when the forwarding progress is determined; and transmitting the geo-networking packet, when the timer expires.
US11258545B2 Counting method and communications apparatus
A counting method and a communications apparatus are provided. The method includes: determining to retransmit a first protocol layer data packet; and if the retransmission is retransmission for the first time, initializing a retransmission counter associated with the first protocol layer data packet; or if the retransmission is not retransmission for the first time and the first protocol layer data packet is not pending for retransmission, updating the retransmission counter or keeping a value of the retransmission counter unchanged. In this way, RLF can be correctly triggered, to reduce a quantity of times of unnecessary RLF triggering and reduce overheads.
US11258544B2 Uplink transmission method and corresponding equipment
A method performed by a user equipment (UE) in a wireless communication system includes receiving, from a base station (BS), code block group (CBG) information via radio resource control (RRC) signaling; identifying a physical downlink shared channel (PDSCH) of a plurality of PDSCHs belonging to a first PDSCH set or a second PDSCH set, based on the CBG information; determining a first hybrid automatic repeat request acknowledgement/negative acknowledgement (HARQ-ACK/NACK) codebook for the first PDSCH set and a second HARQ-ACK/NACK codebook for the second PDSCH set; and transmitting HARQ-ACK/NACK information generated by connecting the first HARQ-ACK/NACK codebook and the second HARQ-ACK/NACK codebook.
US11258529B2 Data transmission method, data receiving method, and data sending and receiving system
A method includes: generating indication information, where the indication information is used to indicate a resource allocation table corresponding to a first data unit in the plurality of data units; sending the indication information in a timeslot previous to a timeslot used to send the first data unit; and sending the plurality of data units, where a resource allocation table corresponding to each data unit is selected from a plurality of resource allocation tables in a cyclic manner, and a cyclically initial resource allocation table is the resource allocation table indicated by the indication information.
US11258524B2 Predictive link adaptation for V2X communications
A method, a computer-readable medium, and an apparatus are provided. The apparatus communicates with a second apparatus, including transmitting or receiving a first transmission. The apparatus receives information about the second UE from a sensor at the first UE and/or from a BSM. The apparatus determines whether the first apparatus and the second apparatus are in a LOS condition based on a correlation of the information with one or more of a channel estimation, PMI feedback, or RI feedback. The apparatus may adapt a transmission parameter for a second transmission based on a predicted location of the first apparatus or the second apparatus. The transmission parameter may include at least one of a modulation, a code rate, a DMRS density, a precoder, a CSI-RS transmission periodicity or a feedback rate.
US11258520B2 High power and data delivery in a communications network with safety and fault protection
In one embodiment, a method includes receiving at a remote network device, power and data from a central network device, wherein the power is used to power the remote network device, performing auto-negotiation with the central network device, wherein the auto-negotiation includes operating the remote network device in a low voltage mode during fault sensing of a power circuit at the remote network device, and selecting a power operating mode, wherein selecting the power operating mode includes selecting a high voltage mode if no fault is detected during the fault sensing, the high voltage mode comprising DC (direct current) pulse power. An apparatus is also disclosed herein.
US11258517B2 Burst mode spectral excursion mitigation
Techniques are described for configuring an optical network unit (ONU) in a pre-burst state prior to transitioning the ONU to a burst-on state. During the pre-burst state, a laser emitter of the ONU stabilizes to its wavelength, thereby reducing the impact of wavelength drift when the ONU transitions to the burst-on state.
US11258507B2 Ground network for end-to-end beamforming
Methods and systems are described for providing end-to-end beamforming. For example, end-to-end beamforming systems include end-to-end relays and ground networks to provide communications to user terminals located in user beam coverage areas. The ground segment can include geographically distributed access nodes and a central processing system. Return uplink signals, transmitted from the user terminals, have multipath induced by a plurality of receive/transmit signal paths in the end to end relay and are relayed to the ground network. The ground network, using beamformers, recovers user data streams transmitted by the user terminals from return downlink signals. The ground network, using beamformers generates forward uplink signals from appropriately weighted combinations of user data streams that, after relay by the end-end-end relay, produce forward downlink signals that combine to form user beams.
US11258506B2 Method and apparatus for transmitting and receiving multiple carriers with multiple antennas
A method and apparatus for receiving and processing multiple carriers with multiple antennas. The device includes a plurality of antennas for receiving signals over a plurality of carriers, and a plurality of receive chains connected to each antenna for processing a signal received on each antenna. The signal received on each antenna is split into multiple receive chains for receive processing. The antennas are grouped into a plurality of sub-groups and a signal on a first carrier is received on a first sub-group of antennas and a signal on a second carrier is received on a second sub-group of antennas. A signal on a third carrier may be received on all antennas. Multiple-input multiple-output (MIMO) on the first and second carriers may be implemented using the first and second sub-group of antennas, respectively, and MIMO on the third carrier may be implemented using all antennas.
US11258500B2 Hybrid sector selection and beamforming
An example method may include configuring a pattern of a sounding packet of a first wireless node in a resource space. Configuring the pattern may include assigning first precoders to a first subset of the resource space for a first antenna sector of the first wireless node; and assigning second precoders to a second subset of the resource space for a second antenna sector of the first wireless node. The method may include wirelessly transmitting the sounding packet with the configured pattern to a second wireless node. The method may include transmitting data packets from the first wireless node to the second wireless node according to one or more transmission parameters that are at least one of received from the second wireless node or determined based on channel state information (CSI) feedback received from the second wireless node.
US11258496B2 Communication devices and methods with hybrid beamforming
A communication device for RF-based communication with another communication device comprises digital beamforming circuitry configured to perform digital beamforming based on digital beamforming information to obtain RF data streams, and analog beamforming circuitry configured to perform analog beamforming for the obtained RF data streams. The analog beamforming circuitry is configured to perform analog beamforming training with the other communication device enabling the other communication device to compute the digital beamforming information corresponding to one or more combinations of analog beams used in said analog beamforming training. The digital beamforming circuitry is configured to receive the computed digital beamforming information and to use it for performing the digital beamforming.
US11258495B2 Hybrid beamforming method for wireless multi-antenna and frequency-division duplex systems
This invention presents a method and systems for beamforming in wireless communication comprising a base station with a plural of antennas and radio frequency transmitting and receiving chains, a plural of base band transmitting paths and base band receiving paths, and a processor that constructs a subspace for each user equipment using the principal angle information contained in partial channel state information obtained on channels associated with a part of the BS antennas, derives an analog beamforming matrix and/or an analog combining matrix from the subspaces of all the user equipment selected for communication with the base station to achieve analog beamforming, and further performs beamforming at the base band.
US11258485B2 Enhanced timing advance scheme to support MU-MIMO in integrated access and backhaul
Various embodiments disclosed herein provide for an enhanced timing advance scheme to support MU-MIMO in an integrated access and backhaul system. The timing advance scheme disclosed herein aligns the arrival time between backhaul links and access links to enable MU-MIMO gain at the receiver side. In the integrated access and backhaul system, which comprises distributed nodes, the timing advance offset for an access link transmission (a transmission to a node further away in hops from the core network, or to a user equipment device) can be modified by offsetting it with the timing advance of the backhaul link (e.g., from a parent node). This enables the arrival time for transmissions, both access link transmissions from the UE or child node, and backhaul link transmissions from a parent node to arrive at the same time.
US11258483B2 Communication device, communication method, and recording medium
Provided is a mechanism that enables appropriate resource setting with respect to a terminal device including a plurality of antenna panels. A communication device includes: a plurality of antenna panels (70) each including one or more antennas; and a control section (240) that reports, to a base station, report information regarding the number of beams that are transmittable or receivable in a same time resource on the basis of configurations of a plurality of the antenna panels.
US11258482B2 Method and apparatus for medium access control for uniform multiple access points coverage in wireless local area networks
A method and apparatus may be used in multi-AP and multi-wireless transmit/receive unit joint transmissions. The apparatus may be configured to transmit a joint transmission request on a first medium, and receive a joint transmission response on the first medium. In response, the apparatus my perform a joint transmission negotiation on a second medium and transmit data on the second medium based on the joint transmission negotiation. The apparatus may be configured to perform coordinated sectorized or beamformed transmissions through access point (AP)/PCP negotiations. The apparatus may provide an indication of support for joint transmission and coordinated sectorized or beamformed transmissions. The method and apparatus may also implement multi-AP/WTRU request-to-send (RTS)/clear-to-send (CTS) procedures. The apparatus may be configured to perform coordinated sectorized or beamforming grouping.
US11258481B2 Magnetic coupling device and communication system
According to one embodiment, there is provided a magnetic coupling device including a first coil, a second coil, a third coil, a fourth coil, a first constant-potential node and a second constant-potential node. The second coil is electrically connected with one end of the first coil and wound in a direction opposite to a direction in which the first coil is wound. The third coil faces the first coil. The fourth coil faces the second coil. The first constant-potential node is electrically connected with one end of the third coil. The second constant-potential node is electrically connected with one end of the fourth coil.
US11258480B2 System and method of optimized backup functionality for electronic control key
A key fob including at least one wireless communication circuit, a power supply node coupled to provide power to the at least one wireless communication circuit, a battery node, a battery power circuit, and an inductive power circuit. The battery power circuit provides power when a battery with sufficient charge is provided. The inductive power circuit only provides power when energized with inductive power when the battery is not provided or is not sufficiently charged. The inductive power circuit may include a rectifier circuit and an inductor and may further include regulator circuitry. The inductive power circuit does not perform wireless communications thereby simplifying circuitry and operation of the key fob and a corresponding access system. Since only configured to transfer power, the inductive power circuit may be optimized for power transfer. The access system inductively couples power to the key fob when within a predetermined coupling zone distance.
US11258478B1 Autonomously motile device with residual echo suppression
A device capable of autonomous motion includes a residual echo suppressor for suppressing echoes caused by an output reference signal. When the device outputs audio while moving with a velocity, it may receive echoes that are Doppler-shifted due to the motion. The residual echo suppressor generates estimated residual error data based on phase-shifted reference data to account for and suppress the Doppler-shifted echoes.
US11258477B2 Specific hopping patterns for repeated transmission and reception of data and methods for generating the same
In embodiments, data transmitters and data receivers use, in a first mode, a first hopping pattern and a second hopping pattern for a repeated transfer of data, and, in a second mode, a third hopping pattern for the single transfer of data, wherein the hopping patterns of the first mode and the second mode are different so that a collision probability in the repeated transmission of data by a further data transmitter in a respectively different mode may be decreased and the transmission reliability may therefore be increased.
US11258475B2 Electronic device for attenuating at least part of signal received by antenna and method for controlling communication signal
An electronic device according to a disclosed embodiment includes a first antenna, a second antenna, a first communication circuit configured to communicate in a first frequency band with the first antenna at a first data rate, a second communication circuit configured to communicate in a second frequency band with the second antenna at a second data rate, a first coupler electrically connected between the first antenna and the first communication circuit, and at least one communication circuit configured to control to identify, during at least part of a period of simultaneously transmitting a first transmit signal with the first antenna and a second transmit signal with the second antenna, an amplitude of a first receive signal including at least part of the second transmit signal detected by the first coupler, disable an operation of attenuating the at least part of the second transmit signal included in the first receive signal based on the amplitude of the first receive signal falling in a first designated range, and enable the operation of attenuating the at least part of the second transmit signal included in the first receive signal based on the amplitude of the first receive signal falling in a second designated range.
US11258472B2 Radio frequency loopback for transceivers
Methods and devices for radio frequency (RF) loopback for transceivers are described. A transceiver for communicating RF signals with a target device may transmit signals at a transmit frequency and receive signals at a (different) receive frequency. The transceiver may include a waveguide diplexer for separating and combining signals based on frequency. The transceiver may be configured to couple a loopback signal from a common port of the waveguide diplexer; the loopback signal may be based on a transmit signal. The transceiver may include a loopback translator to translate the loopback signal from the transmit frequency to the receive frequency and provide the translated loopback signal to a receiver used for receiving signals from the target device. The receiver may compare the translated loopback signal with a representation of the transmit signal to generate a compensation signal. A transmitter may use the compensation signal to adjust subsequent transmit signals.
US11258470B2 Wireless transceiver
An example device may include an antenna node configured to be coupled to an antenna element. The antenna node may be configured to pass wireless communications over multiple frequency bands. The device may also include multiple signal paths coupled to the antenna node. Each of the multiple signal paths may be configured to carry a signal from a different one of the multiple frequency bands. The device may further include a switch element coupled to the antenna node by the multiple signal paths and an amplifier circuit within the multiple signal paths between the switch element and the antenna node. The amplifier circuit may be configured to amplify the signals carried by the multiple signal paths.
US11258469B1 Demodulating surveillance signals
In some examples, a system includes at least two antennas configured to receive signals encoding first, second, and third messages in first, second, and third frequency bands. The system also includes a set of splitters configured to generate separate signals in the first, second, and third frequency bands. The system further includes a set of combiners, wherein each combiner of the set of combiners is configured to combine two or more of the separate signals. The system includes a set of mixers configured to down-convert the combined signals and at least one analog-to-digital converter configured to sample the down-converted signals. The system also includes processing circuitry configured to determine data in the first, second, and third messages based on an output of the at least one analog-to-digital converter.
US11258467B2 Filter, multiplexer, radio frequency front-end circuit, and communication device
A filter includes series resonators in a signal path. An IDT electrode included in the series resonators includes at least either first electrode fingers including variant portions or second electrode fingers not including variant portions. In the IDT electrode included in one or more series resonators of the series resonators, a direction that connects the respective other ends of a plurality of electrode fingers intersects an acoustic wave propagation direction. In a first portion and a second portion of the IDT electrode, the first and second electrode fingers are arranged in a predetermined order.
US11258466B1 System and method for high reliability fast raid soft decoding for NAND flash memories
A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate first soft information of the first codeword. The circuit may be further configured to generate second soft information of a second codeword. The circuit may be configured to generate third soft information based on the first soft information and the second soft information. The circuit may be configured to decode the result of the read operation on the flash memory using the third soft information.
US11258459B2 Methods and apparatus to parallelize data decompression
Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
US11258456B2 Method for compressing a quantum state vector and process for storing a quantum state vector
A method for compressing a quantum state vector includes: aggregating a group of several neighboring states of the vector into a cluster of states of the vector, a parameter representative of the probability of this cluster being associated with it and corresponding to the sum of the probabilities of the aggregated neighboring states in this cluster, the probability of each aggregated neighboring state being below a given aggregation threshold, and/or the sum of the probabilities of the aggregated neighboring states in a cluster being below another given aggregation threshold; and preserving a state of the vector not aggregated in a cluster, the parameter representative of its probability remaining unchanged. The method includes several steps of aggregating several distinct groups of several neighboring states of the vector, respectively into several clusters of states of the vector, and/or an aggregation step and a preservation step.
US11258454B2 Analog-digital converter
An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2L reference times corresponding to 2L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.
US11258451B2 Apparatus and method for generating an oscillation signal, mobile communication systems and mobile device
An apparatus for generating an oscillation signal is provided. The apparatus includes an input configured to receive a first reference oscillation signal, and a phase detector circuit configured to determine a phase drift of the first reference oscillation signal with respect to a second reference oscillation signal. Further, the apparatus includes a phase shifter circuit configured to generate the oscillation signal based on the first reference oscillation signal and a control signal. The control signal is based on the phase drift and a frequency control signal comprising control data for the phase shifter circuit for adjusting a frequency of the oscillation signal to a desired frequency.
US11258447B2 Integration of analog circuits inside digital blocks
A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.
US11258446B2 No-enable setup clock gater based on pulse
Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.
US11258443B2 Fast active clamp for power converters
A switching system can include a main switching device configured to switch a voltage, a gate driver having an output coupled to a drive terminal of the main switching device and configured to deliver a drive signal to the main switching device, and a clamp circuit. The clamp circuit can be coupled to the drive terminal of the main switching device. The clamp circuit can include a logic gate configured to drive a clamp switching device coupled to and configured to clamp a voltage at the drive terminal of the main switching device. A drive signal of the clamp switching device can be substantially complementary to the main switching device drive signal. The logic gate can provide at least a portion of a delay between switching transitions of the main switching device and switching transitions of the clamp switching device.
US11258441B2 Drive circuit
A drive circuit includes: a current capability switch configured to switch a current capability of driving an output transistor of a switching power supply according to whether a switch current flowing through the output transistor is in a continuous mode or in a discontinuous mode.
US11258439B2 High-voltage fast switching devices
A device for switching a high-voltage source, comprising: a plurality of switching devices coupled in series starting from a first switching device and ending in a last switching device, said device enabling coupling of said high-voltage source with at least a selected one of said switching devices; a voltage limiter coupled with said switching devices; and a switching time synchronizer; wherein said first switching device is configured to directly receive a control signal for changing a switching state of said device, said first switching device is configured to facilitate a cascaded transition of switching states in successive said switching devices in said series, where said switching time synchronizer is configured to synchronize a time at which transitions to said switching states of successive said switching devices take effect, and said voltage limiter is configured to limit overvoltage conditions to said switching devices during said transitions.
US11258436B1 Self-calibrating quadrature clock generator and method thereof
A quadrature clock generator includes a variable delay clock generator configured to receive a first clock and a third clock and output a second clock and a fourth clock in accordance with a control signal, wherein the first clock and the third clock are substantially the same but offset in timing by one half of the period; a quadrature phase error detector configured to receive the first clock, the second clock, the third clock, and the fourth clock and output a first phase detection signal and a second phase detection signal, wherein the first phase detection signal represents a relative timing between the first clock and the second clock and the second phase detection signal represents a relative timing between the second clock and the third clock; and an amplifier configured to amplify a difference between the first phase detection signal and the second phase detection signal into the control signal.
US11258433B1 Semiconductor integrated circuit and receiving device
A semiconductor integrated circuit includes a first circuit and a second circuit. The first circuit is configured to divide a first pulse signal having a first duty cycle by N (where N is an integer of 2 or more), and output 2×N second pulse signals of which phases are different from each other. The first pulse signal is a pair of differential signals. The second circuit is configured to receive one or more selection signals and calculate a logical product of one of the one or more selection signals and two of the 2×N second pulse signals to generate a third pulse signal having a second duty cycle less than the first duty cycle.
US11258429B2 Acoustic wave filter including two types of resonators
Acoustic wave devices are disclosed. An acoustic wave device can include a first filter and a second filter coupled to a common node. The second filter includes acoustic wave resonators of a first type (e.g., bulk acoustic wave resonators) and a series acoustic wave resonator of the second type (e.g., a surface acoustic wave resonator) that is coupled between the acoustic wave resonators of the first type and the common node. The acoustic wave device can further include a loop circuit coupled to the first filter, in which the loop circuit is configured to generate an anti-phase signal to a target signal at a particular frequency. In certain embodiments, the first filter is a receive filter and the second filter is a transmit filter.
US11258427B2 Acoustic wave devices
An acoustic wave device that has a better TCF and can improve a resonator Q or impedance ratio is provided. The acoustic wave device includes a substrate 11 containing 70 mass % or greater of silicon dioxide (SiO2), a piezoelectric thin film 12 including LiTaO3 crystal or LiNbO3 crystal and disposed on the substrate 11, and an interdigital transducer electrode 13 disposed in contact with the piezoelectric thin film 12.
US11258422B2 Communication module
A communication module includes an input/output switch, a duplexer, a transmit filter, and a receive filter. In the duplexer, a second side is disposed at a position farther from the input/output switch than a first side in a second direction orthogonal to a first direction. Any one of the transmit filter and the receive filter is disposed adjacent to the input/output switch in the first direction.
US11258421B2 Combiner and distributor for adjusting impedances or power across multiple plasma processing stations
Systems and methods for adjusting impedances or power or a combination thereof across multiple plasma processing stations are described. One of the systems includes a first radio frequency (RF) generator that generates a first RF signal having a first frequency, a second RF generator that generates a second RF signal having a second frequency, and a first matching network coupled to the first RF generator to receive the first RF signal. The first impedance matching network outputs a first modified RF signal upon receiving the first RF signal. The system further includes a second matching network coupled to the second RF generator to receive the second RF signal. The second matching network outputs a second modified RF signal upon receiving the second RF signal. The system further includes a combiner and distributor coupled to an output of the first matching network and an output of the second matching network.
US11258419B2 Glass-ceramic microwave filters
Embodiments of a filter for electromagnetic radiation are disclosed herein. The filter includes a first glass-ceramic substrate having a first refractive index, a second glass-ceramic substrate having the first refractive index, and a first region disposed between the first glass-ceramic substrate and the second glass-ceramic substrate. The first region has a second refractive index that is less than the first refractive index. Further, the second glass-ceramic substrate is arranged substantially parallel to and spatially disposed from the first glass-ceramic substrate. The filter transmits at least 70% of electromagnetic radiation within a band of frequencies and reflects at least 80% of electromagnetic radiation outside the band of frequencies. The band of frequencies is located within the frequency range of 20 GHz to 100 GHz.
US11258415B2 Neuromimetic circuit
A neuromimetic circuit includes: a primary single photon optoelectronic neuron; a synapse in optical communication with the primary single photon optoelectronic neuron; and an axonic waveguide in optical communication with the primary single photon optoelectronic neuron and the synapse such that the axonic waveguide optically interconnects the primary single photon optoelectronic neuron and the synapse.
US11258413B2 Power amplifier arrangement
A power amplifier arrangement comprises a power amplifier comprising at least one transistor having a first gate and a second gate. The first gate is configured to receive a radio frequency input signal superimposed with a first control signal, and the second gate is configured to receive a second control signal. The first control signal is a linearization signal varying in relation to an envelope of the input signal and the second control signal is a temperature compensation signal varying in relation to a temperature of the power amplifier, or vice versa.
US11258412B2 Radio frequency (RF) device having tunable RF power amplifier and associated methods
A radio frequency (RF) device may include an RF signal source having a selectable frequency, an RF antenna, and an RF power amplifier module coupled between the RF signal source and the RF antenna. The RF power amplifier module may include at least one input tunable cavity impedance matching device, at least one output tunable cavity impedance matching device, and a power amplifier device connected therebetween. A controller may select the selectable frequency of the RF signal source, tune the at least one input tunable cavity impedance matching device based upon the selected frequency, and tune the at least one output tunable cavity impedance matching device based upon the selected frequency.
US11258408B2 Power envelope tracker and adjustable strength DC-DC converter
An apparatus is provided which comprises: a low-side switch; at least two high-side switches coupled to the low-side switch; a supply boost circuitry coupled to one of the at least two high-side switches; and a high-side switch selection circuit which is operable to enable one of the at least two high-side switches according to a relative difference between a signal and a threshold.
US11258396B2 Method for operating a power converter, power converter for a permanently excited electric machine, vehicle and computer program product
Method for operating a power converter for a permanently excited electric machine, wherein temperature information, which describes a temperature of at least one permanent magnet of the electric machine, is determined by means of an observer as a function of operating parameters of the electric machine, and the power converter is controlled as a function of the temperature information, wherein a computing device, which handles processes in time slices, carries out a first process in a first time slice for detecting parameter values for determining the operating parameters and carries out a second process, which determines the temperature information, in a second time slice, which is retrieved less frequently than the first time slice.
US11258394B2 Method for detection of upcoming pole slip
A method for detecting an imminent pole slip of a synchronous generator electrically connected to a power supply network, whereby a signal characteristic of a power fault is detected and an imminent pole slip is determined via a predefinable value when a load angle of the synchronous generator increases, whereby the following steps are performed. Determination of a first load angle during operation without a power fault, determination of a generator frequency as a function of time when a power fault occurs, and precalculation of a second value of a load angle resulting from the power fault by adding the first value of the load angle to a load angle difference occurring during the power fault, whereby this load angle difference is caused by a deviation of a generator frequency relative to a power frequency.
US11258392B2 Electronic circuitry for converting DC voltage to AC voltage
According to one embodiment, an electronic circuitry that converts DC voltage into AC voltage includes first to fourth switching circuitries. A cycle includes first and second periods. During the first period, the first and second switching circuitries are turned on, and the third and fourth switching circuitries are turned off, and during the second period, the first switching and second circuitries are turned off, and the third and fourth switching circuitries are turned on. At least one of the first to fourth switching circuitries includes a first switching element and a second switching element in parallel. During a time period during which at least one of the first to fourth switching circuitries is turned on, the first switching element is turned on during a first subperiod, and the second switching element is turned on during a second subperiod that overlaps the first subperiod.
US11258389B2 Power tool and control method thereof
A controller of a power tool is configured to, based on a sampled current of a motor of the power tool, output control signals that change with a change of a position of a rotor of the motor to control a drive circuit of the power tool such that an input voltage and/or a current of the motor changes approximately in a sine wave.
US11258388B1 Systems and methods for performing motor control operations agnostic of speed data
A system may include an inverter configured to convert a direct current (DC) voltage to an alternating current (AC) voltage. The system may also include a control system communicatively coupled to the inverter. The control system may receive a torque current feedback from a motor and may generate, based on the torque current feedback, a command torque current and a command flux current. The control system may generate, based on the command torque current and the command flux current, a command torque voltage and a command flux voltage and may generate, based on a slip frequency and a rotor frequency, a command frequency. The control system may determine one or more operating parameters for the inverter based on the command frequency, the command torque voltage, and the command flux voltage and may control the inverter based on the one or more operating parameters.
US11258382B1 Rotation speed regulation system for electric tool switch
A rotation speed regulation system for an electric tool switch includes a controller, a resistance regulating copper foil electrically connected to the controller, and a resistance regulating reed matched with the resistance regulating copper foil. The resistance regulating copper foil includes a first foil and a second foil separated from each other. The first foil is an intact long strip foil. The second foil includes a plurality of short-circuit gold fingers arranged at equal intervals in the middle part and a full-resistance foil and a zero-resistance foil at both ends. The width of the short-circuit gold finger is 0.27 mm, and the distance between two adjacent short-circuit gold fingers is 0.2 mm. An inclination angle α is formed between the short-circuit gold finger and the sliding direction of the resistance regulating contact end, α is 107°-110° and the length L of the contact strip is 2.3-2.9 mm.
US11258380B2 Control device and corresponding production method
A method for producing a control device for mechanically controlling a component. The control device may have a device housing including a motor accommodating space in which an electric motor is arranged. The electric motor may include a motor housing having a stator and a rotor, the rotor including a rotor shaft. The method may include selecting an electric motor from a plurality of electric motors each suitable for a specified application. Each of the plurality of electric motors may have a different respective axial motor length and may have a same respective motor cross section. Further, the method may include adapting the motor accommodating space to the respective axial motor length of the selected electric motor.
US11258379B2 Quantum noise power devices
Described herein are devices in which quantum noise is reduced, such as by incorporating the devices as part of or adjacent to a Casimir cavity. The devices with reduced quantum noise can be paired with a free-space electric device to allow for a difference in noise power between the two to be captured.
US11258373B2 Power supply and method of supplying power to load
A power supply includes an inverter configured to convert direct current (DC) power into alternating current (AC) power, an impedance matching circuit configured to supply the AC power to a load, and a controller configured to detect a delay time of an output voltage and an output current output to the impedance matching circuit and the load and to adjust a frequency of the output voltage according to the detected delay time.
US11258371B2 Switched capacitors for AC-DC applications
An apparatus for conversion between AC and DC voltages includes a rectifier and first and second stages coupled to each other and having a regulator and a switched-capacitor circuit respectively. The first stage receives a first voltage from the rectifier and the second stage provides a second voltage. A controller controls the first and second stages.
US11258370B2 High frequency medium voltage drive system for high speed machine applications
In one aspect, a medium voltage power converter includes a plurality of slices each having: a transformer including a plurality of primary windings to couple to a utility source of input power and a plurality of secondary windings; and a plurality of power cubes coupled to the plurality of secondary windings, each of the plurality of power cubes comprising a low frequency front end stage, a DC link, and a high frequency silicon carbide (SiC) inverter stage to couple to a high frequency load or to a high speed machine.
US11258369B2 Inductive charging circuit to provide operative power for a controller
An inductive charging circuit coupled to a winding of a power converter and a supply terminal of a controller of the power converter. The inductive charging circuit comprising an input coupled to the winding, the input coupled to receive a switching voltage generated by the power converter, an inductor coupled to the input to provide an inductor current in response to the switching voltage, a first diode coupled to the inductor to enable the inductor current to flow from the input of the inductive charging circuit to an output of the inductive charging circuit; and the output of the inductive charging circuit coupled to the supply terminal of the controller, the output of the inductive charging circuit configured to provide an operational current responsive to the inductor current to the controller, the controller is configured to control a power switch of the power converter to generate the switching voltage.
US11258366B2 Power manager with reconfigurable power converting circuits
A reconfigurable power circuit (400) includes a single one-way DC to DC power converter (220, 221). The reconfigurable power circuit is configurable by a digital data processor as one of three different power channels (230, 232, and 234). Power channel (230) provides output power conversion. Power channel (232) provides input power conversion. Power channel (234) provides bi-directional power exchange without power conversion.
US11258364B2 Flexible array of DC-DC converters reconfigurable using a shared serial bus
A re-configurable bank of DC-DC converters has many channels, each with a DC-DC converter and a controller that senses the channel's output voltage and current to adjust a duty cycle of switch signals to the DC-DC converter. A serial bus connects to all controllers and writes digital voltage and current control targets into each controller. The controller has Digital-to-Analog Converters (DACs) that convert the targets to analog voltages that are compared to sensed output voltage and current. The comparison results are compared to a sawtooth wave to generate pulses of the switch signals that have a duty cycle adjusted for the target comparisons. In combined mode, a primary channel's controller generates switch signals for secondary channels having outputs shorted to the primary channel. Secondary channels have a mux to select switch signals from the primary controller during combined mode, and from the secondary controller during separated mode.
US11258360B2 Switched-capacitor power converting apparatus and operating method thereof
A switched-capacitor power converting apparatus and an operating method thereof are disclosed. The switched-capacitor power converting apparatus includes an output stage, a determination circuit, a switch control circuit and a voltage regulation circuit. The output stage has an output terminal. The determination circuit is coupled to the output terminal, and generates a mode switching signal according to an output voltage of the output terminal and a reference voltage. The switch control circuit is coupled to the output stage and the determination circuit and controls the output stage to operate in a default voltage mode or an operation mode according to the mode switching signal. The voltage regulation circuit is coupled to the output terminal and the determination circuit and maintains the output voltage of the output terminal at a default value in the default voltage mode.
US11258354B2 PFC control circuit for a boost converter, related integrated circuit, boost converter, power supply and method
An embodiment PFC control circuit includes a first terminal providing a drive signal to an electronic switch of a boost converter, a second terminal receiving a feedback signal indicative of an output voltage generated by the boost converter, and a third terminal connected to a compensation network. An error amplifier generates a current as a function of the voltage at the second terminal and a reference voltage, wherein an output of the error amplifier is coupled to the third terminal. A driver circuit generates the drive signal as a function of the voltage at the third terminal, and selectively activates or deactivates the generation of the drive signal as a function of a burst mode enable signal. A detection circuit generates the burst mode enable signal as a function of the voltage at the second terminal.
US11258353B2 Power converter
According to one embodiment, there is provided a power converter including a totem-pole power factor correction circuit that can achieve reduction in recovery loss with a simple structure. A power converter according to an embodiment includes a totem-pole power factor correction circuit, a series connection of a first current detector and a second current detector, and a control circuit.
US11258346B2 Power conversion device and harmonic restraint device
A power converter is configured to convert, into an AC voltage, a DC voltage supplied from a DC power supply connected between a first power supply wiring and a first ground wiring. A control device is connected between a second power supply wiring and a second ground wiring. The second power supply wiring is configured to supply a second power supply voltage lower than the first power supply voltage. The control device is configured to control the power converter. A separation device is configured to separate the first ground wiring and the second ground wiring from each other. The first ground wiring and the second ground wiring are electrically connected to each other at a single node.
US11258344B1 High torque reluctance brake device
A high torque reluctance brake device for fitness equipment, comprising: an external rotor including a flywheel and an outer ring body; at least two magnetic resistance mechanisms, each of them has a brake field core, a magnetic coil; a support frame for arranging magnetic resistance mechanisms to form an angle larger than 30 degree and to make between the outer periphery of the brake field core and the outer ring body has a gap; the control circuit unit transmits suitable current to the magnetic coil, then between the brake field core and the magnetic ring produced a eddy current magnetic resistance and forms a reverse resistance to the external rotor. By choosing different resistance setting can increase the variability of exercise and improve the comfort of exercise.
US11258343B2 Double helix actuator with magnetic sections having alternating polarities
A double helix actuator is disclosed that includes a double helix coil wound around a movable proof mass that is enclosed within a magnetic structure. The double helix coil and the magnetic structure are arranged relative to each other so that the magnetic field generated by the entirety of the double helix coil contributes to a linear force direction of the actuator. The double helix actuator produces a greater linear force density compared to traditional racetrack coil actuators, where only a portion of the coil contributes to the linear force. The double helix actuator also produces torque in addition to linear force which allows the double helix to provide unique haptic sensations in a variety of applications.
US11258342B2 Electrical machine
An electrical machine includes a stator containing bearing plates and windings conducting electrical current and the rotor. The stator has windings conducting electric current embedded in a composite material and shaped into winding segments forming a ring segment of an angular span constituting a part of the full angle. The segments are inserted between the external and internal discs of the rotor. The magnetic poles are embedded and magnetised towards the axial direction of internal discs. The poles are separated from each other with a spacing made of a non-magnetic composite material of the internal and external discs structure. Each external and internal disc has an external reinforcing ring, made of a non-magnetic composite material reinforced with fibres of strength exceeding 1 GPa, formed by winding the fibres together with resin on the cylindrical surface of the discs. The external discs have a ring closing the magnetic circuit.
US11258339B2 Manufacturing method of iron core product
A manufacturing method of an iron core product includes: heating an iron core body attached to a jig together with the jig; removing the iron core body from the jig when the jig and the iron core body are heated to denote a first temperature; and separately cooling, after removing the iron core body from the jig, the iron core body and the jig such that the iron core body is at a second temperature lower than the first temperature and the jig is at a third temperature lower than the first temperature.
US11258336B2 Sensing device having a stator having a stator ring with protrusions to be secured to a stator holder
An embodiment relates to a sensing device comprising: a rotor; and a stator arranged on the outer side of the rotor, wherein the stator comprises a stator holder and a stator ring arranged on the stator holder; the stator ring comprises a body, a plurality of teeth formed to protrude from the inner peripheral surface of the body, and a protrusion part formed to protrude from the outer peripheral surface of the body; and, when seen in the radial direction, the protrusion part is arranged between the teeth and comprises at least two protrusions arranged to be spaced from each other. Accordingly, the coupling force between the stator holder and the stator ring can be improved.
US11258335B2 Motor stator anti-interferences structure
A motor stator anti-interference structure includes: a silicon steel sheet assembly, the silicon steel sheet assembly including multiple silicon steel sheets held between an insulation support assembly; a winding assembly wound on the silicon steel sheet assembly and the insulation support assembly; and a connection member inlaid in the silicon steel sheet assembly to contact all the silicon steel sheets. All the silicon steel sheets are connected to a grounding end of a circuit board through the connection member so as to increase contact area between the connection member and the silicon steel sheet assembly. The electromagnetic interference is conducted through the connection member to the grounding end of the circuit board.
US11258334B2 Motor
A motor includes a motor body, a housing, a heat sink, a controller, a connector, and a cover. The heat sink includes two arm portions each extending radially outward. The connector is held between the two arm portions. The heat sink and the connector include a cover joint portion extending all the way around surfaces of the heat sink and the connector along a circumferential direction, is loop-shaped, and surrounds the controller, when viewed in an axial direction. The cover is joined to the cover joint portion. The connector includes a connector outside surface exposed between the two arm portions, and including circumferential end portions adjacent to the arm portions and overlapping with an imaginary line joining distal ends of the two arm portions or located radially inward of the imaginary line when viewed in the axial direction.
US11258333B2 Propulsor system with integrated passive cooling
Propulsors (e.g., an electric motor mechanically coupled to a rotor) are described that passively cool the electric motors via an airflow path through the electric motor and out of the rotors. One embodiment comprises a method of cooling an electric motor. The method comprises operating the electric motor of a propulsor for an aircraft to rotate a rotor of the propulsor, where the rotor has one or more air outlets, and where the electric motor has a housing that includes one or more air inlets in fluid communication with the one or more air inlets. The method further comprises generating, by rotating the rotor using the electric motor, an airflow through the electric motor from the one or more air inlets to the one or more air outlets to cool the electric motor.
US11258329B2 Stator core and electric motor with improved water resistance
A stator core of an electric motor is provided with a first core block and a second core block formed by laminating a plurality of large-diameter thin plates in a reversed arrangement with respect to each other causing outer circumferential edge burrs of the large-diameter thin plates to face each other, and with a small-diameter thin plate sandwiched between the first core block and the second core block, and having an outer diameter smaller than the cuter diameter of the large-diameter thin plate.
US11258324B2 Electric drive systems
Fault-tolerant four-phase electric drive systems are provided. One such system comprises: a rotary electric machine having a permanent magnet rotor and an alternate-wound stator having eight evenly-spaced coils arranged in pairs, each coil in each pair being separated by 180 degrees; a first phase (ΦA) comprising a first one of the coil pairs and a first phase drive circuit connected therewith; a second phase (ΦB) separated by +45 degrees from the first phase and comprising a second one of the coil pairs and a second phase drive circuit connected therewith; a third phase (ΦC) separated by +90 degrees from the first phase and comprising a third one of the coil pairs and a third phase drive circuit connected therewith; a fourth phase (ΦD) separated by +135 degrees from the first phase and comprising a fourth one of the coil pairs and a fourth phase drive circuit connected therewith; and a controller connected with the first, second, third and fourth phase drive circuits to control operation thereof.
US11258322B2 High speed induction machine
In one embodiment, a high speed induction machine includes: a stator formed of a first plurality of laminations having a thickness of less than approximately 0.01 inch and a winding comprising a coil formed of Litz wire adapted about the stator; and a rotor adapted within the stator. The rotor may include: a rotor core formed of a second plurality of laminations having a second thickness of greater than approximately 0.10 inch and formed of high strength steel and sandwiched between a first end region including at least one first peripheral second lamination and a second end region including at least one second peripheral second lamination, the first end region having a first end ring retained by a first retaining ring adapted there around, the second end region having a second end ring retained by a second retaining ring adapted there around.
US11258321B2 Motor having rotor frame with magnet fixing jig holes
A motor includes a stator and a rotor rotatably coupled to a rotation shaft. The rotor includes: rotor core segments arranged along a circumferential direction of the rotor on the inner side or the outer side of the stator and spaced apart from one another to define permanent magnet arrangement slots between the rotor core segments; permanent magnets inserted into the permanent magnet arrangement slots, respectively; and a rotor frame including rotor frame pins that fix each of the permanent magnets between the rotor core segments. Each of the rotor core segments defines a rotor core hole that extends parallel to an axial direction of the rotation shaft. The rotor frame comprises: a base formed to surround the plurality of rotor core segments and the plurality of permanent magnets in a direction parallel to an axial direction of the rotation shaft; and a plurality of permanent magnet fixing jig holes formed only at an inner end between the inner and outer ends of the base to expose the plurality of permanent magnets.
US11258314B2 Method and device for improving efficiency of electromagnetic transients program phase domain synchronous machine model
The present disclosure provides a method for improving the computational efficiency of an electromagnetic transients program (EMTP-type) phase domain synchronous machine model. The method comprises: acquiring a traditional phase domain synchronous machine model; acquiring matrix relations between mutual inductance matrices of stator windings and rotor windings according to a trigonometric transformation equation; substituting the matrix relations into the original expression of Req and the original formulation of eh(t), respectively, and deriving to obtain a simplified formulation of the equivalent resistance matrix Req and a simplified formulation of the total history term eh(t); and acquiring an efficient phase domain synchronous machine model. According to the embodiment of the disclosure, in the provided model, the equivalent resistance matrix of the phase domain synchronous machine model and the matrix used in the calculation of the history term are converted into constant sparse matrices, thereby improving the calculation efficiency of the model.
US11258313B2 Wireless power transfer apparatus and method of controlling the same
Disclosed are a wireless power transfer apparatus and a method of controlling the same. The wireless power transfer apparatus in one example can include a power transmission circuit including a plurality of coils and configured to transfer power through the plurality of coils, and a controller, wherein the controller is configured to calculate a data value of a coil with respect to each of the plurality of coils, and determine a position of an object in a charge region corresponding to the plurality of coils in a charge region based on a comparison result obtained by comparing the data value calculated for each of the plurality of coils.
US11258312B2 Systems and methods for wireless charging
A wireless charging system comprises at least one wireless power transmitter at a fixed location, at least two wireless communication beacons in proximity and at known locations relative to the wireless power transmitter, and a portable electronic device in proximity to the wireless power transmitter. The portable electronic device comprises a wireless power receiver connected to charge a battery through a tunable power electronic circuit, a wireless communication receiver, a 3-axis accelerometer, a 3-axis magnetometer, a 3-axis gyroscope, and a controller configured to determine the position and orientation of the wireless power receiver with respect to the wireless power transmitter and tune the tunable power electronic circuit based on the determined orientation.
US11258310B2 Dual decoder for wireless charging receiver and wireless charging receiver using the same
A dual decoder for a wireless charging receiver and a wireless charging receiver using the same are provided. The wireless charging receiver includes a resonant circuit, a rectifier circuit and a dual decoder for the wireless charging receiver. The rectifier circuit coupled to the resonant circuit converts wireless energy received by the resonant circuit into a direct current. The dual decoder includes a frequency decoding circuit and a voltage amplitude decoding circuit. The frequency decoding circuit performs decoding according to a frequency of a voltage of the resonant circuit to obtain an instruction of a wireless transmitter. The voltage amplitude decoding circuit extracts a carrier on the voltage of the resonant circuit through a filter, and decodes the carrier into the instruction of the wireless transmitter. With the complementary of two-way decoding, the communication system becomes robuster.
US11258304B2 Multiple access wireless power transfer
A device configured for wireless power transfer includes a digital controller configured to generate a plurality of switch control signals, and a transceiver configured to generate a wireless signal for the wireless power transfer. The transceiver includes a plurality of switches, each switch of the plurality of switches being responsive to a respective switch control signal of the plurality of switch control signals such that the wireless signal has a waveform shaped in accordance with a code sequence for the wireless power transfer. The code sequence is one of a set of predetermined code sequences, each predetermined code sequence being orthogonal to each other predetermined code sequence of the set of predetermined code sequences.
US11258303B2 Electronic device and method for wired and wireless charging in electronic device
An apparatus for wired and wireless charging of an electronic device are provided. The electronic device includes a housing, a display on a surface of the housing, a battery mounted in the housing, a circuit electrically connected with the battery, a conductive pattern positioned in the housing, electrically connected with the circuit, and configured to wirelessly transmit power to an external device, a connector on another surface of the housing and electrically connected with the circuit, a memory, and a processor electrically connected with the display, the battery, the circuit, the connector, and/or the memory. The circuit is configured to electrically connect the battery with the conductive pattern to wirelessly transmit power to the external device and electrically connect the battery with the connector to transmit power to the external device by wire, simultaneously or selectively, with wirelessly transmitting power to the external device.
US11258296B1 Shared resonant turn off circuit
A static transfer switch is provided for supplying power to a load alternately from two different power sources. Switching between the two power sources may occur within a fraction of one electrical cycle. In response to sensing degraded performance in the power source supplying the load, a main circuit is turned off with a resonant turn off circuit. The resonant turn off circuit is shared between the main circuits of two different power sources such that the resonant turn off circuit is connected to the main circuit of whichever power source is currently supply power to the load.
US11258293B2 Methods and systems for backup power management at a power device
Methods and systems are described for power state management. A critical usage window may be configured at a gateway node. A change in a power state of the gateway node may be detected, at an interface, during the critical usage window. The power state of the gateway node may be adjusted via the interface for a set duration using a backup power node.
US11258290B2 Power supply apparatus
A power supply apparatus includes a control circuit, and first and second power storage connected to a DC link circuit between an inverter and a converter. The control circuit, while the AC power supply is in a normal condition, controls the first power storage to discharge when the control circuit detects that electric power consumption exceeds a threshold, and controls at least one of the first and second power storage to charge when the control circuit detects that the electric power consumption does not exceed the threshold, and while the AC power supply is in an abnormal condition, controls the second power storage to discharge, and controls the first power to discharge when it is detected that the electric power consumption exceeds the threshold.
US11258288B2 Circuit for inducing multi-directional current in a battery
In general, this disclosure includes systems, methods, and techniques for inducing electrical current through one or more battery banks. For example, a circuit may include a switching element. The circuit may be configured to draw, using the switching element, a current from a first battery bank when the switching element is turned on, the first battery bank emitting an excess current after the switching element is turned off, where the current increases a temperature of the first battery bank. Additionally, the circuit may be configured to deliver at least some of the excess current to a second battery bank when the switching element is turned off, where the excess current charges the second battery bank, and where the excess current increases a temperature of the second battery bank.
US11258280B2 Mobile terminal, peripheral device, and charging method thereof
A mobile terminal, a peripheral device, and a charging method thereof that relate to the field of electronic device technologies, where the mobile terminal and the peripheral device are separately powered, and when coupled by a connector, the mobile terminal and the peripheral device charge each other. The mobile terminal includes a first switch, a second switch, a first charging port, a first charging circuit, a first connector, a first battery, and a first electronic controller.
US11258276B2 Power supply control method and apparatus of battery management system
Disclosed is a battery management system (BMS) power supply management apparatus and method. The BMS power supply management apparatus includes an optoelectronic element configured to generate a current in response to an optical signal, a conversion element configured to convert the current into a wake-up voltage, and a first switch configured to switch a wake-up signal for a BMS, in response to the wake-up voltage.
US11258275B2 Industrial truck
An industrial truck including a battery and a battery management system connected to the battery and powered by the battery. The battery includes a plurality of battery stacks each having battery cells connected in series with each other, characterized by a control unit adapted to selectively connect one or more of the battery stacks to the battery management system or to disconnect it from the battery management system.
US11258274B2 Apparatus and method for battery module balancing
The present disclosure relates to an apparatus and method for equalizing the charge of a plurality of battery modules while balancing the plurality of battery modules included in a battery pack. The present disclosure has an advantage of allowing easy manufacture of the battery pack with a reduced size since of the battery pack connectors may be simplified and the volume of wire harness may be reduced.
US11258272B2 Temperature estimation and control systems, methods, and devices for a battery pack charger
A battery pack charger includes a first circuit region, a second circuit region, an input voltage measuring circuit, a temperature measurement device, and a controller. The controller is configured to measure an input voltage to the charger using the input voltage measuring circuit, measure a temperature of the second circuit region using the temperature measurement device, and estimate a temperature of the first circuit region based on the input voltage to the charger and the measured temperature of the second circuit region. The controller is further configured to select one of a plurality of correlations between the temperature of the second circuit region and the temperature of the first circuit region based on the input voltage to the charger to estimate the temperature of the first circuit region. After the temperature of the first circuit region has been estimated, one or more control operations associated with the charger can be performed.
US11258269B2 Systems, apparatus, and methods for power management
Systems, apparatus, and methods for controlling power modes in electronic devices are provided. A system may include an electronic device and an input device that sends power mode selection information via a network to a power mode selection receiving component in the electronic device. The electronic device includes a first power component that powers a first component, and a switching component that controls the first power component. The electronic device may include a second power component that powers a second component. The switching component may control the second power component. The power mode selection receiving component and the switching component may be powered independently of the first and the second component. If the power mode selection information indicates an off mode, the electronic device may provide power to the power mode selection receiving component and the switching component and not to the first and the second component.
US11258267B1 Off-grid solar system with assisted AC power
A method and apparatus is disclosed relating to smart Microgrids or off-grid solar systems with grid power integration supported by AC assisted off-grid power inverters that can (1) intelligently and selectively pull power from one or multiple DC sources including solar panels, wind generators, and batteries based on certain criteria; (2) invert DC power to AC power as generated AC power; (3) intelligently pull power from a connected AC source including grid AC, a gas generator, or a wind generator as input AC power; (4) combine the generated AC power with the input AC power; (5) supply the combined AC power, or the generated AC power, or the input AC power to an off-grid circuit to power various types of AC loads; (6) send no power to the connected AC source; (7) maximize DC power production; (8) minimize the consumption of input AC power; and (9) achieve good system performance under DC and AC power variations and load changes.
US11258266B2 Adaptive voltage control of distributed energy resources
The disclosed system provides an adaptive control system technique generally related to distributed energy resources (DERs) located in distribution circuits. More specifically, the system technique relates to a DER with both active and reactive generation capability. In an embodiment, the system measures a voltage phase angle and a current phase angle of distribution feeder circuit, and measures a voltage value output by a power converter. The system calculates an active power setpoint value and a reactive power setpoint value of the power converter based on the measured voltage value, and the measured voltage phase angle and current phase angle. The system then sets the active and reactive power setpoint values on the power converter. The disclosed system automatically adjusts the setpoints to real-time load characteristics of the distribution feeder circuit, increases distribution feeder hosting capacity, and enables DERs to integrate in distribution feeders more efficiently.
US11258264B2 Photovoltaic string optimizer
Unique systems, methods, techniques and apparatuses of photovoltaic (PV) string power systems are disclosed. One exemplary embodiment is a PV power system comprising a plurality of PV strings and a floating DC-DC optimizer. The floating DC-DC optimizer comprises a first DC bus rail, a second DC bus rail, a plurality of input legs, each leg being coupled across the first DC bus rail and second DC bus rail, including two input leg semiconductor switches coupled at an input terminal, each input terminal being structured to receive an input current from an end of one PV string of the plurality of PV strings, and an output leg including two output leg semiconductor devices coupled at an output terminal.
US11258260B2 Battery optimization control system with data fusion systems and methods
An optimization controller for a battery includes a high level controller configured to receive a regulation signal from an incentive provider cat a data fusion module, determine statistics of the regulation signal, and use the statistics of the regulation signal to generate a frequency response midpoint. The optimization controller further includes a low level controller configured to use the frequency response midpoint to determine optimal battery power setpoints and use the optimal battery power setpoints to control an amount of electric power stored or discharged from the battery during a frequency response period.
US11258258B2 Multi-input power conversion and energy storage
Apparatuses, systems, and methods are presented for energy storage. A plurality of input connectors are configured to receive input power from one or more power sources. A plurality of input power converters are coupled to the input connectors, and are configured to convert the input power to direct current (DC) power for storage. A controller is configured to control power flow through the input power converters on a per-converter basis so that separate converters are separately controlled. One or more output power converters are configured to convert stored DC power to output power for use by one or more loads. The controller is configured to control power flow through the one or more output power converters. One or more output connectors are configured to transfer the output power to the one or more loads.
US11258257B2 Grid voltage stabilization system
A grid voltage stabilization system according to an embodiment of the present invention comprises: a power generation device for generating power by using a new and renewable energy source, and supplying the generated power to a grid; an energy storage system (ESS) for, according to a command value, storing power generated in the power generation device in a battery, or supplying power stored in the battery to the grid in the form of active power and reactive power; and a power management system (PMS) for, when a voltage value of the grid is out of a reference range, controlling the magnitude of the reactive power to be supplied to the grid such that the command value is changed according to the voltage value of the grid to enable the voltage of the grid to be within the reference range.
US11258255B2 Devices and methods for selecting voltage sources
Devices and method for selecting voltage sources. A voltage selection module may include an analog voltage input. The voltage selection module may also include a digital based voltage input. The voltage selection module further includes a control component coupled to the analog voltage input and the digital based voltage input, the control component configured to determine whether to use a first voltage received from the analog voltage input or a second voltage received from the digital based voltage input to generate an output voltage.
US11258253B2 Power sharing of parallel DC sources
A control scheme for controlling power sharing among a plurality of parallel connected DC voltage sources is disclosed. Each of the DC voltage sources in parallel connection is an independent DC power system, which can be an suitable DC power supply that can provide power to a load. By way of example, the present disclosure describes a DC power system that includes a power source, an energy storage unit and a triple active bridge converter that provides power to the common load. Each independent DC power system has its own controller that shares a DC bus with the other DC power system controllers. Each controller executes non-transitory instructions to provide a reference voltage V* to its respective independent DC power system and implements a control scheme that changes the voltage reference to ensure that each independent DC power system only provides a certain share of the load current/power.
US11258250B2 Over current protection with improved stability systems and methods
Systems and methods are provided for improved stability of driver amplifiers. In one example, a system includes an NMOSFET power device operable to generate a current signal at a drain terminal. The system further includes a current comparison amplifier operable to amplify a difference signal comprising a difference between a replica current signal of the NMOSFET power device and a reference current signal to drive a current comparison amplifier voltage output signal. The system further includes a PMOSFET clamp device comprising a source terminal coupled to a gate terminal of the NMOSFET power device operable to limit a voltage at the gate terminal of the NMOSFET power device responsive to the current comparison amplifier voltage output signal.
US11258249B2 Primary and system protection for an electric power delivery system
Primary protection relays and an integrator disclosed for providing primary protection and secondary applications for an electric power delivery system. The primary protection relays obtain signals from, and provide primary protection operations for the power system, and may operate independently from the integrator. An integrator receives signals and status communications from the primary protection relays to perform secondary applications for the electric power delivery system. The secondary applications may include backup protection, system protection, interconnected protection, and automation functions.
US11258241B1 Cable management device and cable management frame
A cable management frame includes a main body, a bracket installed on the main body, a hook installed on the main body, and a pressing member located on an end of the main body. The hook and the bracket are located respectively on two sides of the main body. The hook includes a reinforcing rib coupled to the main body.
US11258239B2 Cable tray section
The present invention relates to a cable tray section which allows being successively coupled to another tray section (1) having similar features, without needing accessories or angle requirements on the horizontal plane, comprising longitudinal metal wires (10); U-shaped transverse metal wires (20); at least one anchoring element (30) installed between the longitudinal wires (10), attached to the last and next to last transverse wires (20), and comprising a single metal wire (31) close to the next to last transverse wire (20); and a pair of straight sections (32, 32′) parallel to one another; where the straight sections (32, 32′) project with respect to the last transverse wire (20), forming a rectangular section (33) perpendicular to the straight sections (32, 32′), such that there is established a free space (40) between the last transverse wire (20) and said rectangular section (33); said space (40) having a dimension corresponding to the thickness of a transverse wire (20).
US11258236B2 Fish stick assembly
A fish stick includes a light emitting component, such as a lighted tip, near the leading end of the fish stick. The lighted tip includes a curved lens that directs some light around an attachment piece at the end of the fish stick and generally in the forward direction parallel to the longitudinal axis of the fish stick. The fish stick may be made of a phosphorescent material and stored in a lit container with an LED and reflective surfaces. The fish stick may be made of multiple rods that are threadably engaged with each other and include a spring biasing element that increases the coefficient of friction between the threads of the rods. The fish stick may also be made of multiple rods that are threadably engaged with each other via collars.
US11258231B2 GaN-based VCSEL chip based on porous DBR and manufacturing method of the same
A GaN-based VCSEL chip based on porous DBR and a manufacturing method of the same, wherein the chip includes: a substrate; a buffer layer formed on the substrate; a bottom porous DBR layer formed on the buffer layer; an n-type doped GaN layer formed on the bottom porous DBR layer, which is etched downward on its periphery to form a mesa; an active layer formed on the n-type doped GaN layer; an electron blocking layer formed on the active layer; a p-type doped GaN layer formed on the electron blocking layer; a current limiting layer formed on the p-type doped GaN layer with a current window formed at a center thereof, wherein the current limiting layer covers sidewalls of the active layer, the electron blocking layer and the convex portion of the n-type doped GaN layer; a transparent electrode formed on the p-type doped GaN layer; an n-electrode formed on the mesa of the n-type doped GaN layer; a p-electrode formed on the transparent electrode with a recess formed therein; and a dielectric DBR layer formed on the transparent electrode in the recess of the p-electrode.
US11258230B2 Pump isolation by polarization splitting
An optical pump may include a polarization element to separate pump light into a first component beam and a second component beam, wherein the polarization element is to separate the pump light such that the first component beam has a first polarization and the second component beam has a second polarization that is different from the first polarization. The optical pump may include a gain medium to absorb a portion of the first component beam and a portion of the second component beam, and transmit an unabsorbed portion of the first component beam and an unabsorbed portion of the second component beam. The optical pump may include one or more optical elements to at least partially isolate a pump source from the unabsorbed portion of the first component beam and the unabsorbed portion of the second component beam.
US11258228B2 Optical communication module
Provided is an optical communication module. The optical communication module includes: an optical device configured to provide an optical output from an electrical input; a circuit board on which the optical device is mounted and which is configured to provide the electrical input to the optical device; a temperature compensation element mounted on a side of the circuit board; and a mechanical switch connected to the temperature compensation element and configured to turn on/off according to ambient temperature for supplying or interrupting power to the temperature compensation element. The optical communication module includes the temperature compensation element configured to heat or cool the optical device according to ambient temperature, thereby maintaining proper modulation performance and optical power over a wide range of temperature in low-temperature and high-temperature environments.
US11258226B2 Optical device
A narrow linewidth laser in which an all-optical feedback line-up is used to improve the linewidth from a conventional laser source, such as a laser diode. The feedback line-up comprises an optical device having a controllable unbalanced optical coupler arranged on a cavity input path to couple a source signal from the laser source into the optical cavity, and to couple a seed signal received back from the optical cavity into the laser source. The seed signal has a lower power than the source signal. The unbalanced optical coupler may be an optical isolator arranged to couple the seed signal into the laser source at a power level selected to promote preferential stimulated emission within a narrower linewidth. By controlling the power of seed signal such that only a small portion thereof influences the lasing cavity, the narrowing effect of the preferential stimulated emission can be enhanced.
US11258224B2 Sensor system
A system, comprising an optical component that, in operational use of the optical component, optically interacts with a laser beam, an electrically conductive element disposed on or within the optical component that, in operational use of the optical component, is exposed to the laser beam, and a monitoring system operative to monitor a physical quantity representative of an electrical resistance of the electrically conductive element and to determine based on the physical quantity, a position of the laser beam relative to the optical component.
US11258223B1 Automated flexible strand feeder assembly
An automated wire feeder assembly to first repetitively receive a wire from a gripper of an automated processing tool and then load the wire into a hollow conduit coupled to the gripper of the automated tool. The wire feeder assembly includes belts that pivot between open and closed positions and each belt rotate to advance a wire into the conduit attached to the gripper of the automated tool. When the belts are in the open position the gripper of the automated tool places a free end of the wire into a wire guide. Pivoting the belts to the closed position engages the belts with the free end of the wire. Once the belt is engaged with the free end of the wire, rotating the belts advances the wire out of the wire feeder and into the gripper conduit.
US11258222B2 Cable connection structure, endoscope, and method of manufacturing cable connection structure
A cable connection structure includes: a substrate that includes: an opening; and a core wire connection electrode that is arranged on one of a principle surface and an inner layer across the opening; a cable that is arranged on a principle surface side of the substrate and includes a core wire that is electrically connected to the core wire connection electrode, the core wire connection electrode being extended so as to be separated from the substrate, the core wire connection electrode being connected to the core wire.
US11258221B2 Rotatable and wet-mateable connector
A mating connector that is rotatable and wet-mateable is disclosed herein. The connector has mating components that can be characterized as male and female. The connector may have one or more electrical and/or non-electrical contacts. As used herein, “wet-mateable” or “wet-connectable” means proper mating of the male and female components can be achieved even in the presence of conductive fluid. Being rotatable means the male and female components can be rotated independently during the mating process. A male component of a rotatable and wet-mateable mating connector is provided that has conductive and non-conductive sealing elements. A female component of the rotatable and wet-mateable mating connector is provided having conductive elements that are complementary to the male component. The male component is inserted into a chamber within the female component to produce the rotatable and wet-mateable mating connector.
US11258218B2 Battery connector assembly and battery device
Provided is a battery connector assembly that allows adaptation of a connector of a battery to both a connector of an electric work vehicle and a connector of a charger. The assembly includes, in a connector assembly box, a battery connecting connector removably connected to a battery side connector having a plurality of terminals to be connected to the battery a vehicle connecting connector removably connected to a vehicle side connector having a plurality of terminals to be connected to the electric work vehicle and a charger connecting connector removably connected to a charger side connector provided in a charger for charging power supplied from an external power source to the battery and having a plurality of terminals.
US11258217B2 Power tool and system
Batteries having different form factors and power tools that are capable of using such batteries are described. In some embodiments, a power tool may use batteries having a post form factor as well as batteries having a slide form factor.
US11258216B2 Floatable connector and wire harness tray
An electrical connector with a housing having a mounting opening with a mounting projection. An outwardly facing wall of the mounting projection has at least one detent. A fixed member has a fixed member opening. The fixed member opening has an inner surface with at least one deflectable member which extends from the inner surface into the fixed member opening. A gap is provided between the inner surface of the fixed member opening and the outwardly facing wall of the mounting projection. The mounting projections are able to float radially with the gap. The at least one deflectable member cooperates with the first detent to retain the electrical connector assembly in a pre-staged position.
US11258211B2 Method of mounting an electrical connector to flexible planar material and apparatus therefor
There is described a method of establishing an electrical connection through a flexible planar material. The method involves attaching an intermediate coupling element to the flexible planar material so as to align an aperture defined by the intermediate coupling element with a hole through the flexible planar material, and coupling an electrical connector to the intermediate coupling element so as to permit electrical connection through the flexible planar material. In this way, the intermediate coupling element can be attached to the garment during the garment manufacture process, and subsequently the electrical connector can be coupled to the intermediate coupling element separately from the main garment manufacture.
US11258210B1 Cable having built-in web portal hosting capability
A cable system includes a sensor connection segment (SCS), a computer connection segment (CCS), and a radio connection segment (RCS). The SCS includes a printed circuit board assembly (PCBA) and a sensor connection cable for connecting the PCBA to a host sensor system. The PCBA includes hardware and software for providing an embedded web server as part of the cable system. The PCBA can send sensor data over a radio network or receive firmware and calibration updates using the RCS and the CCS, respectively.
US11258209B2 Sealed electrical plug with temperature sensors
A sealed electrical plug comprises at least one temperature sensor for monitoring an internal temperature of the electrical plug. The electrical plug further comprises a data cable that is wrapped by a shield for screening electrical noise so as to accurately capture and convey temperature data. The electrical plug further comprises a housing or holder for receiving the at least one temperature sensor, wherein the housing is capable of being embedded within an inner-mold of the electrical plug and positioned close to at least one pin. One or more seals may be placed at junctions between the at least one pin and the inner-mold and a cable for the data cable to seal the inner-mold from air, moisture and particles.
US11258206B2 Terminal assembly
The present disclosure disclosed a terminal assembly comprising a first terminal module and an electric conductive part. The first terminal module comprises a plurality of first ground terminals and a plurality of first signal terminals. At least one first signal terminal is provided between two adjacent first ground terminals. The electric conductive part is disposed on the first terminal module. The first signal terminal is closer to a surface of the electric conductive part than the first ground terminal. The electric conductive part is distancing from both the first signal terminal and the first ground terminal while the first signal terminals are closer to the electric conductive part than the first ground terminals, the electric conductive part and the ground terminal could surround the first signal terminal.
US11258201B2 Unlocking bracket of connector
An unlocking bracket includes a fastener and an unlocking member. The fastener includes a fixing case and a support rod provided on the fixing case. The support rod is configured to bear on a connector. The fixing case is configured to sleeve on the connector. The unlocking member includes a cantilever and an unlocking block. The cantilever is configured to be rotationally mounted on the fixing case. The unlocking block is configured to abut a locking clip of the connector. The cantilever is configured to drive the unlocking block to rotate to push a locking clip of the connector.
US11258200B2 Connector and connector unit
A connector includes a first housing, a second housing and a fitting assuring member. The second housing includes a first locking protrusion portion having a first slope. The fitting assuring member includes a first assuring locking portion that gets over the first locking protrusion portion to be thereby locked to the first locking protrusion portion when the first housing and the second housing are fitted to each other. The first assuring locking portion begins to slide on the first slope before completion of the fitting, and stays on the first slope until the completion of the fitting.
US11258199B2 Connector and connector assembly comprising the same
A connector is provided. The connector includes a connector body formed with a terminal portion, a locking body slidably coupled to the connector body, and a spring including a first leg portion fixed in position inside the connector body and a second leg portion making contact with the locking body. The spring is configured to apply a restoring force to the locking body in a direction in which the second leg portion is moved away from the first leg portion.
US11258191B2 Electrical connection cassette
Provided is an electrical connection cassette with which it is possible to freely expand a device and add functions in accordance with the size of free space. An electrical connection cassette is provided with: a circuit board; and first connection terminals and second connection terminals mounted on the circuit board and having terminal shapes that can be engaged with each other. In a state with a terminal connection direction oriented in a predetermined direction with respect to the circuit board, the first connection terminals are disposed on the side of one main surface of the circuit board, and in a state with a terminal connection direction oriented in a direction parallel to the predetermined direction, the second connection terminals are disposed near the other main surface of the circuit board.
US11258186B2 Antenna apparatus
An antenna apparatus includes a plurality of patch antenna patterns, a plurality of first feed vias each electrically connected to a corresponding patch antenna pattern among the plurality of patch antenna patterns, and a plurality of first feed lines each electrically connected to a corresponding first feed via among the plurality of first feed vias. Each of the first feed vias is electrically connected to the corresponding patch antenna pattern at a point offset from a center of the corresponding patch antenna pattern in a first direction. An angle between a direction in which each of at least one of the plurality of first feed lines starts to extend from the corresponding first feed via and a direction in which each of remaining ones of the plurality of first feed lines starts to extend from the corresponding first feed via is not zero degrees and is not 180 degrees.
US11258181B2 Systems and methods for providing a high gain space deployable helix antenna
Systems and methods for improving an efficiency and a gain of a helical antenna. The methods comprise: configuring a conductive helix element of the helical antenna to comprise a proximal segment having a helical winding that extends along an axis of the conductive helix element and has a plurality of turns with linearly progressing pitch angles; configuring the conductive helix element to comprise a distal segment having a helical winding that extends along the axis of the conductive helix element and has a constant pitch angle; and coupling the distal segment to the proximal segment in a series arrangement so that a radio wave reaches a terminal velocity at a point of the coupling.
US11258177B2 Antenna unit, array antenna, and electronic device
An antenna unit, an array antenna and an electronic device are provided. The antenna unit includes a first microstrip antenna, comprising a first radiating layer coupled to a first dielectric layer wherein the first microstrip antenna operates at a first band, a second microstrip antenna, comprising a second radiating layer, a second dielectric layer, and a ground layer, sequentially coupled, wherein the second radiating layer is coupled to a side of the first dielectric layer facing away from the first radiating layer, and wherein the second microstrip antenna operates at a second band that is smaller than the first band, a first feeder line, electrically coupled to the first radiating layer and the second radiating layer, and a second feeder line, electrically coupled to the second radiating layer and the ground layer.
US11258172B2 Multi-beam shaped reflector antenna for concurrent communication with multiple satellites
A multi-beam antenna including a reflector having a single reflector surface defining a first focal region and a second focal region. A first feed group located within the first focal region includes a first feed oriented relative to the reflector to define a first beam pointed in a first direction. The multi-beam antenna further includes a fixed attachment mechanism attaching the first feed group to the reflector such that a position of the first feed group is fixed relative to the reflector. The multi-beam antenna further includes a second feed group located within the second focal region that includes a second feed oriented relative to the reflector to define a second beam pointed in a second direction. The multi-beam antenna further includes an adjustable attachment mechanism attaching the second feed group to the reflector, whereby a difference between the first direction and the second direction is adjustable.
US11258171B2 Antenna
An antenna includes a dielectric substrate, a radiating element, a parasitic element, and a ground conductor. The dielectric substrate has a plate-like shape having a top face and a back face opposite to each other. The radiating element is placed between the top face and the back face of the dielectric substrate and transmits and receives a radio frequency signal of a first frequency. The parasitic element is placed on the top face of the dielectric substrate and transmits and receives a radio frequency signal of a second frequency. The ground conductor is placed on the back face of the dielectric substrate. The second frequency is a lower frequency than the first frequency. The dielectric substrate has an electric field boundary plane that reflects a radio frequency signal of the second frequency at an intermediate position in a thickness direction orthogonal to the top face and the back face.
US11258165B2 Asymmetric antenna structure
Certain aspects of the present disclosure provide an asymmetric antenna structure. An example antenna device generally includes a first antenna element, a second antenna element, and a flexible coupling element asymmetrically positioned between surfaces of the first and second antenna elements and electrically coupling the first antenna element to the second antenna element.
US11258161B2 Antenna-on-package integrated circuit device
An integrated circuit package is provided. In some examples, the integrated circuit package is an antenna-on-package package that includes a plurality of dielectric layers, a plurality of conductor layers interspersed with the plurality of dielectric layers, and an integrated circuit die disposed on a first side of the plurality of dielectric layers. The plurality of conductor layers includes a first layer disposed on a second side of the plurality of dielectric layers that includes a set of antennas. In some such examples, the integrated circuit die includes radar processing circuitry, and the AOP integrated circuit package is configured for radar applications.
US11258158B2 Apparatus and method for providing linear motion of a device
A system includes a compound flexure having a frame, a flexure, and a post flexure. The frame has an axis, and the flexure is located within the frame. The flexure is movable relative to the frame, and the frame and the flexure form at least part of a monolithic structure. The post flexure extends along the axis and engages the flexure. The system also includes a device coupled to the flexure and configured to move with the flexure relative to the frame. The system further includes an actuator coupled to the flexure and configured to move the flexure and the device relative to the frame.
US11258156B2 Element used for an oscillation or detection of a terahertz wave
Provided is an element that can reduce a parasitic oscillation. An element used for an oscillation or a detection of a terahertz wave includes a resonance unit 108 including a first conductor 102, a second conductor 105, a dielectric 104 arranged between the first conductor and the second conductor, a first negative resistance element 101a and a second negative resistance element 101b mutually connected in parallel between the first conductor and the second conductor, a bias circuit 120 that supplies a bias voltage to each of the first negative resistance element and the second negative resistance element, and a line 103 that connects the bias circuit to the resonance unit, and the element is configured in a manner that a mutual injection locking in a positive phase between the first negative resistance element and the second negative resistance element is unstable, and a mutual injection locking in a reversed phase between the first negative resistance element and the second negative resistance element becomes stable.
US11258155B2 Multilayer electronic component
A multilayer electronic component includes an element body including a plurality of base layers stacked in a first direction, an inner conductor disposed in the element body, and a mounting terminal connected to the inner conductor. The multilayer electronic component has a mount surface positioned on a mounted side when the multilayer electronic component is mounted. The mount surface is disposed so as not to intersect an axis along the first direction. The mounting terminal is disposed on the mount surface and embedded from the mount surface into the element body.
US11258154B2 Launch structures for a hermetically sealed cavity
An apparatus includes a substrate containing a cavity and a dielectric structure covering at least a portion of the cavity. The cavity is hermetically sealed. The apparatus also may include a launch structure formed on the dielectric structure and outside the hermetically sealed cavity. The launch structure is configured to cause radio frequency (RF) energy flowing in a first direction to enter the hermetically sealed cavity through the dielectric structure in a direction orthogonal to the first direction.
US11258153B2 Coupling and decoupling device between a circuit carrier and a waveguide
The invention relates to a coupling and decoupling device between a circuit carrier and a waveguide. The coupling and decoupling device contains a retaining element, which has a first end for coupling to the circuit carrier and a second end for coupling to the waveguide. Two dipole antennas, which are crossed over and oriented orthogonally to each other, are arranged between the first end and the second end. The coupling and decoupling device furthermore contains two conductor pairs, which are arranged crossed over each other and are designed such that the conductor pairs are connected to the two dipole antennas and to associated contact surfaces on the circuit carrier. According to the invention, an electrically conductive layer is fixed on the first end. The retaining element is formed as a hollow conductor having a first opening on the end face of the hollow conductor for coupling to the circuit carrier and a second opening on the end face of the hollow conductor for coupling to the waveguide. The first opening on the end face is closed by the electrically conductive layer.
US11258152B2 Excitation and use of guided surface wave modes on lossy media
Disclosed are various embodiments for exciting a guided surface waveguide probe to create a plurality of resultant fields that are substantially mode-matched to a Zenneck surface wave mode of a surface of a lossy conducting medium and embodiments for receiving energy from a Zenneck surface wave launched on the lossy conducting medium.
US11258147B2 Assembly comprising a sleeve connecting first and second hollow waveguides, wherein grooves for receiving reversible deformable elements therein are located waveguides and sleeve
An assembly includes a first waveguide and a second waveguide extending longitudinally along a first axis, each having an end, each comprising a first annular groove, the two ends being contiguous along the first axis, and an assembly device for assembling the first waveguide and the second waveguide, wherein the assembly device comprises a sleeve surrounding the ends of the first and second waveguides and having an inner wall comprising two first annular grooves facing the first annular grooves of the first and second waveguides, two reversibly deformable waveguides, each being positioned in a first annular groove of the sleeve and positioned in a first annular groove of the first and second waveguides, so as to block the first and second waveguides in terms of translation along the first axis.
US11258146B2 Battery cell having overcharge prevention member
The present invention relates to a battery cell having an overcharge prevention member, and more particularly, to a battery cell including a protective member for preventing explosion due to the pressure caused by various factors inside the battery.
US11258143B2 Battery module, secondary battery and cap assembly thereof
The present disclosure provides a battery module, a secondary battery and a cap assembly thereof. The cap assembly includes a cap plate which is provided with a terminal hole and an electrode terminal provided to the cap plate and covering the terminal hole; the electrode terminal includes an outer surface; the electrode terminal includes a positioning hole which is recessed with respect to the outer surface and includes a first portion and a second portion, the second portion is positioned to a side of the first portion away from the outer surface; a section of the first portion parallel to a central axis of the positioning hole is trapezoidal; a size of the first portion gradually decreases in a direction of the first portion close to the second portion, and a minimum size of the first portion is greater than or equal to a size of the second portion.
US11258139B2 Pouch type secondary battery
A pouch type secondary battery includes: an electrode assembly having an electrode including a positive electrode, a negative electrode, and a separator laminated therein; a battery case having a pouch shape to accommodate the electrode assembly; an electrode tab connected to the electrode and protruding from one side of the electrode; a first electrode lead having one end connected to the electrode tab; a second electrode lead having one end connected to the other end of the first electrode lead and the other end protruding to outside the battery case; and a connection part bonding the first electrode lead to the second electrode lead to connect the first and second electrode leads to each other. In at least one of the first and second electrode leads, a notch is on a bonding surface on which the first and second electrode leads are bonded together through the connection part.
US11258133B2 Binder composition for non-aqueous secondary battery porous membrane, slurry composition for non-aqueous secondary battery porous membrane, porous membrane for non-aqueous secondary battery, and non-aqueous secondary battery and production method therefor
Provided is a binder composition for a non-aqueous secondary battery porous membrane capable of forming a porous membrane having improved adhesiveness in electrolyte solution, heat shrinkage resistance in electrolyte solution, and blocking resistance. The binder composition for a non-aqueous secondary battery porous membrane contains a particulate polymer A and a particulate polymer B having a larger volume-average particle diameter than the particulate polymer A. The particulate polymer A includes a (meth)acrylic acid alkyl ester monomer unit in a proportion of not less than 50 mass % and not more than 90 mass %. The particulate polymer B has a core-shell structure and includes a nitrile group-containing monomer unit in a core portion of the core-shell structure.
US11258131B2 Battery module including module housing
Disclosed is a battery module that reduces damage of internal components during an assembling process and enhances the manufacturing efficiency. The battery module includes a plurality of cylindrical battery cells arranged in a horizontal direction and each standing upright in a vertical direction; and a module housing including outer sidewalls configured to form an inner space, a plurality of hollow tubes having inner sidewalls located in the inner space and extending in the vertical direction to accommodate the plurality of cylindrical battery cells therein, and a cavity formed by opening at least a part of vertical central portions of the inner sidewalls of the plurality of hollow tubes to form an empty space therein.
US11258126B2 Battery rack
The present invention provides a battery rack including: a housing; a plurality of battery modules stacked in the housing; and a connection member configured to electrically connect the plurality of battery modules, wherein each of the plurality of battery modules includes a plurality of battery submodules stacked on each other, and each of the plurality of battery submodules comprises: at least one cooling member; and a plurality of battery cells located on both sides with the at least one cooling member interposed therebetween, wherein at least two of the plurality of battery cells are located on each of both sides of the at least one cooling member.
US11258113B2 Management device, and electricity storage system
A cell voltage measurement unit measures a voltage of each of a plurality of cells that are series-connected. A total voltage measurement unit measures a total voltage of the plurality of cells. A controller manages an internal impedance of each of the plurality of cells. The controller detects a ripple of the total voltage measured by the total voltage measurement unit, estimates a ripple of each cell voltage by multiplying the detected ripple of the total voltage by a ratio of the internal impedance of each cell to a resultant internal impedance of the plurality of cells, and determines whether the ripple of each cell voltage is within an allowable voltage range.
US11258111B2 Vehicular battery charger, charging system, and method with in-vehicle display of charge time
A vehicle battery charger and a vehicle battery charging system are described and illustrated, and can include a controller enabling a user to enter a time of day at which the vehicle battery charger or system begins and/or ends charging of the vehicle battery. The vehicle battery charger can be separate from the vehicle, can be at least partially integrated into the vehicle, can include a transmitter and/or a receiver capable of communication with a controller that is remote from the vehicle and vehicle charger, and can be controlled by a user or another party (e.g., a power utility) to control battery charging based upon a time of day, cost of power, or other factors.
US11258110B2 Vehicular battery charger, charging system, and method with a time delay function
A vehicle battery charger and a vehicle battery charging system are described and illustrated, and can include a controller enabling a user to enter a time of day at which the vehicle battery charger or system begins and/or ends charging of the vehicle battery. The vehicle battery charger can be separate from the vehicle, can be at least partially integrated into the vehicle, can include a transmitter and/or a receiver capable of communication with a controller that is remote from the vehicle and vehicle charger, and can be controlled by a user or another party (e.g., a power utility) to control battery charging based upon a time of day, cost of power, or other factors.
US11258107B2 Vehicular battery charger, charging system, and method for transmitting battery charge threshold information
A vehicle battery charger and a vehicle battery charging system are described and illustrated, and can include a controller enabling a user to enter a time of day at which the vehicle battery charger or system begins and/or ends charging of the vehicle battery. The vehicle battery charger can be separate from the vehicle, can be at least partially integrated into the vehicle, can include a transmitter and/or a receiver capable of communication with a controller that is remote from the vehicle and vehicle charger, and can be controlled by a user or another party (e.g., a power utility) to control battery charging based upon a time of day, cost of power, or other factors.
US11258106B2 Asynchronous multi-purpose battery interface
A method and apparatus for controlling a battery operating mode. The method includes connecting an electronic processor to a first electrical contact of a battery interface via a switch; generating, with the electronic processor, an initialization pulse for a signal demultiplexer of a battery; transmitting the initialization pulse to the signal demultiplexer; generating, with the electronic processor, a data word indicating a desired operating mode; transmitting the data word to the signal demultiplexer; generating, with the signal demultiplexer, a signal to electrically connect a first battery switch to the first electrical contact, the first battery switch selected based on the data word; receiving, with an analog to digital converter of the electrical device, a signal indicating the operating mode voltage; and verifying, with the electronic processor, a correct operating mode based on the operating mode voltage.
US11258105B2 Subsurface marine battery pack
A subsurface battery system includes a ballast mass at the seafloor, a deep-sea electronics module, having an interface to seafloor payloads, and a subsurface buoyant pressure vessel having a battery. The ballast mass is attached to the deep-sea electronics module. The deep-sea electronics module is connected to the battery. The subsurface buoyant pressure vessel is submerged to a water depth of approximately 50 meters to 500 meters. The system is used for powering the seafloor payloads.
US11258101B2 Non-flammable electrolyte containing liquefied gas and lithium secondary batteries containing same
A rechargeable lithium cell comprising a cathode, an anode, an optional ion-permeable membrane disposed between the anode and the cathode, a non-flammable salt-retained liquefied gas electrolyte in contact with the cathode and the anode, wherein the electrolyte contains a lithium salt dissolved in or mixed with a liquefied gas solvent having a lithium salt concentration greater than 1.0 M so that the electrolyte exhibits a vapor pressure less than 1 kPa when measured at 20° C., a vapor pressure less than 60% of the vapor pressure of the liquefied gas solvent alone, a flash point at least 20 degrees Celsius higher than a flash point of the liquefied gas solvent alone, a flash point higher than 150° C., or no flash point, wherein the liquefied gas solvent is selected from methane, fluoromethane, difluoromethane, chloromethane, dichloromethane, ethane, fluoroethane, difluoroethane, tetrafluoroethane, chloroethane, dichloroethane, tetrachloroethane, propane, fluoropropane, chloropropane, ethylene, fluoroethylene, chloroethylene, or a combination thereof.
US11258098B2 High voltage electrolyte additives
Described herein are additives for use in electrolytes that provide a number of desirable characteristics when implemented within batteries, such as high capacity retention during battery cycling at high temperatures. In some embodiments, a high voltage electrolyte includes a base electrolyte and one or more polymer additives, which impart these desirable performance characteristics. The polymer additives can be homopolymers or copolymers.
US11258096B2 Molten inorganic electrolytes for low temperature sodium batteries
A molten sodium-based battery comprises a robust, highly Na-ion conductive, zero-crossover separator and a fully inorganic, fully liquid, highly cyclable molten cathode that operates at low temperatures.
US11258095B2 Solid-state rechargeable battery
A solid-state rechargeable battery includes a pair of electrode layers and a solid electrolyte layer interposed between the pair of electrode layers. The pair of electrode layers each includes a phosphate having an olivine crystal structure. The phosphate contains a transition metal and lithium.
US11258085B2 Electricity generation devices using formic acid
The present disclosure relates generally to new forms of portable energy generation devices and methods. The devices are designed to covert formic acid into released hydrogen, alleviating the need for a hydrogen tank as a hydrogen source for fuel cell power.
US11258084B2 Fuel cell system and opening/closing method for discharge valve
A fuel cell system includes: a fuel cell generating electricity when being supplied with anode gas and cathode gas; a supply channel through which the anode gas to be supplied to the fuel cell flows; a discharge channel through which anode-off gas discharged from the fuel cell flows; a discharge valve provided on the discharge channel and opened to discharge the anode-off gas; and a control section controlling opening/closing of the discharge valve. The control section calculates a valve open time of the discharge valve corresponding to a target value of a discharge amount of the anode-off gas by using an aperture ratio of the discharge channel and the target value, and closes the discharge valve based on the valve open time, the aperture ratio of the discharge channel being calculated from a first discharge amount of the anode-off gas, which is discharged by opening of the discharge valve.
US11258083B2 On-board aircraft electrochemical system
An onboard electrochemical system of an electrochemical cell including a cathode and an anode separated by an electrolyte separator is selectively operated in either of two modes. In a first mode of operation, water or air is directed to the anode, electric power is provided to the anode and cathode to provide a voltage difference between the anode and the cathode, and nitrogen-enriched air is directed from the cathode to an aircraft fuel tank or aircraft fire suppression system. In a second mode of operation, fuel is directed to the anode, electric power is directed from the anode and cathode to one or more aircraft electric power-consuming systems or components, and nitrogen-enriched air is directed from the cathode to a fuel tank or fire suppression system.
US11258082B2 Fuel cell and temperature control method
The fuel cell includes a power generation unit, a plurality of storage containers that are detachable and house hydrogen absorbing alloy, a heat medium passage through which a heat medium flows, and a temperature control unit for heating the storage containers by controlling the temperature of the heat medium and causing the heat medium to flow. The temperature control unit can carry out a first temperature control mode of controlling the temperature of the heat medium to be equal to or higher than a first temperature, and a second temperature control mode of controlling the temperature of the heat medium to be equal to or higher than a second temperature. The temperature control unit determines whether the second temperature mode is to be carried out or not based on the pressure or the temperature of an attached storage container when a new storage container is attached.
US11258079B2 Humidification device
A humidification device includes a humidification section that humidifies taken-in air and a cover that covers the humidification section. A space is provided between the humidification section and the cover. A supply port for sending out humidified air humidified by the humidification section is further provided. The space communicates with the supply port, and the humidified air flows through the space, thereby utilizing air in the space as a heat insulation layer.
US11258073B2 Electrode assembly and method for manufacturing the same
A method for manufacturing an electrode assembly includes forming each of a negative electrode, a separator, and a positive electrode so as to have a shape having a hole; laminating the negative electrode, the separator, and the positive electrode to manufacture a unit cell; laminating at least two unit cells to form a laminate; folding a folding separator to cover an entire surface of the laminate to wrap an outside of the laminate; removing a portion of a space forming part that is a portion of the folding separator surrounding a space formed by the aligned holes when the folding separator is folded to wrap the laminate; and bonding surplus parts that are portions of the folding separator to each other after the portion of the space forming part is removed so as to finish the folding separator to cover an exposed surface of the laminate is provided.
US11258072B2 Catalyst layer for a fuel cell and method for the production thereof
A catalyst layer (20) for a fuel cell and to a method suitable for producing the catalyst layer (20). The catalyst layer (20) includes a catalyst material (22) containing a catalytic material (24) and optionally porous carrier material (23) on which the catalytic material (24) is supported. The catalyst layer also includes mesoporous particles (21) made from hydrophobic material.
US11258068B2 Positive electrode for metal air battery, metal air battery including the same, and method of preparing the positive electrode for metal air battery
A positive electrode for a lithium battery includes a lithium salt, a carbonaceous material, and a coating on a surface of the carbonaceous material, the coating including a polymer electrolyte including a hydrophilic material and a hydrophobic material, wherein a portion of the polymer electrolyte is anchored to the surface of the carbonaceous material by a chemical bond.
US11258063B2 Method for preparing positive electrode active material
A method of preparing a positive electrode active material which includes forming a pre-sintered mixture by adding a reaction mixture including a lithium raw material and a nickel-manganese-cobalt precursor to a first crucible and performing a primary heat treatment at a temperature of 500° C. to 800° C., and, after discharging the pre-sintered mixture from the first crucible, adding the pre-sintered mixture to a second crucible and performing a secondary heat treatment at a temperature of 700° C. to 1,000° C. to form a lithium nickel manganese cobalt-based positive electrode active material, wherein a volume of the pre-sintered mixture formed after the primary heat treatment is 20% to 50% of a volume of the reaction mixture added to the first crucible.
US11258058B2 Silicon carbon composite powder active material
Systems and methods for generating silicon carbon composite powder that have the electrical properties of thicker, active material silicon carbon composite films or carbon composite electrodes, and may include a cathode, an electrolyte, and an anode, where the electrodes may include silicon carbon composite powder.
US11258056B2 Positive electrode material, positive electrode, and lithium secondary battery which include spinel-structured lithium manganese-based positive electrode active material
The present disclosure relates to a positive electrode material including a spinel-structured lithium manganese-based first positive electrode active material and a lithium nickel-manganese-cobalt-based second positive electrode active material, wherein the first positive electrode active material includes a lithium manganese oxide represented by Formula 1 and a coating layer which is disposed on a surface of the lithium manganese oxide, the second positive electrode active material is represented by Formula 2, and an average particle diameter of the second positive electrode active material is greater than an average particle diameter of the first positive electrode active material, and a positive electrode and a lithium secondary battery which include the positive electrode material: Li1+aMn2−bM1bO4−cAc  [Formula 1] Li1+x[NiyCozMnwM2v]O2−pBp  [Formula 2]
US11258055B2 Cathode active material of lithium secondary battery
The present invention relates to a cathode active material for a lithium secondary battery, and more particularly, to a cathode active material for a lithium secondary battery, which includes a core portion and a shell portion surrounding the core portion, in which a total content of cobalt in the core portion and the shell portion is 5 to 12 mol %, and the content of cobalt in the core portion and the shell portion is adjusted to be within a predetermined range.In the cathode active material precursor and the cathode active material for a secondary battery prepared using the same according to the present invention, optimal capacity of a lithium secondary battery may be increased by adjusting the cobalt content in the particles of the cathode active material, and life characteristics may be enhanced by improving stability.
US11258053B2 Lithium ion solid-state battery and method for producing the same
A method for preparing a lithium ion solid-state accumulator comprising an anode, a cathode, and a solid-state electrolyte includes pressing and sintering pre-calcined electrolyte powder to an electrolyte layer. The pre-calcined electrolyte powder comprises at least one phosphate compound, at least one silicide compound, or at least one phosphorus sulfide. The method further includes applying, on both sides of the electrolyte layer, one electrode each. Prior to the application of the at least one electrode layer on a surface of the sintered electrolyte layer, first, at least one intermediate layer, and, then, on this intermediate layer, the electrode layer is applied. The at least one intermediate layer is a layer of electrolyte and anode material and/or a layer of electrolyte and cathode material.
US11258052B2 Method of manufacturing organic light emitting display device using protection film with top opening patterns
A method of manufacturing an organic light emitting display device includes forming a plurality of display structures on a lower substrate, forming a top protection film including a plurality of top opening patterns on the lower substrate and the display structures such that the top opening patterns do not overlap the display structures, cutting the lower substrate between two adjacent display structures among the plurality of display structures along a first cutting line that is located at at least a portion of the top opening patterns, and separating the lower substrate to form a plurality of display panels each including the display structure and a portion of the lower substrate.
US11258050B2 Organic light emitting display device and method for manufacturing the same
An organic light-emitting display device capable of improving luminance and light extraction efficiency thereof while preventing image blur, and a method for manufacturing the same is disclosed. In accordance with the device and the method, image blur is suppressed and luminance and light-emitting efficiency are improved by forming micro-lenses on an encapsulating layer for protecting organic light-emitting elements at precise positions corresponding to the elements in a self-aligned and self-assembled manner.
US11258049B2 Display device having reflection layers with different refractive indexes
A display device includes a substrate having a light emission area, a light emitting element layer including a light emitting element on the light emission area, and an sensing layer on the light emitting element layer and including a sensing electrode having a first opening overlapping the light emission area, a first refraction layer directly on the sensing electrode and having a second opening overlapping the light emission area, and a second refraction layer on the light emitting element layer and the first refraction layer, a first optical refractive index of the first refraction layer being less than a second optical refraction index of the second refraction layer.
US11258048B2 Display panel with first electrode having different refractive indexes in sub-pixel regions of different colors and display panel device having the same
The present invention provides a display panel and a display device thereof. The display panel includes a substrate, a reflective layer, pixel retaining walls, first electrodes, a light emitting layer, and a second electrode. In the present invention, by adjusting refractive indexes of first electrodes in each sub-pixel region with different colors, microcavity effects are used to enhance color saturation of emitted light and component efficiency. In this way, difficulties resulting from using vacuum evaporation methods along with fine masks to prepare hole transport layers with different thickness and problems such as low utilization of evaporation material are prevented.
US11258047B2 Organic electroluminescent element and measurement apparatus
An organic EL element 100 includes a light emitting layer 110 containing an organic light emitting material, a light shielding electrode 120 being arranged on one surface 110a side of the light emitting layer 110, a light transmissive electrode 130 being arranged on the other surface 110b side of the light emitting layer 110, a reflection filter 160 being arranged on a side opposite to the light emitting layer 110 with respect to the light transmissive electrode 130 and selectively reflecting a light L1 from the light emitting layer 110.
US11258046B2 Light emitting display panel and electronic device including the same
By controlling the optical thickness of the upper stacked structure disposed on the display panel, it is possible to periodically control the tristimulus value of Xr and the tristimulus value of Yg emitted from the electronic device. The optical thickness is determined by the thickness and refractive index of the upper stacked structure. This control may reduce the tristimulus value of Xr periodically or increase the tristimulus value of Yg periodically. The tristimulus value of Xr may be periodically decreased and the tristimulus value of Yg may be periodically increased at the same time.
US11258044B2 Display device having protection layer including photo-hardening resin
A display device includes: a substrate including a first flat area, a second flat area, and a bending area between the first flat area and the second flat area; a display unit overlapping the first flat area and disposed on a surface of the substrate; first and second protection layers on an opposing surface of the substrate and overlapping the first and second flat areas, respectively. The first and second protection layers include a hardening member including a photo-hardening resin, the first protection layer includes a first inclination part at an end, the second protection layer includes a second inclination part at an end, the first inclination part has a first inclination angle with the opposing surface, the second inclination part has a second inclination angle with the opposing surface, and the first and second inclination angles are in a range of about 10 degrees to about 90 degrees.
US11258040B2 Display device
A display device includes an active region and a non-active region. The display device includes a display panel and a polarizing member which is disposed on a surface of the display panel, where the display panel and the polarizing member include a first through hole which penetrates the display panel and the polarizing member in a thickness direction and a hole coating layer which is disposed on an inner wall of the polarizing member of the first through hole.
US11258033B2 Display panel and display module
A display panel and a display module, the display panel includes a substrate. The display panel includes a display area and a non-display area; a switch array layer disposed on the substrate, the switch array layer includes a first metal layer and a second metal layer; an anode layer disposed on the switch array layer, the anode layer includes a first sub-portion positioned within the display area and a second sub-portion positioned within the non-display area; viscosity of material of the second sub-portion is greater than viscosity of material of the first sub-portion. The display panel and the display module of the invention can avoid detach of the anode layer, thereby improving electrical conductivity of the anode layer.
US11258032B2 Organic light emitting device and display device including same
An organic light emitting device and a display device, the organic light emitting device including a first electrode; a first organic layer on the first electrode; a first charge generating layer on the first organic layer; a second organic layer on the first charge generating layer, the second organic layer including a first light absorbing dye having an absorption wavelength of about 380 nm to 410 nm; and a second electrode on the second organic layer, wherein light is emitted from the device in the direction from the first electrode to the second electrode.
US11258029B2 Light-emitting device
A light emitting device includes: a first electrode; a second electrode facing the first electrode; m emission units stacked between the first electrode and the second electrode; and m−1 charge generating layer(s) between the two adjacent emission units from among the m emission units, m−1 charge generating layer(s) including m−1 n-type charge generating layer(s) and m−1 p-type charge generating layer(s), wherein m is an integer of 2 or greater, a maximum emission wavelength of light emitted from at least one of the m emission units differs from that of light emitted from at least one of the other emission units, at least one of the m−1 n-type charge generating layer(s) includes a metal-containing material and an electron transporting metal-non-containing material.
US11258026B2 Nanoparticle, method for preparing display substrate and display device
The nanoparticle of the embodiments of the present disclosure includes nanograins, and a first ligand and a second ligand connected to a surface of each nanograin, wherein the first ligand has alkali solubility, and the second ligand undergoes a crosslinking reaction when heated. The method for preparing the display substrate according to embodiments of the present disclosure includes: forming a nanoparticle layer on a substrate; coating a photoresist on the nanoparticle layer, exposing the photoresist with a mask; developing to remove the photoresist in the photoresist removal region, such that the exposed nanoparticle layer is dissolved into a developing solution; performing post-baking treatment, such that a second ligand of the nanoparticle covered by the photoresist in the photoresist reserved region undergoes a crosslinking reaction, and the nanoparticle layer covered by the photoresist in the photoresist reserved region is fixed on the substrate; and stripping the photoresist, to complete a patterning of the nanoparticle layer.
US11258022B2 Manufacturing method of display device
A display device includes a flexible substrate, and a display region having a plurality of pixels on the flexible substrate. The substrate includes a resin layer, a first inorganic insulating layer provided on the first resin layer, and a second resin layer provided on the first insulating layer. A thickness of the second resin layer is larger than a thickness of the first resin layer, and the first resin layer is a resin layer baked at a higher baking temperature than the second resin layer.
US11258021B2 Display panel and display device having a step portion
A display panel being bendable around a bending axis to form a bendable portion, includes a support film, a display module disposed on a side of the support film. An outer edge of the display module is distant from an outer edge along the first direction of the support film, to form a step portion between the outer edge of the display module and the outer edge of the support film. A polarizing layer and a touch layer are disposed on the other side, facing away the support film, of the display module. An outer edge of the polarizing layer and an outer edge of the touch layer are distant from the outer edge of the display module to form a step portion between the outer edge of the polarizing layer, the outer edge of the touch layer and the outer edge of the display module.
US11258018B2 Compounds and organic electronic devices
The present invention relates to certain fluorenes, to the use of the compounds in an electronic device, and to an electronic device comprising at least one of these compounds. The present invention furthermore relates to a process for the preparation of the compounds and to a formulation and composition comprising one or more of the compounds.
US11258014B2 Manufacturing method of organic thin film pattern
Disclosed is a method for manufacturing an organic thin film pattern, an organic thin film pattern, an array substrate, and a display device. The method for manufacturing the organic thin film pattern includes the steps of forming a liquid droplet in a recessed portion of a thin film definition layer on a substrate, the liquid droplet being a solution containing an organic functional material, gelatinizing the liquid droplet, and performing a drying process on gelatinized liquid droplet to form an organic thin film pattern.
US11258009B2 Switching atomic transistor and method for operating same
Disclosed are a switching atomic transistor with a diffusion barrier layer and a method of operating the same. By introducing a diffusion barrier layer in an intermediate layer having a resistance change characteristic, it is possible to minimize variation in the entire number of ions in the intermediate layer involved in operation of the switching atomic transistor or to eliminate the variation to maintain stable operation of the switching atomic transistor. In addition, it is possible to stably implement a multi-level cell of a switching atomic transistor capable of storing more information without increasing the number of memory cells. Also, disclosed are a vertical atomic transistor with a diffusion barrier layer and a method of operating the same. By producing an ion channel layer in a vertical structure, it is possible to significantly increase transistor integration.
US11258007B2 Reversed stack MTJ
An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
US11258005B2 Magnetoresistive random access memory device and method for fabricating the same
A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.
US11258004B2 Transducer device
A transducer device, including an electroactive polymer transducer, which has at least two electrode layers which are situated in parallel to one another and which are connected to one another by inserting an elastic intermediate layer in each case, and including a circuit having electronic components for the purpose of generating an electrical voltage applied to the electrode layers of the polymer transducer, the circuit increasing an input voltage to a voltage which is increased with regard to the input voltage.
US11258002B2 Thermoelectric sintered body and thermoelectric element
A thermoelectric sintered body according to an embodiment comprises thermoelectric powder, the thermoelectric powder, arranged in a horizontal direction, comprising: a plurality of first powders in the shape of plate-type flakes; and a plurality of second powders in a shape different from that of the first powders, wherein the second powders comprise 5 volume % or less of the total thermoelectric powder.
US11258001B2 Semiconductor light-emitting element and semiconductor light-emitting device
A semiconductor light-emitting element includes: a semiconductor stack including an n-type, layer and a p-type layer and having at least one n exposure portion being a recess where the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer (i) continuously covering inner lateral surfaces of at least one n exposure portion and part of a top surface of the p wiring electrode layer and (ii) having an opening portion that exposes the n-type layer; an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer and in contact with the n-type layer in the opening portion; and at least one first n connecting member connected to the n wiring electrode layer in at least one first n terminal region. The n wiring electrode layer and the p-type layer are disposed below at least one first n terminal region.
US11258000B2 Semiconductor laser device
A semiconductor laser device includes: a package includes a recess and an upper surface that has an outer peripheral surface and a bonding surface positioned between the recess and the outer peripheral surface, the bonding surface having inner corners on the recess side and outer corners on the outer peripheral surface side; at least one semiconductor laser element disposed in the recess of the package; and a light-transmissive member bonded to the bonding surface of the package. The radius of curvature of inner corners is greater than the radius of curvature of outer corners.
US11257998B2 Semiconductor element package and autofocusing device
A semiconductor element package includes: a semiconductor element arranged above a first substrate; first and second electrodes arranged above the first substrate and electrically connected to the semiconductor element; a housing which is arranged above the first substrate and arranged around the semiconductor element, and which has a stepped portion in the upper area thereof; a diffusion part arranged on the stepped portion of the housing and arranged above the semiconductor element; and a plurality of via holes penetrating the first substrate and the housing.
US11257996B2 Light emitting apparatus and method for producing the same
A light emitting apparatus includes: a mount substrate; a first light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the first light emitting device via an adhesive material, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the first light emitting device, and wherein a first lateral surface of the light transparent member is located laterally inward of a lateral surface of the first light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.
US11257995B2 Optical modulating device, back light module, display apparatus, and fabricating method thereof
The present application provides an optical modulating device having a light transmissive region and a light blocking region. The optical modulating device includes a base substrate; a plurality of protrusions on the base substrate in the light transmissive region and configured to allow light emitting out of a side of the optical modulating device; and a reflective layer on the base substrate in the light blocking region and configured to block light from emitting out of the side of the optical modulating device.
US11257994B2 Resin package and light emitting device
A resin package defining a recess includes a first lead having an element-mounting region, a second lead having a wire-connecting region, and a resin body including first to third resin portions. The third resin portion surrounds the element-mounting region. Each of the first and second leads includes a first plating and a second plating covering at least a portion of the first plating. The wire-connecting region is located outward of the third resin portion. The element-mounting region is located on an outermost surface of the second plating. In a top view, the wire-connecting region is located laterally inward of a portion of the second plating of the second lead that has an outermost surface located higher than that of the first plating of the second lead.
US11257993B2 Method of manufacturing light emitting device and light emitting device
A light emitting device includes: a substrate; and at least one light-emitting part comprising a light source and a sealing member covering the light source, wherein the sealing member includes a dent and a peripheral portion surrounding the dent, and includes at least one projection at the peripheral portion.
US11257991B2 Light emitting device, backlight unit and display apparatus
A light emitting device includes a first LED chip to emit a light having a peak wavelength in a range of 410 to 430 nm, a second LED chip to emit a light having a peak wavelength in a range of 440 to 460 nm, a first quantum dot to convert light emitted by the first and second LED chips into light having a peak wavelength in a range of 510 to 550 nm, and a second quantum dot to convert light emitted by the first and second LED chips into light having a peak wavelength in a range of 610 to 660 nm, wherein, in an emission spectrum of final light, intensity of a peak wavelength of the first LED chip is 15% or less of intensity of a peak wavelength of the second LED chip.
US11257990B2 Light emitting device
A light emitting device includes: a first light emitting element and a second light emitting element, each having a peak emission wavelength in a range of 430 nm to 480 nm; a first light transmissive member disposed on an upper face of the first light emitting element and containing a first phosphor; a second light transmissive member disposed on an upper face of the second light emitting element; and an encapsulant covering the first light transmissive member and the second light transmissive member and containing a second phosphor. The first light emitting element and the second light emitting element are configured to be independently driven. A chromaticity of light exiting from the first light transmissive member differs from a chromaticity of light exiting from the second light transmissive member.
US11257988B2 LED holder, LED module and method for manufacturing LED holder
The application relates to an LED module, an LED holder, and a method for manufacturing the LED holder. The LED holder includes an insulating carrier and a lead frame. The insulating carrier includes a first sidewall, a second sidewall opposite to the first sidewall, and a partition portion positioned between the first sidewall and the second sidewall. The lead frame includes a first electrode and a second electrode positioned at two sides of the partition portion respectively. The first electrode includes a first bottom portion and a first wing portion obliquely connected with the first bottom portion. The second electrode includes a second bottom portion and a second wing portion obliquely connected with the second bottom portion. The LED holder can improve the reflectivity of the insulating carrier and can prevent the insulating carrier from aging.
US11257984B2 III-nitride down-conversion nanomaterial for white LEDs
A phosphor component that includes a plurality of nanowires absorbing light at one wavelength and emitting light at a longer wavelength, the longer wavelength being from about 495 nm to about 780 nm, each one of the plurality of nanowires being one of a nanowire described by a composition formula of InxGa1-xN, x being between about 0.1 to about 0.6 or a GaN nanowire having InxGa1-xN discs in a nanowire structure, x being between about 0.1 to about 0.8 and a light emitting device using the phosphor component are disclosed.
US11257980B2 Light-emitting diode
A light-emitting diode is provided. The light-emitting diode includes a multiple quantum well structure to generate a light beam with a broadband blue spectrum. The light beam contains a first sub-light beam with a first wavelength and a second sub-light beam with a second wavelength. A difference between the first wavelength and the second wavelength ranges from 1 nm to 50 nm, and the light-emitting diode has a Wall-Plug-Efficiency (WPE) of greater than 0.45 under an operating current density of 120 mA/mm2.
US11257979B2 Display apparatus and manufacturing method thereof
The present disclosure relates to a display apparatus including a substrate, a thin film transistor disposed on the substrate, a first insulating layer disposed on a source electrode and a drain electrode of the thin film transistor, a light emitting diode disposed on the first insulating layer to emit light toward the substrate, a second insulating layer disposed on the first insulating layer to surround the light emitting diode, an upper electrode disposed on the second insulating layer, and a driver IC chip disposed above the upper electrode to be connected to the upper electrode. According to the above configuration, the driver IC chip is disposed on the back side of a light emitting surface of a display panel, so that a bezel is capable of being minimized or omitted, and manufacturing of the display apparatus is easy and manufacturing costs is reduced.
US11257978B2 Front metal contact stack
A photovoltaic device and a method of forming a contact stack of the photovoltaic device are disclosed. The photovoltaic device may include a first layer deposited on a semiconductor layer including a compound semiconductor material. The photovoltaic device may also include a dopant layer comprising tin (Sn) deposited on the first layer. The photovoltaic device may further include a conductive layer deposited or provided over the dopant layer to form a contact stack with the first layer and the dopant layer.
US11257976B2 Semiconductor devices and methods of manufacturing semiconductor devices
In one example, a semiconductor device comprises a substrate, an optical device on a top side of the substrate, a translucent cover over the optical device, wherein the translucent cover is a unitary monolithic piece comprising a cover base and a cover pipe. and a cover structure on the top side of the substrate to support the translucent cover over the optical device. Some examples and related methods are also disclosed herein.
US11257971B2 Shingled photovoltaic module with bypass diodes
A shingled photovoltaic module with bypass diodes, includes four regions. Each region includes a plurality of cell strings consisting of crystalline silicon cells or crystalline silicon slice cells; the cell strings in the each region are connected in parallel with each other, and circuits between the regions are connected in series with each other; a first region and a second region are protected by one bypass diode, and a third region and a fourth region are protected by another bypass diode; the bypass diodes are positioned in a central part of the module; and positive electrode and negative electrode cables of the module are led out from a junction box which is located on a back side of the module and is close to an edge of the module.
US11257963B1 Semiconductor device
In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.
US11257959B2 Semiconductor device and method for manufacturing the semiconductor device
A semiconductor device having a high on-state current is provided.The semiconductor device includes a first oxide; a first conductor and a second conductor provided over the first oxide to be separated from each other; and a second oxide provided over the first oxide and between the first conductor and the second conductor. Each of the first oxide and the second oxide has crystallinity, the first oxide includes a region where a c-axis is aligned substantially perpendicularly to a top surface of the first oxide, and the second oxide includes a region where the c-axis is aligned substantially perpendicularly to the top surface of the first oxide, a region where the c-axis is aligned substantially perpendicularly to a side surface of the first conductor, and a region where the c-axis is aligned substantially perpendicularly to a side surface of the second conductor.
US11257956B2 Thin film transistor with selectively doped oxide thin film
A thin film transistor (TFT) device is provided, where the TFT may include a source and a drain, a gate stack, and a semiconductor body. The gate stack may include a gate dielectric structure and a gate electrode, and the gate stack may be between the source and the drain. A first section of the semiconductor body may be adjacent to at least a section of the gate stack. A spacer may be between the gate stack and the source, where the spacer may be on the semiconductor body, and where a second section of the semiconductor body underneath the spacer may comprise dopants.
US11257955B2 Thin film transistor, array substrate, and method for fabricating the same
The disclosure provides a thin film transistor, an array substrate, and a method for fabricating the same. An embodiment of the disclosure provides a method for fabricating a thin film transistor, the method including: forming a gate, a gate insulation layer, and an active layer above an underlying substrate successively; forming a patterned hydrophobic layer above the active layer, wherein the hydrophobic layer includes first pattern components, and orthographic projections of the first pattern components onto the underlying substrate overlap with a orthographic projection of a channel area at the active layer onto the underlying substrate; and forming a source and a drain above the hydrophobic layer, wherein the source and the drain are located respectively on two sides of a channel area, and in contact with the active layer.
US11257952B2 Source/drain structure
Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
US11257949B2 Transistor devices and methods of forming transistor devices
An LDMOS transistor device may be provided, including a substrate having a conductivity region arranged therein, a first isolation structure arranged within the substrate, a source region and a drain region arranged within the conductivity region, a second isolation (local isolation) structure arranged between the source region and the drain region, and a gate structure arranged at least partially within the second isolation structure. The first isolation structure may extend along at least a portion of a border of the conductivity region, and a depth of the second isolation structure may be less than a depth of the first isolation structure. In use, a channel for electron flow may be formed along at least a part of a side of the gate structure arranged within the second isolation (local isolation) structure.
US11257946B2 Method of forming a power semiconductor device
A method of forming a power semiconductor device includes: arranging a control electrode at least partially on or inside a semiconductor body; forming elevated source regions in the semiconductor body by: implanting first conductivity type dopants into the semiconductor body; forming a recess mask layer covering at least areas of intended source regions; and removing portions of the semiconductor body uncovered by the recess mask layer to form the elevated source regions and recessed body regions at least partially between the source regions. A dielectric layer is formed on the semiconductor body. A contact hole mask layer is formed on the dielectric layer. Portions of the dielectric layer uncovered by the contact hole mask layer are removed to form a contact hole which is filled at least partially with a conductive material to establish an electrical contact with at least a portion of the elevated source and recessed body regions.
US11257945B2 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device, including a first semiconductor layer of the first conductivity type formed on a semiconductor substrate, a first semiconductor region of the first conductivity type, a first base region of a second conductivity type and a first base region of a second conductivity type that are respectively selectively provided in the first semiconductor layer, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer, a second semiconductor region of the first conductivity type selectively provided in the second semiconductor layer, a trench that penetrates the second semiconductor layer and the second semiconductor region, a gate electrode provided in the trench via a gate insulating film, an interlayer insulating film provided on the gate electrode, a first electrode in contact with the second semiconductor layer and the second semiconductor region, and a second electrode provided on a back surface of the semiconductor substrate.
US11257944B2 Semiconductor device and semiconductor device manufacturing method
A semiconductor device according to the present invention includes a semiconductor layer, a gate trench defined in the semiconductor layer, a first insulating film arranged on the inner surface of the gate trench, a gate electrode arranged in the gate trench via the first insulating film, and a source layer, a body layer, and a drain layer arranged laterally to the gate trench, in which the first insulating film includes, at least at the bottom of the gate trench, a first portion and a second portion with a film elaborateness lower than that of the first portion from the inner surface of the gate trench in the film thickness direction.
US11257938B2 Group III nitride semiconductor device with first and second conductive layers
A semiconductor device is provided with, a group-III nitride semiconductor layered structure that includes a heterojunction, an insulating layer which has a gate opening that reaches the group-III nitride semiconductor layered structure and which is disposed on the group-III nitride semiconductor layered structure, a gate insulating film that covers the bottom and the side of the gate opening, a gate electrode defined on the gate insulating film inside the gate opening, a source electrode and a drain electrode which are disposed to be spaced apart from the gate electrode so as to sandwich the gate electrode, a first conductive layer embedded in the insulating layer between the gate electrode and the drain electrode, and a second conductive layer that is embedded in the insulating layer above the first conductive layer in a region closer to the drain electrode side than the first conductive layer.
US11257936B2 Method for making JFET device, JFET device and layout structure thereof
According to some embodiments in this application, a method for making a JFET device is disclosed in the following steps: forming a substrate; performing ion implantation on the first region and the second region of the substrate to form a deep N-type well, wherein the deep N-type well is formed with at least two sub-wells region; forming a field oxide in the second region; forming a P-type well in one side of the sub-well in the deep N-type well; performing P-type ion implantation on the third region and the fourth region to respectively form a first P-type heavily doped region and a second P-type heavily doped region; and performing N-type ion implantation on the fifth region, the sixth region, and the seventh region to respectively form a first N-type heavily doped region, a second N-type heavily doped region, and a third N-type heavily doped region.
US11257930B2 Method of forming fin field effect transistor
A method of forming a fin field effect transistor (FinFET) includes etching a substrate to define a fin comprising a first material. The fin includes a first portion comprising first sidewalls tapered at a first angle and having a first height; and a second portion comprising second sidewalls tapered at a second angle different from the first angle and having a second height. A ratio of the second height to the first height ranges from about 0.2 to about 0.5. The method includes depositing an insulating material over the substrate, wherein the insulating material covers the fin. The method includes recessing the insulating material to expose at least the second portion of the fin. The method further includes forming a gate structure over the fin. The gate structure includes a gate dielectric over the fin and the recessed insulating material; and a conductive material over the gate dielectric.
US11257929B2 Stacked transistors
A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.
US11257928B2 Method for epitaxial growth and device
A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region. Each of the plurality of buffer layers may have an average thickness in a range of about 2 Å to about 30 Å.
US11257923B2 Tuning threshold voltage in field-effect transistors
A method includes removing a dummy gate structure to form a gate trench over a semiconductor layer, forming a high-k gate dielectric layer over an interfacial layer exposed in the gate trench, depositing a metal-containing precursor over the high-k gate dielectric layer to form a metal-containing layer, and subsequently depositing an aluminum-containing precursor over the metal-containing layer, where depositing the aluminum-containing precursor forms an aluminum oxide layer at an interface between the high-k gate dielectric layer and the interfacial layer and where the metal-containing precursor includes a metal different from aluminum. The method further includes, subsequent to depositing the aluminum-containing precursor, removing a portion of the metal-containing layer, depositing a work-function metal layer over a remaining portion of the metal-containing layer, and forming a bulk conductive layer over the work-function metal layer, resulting in a metal gate structure.
US11257921B2 Semiconductor device and method of manufacture
Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.
US11257920B2 Fastening member and semiconductor device
Provided is a fastening member which is a columnar fastening member, and the fastening member includes: a first hole provided in a direction parallel to a height direction of the fastening member; a thread on a side surface of the first hole; a planar portion around the first hole; and a projection between the planar portion and the first hole.
US11257916B2 Electronic device having multi-thickness gate insulator
Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section including a first thickness, and a second gate insulator section including a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.
US11257914B2 Semiconductor die, semiconductor device and IGBT module
A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.
US11257911B2 Sacrificial layer for semiconductor process
A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.
US11257908B2 Transistors with stacked semiconductor layers as channels
A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.
US11257906B2 High surface dopant concentration formation processes and structures formed thereby
Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.
US11257905B2 Semiconductor device including source/drain region
A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.
US11257902B2 SOI device structure for robust isolation
This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.
US11257900B2 Semiconductor device
A semiconductor device, including a substrate of a first conductivity type, an active region and a termination structure portion formed on a front surface of the substrate, and a plurality of regions of a second conductivity type formed concentrically surrounding the periphery of the active region in the termination structure portion. Each region has a higher impurity concentration than one of the regions adjacent thereto on an outside thereof. The plurality regions include first and second semiconductor regions, and an intermediate region sandwiched between, and in contact with, the first and second semiconductor regions. The intermediate region includes a plurality of first subregions and a plurality of second subregions that are alternately arranged along a path in parallel to a boundary between the active region and the termination structure portion, the second subregions having a lower impurity concentration than the first subregions.
US11257898B2 Systems and methods for shielded inductive devices
In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
US11257897B2 Display panel including an initialization voltage line and an auxiliary voltage line and display device including the same
A display panel includes: a substrate including a first area and a second area surrounding the first area; a first initialization voltage line extending in a first direction and electrically connected to the first display element; a second initialization voltage line extending in the first direction and electrically connected to the second display element; an auxiliary voltage line arranged on a layer different from layers on which the first initialization voltage line and the second initialization voltage line are arranged and electrically connecting the first initialization voltage line and the second initialization voltage line that are apart from each other; and a first insulating layer covering the first initialization voltage line, the second initialization voltage line, and the auxiliary voltage line and arranged below the plurality of display elements.
US11257892B2 Light-emitting module and display device
This disclosure provides a light-emitting module and a display device. The light-emitting module includes: a body including a light-emitting panel and a cover plate located on a light emission side of the light-emitting panel; and a conductive layer arranged on a side of the body, the conductive layer having a part which is continuous from the cover plate to the light-emitting panel, wherein the conductive layer is grounded.
US11257889B2 OLED display panel having light shielding layer for shielding light emitted at edges of pixel-emitting region, manufacturing method thereof, and OLED display device
The present invention provides an organic light-emitting diode (OLED) display panel, a manufacturing method thereof, and a display device. The OLED display panel includes a substrate, an electrode layer, a pixel defining layer, and a light shielding layer. The electrode layer is spaced at intervals on the substrate. The pixel defining layer is placed on the substrate. The pixel defining layer includes dams and a light opening between any two adjacent dams. Each dam includes a dam body and a light shielding layer. A projection of the light shielding layer projected on the substrate is larger than or equal to a projection of the dam body projected on the substrate.
US11257888B2 Display panel and method of fabricating thin film transistor
A display panel and a method of fabricating a thin film transistor. The display panel includes a plurality of data writing thin film transistors. Each of the data writing thin film transistors includes a substrate, a light shielding metal layer, a buffer layer, an active region, a gate dielectric layer, and a gate metal layer. The active region includes a channel region and a source region and a drain region on both sides of the channel region. The data writing thin film transistor further includes a first via hole penetrating the gate dielectric layer and the buffer layer, and the gate metal layer is electrically connected to the light shielding metal layer through the first via hole.
US11257887B2 Thin film transistor substrate, display apparatus and method of manufacturing the same
A thin film transistor substrate includes: a substrate, a first electrode disposed on the substrate, a bank disposed on the substrate and having an inclined surface inclined at an angle with respect to the substrate, a second electrode disposed on the bank, an active pattern electrically connected to the first electrode and the second electrode, disposed on the inclined surface, and including a first conductive region and a second conductive region in which impurities are doped, and a channel region between the first conductive region and the second conductive region, and a gate electrode overlapping at least a portion of the channel region of the active pattern. The inclined surface extends in a first direction in a plan view. The first conductive region, the channel region, and the second conductive region are sequentially disposed on the inclined surface along a second direction that crosses the first direction.
US11257886B2 Organic light emitting diode display
An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer.
US11257883B2 Power and data routing structures for organic light-emitting diode displays
An organic light-emitting diode display may have thin-film transistor circuitry formed on a substrate. The display and substrate may have rounded corners. A pixel definition layer may be formed on the thin-film transistor circuitry. Openings in the pixel definition layer may be provided with emissive material overlapping respective anodes for organic light-emitting diodes. A cathode layer may cover the array of pixels. A ground power supply path may be used to distribute a ground voltage to the cathode layer. The ground power supply path may be formed from a metal layer that is shorted to the cathode layer using portions of a metal layer that forms anodes for the diodes, may be formed from a mesh shaped metal pattern, may have L-shaped path segments, may include laser-deposited metal on the cathode layer, and may have other structures that facilitate distribution of the ground power supply.
US11257881B2 Pixel arrangement structure, vapor deposition mask and irregular-shaped display screen
The present invention provides a pixel arrangement structure, a vapor deposition mask and an irregular-shaped display screen. The pixel arrangement structure is used for irregular-shaped display of an irregular-shaped display screen, the pixel arrangement structure is provided with several rows and/or several columns of pixel display units, wherein neighboring rows and/or neighboring columns of the pixel display units are arranged in parallel within an irregular-shaped display region (105). By arranging the pixel display units within the irregular-shaped display region (105) in such a way that the neighboring rows and/or neighboring columns of the pixel display units are parallel rows or columns, a confusion phenomenon at the interface between an irregular-shaped display region (105) and a non-display region (107) on an edge of the irregular-shaped display region (105) can be eliminated.
US11257880B2 Organic light emitting diode display device and organic light emitting diode thereof
There is provided an organic light emitting diode display device. The organic light emitting diode display device includes a substrate divided into an emission area and a non-emission area, an overcoating layer disposed on the substrate and including a plurality of micro lenses, a plurality of first electrode patterns disposed on the overcoating layer and spaced away from each other in the emission area, an organic emission layer disposed on the plurality of first electrodes, and a second electrode disposed on the organic emission layer.
US11257877B2 Display device
Disclosed is a display device capable of reducing the thickness and the weigh thereof. In an organic light-emitting diode display device having a touch sensor, a plurality of routing lines, which are connected respectively to a plurality of touch sensors disposed on an encapsulation unit, are disposed on different planes so as to overlap each other and are electrically connected to each other through a plurality of routing contact holes. Thereby, a connection fault between the routing lines is prevented. In addition, through the provision of the touch sensors above the encapsulation unit, a separate attachment process is unnecessary, which results in a simplified manufacturing process and reduced costs.
US11257875B2 Flexible display device
A flexible display device includes a display panel layer, a touch sensing layer, a reflection prevention layer, and a window layer. The touch sensing layer is disposed directly on a first display panel surface, a second display panel surface facing the first display panel surface in a thickness direction, or a second base surface of the reflection prevention layer. The reflection prevention layer is disposed directly on the second display panel surface or a first base surface of the touch sensing layer. The window layer is disposed directly on the first base surface or the second base surface.
US11257872B2 Display panel and manufacturing method thereof
The present disclosure provides a display panel and a manufacturing method thereof. The display panel includes a first substrate, a second substrate, a cathode layer, a plurality of spacer columns, and an encapsulation layer. The spacer columns are disposed as at least a one-circle structure surrounding an opening hole on the second substrate, and heights of the spacer columns are gradually increased from a center of the opening hole to edges thereof. The spacer columns having different heights can reflect light again, thereby improving light extraction efficiency, luminous brightness of sub-pixels adjacent to the opening hole area, and display effect.
US11257866B2 Integrated reactive material erasure element with phase change memory
A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.
US11257864B2 RRAM structure with only part of variable resistive layer covering bottom electrode and method of fabricating the same
An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.
US11257863B2 Device and method for disturbance free 3D MRAM fabrication
A magnetic random access memory includes a memory cell including a first fixed layer, a second fixed layer, and one or more free layers disposed between the first fixed layer and the second fixed layer. The first and second fixed layers are continuous layers and commonly shared by a plurality of memory cells. The magnetic random access memory has a relatively simple structure that not only reduces magnetic interference between memory cells, but also simplifies the fabrication process and increases the integration level.
US11257861B2 Semiconductor structure and method of forming the same
A semiconductor structure, comprising a substrate and an interconnect layer disposed over a substrate and extending across a memory region and a logic region. The interconnect layer comprises a plurality of tower structures disposed in the interconnect layer within the memory region. Each tower structure comprises at least one metal interconnect structure and a magnetic tunnel junction (MTJ) structure stacked on the metal interconnect structure. The plurality of tower structures are arranged on the substrate in a XY staggered pattern. The at least one metal interconnect structure and the magnetic tunnel junction (MTJ) structure in each tower structure are substantially symmetric along a stacking direction.
US11257854B2 Pixel-level background light subtraction
A pixel circuit, a method for performing a pixel-level background light subtraction, and an imaging device are disclosed. In one example of the present disclosure, the pixel circuit includes an overflow gate transistor, a photodiode, and two taps. Each tap of the two taps is configured to store a background signal that is integrated by the photodiode, subtract the background signal from a floating diffusion, store a combined signal that is integrated by the photodiode at the floating diffusion, and generate a demodulated signal based on a subtraction of the background signal from the floating diffusion and a storage of the combined signal that is integrated at the floating diffusion.
US11257850B2 Backplane structure containing capacitor
A backplane structure containing a capacitor includes a substrate, a first conductive film disposes on the substrate, a second conductive member having one portion spaced apart from the first conductive film and another portion connected to the first conductive film, a third conductive film spaced apart from the first conductive film and the second conductive member, a fourth conductive member connected to the third conductive film, and a fifth conductive member having one portion connected to the fourth conductive member and another portion spaced apart from the second conductive member. The third conductive film is disposed between the first conductive film and the second conductive member in an insulation manner, and the second conductive member is disposed between the third conductive film, the fourth conductive member, and the fifth conductive member in an insulation manner.
US11257845B2 Radio frequency integrated circuit having relatively small circuit area and method of fabricating the same
A radio frequency integrated circuit includes a silicon CMOS substrate with at least one CMOS device buried therein, and at least one thin film transistor formed on the silicon CMOS substrate and functioning as a radio frequency device. The thin film transistor includes a T-shaped gate electrode. A method for the fabricating a radio frequency integrated circuit is also disclosed.
US11257844B2 Ferroelectric random access memory (FRAM) cell
A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.
US11257839B2 Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises sacrificial material of different composition from the first-tier material there-above and from the second-tier material tier there-above. The sacrificial material is of different composition from that of an uppermost portion of the conductor material of the conductor tier. The sacrificial material is isotropically etched selectively relative to the uppermost portion of the conductor material of the conductor tier, selectively relative to the first-tier material there-above, and selectively relative to the second-tier material there-above. After the isotropic etching, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other methods and structure independent of method are disclosed.
US11257838B2 Thickened sidewall dielectric for memory cell
Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
US11257836B2 Dummy vertical structures for etching in 3D NAND memory and other circuits
A memory device comprises a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad. An array of vertical pillars extends through the stack of patterned conductor layers, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers. The array has an array boundary proximal to the pad. A first set of isolation blocks extends through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad. A second set of isolation blocks inside the array boundary extends through the plurality of patterned conductor layers isolating the other strips from the pad.
US11257835B2 Three-dimensional memory device containing a dummy memory film isolation structure and method of making thereof
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, rows of memory openings vertically extending through the alternating stack, memory opening fill structures located within a first subset of the rows of memory openings, where each of the memory opening fill structures includes a respective memory film and a respective vertical semiconductor channel extending through an opening at a bottom portion of the respective memory film and contacting a respective underlying semiconductor material portion, and dummy memory opening fill structures located within a second subset of the rows of memory openings that do not belong the first subset, where each of the dummy memory opening fill structures includes a respective dummy memory film and a respective dummy vertical semiconductor channel that is electrically isolated from a respective underlying semiconductor material portion by a bottom portion of the respective dummy memory film.
US11257832B2 Semiconductor memory device and method for manufacturing same
A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.
US11257830B2 Memory structure
In the memory structure, a pair of gate stack structures is on a first dielectric layer and separated from each other. Each of the gate stack structures includes a word line and a second dielectric layer. A third dielectric layer is on the sidewall of the gate stack structures. A pair of floating gates is between the gate stack structures. Each of the floating gates is on the third dielectric layer on the sidewall of the corresponding gate stack structure. The top surface of the floating gates is not higher than the that of the second dielectric layer. A fourth dielectric layer covers the first and third dielectric layers, and the floating gates. A control gate is on the fourth dielectric layer between the floating gates. A doped region is in the substrate beside the gate stack structures. An erase gate is above the control gate and the floating gates.
US11257828B2 Integral multifunction chip
An integral multifunction chip is provided. The integral multifunction chip includes an electronic fuse and an interface fuse. The interface fuse and the electronic fuse are disposed in parallel and integrated in a single chip. In a case where only a single chip is provided, the integral multifunction chip of the present disclosure can be selectively operated in a working mode of the electronic fuse or the interface fuse, so that convenience of use of the integral multifunction chip can be improved.
US11257826B2 Semiconductor integrated circuit device
A static random access memory (SRAM) cell has first to sixth transistors that are vertical nanowire (VNW) FETs. The second and fifth transistors are placed side by side sequentially on one side in the X direction of the first transistor. The fourth and sixth transistors are placed side by side sequentially on the other side in the X direction of the third transistor. The first and third transistors are placed side by side in the Y direction.
US11257823B2 Semiconductor device having vertical transistors and method of forming same
The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions. A connection region is formed in the bottom electrode region underneath the first, second and third regions, wherein the connection region and the first and third regions are doped with a dopant of a same type. A resistance of a path extending between the first and the third regions through the connection region is lower than a resistance of a path extending between the first and the third regions through the second region. A second aspect is a method of forming the semiconductor device of the first aspect.
US11257822B2 Three-dimensional nanoribbon-based dynamic random-access memory
Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.
US11257818B2 Fin-based field effect transistors
The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.
US11257816B2 Method for manufacturing semiconductor device including dummy gate electrodes
A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.
US11257814B2 Tracking temperature compensation of an x/y stress independent resistor
An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.
US11257813B2 Semiconductor device
A semiconductor device includes: semiconductor layer having surface and rear surface; insulating film formed on the surface; first and second surface electrode layers formed on the insulating film; rear electrode layer formed on the rear surface; active region set in region of the surface covered with the first surface electrode layer; capacitor region set in region of the surface covered with the second surface electrode layer; first trench formed in the active region; first insulating film formed on inner surface of the first trench; first embedded electrode embedded in the first trench and controlling ON/OFF of current flowing between the first surface electrode layer and the rear electrode layer; second trench formed in the capacitor region; second insulating film formed on inner surface of the second trench; and second embedded electrode embedded in the second trench and electrically connected to the first surface electrode layer.
US11257805B2 Hybrid bonding with uniform pattern density
A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.
US11257801B2 Stacked semiconductor package having mold vias and method for manufacturing the same
A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.
US11257798B2 Light emitting diode for display and display apparatus having the same
A light emitting diode pixel for a display including a first LED sub-unit, a second LED sub-unit disposed on a portion of the first LED sub-unit, a third LED sub-unit disposed on a portion of the second LED sub-unit, and a reflective electrode disposed adjacent to the first LED sub-unit, in which each of the first to third LED sub-units comprises an n-type semiconductor layer and a p-type semiconductor layer, each of the n-type semiconductor layers of the first, second, and third LED stacks is electrically connected to the reflective electrode, and the first LED sub-unit, the second LED sub-unit, and the third LED sub-unit are configured to be independently driven.
US11257797B2 Package on package structure
A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.
US11257795B2 Chip-scale LED package structure
A chip-scale LED package structure includes a white light emitting unit for emitting a white light, a red flip-chip LED for emitting a red light, a green flip-chip LED for emitting a green light, a blue flip-chip LED for emitting a blue light, and an encapsulation layer. The encapsulation includes an encapsulation resin and a plurality of refractive particles distributed in the encapsulation resin. The encapsulation layer encapsulates the white light emitting unit, the red flip-chip LED, the green flip-chip LED, and the blue flip-chip LED. Moreover, electrodes of the white light emitting unit, electrodes of the red flip-chip LED, electrodes of the green flip-chip LED, and electrodes of the blue flip-chip LED are exposed from the encapsulation layer.
US11257793B2 Semiconductor devices and methods for manufacturing the same
Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.
US11257792B2 Semiconductor device assemblies with annular interposers
A semiconductor device package is provided. The package can include a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular interposer disposed over the substrate and surrounding the stack of semiconductor dies. The annular interposer can include a plurality of circuit elements each electrically coupled to at least a corresponding one of the plurality of electrical contacts. The package can further include a lid disposed over the annular interposer and the stack of semiconductor dies.
US11257776B2 Semiconductor package structure and method for manufacturing the same
A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.
US11257773B1 Packaged circuit structure and method for manufacturing the same
A package circuit structure includes a metal board including a first surface and a second surface, a plurality of embedded components, an insulating layer, and two antenna circuit boards. At least one first groove is recessed from the first surface. At least one second groove is recessed from the second surface. The first groove and the second groove are spaced with each other along a first direction perpendicular to a thickness direction of the metal board. Each embedded component is mounted in the first groove or the second groove. The insulating layer covers the first surface and the second surface and fills the first groove and the second groove. The antenna circuit boards are respectively stacked on two opposite sides of the insulating layer. Each antenna circuit board includes at least one antenna and at least one ground wiring. The metal board is electrically connected to each ground wiring.
US11257772B2 Fan-out antenna packaging structure and preparation method thereof
The present disclosure provides a fan-out antenna packaging structure and a preparation method thereof. The fan-out antenna packaging structure comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip, a via being formed in the plastic packaging material layer; a conductive pole located in the via and running through the plastic packaging material layer from top to bottom; an antenna structure located on a first surface of the plastic packaging material layer and electrically connected with the conductive pole; a redistribution layer located on a second surface of the plastic packaging material layer and electrically connected with the semiconductor chip and the conductive pole; and a solder bump located on a surface of the redistribution layer, electrically connected with the redistribution layer and insulated from the plastic packaging material layer.
US11257765B2 Chip package structure including connecting posts and chip package method
Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.
US11257756B1 Antifuse structure
An antifuse structure includes an active area, a gate electrode and a dielectric layer. The gate electrode is over the active area, in which the gate electrode is ring-shaped, and a portion of the gate electrode is overlapped with a portion of the active area in a vertical projection direction, and the portion of the active area has a dopant concentration higher than a dopant concentration of another portion of the active area. The dielectric layer is sandwiched between the portion of the active area and the portion of the gate electrode.
US11257742B2 Wiring structure and method for manufacturing the same
A wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are stacked on and contact one another. The conductive through via extends through the dam portions.
US11257738B2 Vertically stacked transistor devices with isolation wall structures containing an electrical conductor
An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.
US11257735B2 Heat sink-equipped power module substrate and manufacturing method for heat sink-equipped power module substrate
The invention provides a power module substrate with a heat sink, which includes a power module substrate provided with an insulating substrate, a circuit layer provided on one surface of the insulating substrate and a metal layer provided on the other surface of the insulating substrate. The heat sink is bonded to the power module substrate via a bonding layer (30) to a surface on an opposite side to the insulating substrate of the metal layer. Bonding layer is a sintered body of silver particles, a porous body having a relative density in a range of 60% or more and 90% or less, and having a thickness in a range of 10 μm or more and 500 μm or less.
US11257734B2 Thermal management package and method
A thermal management package for a semiconductor device includes a high dielectric constant material substrate, a high thermal conductivity slug disposed in a first window in the high dielectric constant material substrate and held therein by a first bonding material, an outer substrate formed from a material having a low dielectric constant and having a second window formed therein, the high dielectric constant material substrate disposed in the second window in the low dielectric constant outer substrate and held therein by a second bonding material.
US11257731B2 RF devices with enhanced performance and methods of forming the same
The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
US11257727B2 Seal for microelectronic assembly
Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
US11257721B2 Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages
A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.
US11257720B2 Manufacturing method for semiconductor device and integrated semiconductor device
A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.
US11257718B2 Contact structures
The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.
US11257717B2 Selective recessing to form a fully aligned via
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
US11257715B2 Integrated fan-out packages and methods of forming the same
A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.
US11257712B2 Source/drain contact formation methods and devices
A method includes providing a structure that includes a semiconductor substrate, an epitaxial source/drain feature over the semiconductor substrate, and one or more dielectric layers over the epitaxial source/drain feature; etching a hole into the one or more dielectric layer to expose a portion of the epitaxial source/drain feature; forming a silicide layer over the portion of the epitaxial source/drain feature; forming a conductive barrier layer over the silicide layer; and applying a plasma cleaning process to at least the conductive barrier layer, wherein the plasma cleaning process uses a gas mixture including N2 gas and H2 gas and is performed at a temperature that is at least 300° C.
US11257704B2 Device for transferring and integrating micro-devices and method of transfer
A device for transferring micro-devices from a holding device to a final surface, avoiding damage during the process and ensuring coplanar presentation onto the final surface, includes a first substrate on the holding device. The holding device carries at least one transfer substrate which itself carries a plurality of micro-devices. At least one buffering member is located between the first substrate and the transfer substrate. The buffering member provides a small range of buffering for the micro-devices during the transfer and also compensates for any slight unevenness when the micro-devices are laid on and bonded to the final surface. A method for transferring the micro-devices is also disclosed.
US11257702B2 Power supply apparatus for electrostatic chuck and substrate control method
The power supply apparatus for the electrostatic chuck of this invention has: DC power source units for applying DC voltage to electrodes of the electrostatic chuck; and an AC power source unit for causing AC current to flow through an electrostatic capacitance of the electrostatic chuck. Provided that: a circuit for charging an electrode, from DC power source unit, with chuck voltage in order to attract and hold in position the to-be-processed substrate with the electrostatic chuck, be defined as a first circuit and that; a circuit for clearing charges of the to-be-processed substrate be defined as a second circuit, the power supply apparatus further includes switching means for switching between the first circuit and the second circuit. The second circuit is provided with an AC power source unit and a voltmeter for measuring AC voltage.
US11257701B2 Substrate processing apparatus, substrate processing method and recording medium
A substrate processing apparatus includes a transfer device configured to transfer at least one substrate as a processing target; a transfer controller configured to control the transfer device to perform a normal transfer of transferring the substrate and a high-accuracy transfer of transferring the substrate with higher positioning accuracy as compared to the normal transfer; a warm-up controller configured to control the transfer device to perform a warm-up operation, which is different from the normal transfer and the high-accuracy transfer, when necessary; and a necessity determination unit configured to make a determination that the warm-up operation is required as a beginning of the high-accuracy transfer is approaching when a duration of a stop state of the transfer device exceeds a preset reference time.
US11257697B2 Temperature monitoring apparatus, heat treatment apparatus, and temperature monitoring method
A temperature monitoring apparatus includes: a calculator configured to calculate a temperature monitoring waveform by a first-order lag function based on an elapsed time from a start of a temperature change from a first temperature to a second temperature, and a time constant calculated based on a locus of the temperature change; and a monitor configured to monitor a temperature changing from the first temperature to the second temperature based on the temperature monitoring waveform calculated by the calculator.
US11257693B2 Methods and systems to improve pedestal temperature control
A semiconductor processing system may include a substrate pedestal. The system may also include at least one fluid channel having a delivery portion configured to deliver a temperature controlled fluid to the substrate pedestal, and having a return portion configured to return the temperature controlled fluid from the substrate pedestal. The system may also include a heater coupled with the delivery portion of the at least one fluid channel. The system may also include a temperature measurement device coupled with the return portion of the at least one fluid channel, and the temperature measurement device may be communicatively coupled with the heater.
US11257690B2 3DIC package comprising perforated foil sheet
A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.
US11257688B2 Embedded semiconductive chips in reconstituted wafers, and systems containing same
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
US11257682B2 Molecular layer etching
A method of etching an organic or hybrid inorganic/organic material. The method etches molecular layer deposition coatings. An etching cycle comprises a first half reaction exposing the coating to a precursor. A second half reaction exposes a second precursor, removing or etching a portion of the coating.
US11257680B2 Methods for processing a workpiece using fluorine radicals
Methods for processing a workpiece with fluorine radicals are provided. In one example implementation, the method includes a workpiece having at least one silicon layer and at least one silicon germanium layer. The method can include placing the workpiece on a workpiece support in a processing chamber. The method can include generating one or more species from a process gas in a plasma chamber. The method can include filtering the one or more species to create a filtered mixture. The method can include exposing the workpiece to the filtered mixture to remove at least a portion of the at least one silicon layer.
US11257679B2 Method for removing a sacrificial layer on semiconductor wafers
One or more embodiments are directed to methods of removing a sacrificial layer from semiconductor wafers during wafer processing. In at least one embodiment, the sacrificial layer is removed from a wafer during an O2 plasma etch step. In one embodiment, the sacrificial layer is poly(p-phenylene-2, 6-benzobisoxazole) (PBO) or polyimide. The O2 plasma etch step causes a residue to form on the wafer. The residue is removed by immersing the wafer a solution that is a mixture of the tetramethylammonium hydroxide (TMAH) and water.
US11257678B2 Plasma processing method
The invention has been made in view of the above problems, and provides a plasma processing method capable of preventing etching shape abnormality in a plasma processing method for forming a mask layer of a polysilicon film. The invention relates to a plasma processing method for plasma-etching a polysilicon film, the plasma processing method comprising plasma-etching the polysilicon film using a mixed gas including a halogen gas, a fluorocarbon gas, an oxygen gas, and a carbonyl sulfide gas.
US11257676B2 Gallium nitride based semiconductor device and manufacturing method of gallium nitride based semiconductor device
A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.
US11257673B2 Dual spacer metal patterning
A method for patterning a metal layer includes depositing a hard mask layer on a metal layer, depositing a first patterned layer on the hard mask layer, forming a first set of sidewall spacers on sidewalls of features of the first patterned layer, forming a second set of sidewall spacers on sidewalls of the first set of sidewall spacers, removing the first set of sidewall spacers, and performing a reactive ion etching process to pattern portions of the metal layer exposed through the first patterned layer and the second set of sidewall spacers.
US11257672B2 Semiconductor devices including active regions in RAM areas with deposition determined pitch
The present disclosure provides manufacturing techniques in which the layout pattern of a RAM cell may be obtained on the basis of a single lithography step, followed by a sequence of two deposition processes, thereby resulting in a self-aligned mechanism for providing the most critical lateral dimensions for active regions. In this manner, the smallest pitch of approximately 80 nm and even less may be accomplished with superior device uniformity, while at the same time reducing overall manufacturing complexity.
US11257668B2 Semiconductor structure and manufacturing method thereof
The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate includes a first region and a second region; forming a first polycrystalline silicon layer on the substrate, wherein the first polycrystalline silicon layer covers the first region and the second region; forming a stacked structure on the first polycrystalline silicon layer; forming a protective layer on the stacked structure; forming a patterned photoresist layer on the protective layer, wherein the patterned photoresist layer exposes the protective layer in the second region; removing the protective layer and the stacked structure in the second region to expose the first polycrystalline silicon layer in the second region; removing the patterned photoresist layer; and forming a second polycrystalline silicon layer on the protective layer in the first region and the first polycrystalline silicon layer in the second region.
US11257667B2 Methods and apparatus for cleaning semiconductor wafers
A method for cleaning a semiconductor substrate without damaging its patterned structure via an ultra/mega sonic device comprises applying liquid into a space between the substrate and the sonic device; setting an ultra/mega sonic device power supply at a frequency f1 and power P1; and at zero output before bubble cavitation occurs; followed by at f1 and P1 again after bubble temperature is lowered; detecting power on time (at P1, f1), power off time or amplitude of each waveform output by the power supply; comparing the detected power on time with a preset time T1, power off time with a preset time τ2, amplitude of each waveform with a preset value, if the detected power on time is longer than τ1, or power off time is shorter than τ2, or amplitude of any waveform is larger than the preset value, shut down the power supply and send out an alarm.
US11257662B2 Annular member, plasma processing apparatus and plasma etching method
An annular member is disposed to surround a pedestal for receiving a substrate in a plasma processing apparatus. The annular member contains quartz and silicon. A content percentage of the silicon in the quartz and the silicon is 2.5% or more and 10% and less by weight.
US11257661B2 Plasma processing apparatus
A plasma processing apparatus includes: a plasma processing chamber; a radio frequency power source; a sample stage on which a sample is mounted; an electrode which is arranged inside the sample stage and electrostatically chucks the sample; a DC power source which applies a DC voltage to the electrode; and a control device which controls an output voltage of the DC power source so that an electric potential difference between an electric potential of the sample and an electric potential of an inner wall of the plasma processing chamber is reduced to an electric potential difference within a predetermined range during interruption of plasma discharge.
US11257659B1 Electrode assembly, electronic apparatus/device using the same, and apparatus of charged-particle beam such as electron microscope using the same
The present invention provides an electrode assembly comprising two or more electrodes arranged around a primary axis forming a non-cylindrical channel space. General electronic apparatus/device, particularly apparatus of charged-particle beam such as electron microscope, may use the electrode assembly to create an optimized pattern of electrical field within non-cylindrical channel space. When the electrode assembly is used as a beam deflector in a magnetic objective lens, the electrical field within the central channel space can be co-optimized with the magnetic field for reducing aberration(s) such as distortion, field curvature, astigmatism, and chromatic aberration, after the beam passes through the central channel space.
US11257658B2 Charged particle beam apparatus
An object of the invention is to correct an aberration or a defocus of an electron beam for irradiation, and control an influence on a deflector by a fluctuation in an electric field of an electrostatic lens. The invention provides a charged particle beam apparatus including a deflector that deflects a charged particle beam with which a specimen is irradiated, an objective lens that focuses the charged particle beam on the specimen, an electrostatic lens that includes a part of the objective lens and to which a voltage for correcting the aberration or the defocus of the charged particle beam is applied, and an constant electric field applying electrode that is provided between the deflector and the electrostatic lens and to which a constant voltage having a same sign with the voltage applied to the electrostatic lens is applied.
US11257656B2 Rotating sample holder for random angle sampling in tomography
A sample holder retains a sample and can continuously rotate the sample in a single direction while the sample is exposed to a charged particle beam (CPB) or other radiation source. Typically, the CPB is strobed to produce a series of CPB images at random or arbitrary angles of rotation. The sample holder can rotate more than one complete revolution of the sample. The CPB images are used in tomographic reconstruction, and in some cases, relative rotation angles are used in the reconstruction, without input of an absolute rotation angle.
US11257647B1 Electromagnetic relay
An electromagnetic relay includes a casing, a coil set, a rotating bridge, first and second extension arm, first and second switch conductive plate assemblies, and first and second gripper modules. The novel design of the rotating bridge allows the first and second switch conductive plate assemblies to have synchronous contact or disconnection and provide sufficient and appropriate force to a first movable contact and a first fixed contact of the first switch conductive plate assembly and a second movable contact and a second fixed contact of the second switch conductive plate assembly to achieve a stable conduction and ensure a reliable separation for a disconnection, so as to achieve the effects of reducing the excessive change of resistance during operation, preventing high temperature caused by incomplete contacts, and improve application performance.
US11257645B2 Relay drive with power supply economizer
Provided are embodiments for a circuit for a relay drive with a power supply economizer. The circuit includes a relay having a relay coil and a relay contact. The circuit also includes a power source to generate power for a coil drive voltage to operate the relay, and a controller configured to provide a command signal to operate the circuit in a plurality of modes. The circuit includes a first gate drive coupled to a first switch, wherein the first switch connects the relay coil to the circuit, and a second gate drive coupled to a second switch, wherein the second switch changes an effective resistance of a resistor network of the circuit to modify the coil drive voltage. Also provided are embodiments for a method for operating a circuit including relay drive with a power supply economizer.
US11257644B2 Switch system
A switch system includes a system main relay, a temperature measuring unit, and a controller. The system main relay is configured to electrically connect a battery and an onboard device to each other by turning on a contact point, and to electrically disconnect the battery and the onboard device by turning off the contact point. The temperature measuring unit is configured to measure temperature of the contact point of the system main relay. The controller is configured to cause the system main relay to repeatedly turn on and off the contact point at a predetermined timing, (i) when the temperature of the contact point of the system main relay is a predetermined temperature or more or (ii) when an amount of rise in the temperature of the contact point is a predetermined amount or more.
US11257638B2 Key structure
A key structure includes a bottom plate, a keycap, a lifting mechanism, a thin-film switch layer and a backlight module. The bottom plate has a through hole. The lifting mechanism is pivotally connected to the bottom plate and the keycap. The thin-film switch layer has a reflective structure corresponding to the through hole. The backlight module includes a light source and a reflective layer. The light source is configured to emit light towards the reflective structure. The reflective layer is disposed surrounding the light source to reflect a reflected light from the reflective structure to the thin-film switch layer.
US11257635B2 Key module for a keyboard, and keyboard
What is presented is a key module for a keyboard. The key module includes a first wing element and a second wing element for guiding a movement of the key module upon actuation. Each wing element includes a bar, a first arm and a second arm. The arms extend away from the bar. A mounting portion is formed on the bar. A first bearing portion for bearing the wing element is formed on the first arm. A second bearing portion for bearing the wing element is formed on the second arm. The first wing element and the second wing element are mechanically coupleable to each other. The key module also includes at least one spring element for providing a reset force upon actuation of the key module. The at least one spring element is mountable to the mounting portion of the first wing element and the mounting portion of the second wing element. The key module further includes a support element for supporting the wing elements. A plurality of accommodating portions for accommodating the bearing portions of the wing elements are formed in the support element.
US11257633B2 Power contact health assessor apparatus and method
A power contact health assessor system includes a pair of terminals adapted to be connected to a set of switchable contact electrodes of a power contact and a contact separation detector configured to determine a time of separation of the set of switchable contact electrodes during deactivation of the power contact. The system includes a controller circuit operatively coupled to the pair of terminals and the contact separation detector. The controller circuit is configured to determine within a first observation window, a plurality of contact stick durations and an average contact stick duration. One or more additional observation windows with corresponding average contact stick durations are configured. A health assessment for the set of switchable contact electrodes may be based on a subsequent contact stick duration for a contact cycle after the first observation window and the corresponding average contact stick durations for the one or more additional observation windows.
US11257631B2 Material property capacitance sensor
A system may include a controller configured to cause a capacitance probe to subject a material to a first electric signal having a first frequency and determine a first capacitance of the material at the first frequency. The controller is configured to cause the capacitance probe to subject the material to a second electric signal at a second frequency and determine a second capacitance of the material at the second frequency. The material includes at least a first constituent phase and a second constituent phase. The first constituent phase and the second constituent phase have substantially similar dielectric constants at the first frequency and substantially different dielectric constants at the second frequency. The controller is further configured to determine a porosity of the material based on the first capacitance and determine a relative phase composition of the first constituent phase and the second constituent phase based on the second capacitance.
US11257626B2 Multi-layer ceramic capacitor
A multi-layer ceramic capacitor includes a ceramic body and external electrodes. The ceramic body includes ceramic layers laminated in a first direction, first and second internal electrodes between the ceramic layers, a facing portion in which the internal electrodes face in the first direction, and a cover that covers the facing portion in the first direction. The facing portion includes a first region including at least one element of manganese, a rare-earth element, or magnesium and having a flat distribution of a concentration of the element along the first direction, and a second region disposed between the cover and the first region and having an increasing concentration of the element from the first region toward the cover. The ceramic layers include a capacitance forming layer between the first and second internal electrodes, and a dummy layer between the first or second internal electrodes and across the first and second regions.
US11257625B2 Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a multilayer body in which a plurality of internal electrodes including Ni and a plurality of ceramic dielectric layers are alternately stacked, and external electrodes. The ceramic dielectric layer includes an inner dielectric layer located between internal electrodes, and an outer dielectric layer located outside in a stacking direction and including at least NiO. A difference between average grain sizes of dielectric grains of the outer dielectric layers and the inner dielectric layers is about 10% or less. A molar amount of NiO with respect to about 100 moles of Ti is larger by about 0.6 mole or more in the outer dielectric layer than in the inner dielectric layer.
US11257617B2 Converter for vehicle
A converter for a vehicle including an inductor which includes at least one coil, a core including a first region having an annular planar shape, around which the at least one coil is wound, and a second region having at least one first through-hole, a case accommodating the at least one coil and the core and including at least one cooling rod inserted into the at least one first through-hole, and a fixing bolt fastened to the at least one cooling rod exposed through the at least one first through-hole to fix the core to the case.
US11257616B2 Power conversion device and high-voltage noise filter
A high-voltage noise filter of a power conversion device includes: a metal housing; an anode bus bar connecting anodes of a power source and a power module; a cathode bus bar connecting cathodes thereof; a first magnetic core having a through hole where the anode bus bar and the cathode bus bar pass through; an X capacitor having one end connected to the anode bus bar, and the other end connected to the cathode bus bar; a first Y capacitor having one end connected to the anode bus bar, and the other end grounded; a second Y capacitor having one end connected to the cathode bus bar, and the other end grounded; and a first cooling unit connected to the first magnetic core and the metal housing. The anode bus bar partly faces the first cooling unit, and the cathode bus bar partly faces the first cooling unit.
US11257613B2 Spin orbit torque (SOT) memory devices with enhanced tunnel magnetoresistance ratio and their methods of fabrication
A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit torque material, where the SOT material includes iridium and manganese and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet structure electrode, a fixed layer and a tunnel barrier between the free layer and the fixed layer and a SAF structure above the fixed layer. The Ir—Mn SOT material and the free magnet have an in-plane magnetic exchange bias.
US11257611B2 Superconducting wire rod and superconducting coil
A superconducting wire rod according to an aspect of the present disclosure is a superconducting wire rod having a flat cross-sectional shape which is characterized in that a voltage is generated with a lower current density or a higher voltage is generated with the same current density in a region on at least one end side in a wire rod width direction as compared with a region other than the region on the at least one end side.
US11257607B2 Electric cable with improved temperature ageing resistance
An electric cable has at least one semi-conductive layer obtained from a polymer composition having at least one polypropylene-based thermoplastic polymer material, at least one first antioxidant and at least one metal deactivator.
US11257600B2 Sodium-cesium vapor trap system and method
Sodium-cesium trap systems and methods for the simultaneous removal of both sodium (Na) and cesium (Cs) in gas are provided. The trap system includes a contacting vessel having an inlet and an outlet with carrier gas channeled therethrough. A heating system maintains a temperature gradient across the contacting vessel between a first temperature at the inlet and a second temperature at the outlet such that sodium and cesium contained within the carrier gas are condensed into liquid and the carrier gas exiting the vessel is substantially free of sodium and cesium.
US11257598B2 Positioning and inspection apparatuses for use in nuclear reactors
Systems are provided for inspection and tooling submerged in nuclear reactors. Systems mount at the reactor edge, such as on a steam dam, to be independently operable from a refueling bridge or refueling operations. A moveable steam dam clamp may hold a position apparatus at the edge. The positioning apparatus includes a rotatable shoulder and arms move a tool, reactor component, and/or inspection device like a camera or VARD to desired and highly-determinable reactor positions. A float may counter shear and rotation on the shoulder from the arms. Motors at the shoulder with internal transmissions may rotate the shoulder and arms, or manual rotation may be used. The arms may also overlap vertically for installation and removal. Power, controls, and/or data may be provided underwater through an umbilical connection to operators.
US11257594B1 System and method for biomarker-outcome prediction and medical literature exploration
A system and method for biomarker-outcome prediction and medical literature exploration which utilizes a data platform to analyze, optimize, and explore the knowledge contained in or derived from clinical trials. The system utilizes a knowledge graph and data analysis engine capabilities of the data platform. The knowledge graph may be used to link biomarkers with molecules, proteins, and genetic data to provide insight into the relationship between biomarkers, outcomes, and adverse events. The system uses natural language processing techniques on a large corpus of medical literature to perform advanced text mining to identify biomarkers associated with adverse events and to curate a comprehensive profile of biomarker-outcome associations. These associations may then be ranked to identify the most-common biomarker-outcome association pairs. Having a comprehensive profile of ranked biomarker-outcome data allows the system to predict biomarkers associated with a given disease and serious adverse events linked to biomarker data.
US11257591B2 Transdermal optical detection of cardiac biomarkers
As described herein, a system includes an optical sensor, and a controller that detects progression of obstructive coronary artery disease using a sensor signal from the optical sensor. For example, the system is used for detecting an occlusion in a cardiovascular system of a user. A computer-implemented method for detecting the occlusion includes generating a light within a predetermined spectral range, the light directed towards a reflective element at a predetermined angle. The method further includes receiving a reflected light caused by a reflection of the light off of a reflecting element that is in contact with the user's epidermis. The method further includes detecting a concentration of a predetermined biomarker in a biofluid in the cardiovascular system based on variations in amplitude of the reflected light. The method further includes determining an occlusion in the cardiovascular system based on the concentration of the predetermined biomarker.
US11257587B1 Computer-based systems, improved computing components and/or improved computing objects configured for real time actionable data transformations to administer healthcare facilities and methods of use thereof
Embodiments of systems and methods of the present disclosure include a database layer queries patient-related raw data from data tables of distinct data collection services, normalizes the patient-related raw data to produce common format normalized patient-related data, and stores the common format normalized patient-related data. An algorithmic processing layer, in real-time, analyzes the common format normalized patient-related data based on patient-related data metrics, a healthcare facility-related data metrics, or both, to determine patient-related data points, where each patient-related data point is associated with a respective threshold condition and a respective ranking score, ranks the patient-related data points based on the threshold condition and the ranking score to determine a priority, and generates actionable medical directives related to patients, where the actionable medical directives cause real-time operational changes in the way that the healthcare facility services the patients. And a visualization layer presents, in real-time, the actionable medical directives.
US11257583B2 Systems and methods for assisting individuals in a behavioral-change program
Methods and systems of enhancing an electronic interaction between a behavioral-modification program and a user in the program by providing customized content specific to the user. The systems and methods allow for coach-counselor assistance to the individual-user or for automated content delivery.
US11257582B2 Methods and apparatus for virtual competition
A system configured to be coupled with a participant of an activity. The system comprises: a participant activity monitoring unit configured for monitoring a performance of the activity by the participant; an activity information module configured for storing performance information corresponding to the activity; and a participant performance correlator configured for delivering comparative performance data based on the monitored performance of the activity by the participant and the stored performance information.
US11257581B2 System and method for computerized visual display of user compliance with a care plan
A display having different segments that correspond to different categories of a care plan for a user may be provided. A dimension for the display segment is determined. The dimension indicates a relative importance of a care plan category that corresponds to the display segment compared to other care plan categories. A brightness is determined for the display segment based on the user's compliance with the care for the care plan category that corresponds to the display segment. The display segment is overlaid over at least a portion of a user-selected image for the display segment. A configuration of the overlay is based on the determined dimension and the determined brightness.
US11257572B1 Remote medical treatment application and operating platform
A user may require medical attention based on one or more preferences, present insurance policies, and other relevant factors. The user may also desire to participate in an audio and/or video medicine treatment option across a network. One example method may identifying an upcoming appointment time for a live medical treatment session stored in a calendar entry, creating a communication session hosted by a server, transmitting a first invitation message to a medical professional device associated with a medical professional identified in the calendar entry, transmitting a second invitation message to a user device associated with a patient identified in the calendar entry, and responsive to receiving a response message from the medical professional device, retrieving a patient profile record associated with the patient and populating a user interface of the medical professional device with patient history information stored in the patient profile record.
US11257571B2 Identifying implied criteria in clinical trials using machine learning techniques
A method and apparatus for identifying implied criteria for a clinical trial is disclosed. An example method generally includes generating a training data set from a corpus of clinical trial specifications. The training data set may include at least a first sample corresponding to a first trial. The first sample may include a first feature based on one or more explicitly stated trial criteria, a second feature based on metadata describing the first trial, and a third feature based on patient data of patients associated with the first trial. A machine learning model is trained, using a supervised learning approach, based on the training data set. A system processes a second trial as an input to the trained machine learning model to determine one or more implied criteria that are not explicitly enumerated in a specification for the second trial.
US11257569B1 Methods of assessing risk of developing a severe response to coronavirus infection
The present disclosure relates to methods and systems for assessing the risk of a human subject developing a severe response to a Coronavirus infection, such as a severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) virus infection.
US11257565B2 Management of test resources to perform testing of memory components under different temperature conditions
Filter information including a first temperature level and a second temperature level associated with a test process to be executed on one or more memory components is determined. Information associated with the test process is distributed to a first test component including a first set of memory components and a first temperature control component and a second test component including a second set of memory components and a second temperature control component. First feedback information associated with execution of the test process by the first test component at the first temperature level established by the first temperature control component is received. Second feedback information associated with execution of the test process by the second test component at the second temperature level established by the second temperature control component is received. Based on at least one of the first feedback information or the second feedback information, a failure of the test process executed using at least one of the first temperature level or the second temperature level is determined.
US11257549B2 Sequential voltage control for a memory device
Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.
US11257546B2 Reading of soft bits and hard bits from memory cells
A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.
US11257545B2 Method of programming memory device and related memory device
In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.
US11257541B2 Memory system and memory device
According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
US11257534B2 Current monitor for a memory device
Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.
US11257529B2 Apparatuses and methods for DRAM wordline control with reverse temperature coefficient delay
Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.
US11257526B2 Sector-aligned memory accessible to programmable logic fabric of programmable logic device
An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.
US11257525B1 Data storage device predicting failure of near field transducer based on slope of thermal gradient
A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a laser and a near field transducer (NFT). A thermal gradient produced in the magnetic media by the NFT is periodically measured, and a failure of the NFT is predicted based on a slope of the thermal gradient measurements.
US11257520B1 Variable hard disc drive idle spindle speeds within a disc array
A data storage rack may only have a subset of the HDDs therein operating in an active mode where read/write operations may be performed. Other HDDs may operate in an idle mode, which is a power-saving state that permits the HDDs to quickly change-over to the active mode, when needed. In storage racks containing numerous HDDs, a majority of the HDDs may be operated at idle mode for a majority of the time. Where a large number of HDDs are operated at idle mode, a fixed common idle speed shared by the numerous HDDs can cause unwanted excitation, vibration, and resonance. This can yield increased wear on rack components, decreased performance from the HDDs therein, and increased noise. Variable HDD idle spindle speeds mitigate the foregoing, which is caused by an idle spindle speed previously common to many, if not all HDDs within the data storage rack.
US11257517B1 Data storage device seeking multiple actuators to improve performance
A data storage device is disclosed comprising a plurality of disk surfaces, a first plurality of heads actuated over a first subset of the disk surfaces by a first actuator, and a second plurality of heads actuated over a second subset of the disk surfaces by a second actuator. A first access command is executed using the first actuator and a second access command is executed using the second actuator. When the first access command finishes before the second access command finishes, a third access command is selected to execute using the first actuator based on a time remaining (To2) to finish the second access command, and at least part of the second access command is executed while concurrently executing at least part of the third access command during To2.
US11257514B2 Magnetic recording devices having negative polarization layer to enhance spin-transfer torque
Aspects of the present disclosure generally relate to a magnetic recording head of a spintronic device, such as a write head of a data storage device, for example a magnetic media drive. In one example, a magnetic recording head includes a main pole, a trailing shield, and a spin torque layer (STL) between the main pole and the trailing shield. The magnetic recording head includes a first layer structure on the main pole, and the first layer structure includes a negative polarization layer. The magnetic recording head also includes a second layer structure disposed on the negative polarization layer and between the negative polarization layer and the STL. The negative polarization layer is an FeCr layer. The second layer structure includes a Cr layer disposed on the FeCr layer, and a Cu layer disposed on the Cr layer and between the Cr layer and the STL.
US11257512B2 Adaptive spatial VAD and time-frequency mask estimation for highly non-stationary noise sources
Systems and methods include a first voice activity detector operable to detect speech in a frame of a multichannel audio input signal and output a speech determination, a constrained minimum variance adaptive filter operable to receive the multichannel audio input signal and the speech determination and minimize a signal variance at the output of the filter, thereby producing an equalized target speech signal, a mask estimator operable to receive the equalized target speech signal and the speech determination and generate a spectral-temporal mask to discriminate a target speech from noise and interference speech, and a second activity voice detector operable to detect voice in a frame of the speech discriminated signal. An audio input sensor array including a plurality of microphones, each microphone generating a channel of the multichannel audio input signal. A sub-band analysis module operable to decompose each of the channels into a plurality of frequency sub-bands.
US11257510B2 Participant-tuned filtering using deep neural network dynamic spectral masking for conversation isolation and security in noisy environments
Isolating and amplifying a conversation between selected participants is provided. A plurality of spectral masks is received. Each spectral mask in the plurality corresponds to a respective participant in a selected group of participants included in a conversation. A composite spectral mask is generated by additive superposition of the plurality of spectral masks. The composite spectral mask is applied to sound captured by a microphone to filter out sounds that do not match the composite spectral mask and amplifying remaining sounds that match the composite spectral mask.
US11257509B2 Techniques for empirical mode decomposition (EMD)-based signal de-noising using statistical properties of intrinsic mode functions (IMFs)
Techniques for EMD-based signal de-noising are disclosed that use statistical characteristics of IMFs to identify information-carrying IMFs for the purposes of partially reconstructing the identified relevant IMFs into a de-noised signal. The present disclosure has identified that the statistical characteristics of IMFs with noise tend to follow a generalized Gaussian distribution (GGD) versus only a Gaussian or Laplace distribution. Accordingly, a framework for relevant IMF selection is disclosed that includes, in part, performing a null hypothesis test against a distribution of each IMF derived from the use of a generalized probability density function (PDF). IMFs that contribute more noise than signal may thus be identified through the null hypothesis test. Conversely, the aspects and embodiments disclosed herein enable the determination of which IMFs have a contribution of more signal than noise. Thus, a signal may be partially reconstructed based on the predominately information-carrying IMFs to result in de-noised output signal.
US11257508B2 Method and apparatus for directional sound
Different embodiments of methods and apparatus to produce audio output signals are disclosed. In one embodiment, an ultrasonic speaker outputting ultrasonic signals can be transformed into first audio output signals, which are directional. A non-ultrasonic speaker can output second audio output signals. The embodiment can be configured to output the first audio output signals or the second audio output signals in a vehicle. Another embodiment can be configured to output the first and the second audio output signals together. Yet another embodiment can be configured to be personalized to hearing characteristics of a user, or to depend on sound level of an environment of the user. One embodiment can include a directional speaker attached to a vehicle, with its output steerable towards a user in the vehicle.
US11257506B2 Decoding device, encoding device, decoding method, and encoding method
A decoding device includes: a separating unit separating first encoded data, a spectrum including a low-band spectrum of audio signals having been encoded, and second encoded data, a high-band spectrum of a higher band having been encoded, based on the first encoded data; a first decoding unit decoding the first encoded data and generating a first decoded spectrum; a first amplitude normalizer dividing amplitude of the first decoded spectrum into sub-bands, normalizing the spectrum of each sub-band by the largest amplitude of the first decoded spectrum within each sub-band, and generating a normalized spectrum; an addition unit adding noise spectrum to the normalized spectrum and generating a noise-added normalized spectrum; a second decoding unit decoding the second encoded data using the noise-added normalized spectrum, and generating a second noise-added spectrum; and a converter performing time-frequency conversion regarding a spectrum coupled based on the first decoded spectrum and second noise-added spectrum.
US11257505B2 Audio encoder, audio decoder and related methods using two-channel processing within an intelligent gap filling framework
An apparatus for generating a decoded two-channel signal includes: an audio processor for decoding an encoded two-channel signal to obtain a first set of first spectral portions; a parametric decoder for providing parametric data for a second set of second spectral portions and a two-channel identification identifying either a first or a second different two-channel representation for the second spectral portions; and a frequency regenerator for regenerating a second spectral portion depending on a first spectral portion of the first set of first spectral portions, the parametric data for the second portion and the two-channel identification for the second portion.
US11257500B2 Emotion-based voice controlled device
Embodiments may process search input for different users based on classifications of information and based on emotional content of search commands from the users. For example, a method may comprise receiving, at a computer system, speech data from a client device, the speech data representing a voice command from a user, obtaining, at the computer system, a plurality of items of content responsive to the voice command by searching for content, determining, at the computer system, at least one class related to the voice command, classifying, at the computer system, each obtained item of content into at least one class, identifying, at the computer system, at least one item of content classified into at least one class related to the voice command, and transmitting, at the computer system, the at least one identified item of content.
US11257497B2 Voice wake-up processing method, apparatus and storage medium
The present disclosure provides a voice wake-up processing method, an apparatus and a storage medium. After acquiring voice wake-up signals collected by audio input devices in at least two audio zones, an electronic device may correct, based on to-be-woken-up audio zones obtained from amplitudes of the voice wake-up signals collected by the audio input devices in the at least two audio zones, a to-be-woken-up audio zone identified using a voice engine, avoiding that audio zones in which a plurality of audio input devices collecting voice wake-up signals produced from a same user are located are all woken up, therefore, it is possible to improve accuracy of a voice wake-up result obtained by the electronic device. Therefore, the present disclosure can solve the technical problem that a vehicle-mounted terminal has low voice wake-up accuracy due to an insufficient degree of sound isolation between audio zones of the vehicle-mounted terminal.
US11257494B1 Interacting with a virtual assistant to coordinate and perform actions
Technologies are disclosed for interacting with a virtual assistant to coordinate, recommend and perform actions. According to some examples, a user may use their voice to interact with a virtual assistant to receive recommendations relating to determining when to perform one or more actions. For example, a user may interact with a virtual assistant to request a recommendation as to when they should leave for the office, leave the office for the day, perform a task, and the like. The recommendation system accesses selected data sources (e.g., calendars, task lists, traffic, transportation schedules, maps, . . . ) to obtain data used in generating the recommendation. In addition, to providing a recommended time, the virtual assistant may also recommend actions to perform. The virtual assistant may also provide notifications to one or more other users that includes information relating to the user leaving.
US11257490B2 Device identification through dialog
Particular embodiments described herein provide for an electronic device that can be configured to receive a verbal command to active a device with an unknown label, derive a probable device and a label for the probable device, activate the probable device, determine that the activated probable device is the same device to be activated by the verbal command, and store the label and a description for the device. In some examples, the label is associated with the description.
US11257482B2 Electronic device and control method
Disclosed are an artificial intelligence (AI) system using a machine learning algorithm such as deep learning, and an application thereof. The present disclosure provides an electronic device comprising: an input unit for receiving content data; a memory for storing information on the content data; an audio output unit for outputting the content data; and a processor, which acquires a plurality of data keywords by analyzing the inputted content data, matches and stores time stamps, of the content data, respectively corresponding to the plurality of acquired keywords, based on a user command being inputted, searches for a data keyword corresponding to the inputted user command among the stored data keywords, and plays the content data based on the time stamp corresponding to the searched data keyword.
US11257477B2 Motor noise masking
A sound synthesis system is provided with a loudspeaker to project sound indicative of synthesized motor sound in response to receiving a synthesized sound (SS) signal, and a processor. The processor is programmed to: estimate motor sound based on a sensor signal indicative of sound present within a passenger compartment; identify a dominant motor harmonic of the motor sound with an amplitude and a frequency; determine an enrichment value of the motor sound; determine if the motor sound is unenriched based on a comparison of the enrichment value to an enrichment threshold value; generate at least one additional motor harmonic with a first frequency that is different than the frequency of the dominant motor harmonic in response to the motor sound being unenriched; and provide the SS signal to the loudspeaker, wherein the SS signal is indicative of the at least one additional motor harmonic.
US11257474B2 Acoustic system and method
An acoustic system is disclosed. The acoustic system includes a number of acoustic panel sections having a variety of acoustic properties. Each acoustic panel section is configured to be mounted on an interior surface of a building and cooperates with the other acoustic panel sections to define a pattern on the interior surface of the building.
US11257472B2 Hydroacoustic device
The invention relates to hydroacoustics and more specifically to hydroacoustic devices comprising, disposed in a single housing, a converter of liquid-medium oscillations and electrical signals, capable of receiving and/or transmitting hydroacoustic signals, the converter being disposed on a board which is connected to a switch cable for providing power and transmitting electrical signals, and may be used as a receiver and/or transmitter of hydroacoustic signals in water. According to the invention, the housing of the to hydroacoustic device is formed by the outer surfaces of the converter and board, and by a protective material which coats all of said surfaces, said material allowing for a transmission of hydroacoustic oscillations and being capable of transitioning from a highly-elastic or viscous-flow state to a solid state. The achieved technical result consists in simplifying the design of the device.
US11257470B1 String instrument with superior tonal qualities
A string instrument is disclosed having a body with an air cavity defined by a top plate, a bottom plate, and one or more ribs, a bass bar being secured to an inside surface of the top plate, the bass bar comprising a layup of a plurality of laminates constructed from western red cedar and comprising particular dimensions and placement on the top plate relative to the length of the instrument body.
US11257468B2 User-mountable extended reality (XR) device
A user-mountable extended reality (XR) device capable of receiving and storing at least one of a plurality of user vision capability profiles. The user-mountable XR device comprises a data processing system configured to process input data representative of an input image to perform a modification of the input image based on performing a selection of a given profile of the at least one of the plurality of user vision capability profiles, thereby generating output data representative of an output image for display by the user-mountable XR device. Also described is a method of controlling such a device.
US11257464B2 User interface for a flashlight mode on an electronic device
An electronic device having a touch-screen display detects a first input on the display while displaying a first user interface on the display. In response to detecting the first input on the display, the device enters a flashlight mode. Entering the flashlight mode includes replacing the first user interface with a first flashlight user interface. The first flashlight user interface has a first total lumen output and a first luminance that is substantially uniform over the display. The device determines whether brightness change criteria are met, and in accordance with a determination that the brightness change criteria are met, displays a second flashlight user interface having a second total lumen output greater than the first total lumen output and a second luminance that is substantially uniform over the display.
US11257457B2 Display device and operation method thereof
A display device operating at high speed is provided.The display device includes a pixel provided with a first memory circuit, a second memory circuit, and a display unit, in which the first memory circuit and the second memory circuit are electrically connected to one electrode of the display unit. The operation of the display device includes a first period of writing first image data to the first memory circuit and writing second image data to the second memory circuit, a second period of supplying a first potential to the first memory circuit, a third period of displaying a first image corresponding to the first image data, a fourth period of setting a potential of the one electrode of the display unit to a second potential, a fifth period of supplying the first potential to the second memory circuit, and a sixth period of displaying a second image corresponding to the second image data.
US11257455B2 Gate drive circuit and display panel
A gate drive circuit and a display panel are provided. The gate drive circuit includes N clock signal lines and a plurality of gate drive units. Each of the gate drive units is connected to at least one of the clock signal lines. Each of the clock signal lines is provided with a capacitance compensation unit, a sum of an area of any one of the clock signal lines and an area of the capacitance compensation unit provided on the same clock signal line is equal to a predetermined area, and N is an integer greater than or equal to 2.
US11257452B2 Touch display device, touch sensing circuit, and driving method
The present disclosure relates to a touch display device, a touch sensing circuit, and a driving method. Further, the present disclosure relates to a touch display device, a touch sensing circuit, and a driving method, in which multiple touch electrodes are grouped into multiple touch electrode groups, and sensing is concurrently performed for each of the multiple touch electrode groups, so that excellent touch sensitivity and a fast touch sensing speed are allowed.
US11257451B2 Display panel and display device
The present application relates to a display panel, including a thin film transistor, a first circuit, and a second circuit. The first circuit includes a first output terminal, a first and a second resistor in series with each other in order, and the first output terminal is configured to output a control voltage to a gate of the thin film transistor. The second circuit includes a third resistor and a compensation control switch in series with each other. When temperature is lower than a preset threshold temperature, the compensation control switch is conductive, and the third resistor is in parallel with the second resistor to increase the control voltage output from the first output terminal to the thin film transistor.
US11257450B2 Display apparatus and method of driving display panel using the same
A display apparatus includes a display panel, a gate driver and a data driver. The display panel is configured to display an image. The gate driver is configured to output a gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The display panel includes a first subpixel row including first subpixels having a first color and a second subpixel row including second subpixels having a second color. A first gate off voltage of a first gate signal applied to the first subpixel row to turn off switching elements of the first subpixel row is different from a second gate off voltage of a second gate signal applied to the second subpixel row to turn off switching elements of the second subpixel row.
US11257446B2 Liquid crystal display device
A plurality of pieces of serial data are supplied to a liquid crystal display device from an outside. An SI signal selection circuit switches processing target data to be captured between one piece of serial data included in the plurality of pieces of serial data and the plurality of pieces of serial data in accordance with a serial data selection signal. The processing target data captured by the SI signal selection circuit is converted into parallel data by a data conversion circuit. In accordance with one clock pulse of a serial clock, serial-parallel conversion processing is performed in parallel on a plurality pieces of serial data.
US11257445B2 Methods for driving electro-optic displays
Methods for driving an electro-optic display having a plurality of display pixels and each of the plurality of display pixels is associated with a display transistor, the method includes applying a first voltage to a transistor associated with a display pixel for a first duration of time to drain remnant voltages from the display pixel, applying a second voltage to the transistor for a second duration of time to stop the draining of remnant voltages from the display pixel, and applying a third voltage to the transistor for a third duration of time to drain remnant voltages from the display pixel.
US11257444B2 Backlight apparatus
A backlight apparatus includes a circuit board, a control board, and a connection cable connecting the above components. A first light source driver and a second light source driver are disposed on the circuit board and are electrically connected to a plurality of first light sources and a plurality of second light sources respectively. A connector is disposed on the circuit board. The first and second light source drivers are individually electrically coupled in series to the connector. The control board outputs electrical power, a first data stream, and a second data stream. The first light source driver controls the first light sources to light individually according to the first data stream. The second light source driver controls the second light sources to light individually according to the second data stream. Thereby, the circuit board can control the operation of the light sources individually.
US11257441B2 Method and device for controlling screen backlight, method and device for setting screen backlight, and multi-screen terminal
Disclosed is a method for controlling screen backlight, the method includes: determining a basic setting value V0, where the basic setting value V0 is a value set for backlight brightness of a first screen and backlight brightness of a second screen; calculating a setting value V1 of the backlight brightness of the first screen and a setting value V2 of the backlight brightness of the second screen respectively based on V0; and adjusting the backlight brightness of the first screen and the backlight brightness of the second screen according to V1 and V2 respectively. Further disclosed are a device for controlling screen backlight, a multi-screen terminal, a storage medium, a method and device for setting screen backlight, and a multi-screen terminal.
US11257439B2 Data transmission method and device, display screen, and display device
The present disclosure relates to a data transmission method and device, a display screen, and a display device, and belongs to the application field of display technology. The method is applicable to a first drive chip in a display device that includes a controller, a plurality of drive chips and a data acquisition apparatus. The first drive chip is one of the plurality of drive chips and connected to the controller and the data acquisition apparatus respectively. The method includes: receiving component-related data acquired by the data acquisition apparatus; and sending backhaul data to the controller, the backhaul data including the component-related data. The present disclosure solves the problem of function singleness of the drive chip. The present disclosure is applicable to drive and control the display device.
US11257435B2 Display apparatus and method of driving display panel using the same
A display apparatus includes a display panel, a gate driver, a data driver, and a driving controller. The display panel displays an image based on input image data. The gate driver outputs a gate signal to the display panel. The data driver outputs a data voltage to the display panel. The driving controller selectively determines a driving mode of the display apparatus between one of a normal driving mode and a low frequency driving mode, and determines a driving frequency of the display panel based on the input image data. The driving controller includes a flicker value storage storing flicker values for grayscale values of the input image data and a data remapper converting the grayscale value of the input image data to decrease a size of a maximum frequency grayscale area corresponding to a maximum driving frequency in the low frequency driving mode.
US11257430B2 Drive method and display device
A drive method according to the disclosure includes a target row determination step of determining a target row to which a target pixel for which a characteristic of at least one of a drive transistor and an electro-optical element is detected belongs, a luminance calculation step of calculating a representative luminance of a pixel in the target row, and a detection determination step of performing a characteristic detection step of detecting monitoring data indicating the characteristic of at least one of the drive transistor and the electro-optical element of the pixel belonging to the target row in a case where the representative luminance is greater than or equal to a threshold, and skipping the characteristic detection step in a case where the representative luminance is less than the threshold.
US11257429B2 Pixel circuit
A pixel circuit including an organic light-emitting element, a switching transistor, a storage capacitor that stores a data signal applied via a data line, a driving transistor that allows a driving current corresponding to the data signal to flow into the organic light-emitting element, an emission control transistor electrically connected to the organic light-emitting element and the driving transistor in series, and sync transistors electrically connected to a bottom metal electrode of the driving transistor. The sync transistors include a first sync transistor electrically connected to a first one selected from a source electrode of the driving transistor, a gate electrode of the driving transistor, the high power voltage, and the low power voltage and a second sync transistor electrically connected to a second one selected from the source electrode of the driving transistor, the gate electrode of the driving transistor, the high power voltage, and the low power voltage.
US11257426B2 Electronic devices with low refresh rate display pixels
A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.
US11257425B2 Display panel and method for manufacturing the same, pixel light emitting compensation method and display apparatus
The present disclosure provides a display panel and a method for manufacturing the same, a pixel light emitting compensation method, and a display apparatus. The display panel comprises a plurality of pixel units arranged in an array, wherein each of the pixel units comprises: an array substrate comprising a pixel driving circuit; a pixel defining layer disposed on a first surface of the array substrate and having a via hole wherein the first surface is far away from a substrate of the array substrate; a light emitting unit disposed in the via hole, wherein the light emitting unit is electrically connected to an output terminal of the pixel driving circuit, so that driving current output by the pixel driving circuit drives the light emitting unit to emit light; and a photoelectric converter configured to receive the light emitted by the light emitting unit.
US11257423B2 Pixel driving circuit and driving method thereof, and display panel
A pixel driving circuit includes a driving control sub-circuit and a driving duration control sub-circuit. The driving control sub-circuit includes a first driving sub-circuit connected to a first node. The driving control sub-circuit is configured to be connected to an element to be driven. The driving control sub-circuit is configured to output a driving signal to drive the element to be driven to operate. The driving duration control sub-circuit includes a second driving sub-circuit connected to a second node. The driving duration control sub-circuit is configured to write a first voltage signal into the second node, write a third voltage signal into the second node, and transmit a second voltage signal to the first node in response to a voltage variation at the second node to stop the first driving sub-circuit from outputting the driving signal, so as to control an operating duration of the element to be driven.
US11257421B2 Display device with single package light emitting diode and driver circuit
Embodiments relate to a display device that includes a control circuit, an array of light emitting diode (LED) zones, and an array of driver circuits that are distributed in the display area. An integrated LED and driver circuit includes one or more LEDs of a LED zone and one or more driver circuits integrated on a substrate in a single package with the LED and driver circuit vertically stacked over a substrate. An addressing scheme configures addresses of the driver circuits using address lines that connect between adjacent driver circuits. Control data is provided to the driver circuits via a power line communication signal that provides both a supply voltage and digital data modulated onto the supply voltage.
US11257420B2 Light-emitting diode display
This disclosure discloses a display including a first carrier, a second carrier, a light-emitting unit, a frame, and a protective layer. The first carrier includes a first electrode and a second electrode. The second carrier is arranged below the first carrier and includes a first connection pad and a second connection pad arranged on a side of the second carrier close to the first carrier. The light-emitting unit is arranged on the first carrier. The frame surrounds the light-emitting unit, and the protective layer covers the light-emitting unit. A distance between the first electrode and the second electrode is smaller than that between the first connection pad and the second connection pad.
US11257418B2 Driving unit and driving method thereof, gate driving circuit and display substrate
The present disclosure provides a driving unit, a driving method thereof, a gate driving circuit, and a display substrate. The driving unit includes: a shift register including a pull-up node, a pull-down node and a driving signal output terminal; and a first output circuit including a first control sub-circuit, a second control sub-circuit, an output sub-circuit, and a first signal output terminal; the first control sub-circuit and the output sub-circuit are coupled at a first node, and the first control sub-circuit, the second control sub-circuit and the output sub-circuit are coupled at a second node.
US11257416B2 Voltage mode pre-emphasis with floating phase
A circuit. In some embodiments, the circuit includes: a drive circuit having an output and including: a pre-emphasis circuit; and an output stage connected to an output of the pre-emphasis circuit. The pre-emphasis circuit may be configured to generate, during a first interval of time, a pre-emphasized signal. The output stage may be configured to produce, at the output of the drive circuit, a constant signal based on the pre-emphasized signal during the first interval of time, and to disconnect the pre-emphasis circuit from the output of the drive circuit during a second interval of time, the second interval of time beginning at the end of the first interval of time.
US11257413B2 Organic light emitting display panel
An OLED panel may include a substrate including a first region and a second region disposed along a first direction. A plurality of first pixels are disposed in the first region on the substrate, the first pixels each having a first area, the first pixels each comprising a first unit pixel, a second unit pixel disposed along a second direction from the first unit pixel, and a transmission portion disposed along the first direction from the first unit pixel and the second unit pixel. A plurality of second pixels are disposed in the second region on the substrate, the second pixels each having a second area less than the first area, the second pixels each comprising a third unit pixel. The first unit pixel, the second unit pixel, and the third unit pixel may have substantially the same shape as each other.
US11257409B1 Gate on array circuit
The present disclosure provides a gate on array (GOA) circuit. Each stages of GOA units of the GOA circuit includes a pull-up control unit, a hand-down unit, a feedback unit, a first pull-up unit, a second pull-up unit, a bootstrap capacitor unit, a pull-down unit, and a pull-down control unit. The bootstrap capacitor and the second pull-up unit of the GOA circuit make the first node have a non-symmetrical waveform. The right part of the waveform is as high as the highest voltage potential of the first node so that the decline time of the scan signal is reduced and the performance of the GOA circuit is improved.
US11257406B2 Aging detection circuit, aging compensation circuit, display panel and aging compensation method
An aging detection circuit, an aging compensation circuit, a display panel, and an aging compensation method are provided. The aging detection circuit includes: a first current mirror circuit, a second current mirror circuit, a voltage converter and an analog-digital converter. An input terminal of the first current mirror circuit is electrically coupled to an initial reference voltage terminal and an anode of a to-be-detected light-emitting diode respectively, and an output terminal of the first current mirror circuit is electrically coupled to an input terminal of the second current mirror circuit. An output terminal of the second current mirror circuit is electrically coupled to an input terminal of the voltage converter.
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