最新美国发明专利第2021-08-03期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US11082312B2	Service chaining segmentation analytics Presented herein are service chaining techniques for selective traffic redirection based on Access Control List (ACL) configurations on switches. Network traffic forwarded along one or more service chains may be monitored on the basis of individual segments of the service chains. In one example, the network traffic forwarded along individual segments may be counted on a per-segment basis.
US11082307B2	E-Line service control A method may include receiving a first message requesting a change associated with an Ethernet service that includes routing data from a user device to a destination device via a first service provider and a second service provider. The method may also include determining, by the first service provider, whether resources are available in a first network associated with the first service provider to fulfill the requested change and determining, by the second service provider, whether resources are available in a second network associated with the second service provider to fulfill the requested change. The method may further include sending a second indicating whether the change is accepted and in response to determining that the change is accepted, automatically implementing the change for the Ethernet service.
US11082305B2	Systems and methods for chaining control-plane virtual functions for ensuring end-to-end quality of service (QoS) of internet services Described are systems and methods for QoS chaining based on control-plane virtual functions for ensuring end-to-end Quality of Service (QoS) of Internet services. The QoS chaining coordinates broadband service delivery via an orchestrated “chain” or Network Service (NS) consisting of control-plane Virtual Network Functions (VNFs) running in the cloud or virtual infrastructure. Separate service elements, network elements, network domains or other service plane or data plane elements or systems have a separate corresponding VNF in the control plane provide monitor and control functions. QoS is ensured End-to-End (E2E) across the chain of VNFs by coordination through the QoS chain or by a coordinating or integrating E2E orchestrator or E2E VNF. The VNFs may be chained, may communicate directly with each other, and may communicate directly with the E2E orchestrator, may communicate with each other through the E2E orchestrator, or may communicate through a shared database.
US11082304B2	Methods, systems, and computer readable media for providing a multi-tenant software-defined wide area network (SD-WAN) node One method occurs at a first network node in a service provider network for providing at least one service to multiple tenants. The method includes generating, using input from an administrator of the service provider network, user configuration information for a first tenant; sending, to the first tenant, at least some of the user configuration information; receiving, from the first tenant, first configuration information for configuring a first conduit for tunneling communications between the service provider network and a first site associated with the first tenant's SD-WAN; configuring, using the first configuration information, the first conduit, wherein the first network node is associated with a plurality of conduits, wherein a second conduit of the plurality of conduits is at least in part configured by a second tenant and not the first tenant; and tunneling, via the first conduit, communications between the service provider network and the first site.
US11082302B2	System and method facilitating reusability of distributed computing pipelines A system and method for facilitating reusability of distributed computing pipelines, initially, captures the distributed computing pipeline designed over a Graphical User Interface (GUI) of a first data processing environment associated with a stream analytics platform. Subsequent to the designing, the distributed computing pipeline may be stored in a repository. The distributed computing pipeline may be stored in a file with a predefined file format pertaining to the stream analytics platform. The system also maintains a repository of different versions of the distributed computing pipeline created by the first and second user. Upon storing the file, the file may be imported in a second data processing environment. After importing the file, the distributed computing pipeline may be populated over the GUI of the second data processing environment, thereby facilitating reusability of the distributed computing pipeline.
US11082301B2	Forecasting computer resources demand An approach for forecasting demand. The approach includes a method that includes receiving one or more variables associated with an event. The method further includes generating, by at least one computing device, a model to forecast future demand based on the one or more variables. The method further includes determining, by the at least one computing device, a load to provision one or more servers to meet the future demand. The load is based on the model.
US11082300B2	Transforming data based on a virtual topology Techniques for transforming data based on a virtual topology are disclosed. A computer network is associated with a physical topology and a virtual topology. A physical topology is a particular arrangement of digital devices. A virtual topology is a description of a particular arrangement of virtual topology entities (VTEs). VTEs of the virtual topology are instantiated on digital devices of the physical topology. A processing component associated with a particular VTE processes data to perform one or more functions of the particular VTE. An emulation component associated with the particular VTE modifies the data to emulate performance of the functions by the particular VTE.
US11082298B2	Controller-based datacenter network bandwidth policy sharing A method of allocating network bandwidth in a network that includes several tenant virtual machines (VMs). The method calculates a first bandwidth reservation for a flow between a source VM and a destination VM that are hosted on two different host machines. The source VM sends packets to a first set of VMs that includes the destination VM. The destination VM receives packets from a second set of VMs that includes the source VM. The method receives a second bandwidth reservation for the flow calculated at the destination. The method sets the bandwidth reservation for the flow as a minimum of the first and second bandwidth reservations.
US11082295B2	Methods and apparatus to implement cloud specific functionality in a cloud agnostic system Methods, apparatus, systems and articles of manufacture are disclosed that implement cloud functionality in a cloud agnostic system. An example apparatus to implement cloud specific functionality in a cloud agnostic system includes a request interpreter to determine whether a first request includes an indication that a cloud resource is to be partially provisioned, a provision determiner to select the cloud resource based on the indication, and a cloud interface to transmit a first resource request to partially provision the cloud resource, and in response to a second request including constraints specific to the cloud resource, transmit a second resource request to fully provision the cloud resource.
US11082291B2	Changing an existing blockchain trust configuration Operating conditions of a blockchain configuration may be dynamic and change automatically under certain circumstances. One example method of operation may include one or more of identifying an existing consensus procedure used in an existing blockchain configuration, identifying current metrics associated with the existing blockchain configuration, comparing the current metrics to predefined rules, identifying one or more deviations based on the current metrics being compared to the predefined rules, and changing the existing consensus procedure to a next consensus procedure for a subsequent block in the existing blockchain configuration responsive to identifying the one or more deviations.
US11082290B2	Method and apparatus for optimizing a software defined network configuration In one example, a method and apparatus for optimizing a software defined network configuration are disclosed. In one example, the method determines a first network relative performance parameter for a current configuration of a network, based on respective weighting profiles associated with services for which the network carries data. The method then determines a second network relative performance parameter for a proposed configuration of the network, based on the respective weighting profiles associated with the services for which the network carries data. The proposed configuration is implemented in the network when the second network relative performance parameter is greater than the first network relative performance parameter.
US11082289B2	Alert intelligence integration An enterprise platform may include a time series database that may include time series data related to a plurality of configuration items associated with an enterprise. The enterprise platform may also include one or more instance data tables having instance data associated with the plurality of configuration items. The enterprise platform may also include an alert interface that may receive an indication of an alert associated with a configuration item of the plurality of configuration items and determine a subset of a plurality of metrics associated with the alert based on the configuration item and the time series data, the instance data, or both. The alert interface may then generate a plurality of visualizations for display via a user interface based on the subset of the plurality of metrics.
US11082288B2	System and method for resolving master node failures within node clusters Fault tolerance techniques for a plurality of nodes executing application thread groups include executing at least a portion of a first application thread group based on a delegation by a first node, wherein the first node delegates an execution of the first application thread group amongst the plurality of nodes and has a highest priority indicated by an ordered priority of the plurality of nodes. A failure of the first node can be identified based on the first node failing to respond to a message sent to it. A second node can then be identified as having a next highest priority indicated by the ordered priority such that the second node can delegate an execution of a second application thread group amongst the plurality of nodes.
US11082284B1	Applying configurations to applications in a multi-server environment System and methods are described for applying a configuration to an application binary image in a multi-server computing environment. The steps include receiving, by a configuration manager in a multi-server computing environment, a request from a client to apply a selected application configuration to a selected application binary image stored on a selected server in the multi-server computing environment, and forwarding, by the configuration manager, the request to an agent executing on the selected server. The steps further include getting, by the agent, the selected application configuration from a repository, the repository storing a plurality of application configurations; and applying, by the agent, the selected application configuration to the selected application binary image.
US11082283B2	Contextual generation of ephemeral networks A method, system, and computer program product for contextual generation of an ephemeral network are provided. The method detects an initiating event for network generation associated with a user of a first computing device. The method determines a duration of the initiating event. A set of network members is determined based on the initiating event and the duration. The method establishes an ephemeral network, connecting at least a portion of computing devices associated with the set of network members. The ephemeral network is terminated in response to detecting a completion event. In response to terminating the ephemeral network, member information for the set of network members is removed from the portion of the computing devices.
US11082281B2	Relay communication method and relay communication device A relay communication device includes a memory and a processor coupled to the memory and configured to: receive data from an application, and determine a relay path of each of a plurality of data received from the application according to a protocol of a disruption tolerant network based on data remaining amount to be relayed to a communication destination in response to receiving of new data of the application and a priority of each of the plurality of data.
US11082275B2	Electrical apparatus and wireless communication method for communication device with multiple antennas An electronic device, and method, at a first communication apparatus having multiple antennas includes a memory for storing computer instructions; and a processing circuit configured to execute the stored computer instructions to: based on channel states of channels between the multiple antennas of the first communication apparatus and a second communication apparatus, determine channel characteristics of a first channel from the first communication apparatus to a second communication apparatus in an angle domain: based on the determined channel characteristics of the first channel in the angle domain, determine a first set of pilot signals used in the angle domain, the pilot signals in the first set of pilot signals being orthogonal to each other; and transform the first set of pilot signals into a second set of pilot signals for transmission over the multiple antennas of the first communication apparatus.
US11082274B2	Preamble symbol generation and receiving method, and frequency-domain symbol generation method and device Provided are a preamble symbol generation method and receiving method, and a relevant frequency-domain symbol generation method and relevant device. The generated preamble symbol contains: a time-domain symbol with a first three-segment structure; or a time-domain symbol with a second three-segment structure; or a free combination of several time-domain symbols with the first three-segment structure and/or several time-domain symbols with the second three-segment structure arranged in any order. Using the entirety or a portion of a certain length of a time-domain main body signal as a prefix, it is possible to perform coherent detection, which solves the issues of performance degradation with non-coherent detection and differential decoding failure under complex frequency selective fading channels, and generating a postfix or hyper prefix based on the truncation of the entirety or a portion of the time-domain main body signal would enable the generated preamble symbol to have sound fractional frequency offset estimation performance and timing synchronization performance.
US11082264B2	Learning in communication systems A method, apparatus and computer program are described includes obtaining or generating a transmitter-training sequence of messages for a first transmitter of a first module of a transmission system, wherein the transmission system includes the first module having the first transmitter and a first receiver, a second module having a second transmitter and a second receiver, and a channel, wherein the first transmitter includes a transmitter algorithm having at least some trainable weights; transmitting a perturbed version of the transmitter-training sequence of messages from the first transmitter to the second receiver over the channel of the transmission system; receiving a first loss function at the first receiver from the second transmitter, wherein the first loss function is based on the transmitted perturbed versions of the transmitter-training sequence of messages as received at the second receiver and knowledge of the transmitter-training sequence of messages for the first transmitter of the transmission system; and training at least some weights of the transmitter algorithm of the first transmitter based on the first loss function.
US11082263B2	Context-based messaging system Socially provided context-based messaging can include receiving a message content in a messaging system from a user, wherein the content includes objects; matching one or more objects of the message content to socially provided context information, which the socially provided context information is information relevant to an object obtained from a social network to which the user belongs; and displaying the socially provided context information with the message content for a recipient user to receive.
US11082249B2	Location determination for device control and configuration Systems and methods for determining locations and configuring controllable devices are provided. Example systems and methods include determining a location estimate for a computing device and capturing image data, by the computing device, of a physical space that includes a controllable device performing an identification action. The example systems and methods may also include identifying the controllable device in the image data based at least in part on the identification action and determining configuration information for the controllable device. The configuration information may be based at least in part on the location estimate for the computing device.
US11082244B2	System and method for enabling service lifecycle based policy, licensing, and charging in a network function virtualization ecosystem Systems and computing devices may be configured to intelligently apply controls in a telecommunication system that implements or uses network slicing and/or virtualized network function technologies. A computing device may be configured to receive a request to instantiate a new network slice from a component in the telecommunication system. The computing device may determine that a virtualized network function (e.g., C-RAN virtual network function, MEC virtual network function, etc.) should be created for the new network slice, and determine whether a policy allows for the creation of the virtualized network function. The computing device may create the virtualized network function if the policy allows for its creation. The server computing device may be a charging and license management (CALM) component.
US11082243B2	Power management device for immediate start-up during power negotiation The present invention relates to an energy management device (40) and a method of operating the same. The energy management device (40) comprising a buffer controller (41) and an energy buffer unit (45) wherein the buffer controller is configured to connect the energy buffer unit (45) to operate a load device upon detecting that the load device is in an accepting operational state and the voltage provided by a power supply device is between the first and second threshold, during a power negotiation period between the power supply device (10) and the load device (20).
US11082242B2	Transistor-based physically unclonable function An integrated circuit is fabricated using a semiconductor fabrication process. One or more uncontrollable random physical processes in the semiconductor fabrication process can cause small differences between the integrated circuit and other similarly designed integrated circuit. These small differences can cause transistors of the integrated circuit to have different threshold voltages. The integrated circuit can use these different threshold voltages to quantify its physical uniqueness to differentiate itself from other integrated circuits similarly designed and fabricated by the semiconductor fabrication process.
US11082240B2	Retrieving public data for blockchain networks using highly available trusted execution environments Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enhancing blockchain network security. Implementations include receiving a request for data from the data source, transmitting the request to a relay system that is external to the blockchain network and that includes a multi-node cluster including a plurality of relay system nodes, receiving a result provided from a relay system node, the result being digitally signed using a private key of the relay system node, verifying that the relay system node is registered, verifying an integrity of the result based on a public key of the relay system node and a digital signature of the result in response to verifying that the relay system node is registered, and transmitting the result to a client in response to verifying the integrity of the result.
US11082239B2	Accelerating transaction deliveries in blockchain networks using transaction resending In a blockchain transaction acceleration system, receive a first transaction sent through a first node in a blockchain. At least one second transaction that is a duplicate of the first transaction is received in the blockchain transaction acceleration system, where the at least one second transaction sent by the first node to at least one second node in the blockchain is different from the first node. The blockchain transaction acceleration system executes a first-received transaction among received transactions that include the first transaction and the at least one second transaction. Upon determining, by the blockchain transaction acceleration system, that remaining transactions of the received transactions are identical to the first-received transaction, discarding the remaining transactions.
US11082234B2	Method and system for privacy-preserving social media advertising A method for operating an aggregator in an electronic commerce system includes receiving ciphertexts and signatures transmitted from multiple clients, each ciphertext encrypting noisy plaintext data of a category of information for a user that purchased a product, generating sums of the ciphertexts and the signatures, verifying the sum of the ciphertexts with a homomorphic signature system based on the sum of the signatures and homomorphic verification data, decrypting the sum of the ciphertexts in a private stream aggregation (PSA) process based on homomorphic decryption data to generate a sum of noisy plaintext data in response to a success of the verification, and identifying aggregate statistical information transmitted from the clients based on the sum of noisy plaintext data while preserving differential privacy of the clients.
US11082231B2	Indirection directories for cryptographic memory protection A processer is provided that includes on-die memory, a protected memory region, and a memory encryption engine (MEE). The MEE includes logic to: receive a request for data in a particular page in the protected region of memory, and access a pointer in an indirection directory, where the pointer is to point to a particular metadata page stored outside the protected region of memory. The particular metadata page includes a first portion of security metadata for use in securing the data of the particular page. The MEE logic is further to access a second portion of the security metadata associated with the particular page from the protected region of memory, and determine authenticity of the data of the particular page based on the first and second portions of the security metadata.
US11082230B2	Performing parallel execution of transactions in a distributed ledger system Disclosed herein are methods, systems, and apparatus for performing parallel execution of transactions in a blockchain network. One method includes receiving multiple transactions; determining whether each transaction is a first-type or a second-type transaction; for a first-type transaction, determining accounts affected by the first-type transaction; for a second-type transaction, pre-executing the second-type transaction; and determining accounts affected by the pre-executing the second-type transaction; performing a consensus process of the multiple transactions and the accounts affected by the pre-executing the second-type transaction; dividing the multiple transactions into groups; executing groups of transactions in parallel; committing the executing each first-type transaction; if the each of the accounts affected by the executing a second-type transaction are the same as accounts affected by the pre-executing of the second-type transaction and the accounts affected by the executing the second-type transaction are not affected by any previously executed transactions, committing the executing the second-type transaction.
US11082220B1	Securing recovery data distributed amongst multiple cloud-based storage services Described is a system for securing recovery information that is distributed amongst multiple cloud-based systems. Encrypted recovery data may be stored on at least one cloud-based system. To decrypt the recovery data, coordination between multiple cloud-based systems may be required to obtain the encryption key. Accordingly, a production system does not have to perform key management. Therefore, even if the production system is compromised by a malicious party, the encryption key remains secure as multiple cloud-based systems would also have to be comprised. In addition, the system may coordinate the creation and distribution of the recovery information, as well as the acquisition of such recovery information as part of a data recovery process. Thus, the system may secure recovery information by leveraging multiple cloud-based systems (or services).
US11082217B1	Session resumption Techniques described herein enhance the durability of cryptographically protected communications sessions. The negotiation of a cryptographically protected communications session results in the negotiation of a primary secret and a secondary secret. The primary secret and secondary secret are stored in separate locations, such as in two locations in RAM, one of which being used as a RAM disk. The primary secret is used to cryptographically protect the communications session. Following the detection of a change of state event, the cryptographically protected communications session switches to the secondary secret in place of the primary secret to cryptographically protect the communications session.
US11082215B2	Immutable broadcasting queues An example operation may include one or more of receiving, by a broadcast server node, data from a plurality of data provider nodes; and executing, by the broadcast server node, a smart contract to: encrypt the data with encryption keys; generate a broadcast queue based on the encrypted data; and assign a subset of consumer nodes authorized to receive the encrypted data of the broadcast queue.
US11082214B2	Key generation apparatus and key update method A key generation apparatus includes a memory, a communication interface, and a processor. The memory stores a first private key corresponding to a first public key. The communication interface communicates with a peer apparatus that stores the first public key. The processor generates a second public key and a second private key in response to a key update request from the peer apparatus, generates a digital signature by encrypting data including the second public key with the first private key, and sends a message including the data and the digital signature to the peer apparatus. In addition, the processor switches the first private key to the second private key.
US11082213B2	Switching authentication and encryption of content between keys based on a key availability assurance value The technologies described herein are generally directed toward facilitating switching encryption keys based on an assurance value. According to an embodiment, a method can comprise receiving, by a device comprising a processor and memory, an assurance value from a key distribution server. The method can further comprise, based on the assurance value, switching, by the device, encryption of a content item from being by a first encryption key to being by a second encryption key, wherein the assurance value is determined in response to a receiving of a second decryption key by a content consuming device, and wherein the first and second decryption keys are generated respectively to decrypt the content item encrypted by the first and second encryption keys.
US11082210B2	Method for sequentially encrypting and decrypting singly linked lists based on double key stream ciphers A method for sequentially encrypting and decrypting singly linked lists based on double key stream ciphers comprises: establishing a plaintext set M according to a plaintext file; using the plaintext set M as an initial value and performing iterative decryption to obtain a ciphertext set C, wherein a key set P and an algorithm set A are used during the iterative decryption; for the ciphertext set C, performing multiple decryptions by calling the key set P and calling keys in the key set P, wherein a key set P and an algorithm set A are used during the decryptions; and, converting the obtained result of decryption into a plaintext file.
US11082205B2	Methods for securing data A method for securely processing data to prevent unauthorized access is provided. The method includes the steps of splitting data into components and with a sequence of a first hashing, a first encryption, a second hashing, a second encryption, and a third hashing, that optimizes the security of the data. The method further provides steps to securely retrieve, update and delete the data once the data has been securely stored.
US11082204B2	Method and system for partitioned blockchains and enhanced privacy for permissioned blockchains A method for generation of blocks for a partitioned blockchain includes: storing blocks comprising a partitioned blockchain, wherein each block includes a header and transaction entries; receiving transaction data entries for each of a plurality of subnets; generating a hash value of the header included in the most recently added block; generating a new block header, the new block header including the generated hash value, a timestamp, and a sequence of pairs including a pair for each of the plurality of subnets, each pair including a subnet identifier associated with the respective subnet and a merkle root of each of the transaction data entries received for the respective subnet; generating a new block, the new block including the generated new block header and the transaction data entries for each of the plurality of subnets; and transmitting the new block to a plurality of nodes associated with the partitioned blockchain.
US11082200B2	Clock data recovery apparatus and method A clock and data recovery apparatus is provided that includes a sampling circuit, a storage circuit and a determining circuit. The sampling circuit includes sampling units each sampling a received data according to one of reference clock signals to generate a sampling result. The storage circuit includes FIFO storage units configured to store the sampling result of the received data corresponding to different time spots. The determining circuit is configured to set a certain number of received data as a reference data pattern, to adjust a starting position of a sampling window according to a transition point of sampled values within the reference data pattern when only one data transition exists therein and adjust a length of the sampling window according to an amount of high state sample points of the sampled values within the reference data pattern when more than one data transitions exist therein.
US11082199B2	Data transmission method in optical network and optical network device This application provides a data transmission method in an optical network and an optical network device. The method includes: obtaining, by a first device, first synchronization information from a first service data stream, and determining a to-be-transmitted service data stream; generating second synchronization information based on the first synchronization information; mapping the second synchronization information and the to-be-transmitted service data stream to an optical carrier container; and sending the optical carrier container. A second device receives the optical carrier container; obtains a second service data stream and third synchronization information from the optical carrier container through demapping; generates fourth synchronization information based on the third synchronization information; and inserts the fourth synchronization information into the second service data stream, to obtain a third service data stream. In this way, time synchronization precision is improved.
US11082198B2	Bi-directional transceiver with time synchronization An optoelectronic module may include an optical receiver optically coupled with an optical fiber. The optical receiver may be configured to receive time synchronization signals from the optical fiber. The time synchronization signals may be frequency modulated, wavelength modulated, or amplitude modulated and may be received along with received data signals. A time synchronization signal detection module may be communicatively coupled to the optical receiver. The time synchronization signal detection module may be configured to receive the time synchronization signals that are transmitted through the optical fiber and detect frequency modulations, wavelength modulations, or amplitude modulations to recover the time synchronization signals.
US11082196B2	Resource allocating method in wireless network and wireless communication device using the same A resource allocating method in a wireless network performed by a first device positioned in a wireless communication network and connected to one or more second devices to constitute a fully connected link includes receiving network information from the wireless communication network, receiving information about a transmission scheme to be used for communication between the first device and the second device from the network information, obtaining information about the second device and an index of the first device, and allocating resources to be used for a communication between the first device and the one or more second devices using information related to at least one of the transmission scheme, the information about the second device, and the index of the first device.
US11082190B2	CQI measurement method, apparatus, and wireless communications system Embodiments of the present invention relate to the communications field, and provide a CQI measurement method, an apparatus, and a wireless communications system, to improve accuracy of downlink CQI measurement performed by UE. The CQI measurement method includes: determining, by a base station, a downlink CQI measurement resource, where the downlink CQI measurement resource is for use by a first UE to perform downlink CQI measurement, the downlink CQI measurement resource includes a frequency domain resource, and a bandwidth of the frequency domain resource is less than a system bandwidth; and sending, by the base station, resource indication information to the first UE, where the resource indication information is used to indicate the downlink CQI measurement resource.
US11082187B2	Rate-matching for single downlink control information multi-transmission reception point transmissions Certain aspects of the present disclosure provide techniques for rate-matching data on a per transmission reception point (TRP) basis for single downlink control information (DCI) multi-TRP transmissions. Transmitters operating according to the present disclosure use a per TRP rate matching technique in which the rate-matching order is to first rate-match across spatial layers transmitted by a TRP, then across frequency, then across time, and then to another TRP, where remaining data is rate-matched across the spatial layers of that other TRP, then across frequency, and then across time. The described per TRP rate-matching technique causes code blocks of a transport block to be transmitted by one TRP, instead of each code block being transmitted by a group of TRPs.
US11082185B2	Method of transmitting scheduling request in a wireless communication system A method and apparatus for requesting uplink resources in a wireless communication system is provided. A user equipment determines whether a scheduling request for requesting uplink resources is triggered. If the scheduling request is triggered, the user equipment transmits a first set of frequency domain sequences and a second set of frequency domain sequences in a subframe.
US11082184B2	Method and device for indicating reference signal Embodiments of this application provide a data transmission method and a device. The method includes: obtaining, by a terminal, first indication information or second indication information, where the first indication information is used to indicate that a reference signal is carried in a resource unit, and the second indication information is used to indicate that no reference signal is carried in a resource unit; and performing, by the terminal, data transmission according to the first indication information or the second indication information. The reference signal can be properly configured in the embodiments.
US11082181B2	System and method for orthogonal frequency division multiple access communications A method for operating a communications device adapted for orthogonal frequency division multiple access (OFDMA) wireless local area network (WLAN) communications includes generating an OFDMA preamble comprising an OFDMA signal (SIG) field including an indication of an allocation of an OFDMA resource to a station, and transmitting the OFDMA preamble in a frame.
US11082176B2	System and method for transmitting a sub-space selection Embodiments of this disclosure provide techniques for receiving reference signals by a user equipment (UE) from a base station in a downlink channel, as well as transmitting a linear combination index from the UE to the base station. In particular, the linear combination index identifies a combination of beams selected from a set of beams in accordance with the RS.
US11082170B2	Method for transmitting and receiving data in wireless communication system supporting short transmission time interval and apparatus therefor Disclosed are a method for transmitting and receiving data in a wireless communication system supporting a short transmission time interval (TTI) and an apparatus therefor. Specifically, the method may comprise the steps of: receiving a downlink control channel for which a first TTI is configured; and transmitting a specific uplink channel for which a second TTI is configured, on the basis of the received downlink control channel, wherein the first TTI and the second TTI are configured to have different lengths, the specific uplink channel is transmitted through a subframe after a specific processing time from the end point of a resource region allocated to the downlink control channel, and the specific processing time is set according to at least one of a first processing time for the downlink control channel and a second processing time for the specific uplink control channel.
US11082167B2	Triggered transmission opportunity and multiple user ACK procedures in WLAN systems Methods and systems for negotiating an ACK policy between a STA and an AP operating in a LAN are provided. Transmission of a modified ULR frame from a STA to an AP is provided. The ULR frame may include information related to a traffic stream for which the STA is requesting one or more transmission opportunities. The related information may include a determined priority associated with the traffic stream and a requested ACK type. The transmission opportunity may be one or more of a single user transmission opportunity, part of a multi-user transmission opportunity, or a peer-to-peer transmission opportunity.
US11082164B2	Data transmission method, terminal device, and network device Embodiments of this application provide a data transmission method, a terminal device, and a network device. The method includes: receiving, by a terminal device, a first indication sent by a network device; receiving, by the terminal device, downlink data based on the first indication, and generating feedback information of the downlink data; receiving, by the terminal device, a second indication sent by the network device, where the second indication indicates a start location of an uplink time unit; determining, by the terminal device based on the first indication and the second indication, a resource location for sending the feedback information; and sending, by the terminal device, the feedback information at the resource location.
US11082163B2	Wireless communication device, network node and methods for handling data transmissions Embodiments herein relate to a method implemented by a wireless communication device. The wireless communication device transmits data to a radio node of a wireless communication network. The wireless communication device monitors for a positive acknowledgement or a negative acknowledgement of the data from the radio node. The wireless communication device retransmits the data to the radio node when said monitoring indicates reception of a negative acknowledgement of the data. The wireless communication device refrains from retransmitting the data to the radio node when said monitoring indicates reception of a positive acknowledgement of the data. The wireless communication device also refrains from retransmitting the data to the radio node when said monitoring indicates neither reception of a positive acknowledgement of the data nor reception of a negative acknowledgement of the data.
US11082154B2	Method by which terminal monitors control channel in wireless communication system, and terminal using method A method by which a terminal monitors a control channel in a wireless communication system, and a device using the method are provided. The method determines whether physical downlink control channel (PDCCH) monitoring occasions overlap in a plurality of control resource sets (CORESETs), selects at least one CORESET from among the plurality of CORESETs when the PDCCH monitoring occasions overlap, and monitors a PDCCH only in the selected at least one CORESET from among the plurality of CORESETs.
US11082151B2	Electronic device and coverage compensation method thereof for short range communication An electronic device and communication coverage compensation method thereof for use in short range communication. An electronic device includes a housing, a radio communication circuit arranged in the housing and configured to support radio communication with a neighboring electronic device, a processor arranged in the housing and electrically connected to the radio communication circuit, a memory arranged in the housing and electrically connected to the processor, the memory storing instructions that, when cited by the processor, cause the processor to communicate with the neighboring electronic device with the radio communication circuit, change, when detecting an event triggering a change from a first symbol rate to a second symbol rate, from the first symbol rate to the second symbol rate, determine a compensation value based on a coverage range, and adjust a transmit power of the radio communication circuit based on the compensation value.
US11082147B2	Processing method, device and system for overlap multiplexing system Provided are a processing method, device, and system for an overlapped multiplexing system. The method includes: receiving encoded information output by a transmit end, where the encoded information is information obtained by performing error-correcting code encoding and overlapped multiplexing encoding on input information; decoding the encoded information according to an overlapped multiplexing decoding algorithm, to obtain a first decoding result; performing error-correcting processing on the first decoding result according to an error-correcting code decoding algorithm, to obtain a second decoding result; and outputting the second decoding result.
US11082139B2	Mobile radio testing device and method for protocol testing A mobile radio testing device for protocol testing of a device under test is provided. The mobile radio testing device comprises a downlink path and an uplink path, wherein the uplink path comprises at least a first analysis mode and a second analysis mode. In this context, the mobile radio testing device includes a demodulation processing unit for analyzing signals from the device under test in the first analysis mode. In addition, the second analysis mode analyzes signals from the device under test without using the demodulation processing unit.
US11082132B1	Optoelectronic systems and methods for inspection of optically encoded data A system can include at least one optical encoder section configured to transform a first optical signal carrying first data into a second optical signal carrying the first data and an additional optical feature not present in the first optical signal; at least one optical modulator configured to optically modulate the second optical signal according to a compare data to generate an optical match signal that indicates matches between the compare data and the first data; and at least one photodetector configured to generate an electrical match signal in response to the optical match signal; wherein the optical match signal has at least first values when the first data matches the compare data, and at least second values when the first data does not match the compare data. Corresponding methods are also disclosed.
US11082131B2	Optical signal transmission system and optical signal transmission method Embodiments of the present invention disclose an optical signal transmission system and an optical signal transmission method. A specific solution is as follows: a first coherent transceiver is configured to: convert N channels of downlink data into N modulating signals, convert the N modulating signals into a first wavelength division multiplexing signal, and send the first wavelength division multiplexing signal to an optical transport unit; the optical transport unit is configured to: receive the first wavelength division multiplexing signal, convert the first wavelength division multiplexing signal into N second optical signals, and correspondingly send the N second optical signals to N second coherent transceivers; and one of the N second coherent transceivers is configured to: receive the N second optical signals, and process the N second optical signals to obtain information in downlink data carried in the N second optical signals.
US11082130B2	System for managing a fibre-optic ethernet network of a vehicle The invention relates to a system for managing (1) a communication network (W) of a vehicle, said management system (1) comprising a plurality of computers (10, 20) connected to said network (W), and a two-way wired link (L) connecting said plurality of computers (10, 20), said network (W) having a standby state and an awake state, said plurality of computers (10, 20) comprising a master computer (10) and at least one slave computer (20), said master computer (10) and said at least one slave computer (20) being configured to emit and receive a message relative to a requested state of the network (W) via said two-way wired link (L), the state of at least one of the plurality of computers (10, 20) being controlled from said message relative to the requested state, so as to monitor the state of the network (W), said communication network (W) being a fiber-optic Ethernet network.
US11082124B2	Passive collection of air-to-ground network parameters for network planning and control A network analytics control module may include processing circuitry configured to receive three dimensional location information and corresponding signal quality information for a particular asset in an air-to-ground (ATG) network, make a service quality inference for the particular asset based at least in part on the received information, and provide an instruction for a network control activity based on the service quality inference.
US11082118B2	Methods for assisting in beam sweeping, tracking and recovery Certain aspects of the present disclosure provide various appropriate frame structures, sweep sequences, and procedures that may assist in beam sweeping, tracking and recovery.
US11082116B1	Method and apparatus for handling beam failure recovery regarding medium access control reset in a wireless communication system A method and device are disclosed from the perspective of a User Equipment (UE). In one embodiment, the method includes the UE triggering a Beam Failure Recovery (BFR) associated with a cell. The method also includes the UE triggering a Scheduling Request (SR) for Secondary Cell (SCell) beam failure recovery in response to the triggered BFR. The method further includes the UE cancelling the triggered BFR and the triggered SR in response to reset of a Medium Access Control (MAC) entity associated with the cell.
US11082115B2	Beam management using adaptive learning Certain aspects of the present disclosure provide techniques for beam management using adaptive learning. Certain aspects provide a method that can be performed by a node, such as user equipment (UE) or a base station (BS). The node determines one or more beams to utilize for a beam management procedure using adaptive learning. The node performs the beam management procedure using the determined one or more beams. In some aspects, the node uses an adaptive reinforcement learning algorithm to select beams for measurement in beam discovery procedure. The node may adaptive the beam management algorithm based on feedback associated with the beam selection, such as based on a throughput achieved using a beam pairing determined during the beam management procedure.
US11082113B2	Method for performing training for signal beamforming in wireless LAN system, and device for same Presented in the present specification are a method whereby a station performs beamforming training in a wireless LAN (WLAN) system, and a device for same. In particular, presented in the present specification are a method whereby a station performs beamforming training for frequency division multiple access (FDMA) transmission, and a device for same. The method according to the present specification comprises the steps of: transmitting a beamforming setup frame including beamforming training operation information and identification information on one or more second stations corresponding to one FDMA group; performing FDMA beamforming training by using multiple transmission sectors simultaneously on the basis of the beamforming training operation information; receiving a feedback result of the performed FDMA beamforming training from the one or more second stations; and transmitting a selection frame including channel allocation information for each station and FDMA transmission configuration information determined on the basis of the received feedback result.
US11082112B2	Base station and reception method for receiving repetition signals using a channel format that accommodates SRS transmission A repeater generates repetition signals by repeating an uplink signal over a plurality of subframes. If the plurality of subframes do not include a transmission candidate subframe of a sounding reference signal used to measure uplink reception quality, a controller sets a first transmission format to all the plurality of subframes, and if the plurality of subframes include the transmission candidate subframe, the controller sets a second transmission format to all the plurality of subframes. A transmitter transmits the repetition signals using the set transmission format.
US11082106B2	Information processing method and device, and storage medium The present invention provides an information processing method, comprising: generating signaling comprising configuration information of channel state information process (CSI process); and sending the signaling comprising the configuration information of the CSI process. The present invention resolves the problem in the related art of being unable to use one CSI-RS resource overhead to meet the transmission requirements of multiple CSI-RSs having different port numbers, thereby achieving the technical effect of reducing resource overheads. The present invention also provides an information processing device and a storage medium.
US11082105B2	RLM monitoring using signaled dynamic parameter In order to provide a more robust RLM procedure for 5G/NR, a base station may provide a dynamic relationship between a PDCCH and another reference signal (e.g., SS/CSI-RS) to a UE. For example, an apparatus may receive an adjustment parameter regarding a PDCCH from a base station. The adjustment parameter may comprise a relationship between the PDCCH and the at least one of the SS or the CSI-RS for deriving a radio link quality of a hypothetical PDCCH. The apparatus may receive an SS/CSI-RS that is QCL with the PDCCH and perform a radio link measurement based on the received at least one of the SS or the CSI-RS using the adjustment parameter regarding the PDCCH. Among other relationships/offsets, the adjustment parameter may indicate a TPR difference, a beamforming gain difference, a beam width difference, a beam orientation difference.
US11082093B2	Communication apparatus, method of controlling the same, and storage medium A communication apparatus includes communication means for performing radio communication with a partner apparatus, and supply means for wirelessly supplying power to the partner apparatus. The communication apparatus acquires information on a communication circuit for radio communication in the partner apparatus, and controls the supply means so as to determine an amount of power to be supplied per unit time depending on the information.
US11082089B2	Single-ended vectored DSL system As fiber networks are extended closer to the subscriber, 5G small cell, multi-dwelling units, and office buildings, in some applications Digital Subscriber Line (DSL) becomes an extension for the fiber network over the last 100 to 300 meters of twisted wire-pair telephone lines. Utilizing techniques such as bonding of coterminous twisted wire-pairs, increasing the bandwidth into the VHF spectrum, emerging 5th generation DSL technology is poised to deliver aggregate bandwidth approaching 10 Gb/s. Underpinning the capability to reach these speeds over twisted wire-pair, requires Vectored DSL to cancel Far-End crosstalk (FEXT); the dominant impairment to high-speed DSL. Improving on current Vectored DSL technology, both one-sided and two-sided, through utilization of Single-Ended Vectored DSL to cancel FEXT offers significant improvements to several aspects of deploying DSL at gigabit speeds.
US11082086B2	Sleepy device operation in asynchronous channel hopping networks A radio communications device includes a RTC configured to run even during sleep for receiving from a coordinator node (CN) in an asynchronous channel hopping WPAN an asynchronous hopping sequence (AHS) frame that includes the CN's hopping sequence. A processor implements a stored sleepy device operation in asynchronous channel hopping networks algorithm. The algorithm is for determining a time stamp for the AHS frame and the CN's initial timing position within the hopping sequence, storing the time stamp, going to sleep and upon waking up changing a frequency band of its receive (Rx) channel to an updated fixed channel. A data request command frame is transmitted by the device on the CN's listening channel that is calculated from the CN's hopping sequence, time stamp, CN's initial timing position and current time, and the device receives an ACK frame transmitted by the CN at the updated fixed channel of Rx operation.
US11082085B2	Device system and method for new radio (NR) communication The disclosure relates to a communication device, a base station and respective methods for a communication device and a base station. The communication device comprises a transceiver which, in operation, receives, from a base station, a hopping pattern indicator, a hopping pattern being an order of a plurality of bandwidth parts by which a signal is to be received or transmitted in a plurality of transmission time intervals, TTIs, a bandwidth part being formed by at least one physical resource block. The communication device further comprises circuitry which, in operation, determines a hopping pattern to be applied based on the hopping pattern indicator. The transceiver, in operation, further receives or transmits the signal in the plurality of TTIs according to the determined hopping pattern.
US11082080B1	Transceiver circuit A transceiver circuit includes a transceiver antenna, a transmitter circuit, a receiver circuit, a frequency synthesizer and a baseband circuit. The transmitter circuit transmits a radio frequency signal corresponding to a radio frequency through the transceiver antenna. The frequency synthesizer provides a first local oscillation signal and a second local oscillation signal having a first local oscillation frequency and a second local oscillation frequency, respectively. The baseband circuit operates in a transmitting mode and a receiving mode. In the transmitting mode, the frequency synthesizer provides the first local oscillation signal, and in the receiving mode, the frequency synthesizer provides the second local oscillation signal, the first local oscillation frequency is a non-integer multiple of the radio frequency, and the second local oscillation frequency is an integer multiple of the radio frequency.
US11082077B2	Integrous signal combiner A front-end module (FEM) is disclosed that includes an integrous signal combiner. The integrous signal combiner can process received signals and use a set of resonant circuits to filter signal noise prior to recombination of a plurality of signal bands that form an aggregate carrier signal. These resonant circuits may be placed after a set of low noise amplifiers and can be used to more efficiently reduce noise and parasitic loading within each of a set of signal paths. Each resonant circuit may be configured to filter noise relating to a bandwidth for a signal that is to be combined with the signal of the signal path that includes the resonant circuit. In some implementations, the integrous signal combiner can be a tunable integrous signal combiner with resonant circuits that may be reconfigurable or dynamically configurable.
US11082075B2	Automatic gain control symbol partial use for decoding A method including receiving a data subframe having a plurality of symbols, determining a location of invalid pseudo time-domain samples in the data subframe, and discarding invalid pseudo time domain samples and recovering valid pseudo time domain samples to produce an updated data subframe, and processing the updated data subframe to produce demodulated data.
US11082072B2	Coherent multi band peak detection Systems and methods for detecting peaks in a multi-band transmit signal are disclosed. In some embodiments, a method of operation of a multi-band transmitter for detecting peaks in a multi-band transmit signal which includes multiple transmit signals on a respective multiple frequency bands includes receiving a first band input signal for a first frequency band of the multi-band transmit signal and at least one additional band input signal for a respective at least one additional frequency band of the multi-band transmit signal. The method also includes detecting a peak of a combination of the first band input signal and the at least one additional band input signal taking into account phase information of the first band input signal and the at least one additional band input signal. In this manner, the detected peak might not be overestimated as when the peak detection fails to take into account the phase information.
US11082071B2	Quality of service (QoS) aware data storage decoder Techniques related to a QoS-aware decoder architecture for data storage are described. In an example, QoS specifications include a QOS latency specification indicative of an acceptable latency for completing the processing of a data read command. The decoder may store this QOS latency specification. In operation, the decoder generates a latency measurement indicative of the actual latency for the processing. If a comparison of the latency measurement and QOS latency specification indicates a violation of the QOS latency specification, the decoder can terminate the decoding and generate a decoding failure.
US11082066B2	Efficient control channel design using polar codes Aspects of the disclosure relate to wireless communication systems configured to provide techniques for multiplexing dedicated control information for a plurality of users in a single information block and polar coding the information block to produce a polar code block of dedicated control information for transmission over a wireless air interface. The information block may further include group cyclic redundancy check (CRC) information for the information block and individual CRC information for each dedicated control information.
US11082065B2	Data processing apparatus and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio The present technology relates to a data processing apparatus and a data processing method that are able to provide an LDPC code with a good error rate.An LDPC encoder performs coding by an LDPC code having a code length of 16200 bits and a code rate of 12/15. The LDPC code includes an information bit and a parity bit, and a parity check matrix H is configured with an information matrix portion corresponding to the information bit of the LDPC code and a parity matrix portion corresponding to the parity bit. An information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table representing a position of an element of 1 in the information matrix portion at an interval of 360 columns. The present technology may be applied to a case of performing an LDPC coding and an LDPC decoding.
US11082064B2	Transmitting apparatus and mapping method thereof A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.
US11082060B2	LPDC code transmission method using row-orthogonal structure and apparatus therefor A method for encoding a quasi-cyclic low-density parity-check (LDPC) code according to an embodiment of the present invention comprises: a step of generating a multi-edge LDPC code matrix which comprises a high rate code matrix and a single parity check code matrix; and a step of encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix may be configured by connecting a first matrix which is configured as a quasi row-orthogonal structure matrix and a second matrix which is configured as a pure row-orthogonal structure.
US11082059B1	Method and system for obtaining and storing sensor data A computer-executable method and system for querying sensor data of a plurality of sensors is provided. Sensor data is received that comprising sensor data values sampled by a first sensor of said plurality of sensors according to a first compressive sampling scheme. The first compressive sampling scheme can be applied by the first sensor within a sampling time window and the received sensor data corresponds to samples of a signal within the sampling time window. The sensor data is stored in a first database. A frequency decomposition of the signal is computed based on a sparsifying transform associated with the first compressive sampling scheme and the received sensor data. The frequency decomposition comprises one or more frequency components. The one or more frequency components are stored in a second database. A query is received from a client. The query specifies an event that indicates a critical signal condition of a signal. It is detected whether the event exists using the received sensor data or the one or more frequency components.
US11082058B2	Concept of capacitor scaling The present disclosure addresses a concept for capacitor scaling. A first capacitor is provided with a first signal capacitance between a first electrode and a second electrode of the first capacitor and with a first parasitic capacitance between the first capacitor's first electrode and AC ground. A sum of the first signal capacitance and the first parasitic capacitance yields a first total capacitance. A second capacitor is provided with a second signal capacitance between a first electrode and a second electrode of the second capacitor and with a second parasitic capacitance between the second capacitor's first electrode and AC ground. A sum of the second signal capacitance and the second parasitic capacitance yields a second total capacitance. While the first signal capacitance differs from the second signal capacitance, the first total capacitance equals the second total capacitance.
US11082054B1	Apparatus and method for time-interleaved analog-to-digital conversion The present disclosure relates to a time-interleaved ADC circuit. The time-interleaved ADC circuit comprises an input for an analog input signal, a first ADC bank comprising a first plurality of parallel time-multiplexed ADCs, wherein the first plurality of parallel time-multiplexed ADCs is configured to subsequently generate a first plurality of samples of the analog input signal during a first time interval, a first buffer amplifier coupled between the input and the first ADC bank. The time-interleaved ADC circuit further comprises a second ADC bank comprising a second plurality of parallel time-multiplexed ADCs, wherein the second plurality of parallel time-multiplexed ADCs is configured to subsequently generate a second plurality of samples of the analog input signal during a second time interval, wherein the first and the second time intervals are subsequent time intervals, a second buffer amplifier coupled between the input and the second ADC bank. The first ADC bank has associated therewith a first dummy sampler, wherein the ADC circuit is configured to activate the first dummy sampler before the start of the first time interval. The second ADC bank has associated therewith a second dummy sampler, wherein the ADC circuit is configured to activate the second dummy sampler before the start of the second time interval.
US11082051B2	Apparatus and methods for timing offset compensation in frequency synthesizers Apparatus and methods for timing offset compensation of frequency synthesizers are provided herein. In certain embodiments, an electronic system includes a frequency synthesizer, such as a fractional-N phase-locked loop (PLL), which generates an output clock signal based on timing of a reference clock signal. Additionally, the electronic system includes an integer PLL configured to compensate for a timing offset, such as a phase offset and/or frequency offset, of the frequency synthesizer based on timing of the output clock signal.
US11082050B2	Clock distribution circuit using adjustable phase control and voltage converter including the same A clock distribution circuit including a Phase Locked Loop (PLL), a first Phase Detecting and Converting (PDC) circuit, a second PDC circuit, and a clock generating and compensating (CGC) circuit may be provided. The PLL may generate reference clock signals. The first PDC circuit may generate input phase difference voltages based on phase differences between respective pairs of two reference clock signals among the reference clock signals. The second PDC circuit may generate output phase difference voltages based on phase differences between respective pairs of two power switching signals among power switching signals received from external switching regulators. The CGC circuit may generate input clock signals provided to the plurality of external switching regulators by shifting phases of the reference clock signals, and additionally control a phase of at least one of the input clock signals based on the input phase difference voltages and the output phase difference voltages.
US11082049B2	Semiconductor device A semiconductor device includes a delay code generation circuit configured to adjust a shifting code for delaying a first internal clock, by comparing phases of a second internal clock and a delayed clock, the delayed clock generated by delaying the first internal clock, and configured to generate a first delay code and a second delay code from the shifting code.
US11082047B2	Low dropout linear voltage regulator A low dropout linear voltage regulator is provided. In the low dropout linear voltage regulator, a power transistor has a source connected to a power source, a gate connected to an output terminal of an error amplifier, a drain connected to an output terminal of the low dropout linear voltage regulator. A dynamic Miller compensation network has a first terminal connected to the output terminal of the error amplifier, a second terminal connected to the output terminal of the low dropout linear voltage regulator. A controller has a first terminal connected to the gate of the power transistor, and a second terminal connected to a third terminal of the Miller compensation network. The controller is configured to detect a current at the output terminal of the low dropout linear voltage regulator and generate control signals according to the current to control connection and disconnection of each second resistance-capacitance branch in the dynamic Miller compensation network.
US11082045B2	Bias circuitry and biasing method A bias circuitry includes a simulation circuit and a level shifter circuit. The simulation circuit is configured to simulate circuit architecture of a processing circuitry, in which the processing circuitry is biased by a bias signal, in order to generate output signals according to input signals. The level shifter circuit is configured to increase a voltage difference between a first node and a second node of the simulation circuit, in which the first node is for tracking an output common mode voltage of the output signals, and the second node is for outputting the bias signal.
US11082041B2	Switching circuit and operation method A switching circuit includes a live wire power obtaining circuit, a control circuit, and a tunable capacitor array. The live wire power obtaining circuit is coupled to a live wire to receive an alternating current (AC) voltage. The control circuit is configured to perform a zero-crossing detection to the alternating current voltage. The tunable capacitor array is coupled to the live wire power obtaining circuit and the control circuit. The control circuit is configured to control the live wire power obtaining circuit to supply power to the control circuit or the tunable capacitor array to discharge to supply power to the control circuit based on a state of a first switch and a zero-crossing detection result.
US11082040B2	Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
US11082037B2	Duty cycle correction circuit A duty cycle correction circuit includes: a first inverter, a first delayer, and a first adjustment circuit. An input terminal and output terminal of the first inverter are respectively configured to receive a first signal and output a third signal. A first input terminal and an output terminal of the first adjustment circuit are respectively configured to receive the third signal and output a first correction signal. An input terminal and output terminal of the first delayer are respectively configured to input a second signal and output a fourth signal to the first adjustment circuit. The fourth signal has a first delay time relative to the second signal. When the third signal and the fourth signal are at a high level, so is the first correction signal. When the third signal and the fourth signal are at a low level, so is the first correction signal.
US11082032B2	System for generating low-jitter digital clock signals using pulsed laser A low-jitter digital clock signal generating system which uses optical pulses output from a pulse laser includes a first balanced photodetector that converts first and second optical pulses with a delayed time interval into first and second electrical pulses through first and second photodiodes and outputs first and second modulated pulses generated by allowing the first and second electrical pulses to partially overlap each other, a second balanced photodetector that converts third and fourth optical pulses with the delayed time interval into third and fourth electrical pulses through third and fourth photodiodes, and outputs a second modulated pulse generated by allowing the third and fourth electrical pulses to partially overlap each other, and a capacitor. The capacitor is charged by the first modulated pulse, is discharged by the second modulated pulse, and outputs a voltage according to the charging and discharging as a clock signal.
US11082029B2	Acoustic wave device with multi-layer interdigital transducer electrode Aspects of this disclosure relate to an acoustic wave device that includes a multi-layer interdigital transducer electrode. The acoustic wave device includes a piezoelectric layer and an interdigital transducer electrode on the piezoelectric layer. The interdigital transducer electrode includes a first interdigital transducer electrode layer positioned between a second interdigital transducer electrode layer and the piezoelectric layer. The second interdigital transducer electrode layer can include aluminum and having a thickness of at least 200 nanometers. The acoustic wave device can include a temperature compensation layer arranged such that the interdigital transducer electrode is positioned between the piezoelectric layer and at least a portion of the temperature compensation layer. Related filters, modules, wireless communication devices, and methods are disclosed.
US11082026B2	Joined body of piezoelectric material substrate and support substrate A bonded body includes a supporting substrate; a piezoelectric material substrate composed of a material selected from the group consisting of lithium niobate, lithium tantalate and lithium niobate-lithium tantalate; and a bonding layer bonding the supporting substrate and the piezoelectric material substrate and contacting a main surface of the piezoelectric material substrate. The bonding layer includes a void extending from the piezoelectric material substrate toward the supporting substrate. A ratio (t2/t1) of a width t2 at an end of the void on a side of the supporting substrate with respect to a width t1 at an end of the void on a side of the piezoelectric material substrate is 0.8 or lower.
US11082024B1	Temperature stable mems resonator A resonant member of a MEMS resonator oscillates in a mechanical resonance mode that produces non-uniform regional stresses such that a first level of mechanical stress in a first region of the resonant member is higher than a second level of mechanical stress in a second region of the resonant member. A plurality of openings within a surface of the resonant member are disposed more densely within the first region than the second region and at least partly filled with a compensating material that reduces temperature dependence of the resonant frequency corresponding to the mechanical resonance mode.
US11082021B2	Advanced gain shaping for envelope tracking power amplifiers Envelope tracking power amplifiers with advanced gain shaping are provided. In certain implementations, a power amplifier system includes a power amplifier that amplifies a radio frequency (RF) signal and an envelope tracker that controls a voltage level of a supply voltage of the power amplifier based on an envelope of the RF signal. The power amplifier system further includes a gain shaping circuit that generates a gain shaping current that changes with the voltage level of the supply voltage from the envelope tracker. For example, the gain shaping circuit can include an analog look-up table (LUT) mapping a particular voltage level of the supply voltage to a particular current level of gain shaping current. Additionally, the gain shaping circuit biases the power amplifier based on the gain shaping current.
US11082020B2	Apparatus for attenuating noise in vehicle and control method thereof A vehicle includes an antenna configured to receive a broadcast signal, an amplifier configured to amplify the broadcast signal, a detector configured to detect an output signal of the amplifier, a variable transformer configured to output a negative feedback signal based on the detected output signal, an auto gain control configured to control an input signal of the amplifier based on the negative feedback signal and a controller configured to control the variable transformer and the auto gain control based on the output signal of the amplifier.
US11082013B2	Method of reducing memory effect of power amplifier A method of reducing memory effect of a power amplifier (PA), for a look-up table (LUT) based memory digital pre-distortion (DPD) circuit of an electronic device is disclosed. The method comprises generating a pre-distorted signal according to a LUT including parameters of an input signal amplitude and an input signal delay associated with a bandwidth of a signal inputted to the memory DPD circuit, and outputting the pre-distorted signal to the PA for improving the nonlinearity of the PA.
US11082010B2	Systems and methods for TIA base current detection and compensation Described herein are systems and methods that can adjust the performance of a transimpedance amplifier (TIA) in order to compensate for changing environmental and/or manufacturing conditions. In some embodiments, the changing environmental and/or manufacturing conditions may cause a reduction in beta of a bipolar junction transistor (BJT) in the TIA. A low beta may result in a high base current for the BJT causing the output voltage of the TIA to be formatted as an unusable signal output. To compensate for the low beta, the TIA generates an intermediate signal voltage, based on the base current and beta that is compared with the PN junction bias voltage on another BJT. Based on the comparison, the state of a digital state machine may be incremented, and a threshold base current is determined. This threshold base current may decide whether to compensate the operation of the TIA, or discard the chip.
US11082008B2	Multi-mode stacked amplifier Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode.
US11082007B2	Envelope tracking integrated circuit and related apparatus An envelope tracking (ET) integrated circuit (IC) (ETIC) is provided. The ETIC includes a number of ET circuits coupled to a number of amplifier circuits configured to amplify a radio frequency signal based on a number of ET voltages, respectively. The ET circuits are configured to generate the ET voltages based on a number of ET target voltages, respectively. The ETIC includes a reference ET circuit configured to generate a reference ET voltage based on a maximum ET target voltage among the ET target voltages. A selected ET circuit(s) among the ET circuits may be configured to not generate a respective ET voltage(s) but instead forward the reference ET voltage to a respective amplifier circuit(s) as the respective ET voltage(s). Hence, it may be possible to partially or completely turn off the selected ET circuit(s) to help reduce peak battery current and improve heat dissipation in an ET amplifier apparatus.
US11082006B2	Low power crystal oscillator A clock signal is generated with an oscillator. A crystal oscillator core within the oscillator circuit is switched on to produce first and second oscillation signals that are approximately opposite in phase. When a difference between a voltage of the first oscillation signal and a voltage of the second oscillation signal exceeds an upper threshold range, the crystal oscillator core is switched off. When the difference between the voltage of the first oscillation signal and the voltage of the second oscillation signal falls below the upper threshold range, the crystal oscillator core is switched back on. This operation is repeated so as to produce the clock signal.
US11082005B2	External electrical contact for solar roof tiles One embodiment can provide a photovoltaic roof tile module. The photovoltaic roof tile module can include a front glass cover, a back glass cover, a plurality of photovoltaic structures positioned between the front and back glass covers, and an internal circuit component electrically coupled to the plurality of photovoltaic structures. The internal circuit component is positioned between the front and back glass covers. The back glass cover can include at least one through hole and a metallic plug inserted inside the through hole. A first surface of the metallic plug can electrically couple to the internal circuit component, and a second opposite surface of the metallic plug can be exposed to surroundings external to the photovoltaic roof tile module, thereby facilitating electrical coupling between the photovoltaic roof tile module and another photovoltaic roof tile module.
US11082002B2	Solar cell assembly and solar cell module A solar cell assembly and a solar cell module are provided. The solar cell assembly includes a solar panel; and an installation member having a supporting portion configured for fixing the solar panel and a connecting portion configured for fixing the installation member onto a support beam. The supporting portion is disposed on a backside of the solar panel, the connecting portion extends out of an edge of the supporting portion along a direction parallel to the solar panel, the connecting portion locates outside of a coverage area of the solar panel, and the connecting portion defines a installation hole therein.
US11082001B2	Self-ballasted heliostat with suspended mirror assembly A heliostat for tracking the sun is disclosed. The heliostat comprises a frame (104) with legs (102); an optical assembly (120) configured to hang between the legs of the frame by means of a plurality of wires (130); and a plurality of actuators (520) configured to change the orientation of the optical assembly via the plurality of wires. The optical assembly may include a mirror (122) or photovoltaic panel that tracks the sun, and concrete backing (610). The optical assembly may further include a tracking controller (150) to energize the plurality of actuators, photovoltaic cell (252) configured to power the tracking controller and actuators, cleaning assembly (1710), and reservoir (770) for capturing rain water on the optical assembly. The optical assembly may further include a camera (254) for capturing images of the frame and determining the orientation of the optical assembly based on the images.
US11082000B2	Thermophotovoltaic panel and a method for making a thermophotovoltaic panel A thermophotovoltaic panel, including a first surface for receiving solar radiation, photovoltaic cells connected to said first receiving surface, a heat exchanger connected to said photovoltaic cells, and a second surface, opposite to the first, for supporting the panel, said heat exchanger being positioned between said first receiving surface and said second supporting surface, wherein said photovoltaic cells and said exchanger are embedded in at least one resin, preferably cold-polymerised epoxy resin, to constitute a body including said first receiving surface and said second supporting surface, wherein at least one layer of resin at said first receiving surface is constituted of substantially transparent resin.
US11081996B2	Variable coil configuration system control, apparatus and method This application generally relates to electric machines with coils or windings (e.g., generators and motors), and more particularly to systems, apparatus, and methods that configure coils or windings of electric machines, for instance dynamically in response to operational condition and under load.
US11081993B2	Method for operating a permanent magnet synchronous motor, and motor assembly A method for operating a permanent magnet synchronous motor, an operational vector being determined in a multi-stage process. A motor assembly configured to perform such a method is also disclosed.
US11081991B2	Real-time resistance estimation and adjustment for permanent magnet synchronous machines A system includes a motor operating with an angular velocity and an operational current, a motor controller circuit to issue control signals to the motor, and a stator resistance calculation circuit. The calculation circuit is to introduce a perturbation signal to the motor through the control signals issued by the motor controller circuit, observe operations of the motor in response to the perturbation signal, estimate stator resistance of the motor based upon the observations of the operations of the motor in response to the perturbation signal, adjust operation of the motor based upon a changed stator resistance.
US11081990B2	Method for operating a steam turbine A method for operating a steam turbine, wherein the pressure of the cooling medium in the generator is changed not only for cooling but also for increasing or decreasing the torque of the generator on the steam turbine, this being utilized for the purpose of the start-up or shut-down process.
US11081989B2	Current-shaping circuit for use with magnetic couplers downhole A power generation device is provided. The power generation device can include a magnetic coupler. The magnetic coupler can be associated with a maximum torque output. The maximum torque output of the magnetic coupler can be based on a size of the magnetic coupler. The power generation device can also include an alternator coupled to the magnetic coupling device. The alternator can convert kinetic energy received from the magnetic coupling device into a current. The kinetic energy can be generated by the magnetic coupler using a rotational force transferred across the magnetic coupling device. The power generation device can also include a power converter device coupled to the alternator to shape the current from the alternator such that the maximum torque output is sufficient to cause the power converter to output a threshold current sufficient for operating a well tool powered using the power generation device.
US11081988B1	Data storage device with spread spectrum spindle motor control A data storage device is disclosed comprising a head actuated over a disk, and a spindle motor configured to rotate the disk. A pulse width modulated (PWM) control signal is generated having a frequency based on a PWM clock, the spindle motor is controlled using the PWM control signal, and a frequency of the PWM clock is swung between a minimum frequency and a maximum frequency at a swing rate.
US11081985B2	Synchronous rotating machine control device and machine learning device A machine learning device includes: a state observer that observes, as a state variable, at least one of driving noise of a synchronous rotating machine and an error with respect to a preset position of a rotational position of the synchronous rotating machine determined by driving voltage; and a learner that determines a value of a parameter on a basis of the state variable observed by the state observer. The learner includes: a reward calculator that calculates a reward on a basis of the state variable; and a function updater that determines the value of the parameter on a basis of the reward that has been calculated. The reward calculator increases the reward when the driving noise is smaller than a target value of driving noise.
US11081984B2	High efficiency electronically commutated motor An electronically commutated electric motor includes a rotor, a stator and an electronic drive. The rotor is journaled to rotate about an axis of rotation, the stator is stationary relative to the rotor, and the electronic drive provides synchronous power to the stator and drives the rotor. The rotor has two ferromagnetic radially spaced apart co-rotating rotor portions having a circumferential array of alternating polarity permanent magnet poles that drive magnetic flux back and forth across an armature air gap between said spaced apart rotor portions, and circumferentially through each of said rotor portions. The stator includes an air core armature supported in the armature airgap, and has a non-ferromagnetic structure where located in the magnetic flux in the armature air gap. Three phase windings wound on the armature magnetically exert torque upon the rotor when the windings are electrically energized by the electronic drive. The phase windings are wound from wire that is formed from bundled together multiple individually insulated conductor strands, wherein said strands are electrically connected in parallel and are electrically insulated between each other along their lengths where they lie in the magnetic flux in the armature airgap. The electronic drive is configured to convert electrical supply power into power that is synchronous with the rotor rotation by regulating power through a switch mode converter that varies voltage to a variable DC link supplying a transistor output H-bridge for commutating the phase windings. The electronic drive electrically energizes only two of the three phase windings simultaneously to provide trapezoidal excitation to the phase windings, leaving one of the three phase windings instantaneously electrically non-energized. The electronic drive monitors the instantaneous non-energized phase winding back-emf zero crossing events for controlling triggering of advances in the commutation.
US11081977B2	Vibrational energy harvester device Provided is an electrostatic-type vibrational energy harvester device that makes it possible to efficiently rectify and charge power from low acceleration to high acceleration of vibrational energy applied from the exterior. The vibrational energy harvester device is provided with: a movable part capable of vibrating in a vibration direction as a result of mechanical vibrational energy, said movable part being provided with a first surface along the vibration direction; and a fixed part provided with a second surface facing the first surface of the movable part with a gap therebetween so that it is possible for the movable part to vibrate in the vibration direction. A plurality of recessed portions and protruding sections are formed in an alternating manner in the vibration direction on the surfaces of each of the first surface of the movable part and the second surface of the fixed part. An electret film is formed on at least one of the fixed part and the movable part. The vibrational energy harvester device is configured so that a force factor (electromechanical conversion factor) having a value that corresponds to the gap between the first surface of the movable part and the second surface of the fixed part becomes small when the vibration amplitude of the movable part is small and large when the vibration amplitude of the movable part is large.
US11081972B2	Potential equalization system for a modular multilevel converter A potential equalization system for a modular multi-level converter. The converter has a plurality of converter modules and each of the modules has a direct current source. The potential equalization system includes pole contacts, which are each electrically connected to one pole of a direct current source, and at least one electrically conductive contacting element, which can be moved between a first end position in which the contacting element is electrically isolated from the converter modules and a second end position in which the contacting element contacts pole contacts of different direct current sources and can be put on ground potential.
US11081971B1	AC/DC power converters including current transformers for bidirectional current sensing An AC/DC power converter includes input terminals, output terminals, a power factor correction circuit coupled between the input and output terminals and including at least one power switch defining a switched current path, and a current transformer including a primary winding and a secondary winding. The primary winding is coupled in series with the switched current path. The power converter also includes a first sense switch coupled with a first end of the secondary winding, a second sense switch coupled with a second end of the secondary winding, and a control circuit. The control circuit is configured to turn on the first sense switch and turn off the second sense switch during a positive polarity of the AC voltage input, and to turn off the first sense switch and turn on the second sense switch during a negative polarity of the AC voltage input.
US11081970B2	Assembly of bus bars forming a casing and heat dissipator for an electronic power device The assembly of bus bars according to the invention comprises a plurality of sectors of bus bars (S1 to S6) which are arranged, in a connected manner and with electrical contact, around a central axis (C) and upper and lower closing plates (BPD) which are perpendicular to the central axis, the sectors of bus bars each comprising an external portion of bus bar (B11 to B16) and at least one internal portion of bus bar (B21 to B26, B31 to B36) which delimit a plurality of internal volumes, the upper and lower closing plates being in contact against upper and lower faces of the portions of bus bar, respectively, and the portions of bus bar comprising a plurality of electrical contact faces of the type referred to as “press pack”.
US11081967B2	Self-adaptive synchronous rectification control system and method of active clamp flyback converter The invention discloses a self-adaptive synchronous rectification control system and a self-adaptive synchronous rectification control method of an active clamp flyback converter. The control system comprises a sampling and signal processing circuit, a control circuit with a microcontroller as a core and a gate driver. According to the control method, a switching-on state, an early switching-off state, a late switching-off state and an exact switching-off state of a secondary synchronous rectifier of the active clamp flyback converter can be directly detected, and the synchronous rectifier and a switching-on time of the synchronous rectifier in next cycle can be controlled according to a detection result. After several cycles of self-adaptive control, the synchronous rectifier enters the exact switching-on state, thus avoiding oscillation of an output waveform of the active clamp flyback converter.
US11081965B1	Universal input voltage detection system for a flyback converter Disclosed is a universal input voltage detection system for a flyback converter having a transformer coupled between an input and an output of the flyback converter. The transformer includes a primary winding coupled to the input of the flyback converter to receive an input voltage and a secondary winding coupled to the output of the flyback converter. The universal input voltage detection system comprises a controller, coupled to a switch, at a primary winding side of the transformer. The switch is coupled to the primary winding of the transformer and a current through the primary winding is generated when the switch is turned on. The controller is configured to operate in either continuous conduction mode (CCM) or discontinuous conduction mode (DCM) and indirectly detect the input voltage to the flyback converter based on the current through the primary winding generated while the switch is turned on.
US11081963B2	Slope detection and correction for current sensing using on-state resistance of a power switch A current estimation circuit is configured to estimate current within a power switch, e.g., within a switching voltage converter, using a voltage measured across its load terminals and its on-state resistance. Ringing and other transient anomalies associated with a turn-on transition of the power switch are neglected by ignoring the measured voltage across the power switch for a blanking interval after the transition. During the remainder of the conduction interval of the power switch, the measured voltage is sampled to provide first and second samples. Also during this interval, a slope of the measured voltage is estimated and tracked. The estimated slope and the first and second samples are combined to produce an estimate of the current for the entire conduction interval of the power switch, including the blanked interval. The estimated slope is used to correct for inaccuracy introduced by not using measured voltage during the blanking interval.
US11081962B2	Methods and systems for power management An apparatus comprises a plurality of voltage sources, one or more processors embedded with the plurality of voltage sources, and memory storing processor executable instructions that, when executed by the one or more processors, cause the apparatus to modify duty cycles of the voltage sources, and to modify timing for each phase of a multiphase cycle. In some cases, the apparatus: transfers, for each phase of the multiphase cycle, power from a different source of a plurality of sources to a load; determines, for each phase of the multiphase cycle, an input voltage associated with the transferred power, an output voltage associated with the transferred power, and current from the source associated with the transferred power; determines a duty cycle associated with the source; modifies duty cycles of the voltage sources; and modifies timing for each phase of the multiphase cycle.
US11081961B2	Power convertor, power generation system, and power generation control method According to one embodiment, a power convertor includes a buck-boost circuit to be applied with an input voltage to convert the input voltage into an output voltage for output, the input voltage being generated by a power generation module that generates direct-current power; a switching controller that executes maximum power-point tracking to control power conversion of the buck-boost circuit such that the power generation module generates maximum direct-current power; and a mode controller that causes the switching controller to execute the maximum power-point tracking when an input current from the power generation module is larger than a preset current threshold, and when the input current is equal to or less than the current threshold, causes the switching controller to stop the maximum power-point tracking, and cause the buck-boost circuit to output the input voltage as the output voltage without the power conversion.
US11081960B2	Timer for power converter controller Aspects of the disclosure provide for a circuit. In an example, the circuit includes an input circuit having a first output and a second output, a first timer having a first input coupled to the first output of the input circuit, a second timer having a first input coupled to the second output of the input circuit, a second input coupled to an output of the first timer, and an output coupled to a second input of the first timer, and an output circuit coupled to the output of the first timer and the output of the second timer.
US11081954B2	Phase shedding control method used in multiphase switching converters with daisy chain configuration A multiphase switching converter with automatic phase shedding control, wherein the multiphase switching converter includes a plurality of switching circuits coupled in parallel, and a plurality of control circuits configured in a daisy chain and respectively configured for driving a corresponding one of the plurality of switching circuits. Each of the control circuit generates a current threshold based on a corresponding sequence information, and compares a current indication signal indicative of a load current of the multiphase switching converter with the current threshold to determine whether to enter into a phase shedding mode.
US11081953B2	Control method and control circuit for a boost converter A control circuit for a boost converter can include: a comparison circuit configured to compare an input voltage of the boost converter against an output voltage of the boost converter, and to generate first and second control signals; an option circuit configured to provide a third control signal generated by a drive circuit of the boost converter to a control terminal of a synchronous power transistor of the boost converter, in accordance with the first and second control signals, when the output voltage is greater than the input voltage; and the option circuit being configured to provide a DC voltage to the control terminal of the synchronous power transistor, in accordance with the first and second control signals, in order to provide a current path for an inductor current of the boost converter through the synchronous power transistor, when the output voltage is not greater than the input voltage.
US11081950B2	Linear vibration motor Provided is a linear vibration motor, including: a housing having a receiving space; a vibration unit received in the receiving space; an elastic assembly configured to suspend the vibration unit in the receiving space, and a driving unit fixed to the housing and configured to drive the vibration unit to vibrate. The linear vibration motor includes a coil assembly and two first permanent magnets respectively provided at two sides of the coil assembly. The vibration unit includes one of the coil assembly and the first permanent magnets, and the driving unit includes the other one. When the vibration unit is static, a central axis of the first permanent magnet perpendicular to a vibrating direction of the vibration unit and a central axis of the coil assembly perpendicular to the vibrating direction of the vibration unit are spaced apart from each other in the vibrating direction of the vibration unit.
US11081946B2	Switched reluctance motor A stator assembly has coils in a distributed winding configuration. A poly-phase switched reluctance motor assembly 3002 may include a stator assembly with multiple coils in a distributed winding configuration. The stator assembly may have a central bore into which a rotor assembly having multiple poles is received and configured to rotate. A method of controlling a switched reluctance motor may include at least three phases wherein during each conduction period a first phase is energized with negative direction current, a second phase is energized with positive current and there is at least one non-energized phase. During each commutation period either the first phase or second phase switches off to a non-energized state and one of the non-energized phases switches on to an energized state with the same direction current as the first or second phase that was switched off. The switched reluctance motor may include a distributed winding configuration.
US11081941B2	Motor and electric power steering device A motor includes a first inverter connected to one end of a winding of each phase and a second inverter connected to another end of the winding of each phase. The first inverter includes a terminal electrically connected to one end of a U-phase winding. The second inverter includes a terminal electrically connected to another end of the U-phase winding. Current output from the terminal of the first inverter and passing through the U-phase winding flows to the terminal of the second inverter. Current output from the terminal of the second inverter and passing through the U-phase winding flows to the terminal of the first inverter. The terminal of the first inverter and the terminal of the second inverter are adjacent to each other.
US11081940B2	Vehicular drive system A drive motor includes a torque sensor on an outer circumference of a shaft. The drive motor includes a rotor, a rotor shaft arranged inside the rotor, and an output shaft that is joined to the rotor shaft by a joint having a loose element. In the drive motor, the output shaft outputs rotational force of the rotor shaft to the output side. The torque sensor is arranged on an upstream side of the joint in a range not overlapping with the joint.
US11081936B2	Wet cavity electric machine A wet cavity electric machine includes a stator core having two stator poles formed by a post and a wire wound about the post to form a stator winding, with the stator winding having end turns, and a rotor having two rotor poles and configured to rotate relative to the stator and a channel for liquid coolant to flow through the rotor, and at least one fluid port in fluid communication with the channel and the stator winding end turns wherein the end turns will be exposed to liquid coolant passing through the channel.
US11081932B2	Electrostatic generator electrode-centering and seismic-isolation system for flywheel-based energy storage modules Robust electro-static (ES) device embodiments, with application to energy storage flywheels as an example, are described that provide reliable, high-efficiency operation in the presence of thermal and mechanical perturbations, as well as seismic events. Electro-static generators and motors, when augmented with magnetic bearings, passive three-dimensional stabilization techniques and dynamic touch-down bearings, enable robust performance in the face of these environmental concerns, as well as efficient operation during typical operational sequences, including spin-up and steady-state modalities.
US11081923B2	Corona shielding system for an electrical machine The present disclosure relates to electrical machines. The teachings thereof may be embodied in a corona shielding system for an electrical machine. For example, a corona shielding system may include: an outer corona shield and an overhang corona shielding. The outer corona shielding and the overhang corona shielding may comprise a first corona shielding material having a nonlinear field strength-dependent electrical resistance.
US11081921B2	Rotor The rotor includes a shaft that allows cooling oil to flow therein; a substantially cylindrical rotor yoke fitted over the shaft; a magnet fitted to the rotor yoke; and a first end plate abutting on one end of the rotor yoke. In this configuration, the rotor yoke includes a cooling oil passage that is formed on a radially inner side of the magnet and allows the cooling oil to flow in an axial direction, the rotor yoke receives a pressing force in the axial direction via the first end plate, and the rotor yoke and the first end plate form a sealing part that seals the cooling oil, in a section positioned between the cooling oil passage and the magnet in the radial direction.
US11081917B2	Electric machine and a turbo machine having the same An electric machine includes at least one rotor module. A rotor module includes a rotor hub having a hub body, and a plurality of first protrusions and a plurality of second protrusions. One or more first protrusions include an elongated portion and a head portion. One or more second protrusions include a wedge-shaped profile. The rotor module further includes a magnetic core having a plurality of core members disposed on the rotor hub. A core member of the plurality of core members is disposed such that the head portion of the first protrusion located between the adjacent second protrusions engages with the core member, and each of the one or more second protrusions extends at least partially in a space between adjacent core members of the plurality of core members. Moreover, the rotor module includes a permanent magnet disposed in a space between the adjacent core members.
US11081910B2	Methods and apparatus for wireless power transmission and reception Methods and apparatus for wireless transmission and reception of power in a wireless power network are disclosed. The wireless power network comprises a wireless power transmitter configured to transmit RF power to at least one wireless power receiver. A method of transmitting power in a wireless power network is disclosed, wherein the wireless power network comprises a wireless power transmitter in bidirectional communication with at least one wireless power receiver. A wireless power transmitter capable of transmitting power to at least one wireless power receiver is also disclosed. In some embodiments, the wireless power transmitter comprises an application processor operably coupled to a plurality of wireless power transmitter channels. A wireless power receiver is also disclosed. The wireless power receiver may be configured to convert an RF power signal to direct current (DC).
US11081908B2	Electronic apparatus and method According to one embodiment, transmission circuitry transmits power with a first electromagnetic wave in a first frequency band. A processor circuitry executes a carrier sense during a first period, in at least a second frequency band different from the first frequency band. The transmission circuitry transmits power with a second electromagnetic wave in the first frequency band in a second period following the first period, if a wireless signal is not detected by the carrier sense during the first period. The processor circuitry executes the carrier sense during a third period following the first period in the at least the second frequency band, if the wireless signal is detected by the carrier sense during the first period.
US11081906B2	Contactless power transmission apparatus A contactless power transmission apparatus includes a receiver that includes a resonant circuit including a receiver coil that receives electric power from a transmitter coil included in a transmitter and a resonant capacitor connected in parallel to the receiver coil. The receiver outputs, through an output coil having fewer turns than the receiver coil and a coil connected to the output coil, electric power received by the resonant circuit and rectifies the output power with a rectifier circuit. The transmitter includes a control circuit that controls a voltage and a switching frequency of alternating current power to be supplied to the transmitter coil from a power supply circuit to allow the contactless power transmission apparatus to continuously perform a constant voltage output operation.
US11081905B2	Information processing apparatus, information processing method, and information processing system A power charging system is provided. The power charging system may have an information processing apparatus having a first communication unit and a power receiving unit, and an external apparatus having a second communication unit and a power transmission unit. The second communication unit may be configured to wirelessly communicate with the first communication unit using a first carrier wave having a first frequency and the power transmission unit may be configured to wirelessly transmit power to the power receiving unit using a second carrier wave having a second frequency, the second frequency being different from the first frequency.
US11081902B2	Power supply device and power supply system including power supply device A power supply device according to an embodiment of the disclosure includes a power supply unit including a first power supply unit transmitting standby power to an electronic device and a second power supply unit transmitting main power to the electronic device and a cable including a standby power transmission line transmitting the standby power to the electronic device, a main power transmission line transmitting the main power to the electronic device, a first detect line receiving a power-on signal for operating the second power supply unit from the electronic device, and a second detect line determining whether the power-on signal is received. The second power supply unit does not operate when at least one of the first detect line and the second detect line is opened and the power-on signal is not received. Moreover, various embodiment grasped through the disclosure are possible.
US11081896B2	Portable charger connection frame and case comprising the same The present disclosure provides a portable charger connection frame, comprising: a storage box, a cover body, and an engaging element. The storage box comprises a head portion, a body and an end portion which are sequentially connected, wherein the head portion has a head accommodation chamber inside and one side of the body close to the head accommodation chamber has a opening communicating with the head accommodation chamber; the cover body is in the head accommodation chamber, covers the opening, and is pivotally connected to a side wall of the head portion; the engaging element is used to restrict the cover body from leaving the head accommodation chamber. In the present invention, a portable charger is placed in the storage box as well as is directly used and taken through detaching the cover body, therefore charging operation saves time and is effortless.
US11081895B2	Charging apparatus A charging apparatus includes a plurality of batteries, a changeover relay that can be changed over between a first state where the plurality of the batteries are connected in series to one another and a second state where the plurality of the batteries are connected in parallel to one another, an electric storage device, a main relay that is provided between the electric storage device and an electric load of a vehicle, and a control device that controls the opening/closing of the changeover relay. The control device renders the changeover relay in the first state when the main relay is in an open state.
US11081894B2	Battery pack A battery pack includes at least two battery cells; a circuit board to control charging and discharging operations of the battery cells; and a connection tab electrically connected to the battery cells, extending towards the circuit board, and including a bent portion proximal to the battery cells and located within a battery area defined by the battery cells. A battery pack suitable for a compact type device is provided and a low-resistive design may be applied to the battery pack.
US11081891B2	Electrical power systems having reactive power and harmonic support components An electrical power system connectable to a power grid includes a cluster of electrical power subsystems, each of the electrical power subsystems including a power converter electrically coupled to a generator having a generator rotor and a generator stator. Each of the electrical power subsystems defines a stator power path and a converter power path for providing power to the power grid. Each of the electrical power subsystems further includes a transformer. The system further includes a subsystem breaker configured with each of the electrical power subsystems, and a cluster power path extending from each subsystem breaker for connecting the cluster of electrical power subsystems to the power grid. The system further includes a reactive power compensation inverter electrically coupled within the electrical power system, the reactive power compensation inverter operable to increase the reactive power level in the electrical current flowing to the power grid.
US11081882B2	ESD suppression using light emissions A protected electric circuit, and method of protecting a protected circuit is provided. The circuit comprises at least one sensitive device wherein the sensitive device operates at a device voltage and has a maximum voltage capability. At least one light emitting diode electrically connected with the sensitive device wherein the light emitting diode has a first trigger voltage wherein the first trigger voltage is above the device voltage and below the maximum voltage capability. When any said extraneous energy above the first trigger energy is experienced the light emitting diode emits photons thereby converting at least some of the extraneous energy to photon energy.
US11081881B2	Full swing positive to negative MOSFET supply clamp for electrostatic discharge (ESD) protection Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit including a trigger actuated MOSFET device. Triggering of the MOSFET device is made in response to detection of either a positive ESD event or a negative ESD event.
US11081879B2	Direct current distance protection controllers A DC distance protection controller for identifying a fault within a protection zone that extends between a first terminal and a set point along a DC power transmission conduit which lies between the first terminal and a second terminal within a DC electrical power network. The protection controller periodically obtains as respective sampled pairs a measured voltage value and a measured current value of the DC power transmission conduit; isolates a fault component voltage value and a fault component current value to define a respective corresponding isolated pair; calculates from each isolated pair a fault component operating voltage of the DC power transmission conduit at the set point; compare a given calculated fault component operating voltage with a historical voltage value; and identifies a fault within the protection zone when the given calculated fault component operating voltage is greater than the historical voltage value.
US11081878B2	Method for coordinating switches in multiple reclosers in a distribution feeder line in response to detection of a fault A method for controlling multiple switching devices in an electrical power distribution network in response to detecting a fault. The method determines that a fault current is present, and opens a switch in each of the switching devices in response thereto. The method then initiates a current pulse in the switch in a farthest upstream switching device for a first pulse duration time, closes the switch in the farthest upstream recloser if no fault current is detected during the first pulse duration temporarily changes the TCC curve of the farthest upstream recloser to a second TCC curve that is an instantaneous or near instantaneous TCC curve, and initiates a current pulse in the switch in a next farthest upstream switching device that is downstream of the farthest upstream switching device after the switch in a farthest upstream switching device is closed.
US11081875B2	System, method and apparatus for power distribution in an electric mobile application using a combined breaker and relay A system including a vehicle having a motive electrical power path; a power distribution unit including a current protection circuit comprising a breaker/relay including: a fixed contact; a movable contact; a physical opening response portion responsive to a current value in the motive power circuit; a current source circuit electrically coupled to the breaker/relay and structured to inject a current across the fixed contact; and a voltage determination circuit electrically coupled to the breaker/relay and structured to determine at least one of an injected voltage amount and a contactor impedance value, wherein the voltage determination circuit comprises a high pass filter having a cutoff frequency selected in response to a frequency of the injected current.
US11081870B2	Bus bar unit, motor, electric power steering device A bus bar unit includes a bus bar holder and bus bars. The bus bar holder is provided on an upper side of a stator disposed in a ring around a central axis extending in a vertical direction. The bus bars are supported by the bus bar holder and connected to coil wires extending from the stator. The bus bars are plate-shaped conductors and are supported by the bus bar holder with a plate surface facing in the vertical direction. The bus bars include coil connecting portions connected to the coil wires, and a bus bar body portion connecting the coil connecting portions through a radially inner side of the plurality of the coil connecting portions, respectively, and at least one bus bar crosses over an upper side or a lower side of at least one of the other bus bars.
US11081869B2	Electrical junction box An electrical junction box includes: a circuit board to which an electronic component is connected; and a frame positioned with respect to the circuit board. The frame integrally includes a sub frame that surrounds at least part of a periphery of the electronic component. The sub frame is provided with a holding portion that holds the electronic component in the holding portion.
US11081868B2	Enclosure arrangements; components; and methods Aspects and techniques of the present disclosure relate to enclosures, such as, electrical enclosures, for example, explosion-proof enclosures, and including advantageous features and methods usable with such enclosures. Disclosed features and techniques relate to: an enclosure fastening device; a visual indicator; an enclosure handling assist arrangement; a control handle; and a reset controller.
US11081865B2	Device for setting the electrode gap on a spark plug An apparatus for setting a gap between a first electrode and a second electrode of a spark plug, encompassing at least a counter-brace, a gap plate, and a plunger, which are disposed along a longitudinal axis; the counter-brace being configured to brace the spark plug; the gap plate being disposed between the counter-brace and the plunger in the direction of the longitudinal axis; the gap plate being configured to be disposed between the first electrode and the second electrode; and the plunger being configured to apply a deformation force in the direction of the longitudinal axis onto the second electrode.
US11081859B2	Optical resonator with localized ion-implanted voids A high Q whispering gallery mode resonator with ion-implanted voids is described. A resonator device includes a resonator disk formed of an electrooptic material. The resonator disk includes a top surface, a bottom surface substantially parallel to the top surface, and a side structure between the top surface and the bottom surface. The side structure includes an axial surface along a perimeter of the resonator disk, where a midplane passes through the axial surface dividing the axial surface into symmetrical halves. The whispering gallery mode resonator disk includes voids localized at a particular depth from the top surface. At least one of the voids localized at the particular depth from the top surface is located at an outer extremity towards the perimeter of the resonator disk. The resonator device can further include a first electrode on the top surface and a second electrode on the bottom surface.
US11081858B2	Optical transmitter module, optical module, optical transmission equipment and method of manufacturing thereof An optical transmitter module includes optical semiconductor devices including a first optical semiconductor device, a temperature adjustment means for collectively performing temperature adjustment on the optical semiconductor devices, and a first thermal resistor that is disposed between the first optical semiconductor device and the temperature adjustment means, in which, when the temperature adjustment means is driven, the temperature of the first optical semiconductor device is higher than temperatures of other optical semiconductor devices which are different from the first optical semiconductor device.
US11081855B2	Laser-MOPA with burst-mode control A laser master-oscillator power-amplifier (MOPA) is operated to provide successive bursts of ultrashort pulses. The pulse-bursts are selected by an optical modulator from a pulse train delivered by the master oscillator prior to amplification in the power amplifier. The optical modulator has a selectively variable transmission specified by an analog voltage signal having a stepped waveform. The voltage signal is delivered by a sequentially-switched parallel switch-array connected in parallel with a parallel DAC having multiple parallel DC voltage outputs corresponding to steps of the stepped waveform.
US11081854B2	Laser oscillator monitoring control system A laser oscillator capable of detecting scattered light intensity when a laser beam is incident on an end surface of a fiber more appropriately is provided. A laser oscillator monitoring control system includes: a scattered light detection unit that detects a scattered light intensity on an input end surface of a process fiber of a fiber laser oscillator; a control unit that controls a laser output value on the basis of a laser output command value from a CNC and a detection result obtained by the scattered light detection unit; a normal scattered light calculation unit that calculates a normal index value; a first threshold setting unit that sets a first threshold indicating an abnormality resulting from a contamination and/or a scratch; a second threshold setting unit that sets a second threshold indicating an abnormality resulting from an optical axis shift; and a third threshold setting unit that sets a third threshold indicating an abnormality of a level in which a component is destroyed. The control unit controls a laser output value on the basis of the scattered light intensity detected by the scattered light detection unit, the first threshold, the second threshold, and the third threshold.
US11081853B2	Optical element moving apparatus, narrowed-line laser apparatus, and method for manufacturing electronic device An optical element moving apparatus includes a first holder configured to hold a first optical element, a second holder configured to hold a second optical element and having an inclination that inclines with respect to a first direction in which the second holder approaches the first holder, a guide section configured to be capable of moving the second holder in a direction parallel to the first direction, and an elastic member disposed in a position which is located between the first holder and the second holder and through which a first plane passes, the first plane intersecting the inclination at right angles and being parallel to the first direction.
US11081850B2	Gas laser apparatus A gas laser apparatus may include: a laser chamber connected through a first control valve to a first laser gas supply source that supplies a first laser gas containing a halogen gas; a purification column that removes at least a part of the halogen gas and a halogen compound from at least a part of a gas exhausted from the laser chamber; a booster pump; and a controller that calculates, on a basis of a first amount of a gas supplied from the booster pump to the laser chamber, a second amount of the first laser gas that is to be supplied to the laser chamber and controls the first control valve on a basis of a result of the calculation of the second amount.
US11081849B2	Slip ring, motor, and vehicle having same The present invention relates to a slip ring, a motor, and a vehicle having same, the slip ring comprising: a cylindrical slip ring body; a plurality of blades formed protruding in the lengthwise direction of the slip ring body on an end portion of the slip ring body; and a brush contacting part disposed on the outer circumferential surface of the slip ring body, wherein the slip ring body and the blades are integrally formed. Accordingly, the motor, by means of the rotation of the blades, can dissipate frictional heat generated from friction between a brush and the slip ring and thus reduce the effects of heat, and can also guide and disperse airborne dust generated from friction between the brush and the slip ring to the outside.
US11081848B2	Charger extension device A charger extension device has a housing having a top side, a left side, a bottom side, a right side, a rear side, and a front side, an USB port on the front side of the housing, and a Lightning port on the rear side of the housing. Another charger extension device has a housing having a top side, a left side, a bottom side, a right side, a rear side, and a front side, an USB port on the front side of the housing, a cable retention assembly on the front side of the housing, and a Lightning port on the rear side of the housing.
US11081844B2	Electrical power and control unit for work areas An electrical power or electronic data unit is provided for mounting in an isolated work space such as a work pod that is at least partially enclosed by walls or other surfaces. The unit includes a housing body, an electrical power outlet and/or an electronic data connector, and an occupancy sensor that is in communication with a controller. The controller is operable to energize and de-energize a lighting or ventilation system associated with the isolated work space in response to a signal received from the occupancy sensor, and may further be operable to energize and de-energize the power outlet or data connector. Optionally, an environmental sensor is provided with the unit, and is in communication with a building automation system.
US11081843B1	Intelligent socket control system for preventing children from electric shock The present application provides an intelligent socket control system for preventing children from electric shock, which includes: personnel monitoring module, configured to continuously monitor if there is a person in the monitored area; information determining module, configured to determine the age of a person in the monitoring area when it is monitored the person in the monitoring area; socket control module, configured to control the power-on indicator of the socket in the monitoring area turn off and control the jack baffle of the socket in the monitoring area close according to the age of the person in the monitoring area, wherein, when the jack baffle of the socket is closed, the jack of the socket cannot be inserted. In this way, when the person in the monitoring area is considered as a child because of his/her age, the power-on indicator of the outlet in the control monitoring area is controlled to turn off, preventing the indicator light on the socket from attracting the child to touch the card, to prevent the child from getting an electric shock when playing the socket. At the same time, the jack baffle of the socket in the monitoring area is controlled to close, to prevent the child from inserting a finger or a metal object into the jack of the socket to protect the safety of the child and prevent the child from operating the socket to cause harm to the child.
US11081841B2	Electrical connector haiving contact wafer equipped with transverse grounding bar An electrical connector includes an insulative housing defining a space. A connection module is received within the space. The connection module includes a pair of contact modules commonly sandwiching a grounding module therebetween in the transverse direction. Each contact module includes a plurality of contacts integrally formed within the corresponding insulative wafer via insert-molding. The grounding module includes a grounding plate embedded within an insulative wafer. The grounding plate forms a plurality of fingers respectively electrically and mechanically connecting to the corresponding grounding contacts of the contact modules. The wafer forms a plurality of transverse grooves to receive corresponding grounding bars each having a plurality of inward parts respectively mechanically and electrically connecting to the grounding plate, and a plurality of outward parts respectively mechanically and electrically connecting to the grounding contacts of the contact modules.
US11081838B2	Electrical connector part having a locking element An electrical connector part for connecting to a mating electrical connector part includes: a housing that has an insertion portion for making a plug-in connection with the mating electrical connector part, and a locking element, arranged moveably on the housing, for locking the mating electrical connector part to the housing in a locked position, and which is movable out of the locked position in order to release the locking connection between the mating electrical connector part and the housing when in an unlocked position; and a connecting device that connects the locking element to the housing and has a guide portion, a guide element guided at the guide portion, and a spring element, the spring element having a locking leg for latching the guide element to the guide portion in the locked position and/or the unlocked position.
US11081837B2	Multi core plug in electrical connection structure for logging while drilling tools The present invention relates to multi-core plug-in electrical connection structures, in particular to a multi-core plug-in electrical connection structure for logging while drilling tools, which comprises a socket shell with a guiding function arranged at an end of a logging while drilling tool A and a plug shell with a guiding function arranged at an end of a logging while drilling tool B; wherein the socket shell is provided with a socket inner core with a buffering effect therein; and the plug shell is provided with a plug inner core with a buffering effect therein. The present invention has the following beneficial effects: with the above technical scheme, multi-core electrical connection between downhole logging while drilling tools can be achieved, the electrical connection pins can be increased to 25 pins or more, mixed heavy current and light current connections can be realized, and the electrical connection structure is simple with short axial dimension, good anti-vibration performance, and reliable connection. The blind insertion and the convenient connection can be realized.
US11081834B2	Waterproof USB socket and manufacturing method of the same A waterproof USB socket includes a connector, a metal housing, a waterproof glue filled in a tail portion of the connector, and a waterproof ring. The connector includes a metal intermediate plate, first and second terminal groups, and an insulating body. The insulating body includes a base portion, a step portion formed by extending forward from the base portion, and a docking portion formed by extending forward from the step portion. The metal housing includes an inner metal shell having a seamless outer wall. A stopping member is integrally formed on the base portion of the insulating body, and includes a spot-welding platform and a stopping portion; and the spot-welding platform of the stopping member is in contact with the inner metal shell and the two are fixed into one piece by means of spot-welding. The present disclosure further provides a manufacturing method of the waterproof USB socket.
US11081833B2	Electrical connector An electrical connector includes a contact module essentially composed of a plurality of contacts integrally formed within an insulator via an insert-molding process. The insulator includes a base, tongue extending forwardly from the base, and a mounting port extending rearwardly from the base. The contact includes a front contacting section exposed upon the tongue, a rear soldering tail exposed outside of the base and a middle retaining section therebetween. A groove is formed between the base and the mounting port to expose middle sections of the contacts. An insulative housing is over molded upon the contact module for not only forming an exterior structure of the connector but also filling the groove for enhancing sealing between the contacts and the insulator.
US11081831B2	Waterproof connector A waterproof connector includes a housing including a first tubular portion forming a first end of the housing and a second tubular portion forming a second end of the housing, an inner member to hold a terminal, a seal member having a wire insertion hole, the seal member being to be attached to the second tubular portion at the second end of the housing and a filler filling a space inside the housing and between the inner member and the seal member. The housing has a bent structure. The second tubular portion includes a recessed portion on an inner peripheral portion on a side where an inside corner of the bent structure of the housing is provided. The seal member includes a protruding piece to be fitted into the recessed portion when the seal member is attached to the second tubular portion.
US11081827B2	Protecting cover and board edge connector The present disclosure provides a protecting cover and a board edge connector. The protecting cover is used to a board edge connector. An insulating housing of the board edge connector comprises a board edge slot and a tower portion at least positioned at an end of the board edge slot. Two positions of the tower portion provide a guiding groove and a pair of clamping arms, the guiding groove and the pair of clamping arms are spaced apart from each other, therefore, in the mating process and the unmating process, it maintains stable path and position and provides a holding force. A side edge portion of the protecting cover comprises a stopping block. The stopping block can correspondingly stop onto an inner wall of the tower portion, prevent warpage or deflection deformation of the insulating housing.
US11081826B2	Connector having offset terminal connecting portions A connector (1) includes a housing (2), a first terminal (31) and a second terminal (32). The terminals (31, 32) are side by side and parallel. One end of each terminal is inserted into the housing (2) and the other end projects from the housing (2). Each of the terminals (31, 32) includes a base (33) projecting from the housing (2) and a connecting portion (34) that is wider than the base (33) toward both sides in an arrangement direction (Y) of the first and second terminals (31, 32). The connecting portion (34) of the first terminal (31) projects farther from the housing (2) than the connecting portion (34) of the second terminal (32). An insulating member (4) is at a position adjacent to the connecting portion (34) of the second terminal (32) in the arrangement direction (Y) on a surface of the base (33) of the first terminal (31).
US11081822B2	Printed circuit board having commoned ground plane An electrical connector includes a substrate that includes a plurality of ground traces at first and second surfaces of the substrate, and a ground coupling assembly that couples pairs of ground traces at each of the first and second surfaces, and further couples the ground traces at the first surface to the ground traces at the second surface.
US11081821B2	Direct mate cable assembly A communication system includes a circuit board having circuit board signal and ground contacts on the upper surface. The communication system includes a cable assembly having a housing holding a cable module with cables. A ground shield and signal contacts are electrically connected to the cables. The ground shield includes ground beams with ground mating interfaces coupled to corresponding circuit board ground contacts. Each signal contact has a terminating pad terminated to the cable conductor and a signal beam with a signal mating interface coupled to the circuit board signal contact. The housing includes contact channels receiving the signal and ground beams with the mating interfaces exposed for interfacing with the circuit board.
US11081819B2	Electrical connector using a metallic sliding block to hold an inner insulator during the overmolding of an outer insulator onto the inner insulator An electrical connector includes an insulative housing having a first insulator integrally formed with the contacts via an insert-molding process, and a second insulator, i.e., the cover, overmolded upon the first insulator wherein an internal cavity is formed within the housing and between the first insulator and the second insulator in the transverse direction, through which a sliding block presses the first insulator in position in the transverse direction during overmolding the second insulator.
US11081817B2	Connector having terminals with bent portions A connector (1) includes a housing (2) and first and second terminals (31, 32). One end of each terminal (31, 32) is inserted into the housing (2) and the other end thereof projects from the housing (2). Each terminal (31, 32) includes a base (33) projecting from the housing (2) and a connecting portion (34) that is wider than the base (33) toward both sides in a (Y) direction. The connecting portion (34) of the first terminal (31) projects farther from the housing (2) than the connecting portion (34) of the second terminal (32) in an (X) direction. The base (33) includes a flat plate (330) having a thickness in a (Z) direction. A side part of the base (33) of the first terminal (31) adjacent to the connecting portion (34) of the second terminal 32 in the (Y) direction is bent with respect to the flat plate (330).
US11081814B2	Wiring module Provided is a wiring module with a reduced weight. The wiring module is a vehicle-mounted wiring module that includes a conductor plate formed from a conductor that supplies power from an electricity storage device to an electric device. The wiring module includes a flat, conductive first conductor plate, a flat, conductive second conductor plate, and a conductive first coupling member. The first conductor plate has a first cross-sectional area. The second conductor plate has a second cross-sectional area smaller than the first cross-sectional area is, and is to be connected to the first conductor plate. The first coupling member couples the first conductor plate and the second conductor plate to each other.
US11081811B2	Transmitter A controller of a transmitter outputs cyclically different digital data to equivalent transmission circuits, that is, RF circuits to generate a rotation polarized wave.
US11081810B2	TFT substrate and scanned antenna having TFT substrate A TFT substrate includes a dielectric substrate, a plurality of antenna element regions provided on the dielectric substrate, each antenna element region including a TFT and a patch electrode electrically connected to a drain electrode of the TFT, and a flattening layer provided on the dielectric substrate, located above a layer including the patch electrode, and formed of a resin.
US11081807B2	Electronic device comprising array antenna An antenna device is provided and includes a plurality of antenna radiators arranged in an array, a ground member in operable communication with the plurality of antenna radiators, a plurality of conductive cells arranged on the plurality of antenna radiators, and a plurality of feeding lines electrically connected to the plurality of antenna radiators.
US11081806B2	Antenna apparatus An antenna apparatus includes a first feed line and a second feed line spaced apart from each other, a ground plane surrounding a portion of each of the first and second feed lines, a first end-fire antenna pattern and a second end-fire antenna pattern having different sizes spaced apart from each other, spaced apart from the ground plane, and respectively electrically connected to the first and second feed lines, and a first feed via and a second feed via respectively electrically connecting the first and second feed lines to the first and second end-fire antenna patterns. The first feed via extends away from the first feed line in one direction, and the second feed via extends away from the second feed line in another direction different from the one direction.
US11081805B2	Antenna array and collision avoidance radar having the same An antenna array is provided, which may include a connection portion and a plurality of antenna units. The antenna units may be disposed on the two sides of the connection portion respectively. The proximal end of each of the antenna units may be connected to the connection portion and the distal end of one or more of the antenna units may be grounded. The length of each of the antenna units may be less than or equal to ¼ wavelength of the operating frequency of the antenna array, and the distance between any two adjacent antenna units may be less than or equal to ½ wavelength of the operating frequency of the antenna array.
US11081804B2	Antenna-integrated type communication module and manufacturing method for the same A multilayer substrate includes a first dielectric layer and a conductor pattern disposed in at least an interior of the first dielectric layer. A second dielectric layer formed of a different material from a material of the first dielectric layer is disposed on the multilayer substrate. At least one radiation element is formed on the second dielectric layer. A feeding wire connects the radiation element and the conductor pattern. The feeding wire includes a conductor pin that is conductive and extends in a thickness direction of the second dielectric layer. The conductor pin electrically connects the radiation element and the conductor pattern. Provided is an antenna-integrated type communication module having such a structure that the accuracy of circuit simulation is easily enhanced and the degree of freedom in selection of dielectric materials is large.
US11081803B2	Instrument comprising plane lens antenna and control method thereof Various embodiments of the present invention pertain to an instrument comprising a plane lens antenna and a control method thereof. Particularly, embodiments pertain to an instrument comprising a plane lens antenna capable of adjusting the gain and/or coverage of a wireless communication radio wave, and to a control method of the instrument. The instrument according to the various embodiments may comprise: a first plane lens antenna in which a plurality of unit cells are disposed in a predetermined pattern; and a first support member for retaining the first plane lens antenna such that the antenna can have a predetermined distance with an external antenna device.
US11081801B2	Cavity backed antenna with in-cavity resonators A compact wideband RF antenna for incorporating into a planar substrate, such as a PCB, having at least one cavity with a radiating slot, and at least one transmission line resonator disposed within a cavity and coupled thereto. Additional embodiments provide stacked slot-coupled cavities and multiple coupled transmission-line resonators placed within a cavity. Applications to ultra-wideband systems and to millimeter-wave systems, as well as to dual and circular polarization antennas are disclosed. Further applications include configurations for an antenna based on a monopole element and having a radiation pattern that is approximately isotropic.
US11081800B2	Dual-polarized antenna The present disclosure relates to a dual-polarized antenna comprising a dipole radiator, a resonant cavity radiator and a reflector. The resonant cavity radiator is arranged below the reflector and radiates through a slot in the reflector, and the dipole radiator is arranged above the reflector, with a signal line and/or a carrier of the dipole radiator extending through the slot.
US11081798B2	Low-complexity full-duplex radio system with enhanced digital self-interference cancellation A full-duplex radio system includes a monostatic antenna, digital self-interference cancellation (DSIC) and cyclic prefix noise reduction (CPNR) method and circuitry applying said method suitable for orthogonal frequency division multiplexing (OFDM) based full-duplex wireless communications. Said system, method and circuitry applying said method are implementable within the paradigm of in-band full-duplex (IBFD) monostatic antenna architecture, an embodiment of which comprises a dual-polarized, slot-coupled antenna.
US11081796B2	Full duplex using OAM A system for providing full-duplex communications comprises a first transceiver for simultaneously transmitting first signals having a first orthogonal function applied thereto on a first channel and simultaneously receiving second signals having a second orthogonal function applied thereto at a same time. A second transceiver simultaneously receives the first signals having the first orthogonal function applied thereto on the first channel and simultaneously transmits the second signals having the second orthogonal function applied thereto at the same time. Application of the first orthogonal function to the first signals and application of the second orthogonal function to the second signals prevents interference between the first signals and the second signals.
US11081795B2	Antenna structure and electronic device including the same An electronic device is provided. The electronic device includes a communication circuit configured to communicate with an external device, and a processor configured to control the communication circuit, wherein the communication circuit includes a coil antenna including a first coil of a loop type which rotates with a number of times in a first direction, and a second coil of a loop type which is extended from the first coil, configured to rotate with a number of times in a second direction, and spaced from the first coil by a specific distance, and an antenna control circuit electrically connected with the coil antenna and configured to transmit or receive a signal with the coil antenna.
US11081791B2	Wireless communication device, control method, and program The present invention is provided with: a plurality of antenna units each including a plurality of antenna elements and a partial synthesizer that synthesizes first output signals of the respective antenna elements and outputs a second output signal; a partial power detection means that measures signal intensities of the respective second output signals; a position determination unit that determines the position of a communication device serving as a communication target based on the measured signal intensities of the respective second output signals; a summing synthesizer that synthesizes the second output signals of the plurality of antenna units and outputs a third output signal; and a phase control unit that controls phases of the respective antenna elements such that a main lobe, which is a beam having a maximum signal intensity for the third output signal, is directed to the position of the communication device determined by the position determination unit.
US11081790B2	Scanned antenna and method of inspecting scanned antenna A scanning antenna includes a TFT substrate including a plurality of patch electrodes, a slot substrate including a slot electrode, and a liquid crystal layer provided between the TFT substrate and the slot substrate. The slot electrode includes a plurality of slots disposed corresponding to the plurality of patch electrodes and a solid portion not including the plurality of slot. When viewed from a normal direction of the substrate, the patch electrode is disposed across the slot in a first direction and overlaps the solid portion at both ends of the slot in each of a plurality of antenna units, and when viewed from the normal direction of the substrate, at least one of a periphery of the solid portion and a periphery of the patch electrode includes a recessed portion or a protruding portion in at least one antenna unit of the plurality of antenna units.
US11081789B2	Base station antennas including wiper phase shifters Base station antennas are provided herein. A base station antenna includes first and second wiper phase shifters. In some embodiments, the base station antenna includes first and second wiper supports that are on the first and second wiper phase shifters, respectively, and the first wiper support includes a portion that is beside and interlocked with a portion of the second wiper support. In some embodiments, the base station antenna includes a first linkage that is on the second wiper phase shifter, and a second linkage that intersects, and is coupled to, the first linkage and is configured to adjust the first and second wiper phase shifters via the first linkage. In some embodiments, the first and second wiper phase shifters are a mirror-image pair of wiper phase shifters. Related methods of operating a base station antenna are also provided.
US11081788B1	System and method for near-field testing of a phased array antenna A near-field test system for a phased array antenna includes a probe, a beam forming network, and a computing system. The probe is disposed at a fixed position in a near-field of the antenna and is configured to receive at least a portion of a test beam radiated by the antenna. The beam forming network is coupled to the antenna and includes a plurality of phase shifters configured to steer the test beam to a position in the near-field when radiated by an array of antenna elements of the antenna. The computing system is coupled to the probe and is configured to normalize received power of the test beam based on the position of the beam in the near-field relative to the fixed position of the probe, and generate a far-field antenna pattern for the antenna from normalized received power of the test beam.
US11081785B2	Antenna module An antenna module includes a grounding conductor, a first radiator, a second radiator, and a grounding component. The grounding conductor has a grounding function. The first radiator includes a first feeding portion and a first radiating portion. The second radiator includes a second feeding portion and a second radiating portion. The grounding component is located between the first radiator and the second radiator, and includes a first coupling portion, a second coupling portion, a capacitor, and a first grounding portion. The first radiating portion is spaced apart from the first coupling portion and the second radiating portion is spaced apart from the second coupling portion. The capacitor is located among the first coupling portion, the second coupling portion, and the first grounding portion. The first grounding portion is connected to the grounding conductor.
US11081781B1	Cellular base station keyed cable connectors Various arrangements of a connection system are presented. The system can include radio cable ports. Each radio cable port may be communicatively connected with a different antenna of an antenna system. Each radio cable port may be keyed different such that only a particular keyed cable assembly can be mated with the radio cable port. The system can also include antenna cable ports. Each antenna cable port can be configured to be communicatively connected with a different radio of a radio system. Each antenna cable port may be keyed different such that only a particular keyed cable assembly can be mated with the antenna cable port. Each radio cable port is keyed in a same pattern as an antenna cable port with which the radio cable port is intended to be communicatively connected.
US11081780B2	Multi-band antenna architecture Disclosed is a multi-band antenna architecture, provided in a matrix of a wireless communication device, including: a first antenna, typically an LTE antenna, located in left outer side and right outer side areas of the matrix, a second antenna, typically a Sub-6 GHz MIMO antenna, located in upper outer side and lower outer side areas of the matrix, and a third antenna, typically a millimeter-wave antenna, located in left inner side and right inner side areas of the matrix. The above-mentioned areas are spaced from each other. The first antenna, the second antenna, and the third antenna work at different frequency bands. The third antenna can implement broadband and large-angle beam scanning.
US11081779B2	Electronic device having an antenna An electronic apparatus capable of reducing specific absorption rate (SAR) is disclosed. The antenna device includes an antenna element to which power is supplied, and at least one resonant antenna element which is disposed such that the longitudinal direction thereof and the longitudinal direction of the antenna element are substantially parallel to each other and which can resonate with the antenna element.
US11081775B2	Actuating support member A deployable structure includes a plurality of interconnected elongated support members, deployed from a stowed state to an expanded state in which the support members are arranged in a ring. Each support member is provided with a connector (28) for longitudinal movement during deployment with respect to the support member. An actuating support member (27) has a drive member (50) for longitudinal movement with respect to the actuating support member, and an electromagnetic device arranged to drive the drive member in one direction with respect to the actuating support member. The drive member is connected to the connector by a lost motion connector, thus the connector is capable of moving in said one direction even if the drive member is not moved by the electromechanical device.
US11081773B2	Apparatus for splitting, amplifying and launching signals into a waveguide to provide a combined transmission signal An apparatus includes a signal splitter configured to receive an input signal for transmission and to split the input signal to form two or more sub-signals. The apparatus further includes a first amplifier configured to generate a first amplified sub-signal, a second amplifier configured to generate a second amplified sub-signal, a first launcher coupled to the first amplifier and to a waveguide, and a second launcher coupled to the second amplifier and to the waveguide. The first and second launchers are coupled to the waveguide such that a first radiative signal generated by the first launcher responsive to the first amplified sub-signal and a second radiative signal generated by the second launcher responsive to the second amplified sub-signal are combined in the waveguide to form a transmission signal corresponding to the input signal.
US11081772B2	Antenna device and receiver An antenna device in which two antenna elements are provided on both sides of an insulation substrate and at least one of the antenna elements includes a metal wire that is capable of holding shapes of two or more elements and is capable of being bent so as to flexibly deform the shape of the antenna element.
US11081770B2	Low temperature co-fireable dielectric materials Disclosed herein are embodiments of low temperature co-fireable dielectric materials which can be used in conjunction with high dielectric materials to form composite structures, in particular for isolators and circulators for radiofrequency components. Embodiments of the low temperature co-fireable dielectric materials can be scheelite or garnet structures, for example barium tungstate. Adhesives and/or glue is not necessary for the formation of the isolators and circulators.
US11081769B2	RF dielectric waveguide duplexer filter module An RF dielectric waveguide duplexer filter module with antenna and lower and upper Tx and Rx signal transmission blocks of dielectric material attached together in a side-by-side and stacked relationship. The blocks are covered with conductive material. Antenna and Tx and Rx input/outputs are defined at opposite ends of the filter module. RF signal transmission windows define direct coupling RF signal transmission paths between the antenna and the Tx and Rx blocks and between the lower and upper Tx and Rx blocks. One or more bridges of dielectric material on the lower Tx and Rx blocks define inductive cross-coupling Tx and Rx signal transmission paths. The Tx signal is transmitted only in the direction of the antenna block or between the upper and lower Tx blocks. The Rx signal is transmitted only in the direction of the Rx RF signal input/output or between the upper and lower Rx blocks.
US11081768B2	Fabricating an RF filter on a semiconductor package using selective seeding A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.
US11081767B2	Multilayered filter device A multilayered filter device includes a multilayer stack, a band pass filter, a first band elimination filter, and a second band elimination filter. The band pass filter and the first and second band elimination filters are each constructed using the multilayer stack. The band pass filter includes a plurality of first resonators with open ends. Each band elimination filter includes a connection path, and a second resonator coupled to the connection path. The connection path includes an impedance transformer. The second resonator includes a conductor line constituting a distributed constant line.
US11081759B2	Secondary battery The present invention provides a secondary battery 1 including: a battery case 10 having a safety valve 13; an electrode body 40; an electrolyte; and a cover member 41 arranged between the safety valve 13 and the electrode body 40 so as to be separated from the safety valve 13. The electrode body 40 is housed in the battery case 10 so that a lamination surface opposes the safety valve 13. The cover member 41 is configured to cover a portion of the battery case 10 in which the safety valve 13 is formed in a state where the cover member 41 holds the lamination surface of the electrode body 40.
US11081758B2	Cover for a battery housing of a high-voltage vehicle battery and battery housing A cover for a battery housing of a high-voltage vehicle battery. The cover includes a composite material which for its part comprises a polymer matrix and an at least fire retardant material embedded in said polymer matrix. In addition, the cover includes an electrically conductive layer which forms an electromagnetic shield.
US11081756B2	Power bank for electronic cigarette A power bank includes a face shell; a back shell; a first panel; a second panel; an on-off button; a power adjustment button; a thread ring; a seal ring; a first electrode; a spring; an insulator; a sleeve piece; a second electrode; a silica seal; a battery cell; a control board; a silicone pad; a fixed ring; a display screen; and a light guide film. The face shell and the back shell are combined to form a cylinder including a first end and a second end. The face shell includes a front face and a back face, and the first panel and the second panel are attached to the front face and the back face, respectively. The first panel includes a first groove and a second groove, and the on-off button and the power adjustment button are disposed in the first groove and the second groove, respectively.
US11081752B2	Square secondary battery and method of manufacturing same A square secondary battery includes an electrode body including a positive electrode plate and a negative electrode plate, a square outer package housing the electrode body, a metal sealing plate sealing an opening of the square outer package, and a positive electrode collector electrically connected to the positive electrode plate and the sealing plate. The positive electrode collector includes a base portion disposed to oppose the sealing plate, and a lead portion extending from an edge portion of the base portion towards the electrode body. In a short direction of the sealing plate, a boundary between the base portion and the lead portion is positioned on a first side with respect to a center of the sealing plate, and a connection between the sealing plate and the base portion of the positive electrode collector is offset to a second side with respect to the center of the sealing plate.
US11081751B2	Battery cover and method of construction thereof A flexible, insulative battery cover and method of construction thereof are provided. The batter cover includes a flexible, tubular wall circumferentially bounding a cavity extending between a bottom end and a top end. The flexible, tubular wall has a composite outermost layer, a first thermoplastic innermost layer, and a nonwoven intermediate layer. The nonwoven intermediate layer is sandwiched between the composite outermost layer and the first thermoplastic innermost layer. The composite outermost layer includes a reflective outermost thermoplastic layer, a second thermoplastic innermost layer and a metal layer sandwiched between the reflective outermost thermoplastic layer and the second thermoplastic innermost layer.
US11081743B2	Battery module with heat dissipating encapsulant material and methods therefor Disclosed herein, is a battery module that comprises an encapsulant material exhibiting improved thermal transfer and heat dissipation characteristics. In one example embodiment, the battery module comprises a “stack” of cells, wherein at least some of the cells, and optionally each cell, is not separated by a metal plate or tab-shaped heat sink layer, and instead, the cells are substantially surrounded by an encapsulant material and stacked directly upon one another.
US11081723B2	Energy storage device and energy storage device production method An energy storage device includes: an electrode body including curved portions formed by winding an electrode; a container in which the electrode body is accommodated; and a cover plate structure including a cover plate closing the container. The electrode body is accommodated in the container while one end portion in a winding axis direction of the electrode body faces the cover plate structure. The energy storage device includes spacers (side spacers) that are attached to curved portions, and one end portion of the spacer abuts on a part of the cover plate structure.
US11081713B2	Fuel cell activation method A voltage is applied between an anode and a cathode in a fuel cell. The voltage is increased to a predetermined upper limit, and then decreased to a predetermined lower limit. The voltage increase and decrease are repeated a predetermined number of times. The voltage is applied to the fuel cell while supplying a hydrogen-containing gas to an anode and supplying an inert gas to a cathode.
US11081710B2	Power-on shutdown of fuel cell power plant for enhanced durability A technique is disclosed of modified shutdown of a fuel cell power plant (14) having a fuel eel! stack assembly (26) contained with and supplying electrical power to a mobile vehicle (12). The -vehicle characteristically proceeds at intervals to a station. (10) containing one or more resources (20, 20A, 20B, 20C, etc) utilized by the fuel cell power plant, for resupply thereof. One such, resource provided at/by the station is electrical energy (20A), aid operation of the fuel cell power plant (14) is controlled to utilize the availability of that electrical energy (20A) to maintain, an active protective Hydrogen On condition for greatly extended intervals, for example many hours to several days or longer, via a Power On mode of operation. The Power On mode maintains at least a low level of hydrogen introduction and circulation sufficient to maintain a predetermined presence, e.g., pressure, of hydrogen at the fuel cell stack assembly (26).
US11081707B2	Fuel cell The invention relates to a fuel cell (2), comprising at least one membrane-electrode unit (10) having a first electrode (21) and a second electrode (22), which are separated from each other by a membrane (18), and at least two bipolar plates (40), which connect the membrane-electrode unit (10) on both sides, wherein the bipolar plates (40) are penetrated by a first supply channel, for supplying a fuel, and by a second supply channel, for supplying an oxidation means, wherein a first distribution structure (50) facing the first electrode (21) connects to a first edge of the first supply channel, and a second distribution structure (60) facing the second electrode (22) connects to a second edge of the second supply channel. The first electrode (21) extends along the membrane (18) in a region which is spaced apart from the first edge of the first supply channel, and the second electrode (22) extends along the membrane (18) in a region which is spaced apart from the second edge of the second supply channel.
US11081706B2	Fuel cell stack A fuel cell stack includes a stack body of power generation cells stacked in a horizontal direction. An oxygen-containing gas flow field is formed in the fuel cell stack, for allowing an oxygen-containing gas to flow along an electrode surface of a membrane electrode assembly. A plurality of oxygen-containing gas discharge passages for discharging the oxygen-containing gas as a reactant gas pass through the fuel cell stack in a stacking direction of the power generation cells. Each of the oxygen-containing gas discharge passages is connected to an outlet. The plurality of oxygen-containing gas discharge passages are connected together by a first connection channel at an end opposite to the outlet.
US11081705B2	Alloy member An alloy member includes a base member constituted by an alloy material containing chromium, a chromium oxide layer for covering at least a portion of a surface of the base member, a pore that is formed in an interface region of the base member that is located 30 μm or less from an interface between the chromium oxide layer and the base member, and an extending portion extending from the pore into the base member. The pore is configured to inhibit the separation of the chromium oxide layer from the base member The extending portion contains an oxide of an element whose equilibrium oxygen pressure is lower than that of a major element of the base member.
US11081701B2	Secondary battery A secondary battery includes an electrode structure, the electrode structure includes a positive electrode changing in volume by expansion or contraction during discharging or charging, and a negative electrode changing in volume in a reverse way to the positive. The positive electrode and the negative electrode have a volume ratio of 1.1 or more, the volume ratio being a value obtained by dividing the volume under expansion by the volume under contraction, and the positive electrode or the negative electrode has the volume ratio of 1.9 or more, and has a total volume ratio of 1.2 or less, the total value ratio being a value obtained by dividing a larger value by a smaller value with respect to a total volume of the positive electrode and the negative electrode in a discharged state and a total volume of the positive electrode and the negative electrode in a charged state.
US11081696B2	Beta-delithiated layered nickel oxide electrochemically active cathode material and a battery including said material The invention is directed towards an electrochemically active cathode material. The electrochemically active cathode includes beta-delithiated layered nickel oxide and an electrochemically active cathode material selected from the group consisting of manganese oxide, manganese dioxide, electrolytic manganese dioxide (EMD), chemical manganese dioxide (CMD), high power electrolytic manganese dioxide (HP EMD), lambda manganese dioxide, gamma manganese dioxide, beta manganese dioxide, and mixtures thereof. The beta-delithiated layered nickel oxide has an X-ray diffraction pattern. The X-ray diffraction pattern of the beta-delithiated layered nickel oxide includes a first peak from about 14.9° 2θ to about 16.0° 2θ; a second peak from about 21.3° 2θ to about 22.7° 2θ; a third peak from about 37.1° 2θ to about 37.4° 2θ; a fourth peak from about 43.2° 2θ to about 44.0° 2θ; a fifth peak from about 59.6° 2θ to about 60.6° 2θ; and a sixth peak from about 65.4° 2θ to about 65.9° 2θ.
US11081692B2	Composite electrodes The present invention pertains to an electrode-forming composition, to use of said electrode-forming composition in a process for the manufacture of a composite electrode, to said composite electrode and to a secondary battery comprising said composite electrode.
US11081690B2	Compositions and uses thereof A silicon-carbon particulate composite suitable for use as active material in a negative electrode of a Li-ion battery, a precursor composition comprising the silicon-carbon particulate composite, a negative electrode comprising the silicon-carbon particulate composite and/or precursor composition, a Li-ion battery comprising the negative electrodes, a method of manufacturing the silicon-carbon particulate composite, precursor composition, negative electrode and Li-ion battery, the use of the silicon-carbon particulate composite in a negative electrode of a Li-ion battery to inhibit or prevent silicon pulverization during cycling, for example, during 1st cycle Li intercalation or de-intercalation and/or to maintain electrochemical capacity after 100 cycles, and a device, energy storage cell, or energy storage and conversion system comprising the silicon-carbon particulate composite and/or precursor composition.
US11081683B2	Method for estimating filter clogging with slurry for electrode preparation A method for predicting the likelihood of coagulation of active material particles contained in a slurry for electrode preparation includes measuring rheological properties before and after the slurry is subjected to a shear. The estimation method enables a prediction of filter clogging with a slurry, and thus makes it possible to estimate the likelihood of filter clogging with a slurry without passing the slurry directly through the filter, thereby improving the efficiency of a battery manufacturing process.
US11081682B2	Fabricating method of electrode assembly and electrochemical cell containing the same A fabricating method of an electrode assembly according to the present invention includes forming a radical unit having a four-layered structure obtained by stacking a first electrode, a first separator, a second electrode, and a second separator one by one, and stacking at least one radical unit one by one to form a unit stack part.
US11081678B2	Display panel, method for fabricating the same, and display device A display panel, a method for fabricating the same, and a display device are disclosed, where the display panel includes: a base substrate, sub-pixel units in at least two colors on the base substrate, and an anti-reflection layer on a side of the sub-pixel units away from the base substrate, wherein the anti-reflection layer includes anti-reflection components arranged in an array, which correspond to the sub-pixel units in a one-to-one manner, and are configured to alleviate reflected light in the same colors as the corresponding sub-pixel units, and sub-pixel units in different colors correspond to different anti-reflection components.
US11081669B2	Encapsulation film The present application relates to an encapsulation film, a method for producing the same, an organic electronic device comprising the same, and a method for preparing an organic electronic device using the same, which allows forming a structure capable of blocking moisture or oxygen introduced into an organic electronic device from the outside, and can effectively release heat accumulated inside the organic electronic device and prevent occurrence of bright spots of the organic electronic device.
US11081663B2	Organic electroluminescent display panel with auxiliary electrodes, method for manufacturing the same, and display device using the same An organic electroluminescent display panel is provided, comprising a planarization layer; a pixel electrode formed on the planarization layer; and an auxiliary electrode coated by the planarization layer. The planarization layer defines a contact hole extending to a top surface of the planarization layer to have the auxiliary electrode contacted with the corresponding pixel electrode. A display device comprising the organic electroluminescent display panel and a method for manufacturing the organic electroluminescent display panel are further provided.
US11081662B2	Photoelectric conversion element and solar cell A photoelectric conversion element is provided. The photoelectric conversion element comprises a substrate, a first electrode, an electron transport layer, a hole transport layer, and a second electrode. The electron transport layer comprises a photosensitizing compound. The hole transport layer comprises a basic compound A and an ionic compound B. The basic compound A is represented by the following formula (1): where each of R1 and R2 independently represents an alkyl group or an aromatic hydrocarbon group, or R1 and R2 share bond connectivity to form a nitrogen-containing heterocyclic ring; and the ionic compound B is represented by the following formula (2): where X+ represents a counter cation.
US11081661B2	Flexible organic light-emitting diode panel The present invention provides a flexible organic light-emitting diode (OLED) panel, including: a flexible substrate which includes a channel; a buffer layer disposed on the second organic layer, the buffer layer including a buffer layer groove; a first block wall disposed on the buffer layer, the first block wall surrounding the buffer layer groove and defining a display region; a second block wall disposed on the buffer layer and over the channel, the second block wall surrounding the first block wall; and a packaging layer disposed in the display region, the packaging layer including an organic packaging layer, a portion of the organic packaging layer being disposed in the buffer layer groove and in contact with the flexible substrate.
US11081660B2	Display device and support film structure for display device A display device includes a display panel, a support film, and a polymer layer. The display panel includes a display area comprising a first area that is bendable, and a non-display area adjacent to the display area. The support film is coupled to a bottom surface of the display panel. The support film includes a first groove overlapping with the first area. The polymer layer is disposed in the first groove. The polymer layer includes a material with higher flexibility than the support film. Angles formed by a top surface of the support film and inner sides of the support film defining the first groove are acute angles.
US11081658B2	Organic electroluminescent materials and devices A novel compound is disclosed which includes a ligand LA of Formula I, Formula II, Formula III, or Formula IV: wherein: ring B is independently a 5-membered or 6-membered carbocyclic or heterocyclic ring; X1 to X4 are each independently selected from the group consisting of C, N, and CR; at least one pair of adjacent X1 to X4 are each C and fused to a structure of Formula V where indicated by “”; X5 to X12 are each independently C or N; the maximum number of N within a ring is two; Z and Y are each independently selected from the group consisting of O, S, Se, NR′, CR′R″, SiR′R″, and GeR′R″; RB and RC each independently represents zero, mono, or up to a maximum allowed substitutions to its associated ring; each of RB, RC, R, R′, and R″ is independently hydrogen or a substituent selected from the group consisting of deuterium, halogen, alkyl, cycloalkyl, heteroalkyl, heterocycloalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carboxylic acid, ether, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, boryl, and combinations thereof; and two substituents can be joined or fused to form a ring; the ligand LA is complexed to a metal M through the two indicated dash lines of each Formula; and the ligand LA can be joined with other ligands to form a tridentate, tetradentate, pentadentate, or hexadentate ligand.
US11081657B2	Radiation detector According to one embodiment, a radiation detector includes a first conductive layer, a second conductive layer, and a first layer. The first layer is provided between the first conductive layer and the second conductive layer. The first layer includes a first region and a second region. The first region includes a metal complex including a first metallic element. The second region includes an organic semiconductor material. The first metallic element includes at least one selected from the group consisting of Ir, Pt, Pb, and Cu.
US11081654B2	Blue light TADF material, preparation method thereof and electroluminescent device The present invention provides a blue light thermally activated delayed fluorescence (TADF) material, a preparation method thereof, and an electroluminescent device. The blue TADF material achieves high luminous efficiency and TADF efficiency to realize excellent solubility by attaching an alkyl chain for increasing solubility to a periphery of the blue light TADF material, and by attaching a tert-butylcarbazole unit having a high energy state to an end of the alkyl chain of the blue light TADF material, thereby allowing the material to be processed by solution spin coating, and the terminal carbazole can act as a host, enabling non-doping of a luminescent layer while effectively avoiding phase separation.
US11081649B2	Compound for organic electronic element, organic electronic element using same, and electronic device thereof Provided are a compound represented by Formula 1, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode and comprising the compound of Formula 1, and an electronic device comprising the element, where the driving voltage of the organic electronic device is lowered, and the luminous efficiency and life time of the organic electronic device is improved.
US11081647B2	Organic electroluminescent materials and devices The present invention relates to novel light-emitting materials. These materials comprise a non-aromatic spiro polycyclic group. This new side chain could reduce the stacking of the light-emitting materials and result in high PLQY.
US11081644B2	Apparatuses including electrodes having a conductive barrier material and methods of forming same Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.
US11081641B2	Magnetoresistance effect element, magnetic memory, and method for manufacturing magnetoresistance effect element The present invention provides a magnetoresistance effect element which has a high thermal stability factor Δ and in which a magnetization direction of a recording layer is a perpendicular direction with respect to a film surface, and a magnetic memory including the same. Magnetic layers of a recording layer of the magnetoresistance effect element are divided into at least two, and an Fe composition with respect to a sum total of atomic fractions of magnetic elements in each magnetic layer is changed before stacking the magnetic layers.
US11081634B2	Use of selective hydrogen etching technique for building topological qubits Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.
US11081632B2	Micro-LED chips and methods for manufacturing the same and display devices The present disclosure relates to micro-LED chips, methods for manufacturing the same, and display devices. The micro-LED chip includes: a driving backplane including at least one first electrode, a groove being provided above the first electrode, and the first electrode being located at a bottom of the groove; the groove being filled with a conductive material, and the conductive material being obtained by curing a corresponding conductive ink; and a light emitting chip including at least one second electrode; and the first electrode is connected to the second electrode through the conductive material.
US11081626B2	Light emitting diode packages Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED packages are disclosed. A light-altering material may be provided in particular configurations within an LED package to redirect light toward a primary emission direction. The light-altering material may be arranged on any of a first face, a second face, or a plurality of sidewalls of an LED chip in the LED package. In certain embodiments, a lumiphoric material may be arranged on one or more of the sidewalls. A superstrate may be arranged to mechanically support the LED chip from the first face. The light-altering material may be arranged on or dispersed within the superstrate. In certain embodiments, the primary emission direction of the LED package is substantially parallel to the second face of the LED chip in the LED package. An overall thickness or height of the LED package may be less than or equal to 0.25 mm.
US11081624B2	Method of manufacturing light emitting device having light guiding member in groove A method of manufacturing a light emitting device includes: bonding a plurality of light emitting elements each having an outer peripheral lateral surface onto a light-transmissive substrate; forming at least one groove on the light-transmissive substrate to surround an outer periphery of each of the plurality of light emitting elements; disposing at least one light guiding member in the groove to continuously cover the groove and the outer peripheral lateral surfaces of adjacent ones of the plurality of light emitting elements; and singulating the light-transmissive substrate at a position between adjacent ones of the plurality of light emitting elements, to obtain a plurality of light emitting devices in each of which at least one of the light emitting elements is bonded to a single light-transmissive member.
US11081623B2	Oxygen controlled PVD AlN buffer for GaN-based optoelectronic and electronic devices Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.
US11081619B2	Light-emitting element and method of manufacturing same A method of manufacturing a light-emitting element includes: forming a plurality of masks on a surface of a first conductive semiconductor layer; forming a plurality of rods comprising a first conductive semiconductor by partially removing, in a depth direction, a portion of the first conductive semiconductor layer exposed from the masks by etching; forming an insulating film on the rods and a surface of a the remaining first conductive semiconductor layer; performing wet etching, in a state in which a mask covering the insulating film is not formed, to remove a first portion of the insulating film on lateral surfaces of the rods but retaining a second portion of the insulating film on a surface of the first conductive semiconductor layer; forming a plurality of light-emitting layers covering the lateral surfaces of the rods; and forming a plurality of second conductive semiconductor layers covering outer peripheries of the light-emitting layers.
US11081618B2	Buried activated p-(Al,In)GaN layers Methods for fabricating semiconductor devices incorporating an activated p-(Al,In)GaN layer include exposing a p-(Al,In)GaN layer to a gaseous composition of H2 and/or NH3 under conditions that would otherwise passivate the p-(Al,In)GaN layer. The methods do not include subjecting the p-(Al,In)GaN layer to a separate activation step in a low hydrogen or hydrogen-free environment. The methods can be used to fabricate buried activated n/p-(Al,In)GaN tunnel junctions, which can be incorporated into electronic devices.
US11081609B2	Solar cell structure and composition and method for forming the same A semiconductor structure including a bonding layer connecting a first semiconductor wafer layer to a second semiconductor wafer layer, the bonding layer including an electrically conductive carbonaceous component and a binder component.
US11081607B2	Solar panel comprising notably a structure and at least two photovoltaic cells This solar panel includes a structure in contact with an ambient environment and at least two photovoltaic cells each defining a lateral contact face and including a base element, a grid of electric conductors and a protective element made from transparent material, the grid including at least one conductive wire extending along the lateral contact face. The two cells are arranged on the structure such that at least part of each of the lateral contact faces is arranged regarding the other part while forming a panel surface and such that the shortest path passing through the ambient environment between the opposite parts of the lateral faces of the two cells is equal to at least about 20 mm.
US11081596B2	Semiconductor device and manufacturing device of the same To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.
US11081595B1	Multi-gate transistor and memory device using the same A multi-gate transistor includes: a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.
US11081593B2	Integration of graphene and boron nitride hetero-structure device A microelectronic device includes a gated graphene component. The gated graphene component has a graphitic layer containing one or more layers of graphene. The graphitic layer has a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region. A patterned hexagonal boron nitride (hBN) layer is disposed on the graphitic layer above the channel region. A gate is located over the patterned hBN layer above the channel region. A first connection is disposed on the graphitic layer in the first contact region, and a second connection is disposed on the graphitic layer in the second contact region. The patterned hBN layer does not extend completely under the first connection or under the second connection. A method of forming the gated graphene component in the microelectronic device is disclosed.
US11081591B2	Semiconductor device and display unit A semiconductor device includes a substrate, a first semiconductor auxiliary film, a semiconductor film, a gate insulating film, and a gate electrode. The first semiconductor auxiliary film is provided in a selective region on the substrate. The semiconductor film includes an oxide semiconductor material, and has a low-resistive region in contact with the first semiconductor auxiliary film and a channel region provided in a portion different from the low-resistive region. The gate insulating film covers the semiconductor film from the channel region to at least part of the low-resistive region. The gate electrode is opposed to the channel region of the semiconductor film via the gate insulating film.
US11081585B2	Via structure with low resistivity and method for forming the same A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.
US11081583B2	FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.
US11081582B2	High voltage (HV) metal oxide semiconductor field effect transistor (MOSFET) in semiconductor on insulator (SOI) technology A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.
US11081581B2	Semiconductor device and method of manufacturing the same The n-type body extension region BER is separated from the n+ buried region BL by the p-type impurity region PIR and is in contact with the p-type drift region DFT1. At the end of the n-type body extension region BER closest to the p+ drain region DC, the first portion FP of the n-type body extension region BER located closest to the second surface SS is located closer to the p+ drain region DC than the second portion SP of the n-type body extension region BER located at the first surface FS, and is located closer to the second surface SS than the bottom surface BS of the element isolation insulating film SIS.
US11081580B2	High-voltage semiconductor devices and methods for manufacturing the same A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, and a first high-voltage well region disposed in the semiconductor substrate and having a second conductivity type that is opposite to the first conductivity type. The high-voltage semiconductor device also includes a first buried layer disposed on the first high-voltage well region and having the first conductivity type, and a second buried layer and a third buried layer disposed on the first high-voltage well region and having the second conductivity type, wherein the first buried layer is between the second buried layer and the third buried layer. The high-voltage semiconductor device further includes a source region and a drain region disposed on the first buried layer and having the second conductivity type.
US11081577B2	Electronic device including two-dimensional electron gas and method of fabricating the same An electronic device including a two-dimensional electron gas is provided. The electronic device includes a substrate, a first material layer disposed on the substrate and formed of a binary oxide, a second material layer disposed on the first material layer and formed of a binary oxide, and a two-dimensional electron gas generated between the first material layer and the second material layer.
US11081576B2	Insulated-gate semiconductor device and method of manufacturing the same A method of manufacturing an insulated-gate semiconductor device, includes: digging a gate trench and a dummy trench; burying a dummy electrode in the dummy trench via a gate insulating film and burying a gate electrode in the gate trench via the gate insulating film; exposing an upper portion of the dummy electrode and selectively forming an insulating film for testing so as to cover the gate electrode; depositing a conductive film for testing on the dummy electrode and the insulating film for testing; and selectively testing an insulating property of the gate insulating film in the dummy trench by applying a voltage between the conductive film for testing and the charge transport, region.
US11081567B2	Replacement-channel fabrication of III-V nanosheet devices Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.
US11081564B2	Semiconductor device and method for manufacturing semiconductor device A semiconductor device includes a first electrode, a silicon carbide substrate having a first surface electrically connected with the first electrode and a second surface opposite to the first surface, an ohmic junction layer disposed on the second surface, and a second electrode disposed on the ohmic junction layer. The ohmic junction layer has a first layer that is directly disposed on the second surface and includes a first silicide of titanium and a first silicide of a metal element other than titanium, and a second layer that is directly disposed on the first layer, includes a second silicide of titanium and a second silicide of the metal element, and has a lower titanium concentration than the first layer.
US11081563B2	Formation of silicide contacts in semiconductor devices Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.
US11081561B2	Field-effect transistors with vertically-serpentine gates Structures for a field-effect transistor and methods of forming a field-effect transistor. An isolation region is arranged to surround an active device region, which is composed of a semiconductor material. A trench is arranged in the active device region. The trench includes a bottom surface and a sidewall extending from the bottom surface to a top surface of the active device region. A gate electrode of the field-effect transistor has a first section on the top surface of the active device region, a second section on the bottom surface of the trench, and a third section on the sidewall of the trench.
US11081559B1	Backside contact of a semiconductor device Certain aspects of the present disclosure generally relate to a semiconductor device having a backside gate contact. An example semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region and wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.
US11081556B2	Silicon carbide semiconductor device A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating layer provided on a surface of the silicon carbide substrate, a gate electrode provided on the gate insulating layer, a first insulting layer provided on the gate electrode, a first layer provided on the first insulating layer, a second insulating layer provided on the first insulating layer, and an interconnect layer provided on the second insulating layer. The second insulating layer includes SiN or SiON. The first layer includes one of Ti, TiN, Ta, and TaN. The interconnect layer includes Al or Cu.
US11081555B2	Electronic devices with ultra-high dielectric constant passivation and high mobility materials Dielectric super-junction transistors use combinations high dielectric relative permittivity materials and high-mobility materials. An associated electronic device includes a junction portion of a barrier layer adjacent a gate contact and a drain contact. A layered semiconductor device is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity in the channel layer. The junction portion has a dielectric structure that polarizes carriers within the junction portion such that excess charge on the gate is compensated by an opposite charge in the junction portion of the barrier layer proximate the gate. A sheet charge in the barrier layer is increased to form a depletion region with the channel layer that avoids a conductive parallel channel in the barrier layer to the drain contact.
US11081553B2	Method of forming split gate memory cells A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.
US11081551B2	Method for producing a graphene-based sensor In accordance with an embodiment, a method for producing a graphene-based sensor includes providing a carrier substrate; forming a carrier structure on the carrier substrate, wherein one or more separating structures are formed on an upper side of the carrier structure; and performing a wet chemical transfer of a graphene layer onto the upper side of the carrier structure that comprises the separating structures, where the separating structures and a tear strength of the graphene layer are matched to one another such that the graphene layer respectively tears at the separating structures during the wet chemical transfer.
US11081546B2	Isolation structure for stacked vertical transistors A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.
US11081545B2	Semiconductor device A semiconductor device includes a first conductivity type semiconductor layer having a first surface and a second surface opposite to the first surface and having an element portion formed in the first surface and an outer peripheral portion surrounding the element portion, a semiconductor element structure formed in the element portion, multiple guard ring trenches formed in the outer peripheral portion and each formed in the first surface of the semiconductor layer, and a second conductivity type outer peripheral portion impurity region formed in the outer peripheral portion, in which the multiple guard ring trenches include a first unit consisting of multiple guard ring trenches and a second unit consisting of multiple guard ring trenches arranged on the outside of the semiconductor layer relative to the multiple guard ring trenches belonging to the first unit, and in which the outer peripheral portion impurity region includes a first portion arranged below the multiple guard ring trenches belonging to the first unit and having a first depth with respect to the first surface of the semiconductor layer and a second portion arranged below the multiple guard ring trenches belonging to the second unit and having a second depth smaller than the first depth with respect to the first surface of the semiconductor layer.
US11081544B2	Method of manufacturing a semiconductor device comprising first and second field stop zone portions A method of manufacturing a device in a semiconductor body includes forming a first field stop zone portion of a first conductivity type and a drift zone of the first conductivity type on the first field stop zone portion. An average doping concentration of the drift zone is smaller than 80% of that of the first field stop zone portion. The semiconductor body is processed at a first surface and thinned by removing material from a second surface. A second field stop zone portion of the first conductivity type is formed by implanting protons at one or more energies through the second surface. A deepest end-of-range peak of the protons is set in the first field stop zone portion at a vertical distance to a transition between the drift zone and first field stop zone portion in a range from 3 μm to 60 μm. The semiconductor body is annealed.
US11081541B2	Method of providing partial electrical shielding A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.
US11081538B2	Organic light emitting diode display device having a circuit structure buried in a substrate thereof An organic light emitting diode (“OLED”) display device includes a substrate having a display region including a plurality of sub-pixel regions. A peripheral region at least partially surrounds the display region. A sub-pixel structure is disposed in each of the plurality of sub-pixel regions on the substrate. A circuit structure is disposed within the substrate in the sub-pixel region, and is located adjacent to the peripheral region.
US11081537B2	Substrate and manufacturing method thereof The present invention provides a substrate and a manufacturing method of the substrate. The substrate includes: a glass base plate; a first base layer on the glass base plate; a light shielding layer on the first base layer; multiple pixel units placed on the first base layer, the pixel units including at least one light transmissive region; and a photomask for exposing the light shielding layer. The photomask is used to expose, develop, and etch away a portion of the light shielding layer on the pixel units which need to communicate with each other, so that multiple grooves are formed in the light shielding layer to make the pixel units communicate with each other.
US11081535B2	Display panel, method for manufacturing the same, and display device The present disclosure provides a display panel, a method for manufacturing the same, and a display device. The display panel includes a power supply, and includes a display area and a non-display area. A solar cell is disposed in the non-display area and is configured to convert external light into electric energy when the external light is irradiated on the solar cell, and charge the power supply with the converted electric energy.
US11081534B2	Display panel and display device Provided are a display panel and a display device. After deposition of a thin-film transistor layer and a display layer in which emitting devices are disposed, a sensing layer including a piezoelectric material is disposed under the thin-film transistor layer to facilitate implementation of a display panel having built-in piezoelectric devices. Further, as thin-film transistors for ultrasonic sensing and thin-film transistors for display driving are disposed in different layers, a display panel capable of ultrasonic sensing in an active area may be provided without affecting a display resolution or implementation of display pixels.
US11081529B2	Display device In one example embodiment, a display device for suppressing reflected light includes a driving circuit and a display region which includes a plurality of pixels. In one example embodiment, the plurality of pixels includes a first pixel having a first light emitting element which includes a first light emitting portion having a first layer surface. In one example embodiment, first pixel includes a second light emitting element which includes a second light emitting portion having a second, different layer surface. In one example embodiment, the first pixel includes a third light emitting element which includes a third light emitting portion having a third, different layer surface.
US11081528B2	Imaging device including photoelectric conversion layer An imaging device having pixels, each pixel including: a photoelectric conversion unit including a first electrode, a second electrode, a photoelectric conversion layer between the first and second electrodes, and a hole-blocking layer between the first electrode and the photoelectric conversion layer. The photoelectric conversion unit is applied with a voltage between the first electrode and the second electrode. The photoelectric conversion unit has a characteristic, responsive to the voltage within a range from a first voltage to a second voltage, showing that a density of current passing between the first electrode and the second electrode when light is incident on the photoelectric conversion layer becomes substantially equal to that when no light is incident on the photoelectric conversion layer. The range from the first voltage to the second voltage includes 0V, and a difference between the first voltage and the second voltage is 0.5 V or more.
US11081522B2	Wiring line layout in a semiconductor memory device A semiconductor device includes a plurality of first selection lines extending in a first direction and disposed side by side in a second direction, the second direction intersecting with the first direction, a first metal wiring line formed in a layer above the first selection line layer, a first through wiring line penetrating an insulating layer formed on the first selection line layer, and coupling a first line of the plurality of first selection lines and the first metal wiring line to each other, a second through wiring line penetrating the first selection line layer, the second through wiring line having one end coupled to the first metal wiring line, a first storage element having a first terminal, and a second terminal coupled to the first line, and a first drive circuit coupled to another end of the second through wiring line, and drives the plurality of first selection lines.
US11081519B2	Light emitting device, projector, and method of manufacturing light emitting device A light emitting device includes a light emitting element including a first base member, and a stacked body provided to the first base member, and a second base member provided with the light emitting element, the stacked body includes a first columnar section having a first height, and a second columnar section having a second height smaller than the first height, the first columnar section and the second base member are electrically connected to each other via a first conductive member between the stacked body and the second base member, the second columnar section and the second base member are electrically connected to each other via a second conductive member between the stacked body and the second base member, the first conductive member has a third height, and the second conductive member has a fourth height larger than the third height.
US11081518B2	Semiconductor packaging method and semiconductor device based on molding process The present invention provides a semiconductor packaging method and semiconductor device based on a molding process. In the packaging method, first, at least a portion of a compensation part is kept on at least a portion of a bonding region formed between a first adjoining surface of a semiconductor element and a second adjoining surface of a packaging component, to form a semi-finished product of a semiconductor device; then, during hardening of the packaging component, the compensation part is caused to undergo different degrees of deformation at different positions to compensate for a difference between a magnitude of deformation of the packaging component and a magnitude of deformation of the semiconductor element, so as to package the semiconductor element to form the semiconductor device. By means of the method, undesirable phenomena such as cracking and deformation of the surface of the semiconductor element can be avoided.
US11081514B2	Image sensors and methods of forming the same An image sensor includes a substrate including a light-receiving region and a light-shielding region, a device isolation pattern in the substrate of the light-receiving region to define active pixels, and a device isolation region in the substrate of the light-shielding region to define reference pixels. An isolation technique of the device isolation pattern is different from that of the device isolation region.
US11081506B2	Display component and display device A display component and a display device are provided. The display component includes a display panel including a first substrate, a thin-film transistor array layer, a second substrate and a coil-containing film layer. The coil-containing film layer at least includes a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer. The first metal layer includes at least one first coil and the second metal layer includes at least one signal line, where the one first coil of the first metal layer is electrically connected to one or two signal lines of the second metal layer. An orthographic projection of the first coil on the first substrate is at least partially in the display region. The display component further includes a coil drive circuit, where the coil drive circuit is electrically connected to each of the first coil and the signal line, respectively.
US11081504B2	Display device The present invention provides a display device, including: a display region; a non-display region surrounding the display region; multiple signal lines distributed in the display region; multiple drive chips distributed in the non-display region, each of the drive chips being provided with at least one signal output end; and at least one fan-out line, one end of each fan-out line being connected to the signal output end of one of the drive chips, the other end of each fan-out line being connected to each signal line. The at least one fan-out line is entirely or partially placed over the drive chips. The invention can effectively solve the problems of low reliability of left and right bezels of the display panel and weak antistatic capability, and can make the left and right bezel narrower.
US11081501B2	Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, display device A thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device are provided, the method of fabricating a thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the active layer; and processing the metal layer to form a source electrode, a drain electrode, and a metal oxide layer, the metal oxide layer covering the source electrode, the drain electrode, and the active layer, the source electrode and the drain electrode being spaced apart and insulated from each other by the metal oxide layer.
US11081493B2	Method for forming semiconductor memory device with sacrificial via A method for forming a semiconductor memory device is provided. The method includes forming a sacrificial via in a dielectric layer over a substrate, forming a first active layer over the dielectric layer, forming an insulating layer over the first active layer, and forming a second active layer over the insulating layer. The method also includes forming a trench through the second active layer, the insulating layer and the first active layer and corresponding to the sacrificial via, removing the sacrificial via to form a via hole in the dielectric layer, and filling the trench and the via hole with a conductive material.
US11081492B2	Semiconductor memory device A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.
US11081491B2	Semiconductor device and method of manufacturing the same There is provided a semiconductor device including a first gate pattern on a semiconductor substrate, a second gate pattern adjacent to a side surface of the first gate pattern via an ONO film, and an active region located just below the second gate pattern via the ONO film. Here, an element isolation region is formed just below the first gate pattern. In this manner, capacitance between the first gate pattern and the semiconductor substrate and capacitance between the first and second gate patterns are prevented from being measured when measuring capacitance between the second gate pattern which is an upper electrode and the active region which is a lower electrode in order to measure a film thickness of the ONO film just below the second gate pattern.
US11081484B2	IC unit and method of manufacturing the same, and electronic device including the same There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.
US11081481B2	Semiconductor device with an IGBT region and a non-switchable diode region A semiconductor device includes a semiconductor substrate having a body layer arranged between a front side and a drift layer, and forming a pn-junction with the drift layer. A front metallization is on the front side in Ohmic connection with the body layer, and a back metallization opposite is in Ohmic connection with the drift layer. An IGBT cell region of the device includes a plurality of gate electrodes in Ohmic connection with a gate metallization. Each gate electrode is electrically insulated from the semiconductor substrate by a respective gate dielectric extending through the body layer. A free-wheeling diode region of the device includes a plurality of field electrodes in Ohmic connection with the front metallization. Each field electrode is separated from the semiconductor substrate by a respective field dielectric extending through the body layer. Additional semiconductor device embodiments are described.
US11081480B2	Semiconductor structure, capacitor structure thereof and manufacturing method of the same The present disclosure provides a semiconductor structure, including: a transistor, including a gate structure and a source/drain structure; a source/drain contact, disposed over the source/drain structure; a gate contact, disposed over the gate structure; and a conductive bridge, disposed over the transistor, wherein the conductive bridge overlaps the source/drain contact from a top view perspective and electrically connecting the gate contact. The present disclosure also provides a method for forming the same.
US11081479B1	Integrated circuit layout with asymmetric metal lines A semiconductor device includes a first group of semiconductor fins arranged at a first fin-to-fin spacing and a second group of semiconductor fins arranged at a second fin-to-fin spacing. The first and second groups of semiconductor fins are separated by a fin-free region larger than the first and second fin-to-fin spacings. The semiconductor device further includes a gate structure extending across the first and second group of semiconductor fins, a Vdd line and a Vss line extending across the gate structure. The first and second groups of semiconductor fins are between the Vdd line and the Vss line from a top view, and an overlapping area between the Vdd line and the first group of semiconductor fins is different from an overlapping area between the Vss line and the second group of semiconductor fins from the top view.
US11081475B2	Integrated circuit structure and method for reducing polymer layer delamination An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
US11081472B2	Stacked die multichip module package A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.
US11081468B2	Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.
US11081461B2	Packaging process and packaging structure A packaging process and a packaging structure of an electronic component are provided. By the packaging process and the packaging structure of the disclosure, the groove of the thermal conduction structure is covered by the first metal re-distribution layer. Therefore, the flank of the thermal conduction structure is easy to coat the conducting material. Moreover, because the flank of the thermal conduction structure is coated, the surface of the flank of the thermal conduction structure is difficulty oxidized. Furthermore, the conducting material between the thermal conduction structure and the board is flat, so that automated optical inspection of the packaging structure is easy to implement.
US11081458B2	Methods and apparatuses for reflowing conductive elements of semiconductor devices Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.
US11081457B2	Semiconductor package and methods of manufacturing a semiconductor package In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
US11081455B2	Semiconductor device with bond pad extensions formed on molded appendage A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.
US11081453B2	Semiconductor package structure with antenna A semiconductor package structure is provided. The semiconductor package structure includes a first redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. A second RDL structure is formed on and electrically coupled to an active surface of the semiconductor die. A ground layer is formed in the first RDL structure. A first molding compound layer is formed on the first RDL structure. A first antenna includes a first antenna element formed in the second RDL structure and a second antenna element formed on the first molding compound layer. Each of the first antenna element and the second antenna element has a first portion overlapping the semiconductor die as viewed from a top-view perspective.
US11081451B2	Die stack with reduced warpage A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.
US11081450B2	Radiation shield around a component on a substrate Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a radiation source on the substrate, a ground on the substrate, where the ground is located around the radiation source, and a heat spreader over the radiation source, where the heat spreader includes one or more ground coupling mechanisms that are in contact with the ground on the substrate. The one or more ground coupling mechanisms in contact with the ground on the substrate create a radiation shield that at least partially keeps radiation from the radiation source from extending past the substrate.
US11081449B2	Semiconductor device and method for manufacturing the same and wireless communication apparatus An electromagnetic wave absorption sheet is arranged to contact an upper surface and side surfaces of an electronic component mounted on a wiring board, a heat conduction plate is arranged to contact the electromagnetic wave absorption sheet, a heat transfer sheet is arranged to contact the heat conduction plate, and a heat dissipation member is arranged to contact the heat transfer sheet. Heat conductive particles contained in the heat transfer sheet contact a flat surface portion of the heat conduction plate. The electromagnetic wave absorption sheet, the heat conduction plate, and the heat transfer sheet are interposed between the heat dissipation member and the electronic component, as a heat conduction member for conducting heat generated in the electronic component and the like to the heat dissipation member.
US11081447B2	Graphene-assisted low-resistance interconnect structures and methods of formation thereof A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.
US11081444B2	Integrated circuit with guard ring An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.
US11081441B1	Chip on film and display device The present application provides a chip on film and a display device, the chip on film including a plurality of first source signal lines located at a middle, and a plurality of second source signal lines located at opposite sides, wherein each of the first source signal lines has a cross-sectional area smaller than a cross-sectional area of each of the second source signal lines in a reference plane. Based on the structure, attenuation from the source driver chip to each data lines is substantially the same or even completely the same.
US11081439B2	Integrated circuit and electronic circuit comprising the same According to one embodiment, an integrated circuit includes a chip, a first pin, a second pin, and a third pin. The chip includes an internal circuit and a plurality of pads connected to the internal circuit. The first pin is connected to a first pad among the plurality of pads. The first pin is connected to a power supply provided outside the integrated circuit. The second pin is connected to a second pad among the plurality of pads. The second pin is connected to a ground provided outside the integrated circuit. The third pin is connected to the second pin inside the integrated circuit via a third pad among the plurality of pads. The third pin is insulated from the second pin outside the integrated circuit.
US11081438B2	Method of manufacturing semiconductor device An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.
US11081434B2	Package substrates with magnetic build-up layers The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.
US11081432B2	Semiconductor device with semiconductor element and electrodes on different surfaces The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.
US11081431B2	Circuit device A circuit device includes a first conductive plate and a second conductive plate each having a belt-shaped portion arranged side-by-side with each other, a third conductive plate having a belt-shaped portion is arranged side-by-side with and spaced apart from the other side portion of the first conductive plate, a first circuit component having a first terminal connected to the first conductive plate and a second terminal connected to the second conductive plate, a second circuit component having a first terminal connected to the first conductive plate and a second terminal connected to the third conductive plate, a first external connection portion provided at the belt-shaped portion of the first conductive plate, and a second external connection portion provided at the belt-shaped portion of the second conductive plate or a third external connection portion provided at the belt-shaped portion of the third conductive plate.
US11081425B2	Semiconductor packages A semiconductor package includes a base wafer including a first substrate and at least one first through via electrode extending through the first substrate, and a first semiconductor chip provided on the base wafer. The first semiconductor chip includes a second substrate; and at least one second through via electrode extending through the second substrate. The at least one second through via electrode is provided on the at least one first through via electrode to be electrically connected to the at least one first through via electrode. A first diameter of the at least one first through via electrode in a first direction is greater than a second diameter of the at least one second through via electrode in the first direction.
US11081423B2	Power distribution by a working fluid contained in a conduit A system and method system for conveying power from a heat source is disclosed. The system includes a conduit constructed of a heat conducting material. The conduit defines a passageway containing a primary working fluid, where the conduit is either mounted upon or extends within at least a portion of a barrier. The conduit is configured to conduct thermal energy generated by the heat source and transfer the thermal energy to the primary working fluid flowing within the passageway. The system also includes a thermoelectric generator in thermal communication with the conduit. The thermoelectric generator has a hot side and a cold side. The primary working fluid transfers the thermal energy to the hot side of the thermoelectric generator to heat the hot side of the thermoelectric generator to a temperature greater than the cold side and create electric current.
US11081422B2	Self-healing PDMS encapsulation and repair of power modules A power electronics assembly is provided with a self-healing feature. The power electronics assembly may include a semiconductor electronics device and an insulating substrate coupled to the semiconductor electronics device. A base metal structural component may be provided, coupled to the insulating substrate. The assembly may include a frame component cooperating with the base metal structural component and defining an enclosure containing the semiconductor electronics device and the insulating substrate. The assembly further includes a self-healing polymer comprising disulfide bonds. The self-healing polymer is disposed within the enclosure; additional potting material may also be provided as a multi-layered encapsulation. In various aspects, the self-healing polymer may include polydimethylsiloxane based polyurethane (PDMS-PU) modified with disulfide bonds. The frame component may be configured to direct or confine heat to areas of the assembly where ESD may be problematic.
US11081414B2	Power semiconductor module arrangement A power semiconductor module arrangement includes a substrate arranged in a housing. The substrate includes a first metallization layer arranged on a first side of a dielectric insulation layer and a second metallization layer arranged on a second side of the dielectric insulation layer. At least one semiconductor body is mounted on a first surface of the first metallization layer facing away from the dielectric insulation layer. A connecting element is arranged on and electrically connected to the first surface. A contact element is inserted into and electrically connected to the connecting element, and extends from the connecting element through an interior of the housing and through an opening in the cover of the housing to an outside of the housing in a direction perpendicular to the first surface. A hard encapsulation is arranged adjacent to the first metallization layer and at least partly fills the inside of the housing.
US11081412B2	Semiconductor device A semiconductor device of embodiments includes a first semiconductor chip; a metal plate having a first plane and a second plane facing the first plane and including a first ceramic plate provided between the first plane and the second plane; and a first insulating board provided between the first semiconductor chip and the metal plate and facing the first plane, in which the first ceramic plate does not exist between the first semiconductor chip and the second plane.
US11081407B2	Methods for assessing semiconductor structures Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.
US11081403B2	Methods of forming contact features in field-effect transistors A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.
US11081400B2	Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.
US11081399B2	Method of producing microelectronic components A method is provided for producing a microelectronic component on a substrate including in an exposed manner on a first face thereof, an active zone and an electrical isolation zone adjacent thereto, the method including forming a gate on the active zone, forming spacers each configured to cover a surface of a different edge of the gate, and forming source and drain zones by doping portions of the active zone adjacent to the gate, the method successively including forming a first layer of spacer material above the active zone and the electrical isolation zone; an ion implantation to produce doping of the portions through the first layer; removing a modified portion of the first layer disposed overlooking the portions, the modified portion coming from the ion implantation, the removing being configured to preserve at least part of the first layer at a level of edges of the gate.
US11081394B2	Method of making a FinFET device A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.
US11081392B2	Dicing method for stacked semiconductor devices A method includes providing first and second wafers; forming a first device layer in a top portion of the first wafer; forming a second device layer in a top portion of the second wafer; forming a first groove in the first device layer; forming a second groove in the second device layer; bonding the first and second wafers together after at least one of the first and second grooves is formed; and dicing the bonded first and second wafers by a cutting process, wherein the cutting process cuts through the first and second grooves.
US11081391B2	Wafer level dicing method and semiconductor device A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.
US11081390B2	Multi-pass plating process with intermediate rinse and dry A method includes electroplate depositing a first metal layer to a first thickness on a metal seed layer, rinsing the first metal layer with deionized water, and after the first rinse process, drying the wafer. The method also includes performing one or more additional electroplating processes that respectively deposit an additional metal layer to a second thickness over the first metal layer, performing an additional rinse process that rinses the additional metal layer with deionized water, and performing an additional drying processes that dries the wafer.
US11081389B2	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device, the method including providing a metal precursor on a substrate to form a preliminary layer that includes a first metal; providing a reducing agent on the preliminary layer, the reducing agent including a compound that includes a second metal; and providing a reactant on the preliminary layer to form a metal-containing layer, wherein the second metal has multiple oxidation states, the second metal in the reducing agent having a lower oxidation state among the multiple oxidation states prior to providing the reducing agent on the preliminary layer.
US11081388B2	Forming barrierless contact Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.
US11081386B2	High resistivity SOI wafers and a method of manufacturing thereof A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.
US11081380B2	Chip bonding device A chip bonding apparatus includes a chip separation unit, a chip alignment unit, a chip bonding unit and a bonding robotic arm unit. The bonding robotic arm unit includes a first bonding robotic arm unit and a second bonding robotic arm unit. The first bonding robotic arm unit includes a first motion stage, a first driver configured to drive the first motion stage and at least one first bonding robotic arm arranged on the first motion stage. The first bonding robotic arm is configured to suck up a chip from the chip separation unit and deliver it to the chip alignment unit. The second bonding robotic arm unit includes a second motion stage, a second driver configured to drive the second motion stage and at least one second bonding robotic arm arranged on the second motion stage.
US11081379B2	Load port operation in electronic device manufacturing apparatus, systems, and methods An electronic device manufacturing system may include a factory interface having a controlled environment. The electronic device manufacturing system may also include a load port coupled to the factory interface. The load port may be configured to receive a substrate carrier thereon and may include purge apparatus and a controller. The controller may be configured to operate the load port such that any air located around and between a substrate carrier door and the load port is at least partially or entirely purged, thus reducing or preventing contamination of the controlled environment upon the opening of the substrate carrier door by the load port. Methods of operating a factory interface load port are also provided, as are other aspects.
US11081367B2	Support and method for producing semiconductor device-mounting substrate using the same A support including a heat resistant film layer and a resin layer, wherein the heat resistant film layer is laminated on at least one side (a first side) of the resin layer, and the resin layer is in a semi-cured state (B stage).
US11081366B2	MCM package isolation through leadframe design and package saw process A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
US11081365B2	Treatment to interface between metal film and BARC or photoresist A method of manufacturing a semiconductor device is disclosed. In the method, a metallic layer is formed over a substrate, the metallic layer is surface-treated with an alkaline solution, and a bottom anti-reflective coating (BARC) layer is formed on the surface-treated metallic layer.
US11081361B2	Plasma etching method Provided is a plasma etching method comprising supplying both hexafluoroisopropanol (HFIP) gas and argon (Ar) gas to a plasma chamber receiving an etching target therein, thereby to plasma-etch the etching target.
US11081358B2	Silicide film nucleation Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.
US11081354B2	Fin patterning methods for increased process margins The present disclosure provides a method in accordance with some embodiments. The method includes forming a mandrel over a substrate, the mandrel having a first sidewall and a second sidewall opposing the first sidewall; forming a first fin on the first sidewall and a second fin on the second sidewall; depositing a dielectric material covering the first fin, the second fin, and the mandrel; partially removing the dielectric material, thereby exposing the second fin; etching the second fin without etching the first fin and the mandrel; removing the dielectric material; and removing the mandrel.
US11081351B2	Method of processing substrate, device manufacturing method, and plasma processing apparatus A disclosed method of processing a substrate includes (a) providing a substrate in a chamber of a plasma processing apparatus. The substrate has a patterned organic mask. The method further includes (b) generating plasma from a processing gas in the chamber in a state where the substrate is accommodated in the chamber. The method further includes (c) periodically applying a pulsed negative direct-current voltage to an upper electrode of the plasma processing apparatus, during execution of the generating plasma (that is, the above (b)). In the applying a pulsed negative direct-current voltage, ions from the plasma are supplied to the upper electrode, so that a silicon-containing material which is released from the upper electrode is deposited on the substrate.
US11081348B2	Selective deposition of silicon using deposition-treat-etch process Methods for selective silicon film deposition on a substrate comprising a first surface and a second surface are described. More specifically, the process of depositing a film, treating the film to change some film property and selectively etching the film from various surfaces of the substrate are described. The deposition, treatment and etching can be repeated to selectively deposit a film on one of the two substrate surfaces.
US11081347B2	Method for manufacturing silicon-carbide semiconductor element In this method for manufacturing a semiconductor element, a modified layer produced by subjecting a substrate (70) to mechanical polishing is removed by heating the substrate (70) under Si vapor pressure. An epitaxial layer formation step, an ion implantation step, an ion activation step, and a second removal step are then performed. In the second removal step, macro-step bunching and insufficient ion-implanted portions of the surface of the substrate (70) performed the ion activation step are removed by heating the substrate (70) under Si vapor pressure. After that, an electrode formation step in which electrodes are formed on the substrate (70) is performed.
US11081344B2	Method for manufacturing semiconductor substrate Provided is a method for manufacturing a semiconductor substrate including: preparing a semiconductor substrate having a front surface on which an epitaxial layer has been formed; and forming a fracture layer on a rear surface of the semiconductor substrate before forming elements on the epitaxial layer.
US11081343B2	Sub-stoichiometric metal-oxide thin films Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle.
US11081340B2	Argon addition to remote plasma oxidation Methods for conformal radical oxidation of structures are provided. The method comprises positioning a substrate in a processing region of a processing chamber. The method further comprises flowing hydrogen gas into a precursor activator at a first flow rate, wherein the precursor activator is fluidly coupled with the processing region. The method further comprises flowing oxygen gas into the precursor activator at a second flow rate. The method further comprises flowing argon gas into the precursor activator at a third flow rate. The method further comprises generating a plasma in the precursor activator from the hydrogen gas, oxygen gas, and argon gas. The method further comprises flowing the plasma into the processing region. The method further comprises exposing the substrate to the plasma to form an oxide film on the substrate, wherein a growth rate of the oxide film is controlled by adjusting the third flow rate.
US11081337B2	Formulation for deposition of silicon doped hafnium oxide as ferroelectric materials In one aspect, the invention is formulations comprising both organoaminohafnium and organoaminosilane precursors that allows anchoring both silicon-containing fragments and hafnium-containing fragments onto a given surface having hydroxyl groups to deposit silicon doped hafnium oxide having a silicon doping level ranging from 0.5 to 8 mol %, preferably 2 to 6 mol %, most preferably 3 to 5 mol %, suitable as ferroelectric material. In another aspect, the invention is methods and systems for depositing the silicon doped hafnium oxide films using the formulations.
US11081336B2	Method of making graphene and graphene devices The present invention generally relates to a method of making graphene and graphene devices.
US11081331B2	Mass spectrometers having segmented electrodes and associated methods Disclosed herein are mass spectrometers having segmented electrodes and associated methods. According to an aspect, an apparatus or mass spectrometer includes an ion source configured to generate ions from a sample. The apparatus also includes a detector configured to detect a plurality of mass-to-charge ratios associated with the ions. Further, the apparatus includes segmented electrodes positioned between the ion source and the detector. The apparatus also includes a controller configured to selectively apply a voltage across the segmented electrodes for forming a predetermined electric field profile.
US11081328B2	Maintaining spectral quality over long measuring periods in imaging mass spectrometry The invention relates to imaging mass spectrometry on thin sample sections, in particular using MALDI, where a high lateral image resolution means that a plethora of mass spectra has to be acquired and the image acquisition runs over many hours. The quality of the mass spectra deteriorates considerably over time in such cases. The invention is based on the finding that the decrease in spectral quality of continuous measurement series over many hours is only partially caused by a decrease in detector gain, and that another significant cause is a decrease in the number of usable ions per ion generating pulse, which is attributable to several phenomena that are difficult to regulate. The invention now proposes to instead regulate only the detector gain, and such that not only the decrease in the detector gain is compensated, but also the decrease in the number of usable ions per ion generating pulse.
US11081327B2	System and method for enhanced ion pump lifespan Within an ion pump, accelerated ions leave the center portion of an anode tube due to the anode tube symmetry and the generally symmetrical electric fields present. The apparent symmetry within the anode tube may be altered by making the anode tube longitudinally segmented and applying independent voltages to each segment. The voltages on two adjacent segments may be time varying at different rates to achieve a rasterizing process.
US11081326B2	Sputtering target and method for manufacturing the same A novel metal oxide or a novel sputtering target is provided. A sputtering target includes a conductive material and an insulating material. The insulating material includes an oxide, a nitride, or an oxynitride including an element M1. The element M1 is one or more kinds of elements selected from Al, Ga, Si, Mg, Zr, Be, and B. The conductive material includes an oxide, a nitride, or an oxynitride including indium and zinc. A metal oxide film is deposited using the sputtering target in which the conductive material and the insulating material are separated from each other.
US11081324B2	Sputtering cathode, sputtering cathode assembly, and sputtering apparatus The sputtering cathode has a tubular shape having a pair of long sides facing each other in cross-sectional shape, has a sputtering target whose erosion surface faces inward, and a magnetic circuit is provided along the sputtering target. The pair of long sides are constituted by rotary targets each having a cylindrical shape. The rotary target is internally provided with a magnetic circuit and configured to allow the flow of cooling water. The magnetic circuit is provided parallel to the central axis of the rotary target and has a rectangular cross-sectional shape having a long side perpendicular to the radial direction of the rotary target.
US11081321B2	Substrate processing apparatus There is provided a substrate processing apparatus including: a chamber in which a target substrate is accommodated; a first gas supply part configured to supply a gas containing a first monomer, and a gas containing a second monomer, which forms a polymer through a polymerization reaction with the first monomer, into the chamber so as to form a film of the polymer on the target substrate; an exhaust device configured to exhaust a gas inside the chamber; a first exhaust pipe configured to connect the chamber and the exhaust device; and an energy supply device configured to supply an energy with respect to a gas flowing through the first exhaust pipe so as to cause an unreacted component of at least one of the first monomer and the second monomer contained in the gas exhausted from the chamber to be reduced in a molecular weight.
US11081319B2	Glass sealed gas discharge tubes Glass sealed gas discharge tubes. In some embodiments, a gas discharge tube (GDT) can include an insulator substrate having first and second sides and defining an opening. The GDT can further include a first electrode implemented to cover the opening on the first side of the insulator substrate, and a second electrode implemented to cover the opening on the second side of the insulator substrate. The GDT can further include a first glass seal implemented between the first electrode and the first side of the insulator substrate, and a second glass seal implemented between the second electrode and the second side of the insulator substrate, such that the first and second glass seals provide a hermetic seal for a chamber defined by the opening and the first and second electrodes.
US11081318B2	Geometrically selective deposition of dielectric films utilizing low frequency bias Apparatus and methods for depositing and treating or etching a film are described. A batch processing chamber includes a plurality of processing regions with at least one plasma processing region. A low frequency bias generator is connected to a susceptor assembly to intermittently apply a low frequency bias to perform a directional treatment or etching the deposited film.
US11081314B2	Integrated transmission electron microscope An integrated transmission electron microscope comprising multiple electron sources for tuned beams of ultrafast, scanning probe, and parallel illumination in varied beam energies can be alternated within sub-microseconds onto a sample with dynamic ‘transient state’ processes to acquire atomic-scale structural/chemical data with site specificity. The various electron sources and condenser optics enable high-resolution imaging, high-temporal resolution imaging, and chemical imaging, using fast-switching magnets to direct the different electron beams onto a single maneuverable objective pole piece where the sample resides. Such multimodal in situ characterization tools housed in a single microscope have the potential to revolutionize materials science.
US11081312B2	Method of manufacturing emitter, emitter, and focused ion beam apparatus A method of manufacturing an emitter is disclosed. The method enables a crystal structure of the tip of the front end of the emitter to return to its original state with high reproducibility by rearranging atoms in a treatment, and enables a long lasting emitter to be attained by suppressing extraction voltage rise after the treatment. As a method of manufacturing an emitter having a sharpened needle-shape, the method includes: performing an electropolishing process for the front end of an emitter material having conductivity to taper toward the front end; and performing an etching to make the number of atoms constituting the tip of the front end be a predetermined number or less by further sharpening the front end through an electric field-induced gas etching having constantly applied voltage, while observing the crystal structure of the front end, by a field ion microscope, in a sharp portion having the front end at its apex.
US11081307B2	Electrical power supply disconnector for a protection module and protection module including such a disconnector An electrical power supply disconnector for establishing or severing the connection between current conductors and a power supply circuit. The electrical power supply disconnector includes a housing including a central passage, the walls of which bear contact strips that are located facing one another along a contact axis, and a slider sliding through the central passage in the direction of a centre axis, and bearing at least a first electrically conductive bar, oriented along the contact axis, for electrically connecting at least one first low contact strip and one high contact strip when the slider is in a first position. A protection module including such a power supply disconnector.
US11081296B2	Stationary contact assembly and corresponding switch contact Embodiments of the present disclosure provide a stationary contact assembly and a corresponding switch contact. The stationary contact assembly comprises: a stationary contact body (21); a stationary contact point (23) placed on the stationary contact body (21); and an arc-guiding member (25) fixed on the stationary contact body (21) and including an arc guiding portion (251), the arc guiding portion (251) comprising a first end (A) and a second end (B) that are opposite to each other, the first end (A) being close to the stationary contact point (23), a direction form the first end (A) to the second end (B) defining a main movement direction (F) of arc. The arc guiding portion (251) of the arc-guiding member (25) comprises an arc-guiding section (2511) at the first end (A), the arc-guiding section is adapted to guide the arc away from the stationary contact point (23) into the arc guiding portion (251), and the stationary contact point (23) is close to or in contact with the arc-guiding section (2511) in the main movement direction (F) of the arc. The stationary contact assembly of the embodiments of the present disclosure has an improved arc-guiding member that can guide the arc to quickly leave the contact point, enhance the mechanical strength of the stationary contact and reduce the production cost of the contact.
US11081294B2	Energy storage device An energy storage device is provided which includes a supercapacitor first electrode, a supercapacitor second electrode, a first electrolyte, a metal electrode, and a separator. The supercapacitor first electrode, the supercapacitor second electrode, and the first electrolyte together form a supercapacitor. The metal electrode and the supercapacitor second electrode form an Ohmic contact. The separator is sandwiched between the metal electrode and the supercapacitor first electrode and configured to absorb moisture in a surrounding environment.
US11081293B2	Manufacturing method of a composite photovoltaic structure A manufacturing method of a composite photovoltaic structure including a step of forming a transparent electrode material, a step of forming a first photovoltaic unit, a step of forming a first insulation layer, a step of forming a first transparent conductive layer, a step of forming a second photovoltaic unit, a step of forming a second insulation layer, a step of forming a second transparent conductive layer and a step of splitting a product. Thus, the manufacturing method of the composite photovoltaic structure has a photoelectric reaction area of a significantly improved omnidirectional concentration gain, an efficiently induced current and a low manufacturing cost, without affecting the whole structure thickness.
US11081289B2	Tantalum capacitor A tantalum capacitor includes: a tantalum body comprising tantalum powder and a tantalum wire exposed to one end surface; an anode lead frame comprising a first electrode member and a second electrode member bent perpendicularly thereto; a cathode electrode lead frame comprising a third electrode member spaced apart from the first electrode member having the tantalum body mounted on an upper surface thereof and a fourth electrode member bent perpendicularly thereto; and a encapsulation portion covering the tantalum body so that lower surfaces of the first and third electrode members and one external surfaces of the second and fourth electrode members are exposed. The anode lead frame comprises a bend portion having a connection part of the first electrode member and the second electrode member as an axis, and an end of the bend portion is in contact with the tantalum wire.
US11081286B2	Method for manufacturing electrolytic capacitor, and electrolytic capacitor A method for manufacturing an electrolytic capacitor includes a first step, a second step, and a third step. In the first step, a capacitor element is formed. The capacitor element includes an anode body, a cathode body, and a separator. The anode body includes a dielectric layer formed on a surface of the anode body. And the separator is disposed between the anode body and the cathode body. In the second step, the capacitor element is impregnated with a treatment solution containing an acid component and a base component. In the third step, the capacitor element is, after the second step, impregnated with a conductive polymer dispersion in a state that a part of the treatment solution remains in the capacitor element. The conductive polymer dispersion is obtained by dispersing, in a solvent, conductive polymer particles each including polyanion. A pH of the treatment solution is higher than a pH of the conductive polymer dispersion.
US11081285B2	Electrically conductive electret and associated electret-based power source and self-powered structure This invention provides electrically conductive electret, electret-based direct-current power source and structural electret, with applications including the self-sensing of damage, stress and strain (including structural self-sensing) and electric powering (including structural self-powering). The electret is an electrically conductive material comprising mobile charge carriers (electrons, holes or ions), which exhibit a gradient in the carrier concertation along a line connecting the positive charge center and negative charge center in the electret. The carriers create an electric dipole. The material is electrically continuous along this line, which is along the path of least electrical resistance. The material exhibits microstructure comprising microscopic features that are positioned along said line and that interact with said carriers, with the interaction enhancing said dipole. The materials are preferably metals, carbons and their composites. The electret's electric field preferably ranges from 10′ V/m to 1 V/m. The electrical conductivity preferably ranges from 103Ω−1·m−1 to 108Ω−1·m−1.
US11081280B2	Ionomeric polymer and multilayer capacitor and additives A block copolymer forms a dielectric film with isolated polarizable domains. The block copolymer is a molecule selected to have an ionically functionalized end. The ionically functionalized end is selected to be less soluble in a solvent than another portion of the polymer such that, when a plurality of the block copolymer molecules are dissolved in the solvent, the first ends of the plurality of block copolymers interact with each other and aggregate to form isolated polarizable domains. The block copolymer forms an electrically isolating shell about a core comprised of the ionically functionalized ends. One or more additives may be disposed selectively within the core to increase the dielectric constant of the dielectric film.
US11081275B2	Electronic device An electronic device includes a plurality of chip components, an intermediate metal terminal, and an outer metal terminal. The intermediate metal terminal connects end surfaces of terminal electrodes of the chip components. The outer metal terminal is connectable to the terminal electrode positioned opposite to the terminal electrode connectable to the intermediate metal terminal.
US11081269B2	Movement device composed of subassemblies A movement device comprising a first and a second assembly, the first assembly being composed of a plurality of subassemblies. Two directly adjacent subassemblies are conterminous with each other at a boundary line. The two subassemblies form at least one first pair of directly adjacent first permanent-magnet arrangements that are separated from each other by the boundary line. The two first permanent-magnet arrangements of the first pair are each arranged with a boundary distance from the boundary line that is reduced with respect to a spacing distance, such that they mutually have the spacing distance. There are present in each case within the said two subassemblies at least one second pair of directly adjacent first permanent-magnet arrangements that mutually have the spacing distance.
US11081268B2	Electromagnet assembly An electromagnet assembly has an inner magnet, an outer magnet, arranged around the inner magnet with an annular region extending between the inner magnet and the outer magnet, and a number of support elements extending through the annular region and dividing the annular region into a number of annular segments. The support elements are distributed in the annular region so as to form a small annular segment and a large annular segment.
US11081266B2	Soft magnetic alloy powder, dust core, and magnetic component Soft magnetic alloy powder includes plurality of soft magnetic alloy particles of soft magnetic alloy represented by composition formula (Fe(1−(α+β))X1αX2β)(1−(a+b+c++e+f+g))MaBbPcSidCeSfTig, wherein X1 represents Co and/or Ni; X2 represents at least one selected from group consisting of Al, Mn, Ag, Zn, Sn, As, Sb, Cu, Cr, Bi, N, O, and rare earth elements; M represents at least one selected from group consisting of Nb, Hf, Zr, Ta, Mo, W, and V; 0.020≤a≤0.14, 0.020
US11081264B2	Permanent magnet and rotary electrical machine A high-performance permanent magnet is provided. A permanent magnet expressed by a composition formula: RpFeqMrCutCo100-p-q-r-t-. The magnet comprises a metal structure including a cell phase having a Th2Zn17 crystal phase, and a Cu-rich phase provided to divide the cell phase and having a Cu concentration higher than that of the Th2Zn17 crystal phase. An Fe concentration of the Th2Zn17 crystal phase is not less than 30 atomic % nor more than 45 atomic %. An average length of the Cu-rich phase is not less than 30 nm nor more than 250 nm.
US11081262B2	Grommet A grommet which is configured to cover a periphery of a wire harness includes a panel mounting portion which is configured to be mounted to a panel. The panel mounting portion includes a base portion which is formed in an annular shape, a seal portion which is formed on the base portion and is configured to be in close contact with a surface of the panel, and a groove portion which is formed between the base portion and the seal portion along a peripheral direction of the panel mounting portion. A plurality of reinforcing ribs are configured to connect the base portion and the seal portion and are arranged in the peripheral direction in the groove portion, and the reinforcing ribs are inclined with respect to a mounting direction of the panel mounting portion to the panel.
US11081257B2	Notched conductor for telecommunication cable The present disclosure relates to an insulated conductor for a telecommunications cable. The insulated conductor includes a first surface surrounding a core region of the notched conductor. The first surface defines a plurality of grooves extending radially inward towards the second longitudinal axis of the insulated conductor. Each of the plurality of grooves comprises of a first groove area section and a second groove area section. The first groove area section and the second groove area section are in continuous contact. The insulated conductor includes an insulation layer circumferentially surrounding the conductor. The insulated conductor has a first diameter in a range of about 0.5 millimeters to 0.65 millimeters. The telecommunications cable includes, plurality of twisted pairs of insulated conductors, a separator and a cable jacket.
US11081256B2	Composite cable pair Provided is a composite cable pair with which it is possible to reduce the difference in durability between a right-wheel composite cable and a left-wheel composite cable. A composite cable pair includes a right-wheel composite cable and a left-wheel composite cable. One end of the composite cable is fixed to a cable fixing portion on the vehicle body side or the chassis side of an automobile, and the other end thereof is fixed to a cable fixing portion on the right wheel side. One end of the composite cable is fixed to a cable fixing portion on the vehicle body side or the chassis side of the automobile, and the other end thereof is fixed to a cable fixing portion on the left wheel side. Wires of the respective wire bundles of the composite cable and the composite cable are twisted in twisting directions that are opposite to each other so that the twisting is tightened, without loosening, by an operation of the handle.
US11081247B2	Nuclear instrumentation isolated output signal scaling method and system employing same A method of determining a core design parameter of a nuclear reactor, includes: calibrating an isolated voltage output from a NIS cabinet associated with the nuclear reactor using a calibrated signal source as an input to the NIS cabinet; recording values of the calibrated signal source used in the calibrating and corresponding values of the output voltage from the calibrating in an as-left cabinet calibration data table; using a computing device connected to the isolated voltage output from the NIS cabinet, converting the voltage output signal to a converted detector signal using at least some of the values in the as-left cabinet calibration data table in an improved signal conversion equation; and using the computing device, employing the converted detector signal to determine the core design parameter.
US11081246B2	Cooling air amount adjustment device of concrete cask and concrete cask A cooling air amount adjustment device of a concrete cask is provided. The device includes at least one of an air outlet port opening level adjustment mechanism and an air inlet port opening level adjustment mechanism which are adapted to automatically perform adjustment to reduce a flow rate of a cooling air when a temperature of the cooling air at an air outlet port is lower than an adjustment reference temperature, and adjustment to increase the flow rate of the cooling air so as to restore the flow rate of the cooling air when the temperature of the cooling air at the air outlet port is higher than the adjustment reference temperature.
US11081240B2	Methods for treatment of hypertension with an angiotensin II receptor blocker pharmaceutical composition A method is provided for lowering blood pressure in a subject in need thereof by administering an angiotensin II receptor blocker pharmaceutical composition to a subject qualified for over-the-counter access to the angiotensin II receptor blocker pharmaceutical composition. In some embodiments, the angiotensin II receptor blocker pharmaceutical composition includes azilsartan medoxomil, candesartan, eprosartan, irbesartan, losartan, olmesartan, telmisartan, or valsartan. In some embodiments, the angiotensin II receptor blocker pharmaceutical composition comprises an active ingredient that is (5-methyl-2-oxo-1,3-dioxol-4-yl)methyl 2-ethoxy-1-{[2′-(5-oxo-4,5-dihydro-1,2,4-oxadiazol-3-yl)biphenyl-4-yl]methyl}-1H-benzimidazole-7-carboxylate or a pharmaceutically acceptable salt thereof.
US11081238B2	Interactive graphical user interfaces for implementing personalized health and wellness programs User-specific medical, genetic, fitness, environmental and nutritional data is collected to develop personalized health and wellness programs for improving a user's health and wellness. The user-specific data may be collected from medical or genetic tests, mobile health devices worn by the user and applications through which the user manually inputs information. The user-specific data is then collected and analyzed together based on knowledge of the interrelationships between medical, genetic, fitness, environmental and nutrition data to develop a comprehensive user profile and personalized health and wellness programs that are targeted to improving specific areas of the user's health by implementing changes in fitness, nutrition, medical treatment, environment, etc. The user is provided with a customizable, interactive dashboard graphical user interface of their current health and wellness data, which, along with notifications, incentives and rewards, helps the user improve their overall health and wellness and significantly reduce their risk of morbidity.
US11081231B1	System and computer implemented method for automatically providing a set of procedures A computer implemented optimization method automatically provides a set of dental procedures to be performed during a scheduled appointment. A processor determines, from the first plurality of dental procedures, a first list of dental procedures that are to be performed for a first patient during the scheduled appointment. The processor also generates a second list of additional dental procedures that are available to be optionally performed for the same first patient during the same scheduled appointment, and ranks the additional dental procedures based on at least one criterion. The processor automatically generates from the first list and from the second list an appointment set of procedures to optimize the billing value of the scheduled first appointment.
US11081225B2	System and method for virtual radiation therapy quality assurance A method comprises receiving one or more plan parameters of a first radiation treatment plan for a first patient and one or more passing rate data for the first treatment plan; generating a predictive model for passing rate data from the plan parameters of the first radiation treatment plan and the passing rate data for the first treatment plan; receiving one or more plan parameters of a second radiation treatment plan for a second patient; and applying the predictive model to the plan parameters of the second radiation treatment to generate one or more predicted passing rate data for the plan parameters for the second patient.
US11081223B2	Collection and display of athletic information Systems and techniques for the collection and display of athletic information. Athletic data relating to a single person or group of people is collected at a central location, and subsequently displayed at a desired remote location so that the person or people can review and critique their performance. In addition, athletic data for multiple persons can be collected at a central location, and subsequently displayed to a user at a desired remote location, so that the user can compare his or her athletic activities to others.
US11081222B2	Obstructive sleep apnea treatment screening methods Embodiments include a screening method for evaluating patient suitability for an implanted hypoglossal nerve stimulation (HGNS) device. The screening method evaluates blood oxygen data relating to respiratory events, with the blood oxygen data providing mean blood oxygen desaturation values for comparison to severity thresholds to identify patients who are likely or unlikely to benefit from the implantation of the HGNS device.
US11081218B2	Method and apparatus for verifying therapeutic compliance An identity standard (a name, cell number, face image, etc.), a therapeutic event standard associated with the identity standard (such as a stored image of a person taking a medication), and a parameter standard associated with the identity standard (e.g. a time range for taking medication) are established. If a transmission (such as a selfie from a cell phone) is observed, that transmission is received and determinations are made as to whether the transmission satisfies the identity standard, the therapeutic event standard, and the parameter standard. If the identity standard, therapeutic event standard, and parameter standard are satisfied, a satisfaction reaction is executed (logging data, sending a confirmation message, etc.).
US11081215B2	Medical record problem list generation Embodiments of the invention include methods, systems, and computer program products for generating a medical problem list. A non-limiting example of the method includes receiving, by a processor, a plurality of disease categories. A disease category set that includes a plurality of top level disease categories is defined using the processor, wherein the disease category set is based at least in part upon the plurality of disease categories. The processor is used to extract a plurality of candidate training problems from an electronic patient record training set. The processor is used to assign each of the candidate training problems to the plurality of top level disease categories. The processor is used to generate a disease category model for each of the top level disease categories from the electronic patient record training set using a machine learning technique.
US11081212B2	System and method for computing drug controlled release performance using images A method for computing the release rate of a controlled release drug and medical device using a combination of imaging data and computational physics is described. The method employs a three-dimensional digital representation of a drug sample, derived from two-dimensional or three-dimensional imaging, which captures the drug active pharmaceutical ingredient (API), excipients, and porosity with distinctive contrasts. Direct numerical simulations are conducted on the three-dimensional digital representation to derive effective transport properties of the API going through a porous matrix or membrane. Drug release rate can be predicted more efficiently than laboratory-based methods. When there is strong heterogeneity presented in the drug, a further method is described that engages imaging and release simulations at multiple scales. Computerized systems and programs for performing the methods are also described.
US11081208B2	Systems, methods, and media for de novo assembly of whole genome sequence data Described are computer-implemented methods, systems, and media for de novo phased diploid assembly of nucleic acid sequence data generated from a nucleic acid sample of an individual utilizing nucleic acid tags to preserve long-range sequence context for the individual such that a subset of short-read sequence data derived from a common starting sequence shares a common tag. The phased diploid assembly is achieved without alignment to a reference sequence derived from organisms other than the individual. The methods, systems, and media described are computer-resource efficient, allowing scale-up.
US11081207B2	Energy expenditure Aspects relate to calculating energy expenditure values from an apparatus configured to be worn on an appendage of a user. Steps counts may be quantified, such as by detecting arm swings peaks and bounce peaks in motion data. A search range of acceleration frequencies related to an expected activity may be established. Frequencies of acceleration data within a search range may be analyzed to identify one or more peaks, such as a bounce peak and an arm swing peak. Novel systems and methods may determine whether to utilize the arm swing data, bounce data, and/or other data or portions of data to quantify steps. The number of peaks (and types of peaks) may be used to choose a step frequency and step magnitude. At least a portion of the motion data may be classified into an activity category based upon the quantification of steps.
US11081206B2	Computational analysis of biological data using manifold and a hyperplane A method of analyzing biological data containing expression values of a plurality of polypeptides in the blood of a subject. The method comprises: calculating a distance between a segment of a curved line and an axis defined by a direction, the distance being calculated at a point over the curved line defined by a coordinate along the direction. The method further comprises correlating the distance to the presence of, absence of, or likelihood that the subject has, a bacterial infection. The coordinate is defined by a combination of the expression values, wherein at least 90% of the segment is between a lower bound line and an upper bound line.
US11081203B2	Leakage source detection by scanning access lines Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.
US11081199B2	Shift register and method of driving the same, gate driving circuit, display device The present application provides a shift register and a method of driving the same, and a gate driving circuit. The shift register includes a detection sub-shift register. The detection sub-shift register includes: a detection input sub-circuit configured to provide a signal of the first input terminal to the pull-up control node under the control of the first clock signal terminal, and provide a signal of the second clock signal terminal to the first pull-up node under the control of the pull-up control node; and a detection output sub-circuit configured to provide a signal of the third clock signal terminal to the first output terminal under the control of the first pull-up node.
US11081198B2	Non-volatile memory with countermeasure for over programming A non-volatile storage system includes a mechanism to compensate for over programming during the programming process. That is, after the programming process starts for a set of data and target memory cells, and prior to the programming process completing for the set of data and the target memory cells, the system determines whether a first group of the memory cells has more than a threshold number of over programmed memory cells. If so, then the system adjusts programming of a second group of memory cells to reduce the number of programming errors.
US11081195B2	Programming process which compensates for data state of adjacent memory cell in a memory device Techniques are provided to compensate for neighbor word line interference when programming memory cells connected to a selected word line WLn. Before programming, the assigned data states of WLn and WLn+1 are compared and corresponding compensation data is generated. The compensation data may be stored in latches of sense circuits to modify the verify tests which occur during programming. The compensation can involve adjusting the bit line voltage, word line voltage, sense node discharge period and/or trip voltage. During a verify test, the compensation data can cause a WLn memory cell to complete programming when its threshold voltage is lower than would be the case with no compensation. When the WLn+1 memory cells are subsequently programmed, an upshift in the threshold voltage of the WLn memory cell offsets the compensation.
US11081193B1	Inverter based delay chain for calibrating data signal to a clock Technology is disclosed herein for correcting skew between data signals and a clock signal. In one aspect, a memory system has a delay circuit having delay blocks, with each delay block having one or more inverters. The delay circuit is configured to pass a data signal through either an odd number of the inverters or an even number of the inverters to produce a delayed data signal. The memory system has a skew correction circuit configured to control the number of inverters in the delay circuit through which the data signal is passed in order to correct skew between the data signal and the clock signal. The memory system has a polarity correction circuit configured to invert the data signal in the event that the delay circuit passed the data signal through the odd number of the inverters.
US11081181B2	Flash memory and method for operating the same A flash memory of the invention has a plurality of planes, a controller, a switch unit, and a driving control circuit. The controller is configured to select at least one of the planes. The switch unit is configured to electrically connect bit lines of the unselected plane to a reference voltage. The driving control circuit is configured to commonly provide a gate select signal to select transistors of the selected planes and the unselected planes after the bit lines of the unselected plane is electrically connected to the reference voltage. A flash memory that can reliably seek stability of threshold distribution of memory is provided.
US11081180B2	Memory device with bit lines disconnected from NAND strings for fast programming Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.
US11081179B2	Pre-charge voltage for inhibiting unselected NAND memory cell programming Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming.
US11081178B2	Memory, information processing system, and method of controlling memory Reliability of stored data is improved without increasing power consumption in a case where a threshold of a control element in a memory cell changes. In a memory including the memory cell, a reference cell, and an access control unit, the memory cell changes from a non-conduction state to a conduction state according to an applied voltage at a threshold voltage and changes to a high resistance state and a low resistance state according to the voltage applied in the conduction state. The reference cell changes from a non-conduction state to a conduction state at a reference threshold voltage according to an applied voltage. The access control unit estimates that the reference threshold voltage measured in the reference cell is the threshold voltage of the memory cell and applies a voltage to the memory cell when accessing the memory cell.
US11081174B2	Set/reset methods for crystallization improvement in phase change memories A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.
US11081173B2	Via formation for cross-point memory Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.
US11081166B1	Memory device random option inversion Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.
US11081165B2	Memories for decoding memory access addresses for access operations Memories having block select circuitry having an output that is selectively connected to a plurality of driver circuitries, with each driver circuitry connected to a respective block of memory cells.
US11081163B2	Information processing apparatus, information processing system, and semiconductor storage device According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position.
US11081162B1	Source side precharge and boosting improvement for reverse order program This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.
US11081152B2	Dynamic random access memory (DRAM) device, memory controller therefor, and memory system A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.
US11081151B2	Techniques to improve a read operation to a memory array Examples may include techniques to improve a read operation to a memory array. Examples include identifying characteristics of memory cells in the memory array such as relative positions of memory cells within the memory array and then set multiple read reference voltages or currents to detect a memory state of memory cells based on identified characteristics.
US11081148B2	Binary weighted voltage encoding scheme for supporting multi-bit input precision An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.
US11081141B2	Processing and formatting video for interactive presentation Systems and methods are described for determining a first media item related to an event, of a plurality of stored media items each comprising video content related to the event, that was captured in a device orientation corresponding to a first device orientation detected for the first computing device; providing, to the first computing device, the first media item to be displayed on the first computing device; in response to a detected change to a second device orientation for the first computing device, determining a second media item that was captured in a device orientation corresponding to the second device orientation detected for the first computing device; and providing, to the first computing device, the second media item to be displayed on the first computing device.
US11081140B1	Systems and methods for generating templates for short-form media content The disclosed computer-implemented method may include extracting, from a baseline video file, metadata that identifies at least one characteristic of the baseline video file, creating, using the extracted metadata as a framework, a template for remixing the baseline video file with new content, obtaining at least one new item of content, and creating, using the template, a remixed version of the baseline video file by replacing at least one original item of content in the baseline video file with the new item of content. Various other methods, systems, and computer-readable media are also disclosed.
US11081138B2	Systems and methods for automated music rearrangement A method and apparatus of a device that builds a target using a plurality of processing units is described. In an exemplary embodiment, the device receives an input audio track having a first duration, the input audio track having a plurality of points. The device further generates a transition matrix of the input audio track, wherein the transition matrix indicates a similarity metric between different pairs of the plurality of points. In addition, the device determines a set of jump points using the different pairs of the plurality of points. The device additionally generates the rearranged audio track using the set of jump points, wherein the rearranged audio track has second duration and the second duration is different than the first duration.
US11081130B1	Suspension standoff arrangement for confining adhesive A head gimbal assembly for a data storage device is provided. The head gimbal assembly includes a suspension, and a slider mounting point on the suspension. The slider mounting point includes an adhesive pocket bounded by a plurality of dielectric standoffs.
US11081126B2	Processing of sound data for separating sound sources in a multichannel signal A method for processing sound data for separating N sound sources of a multichannel sound signal sensed in a real medium. The method includes: separating sources to the sensed multichannel signal and obtaining a separation matrix and a set of M sound components, with M≥N; calculating a set of bi-variate first descriptors representative of statistical relations between the components of the pairs of the set obtained of M components, calculating a set of uni-variate second descriptors representative of characteristics of encoding of the components of the set obtained of M components; and classifying the components of the set of M components, according to two classes of components, a first class of N direct components corresponding to the N direct sound sources and a second class of M−N reverberated components, by calculating probability of membership in one of the two classes, dependent on the sets of first and second descriptors.
US11081124B2	Acoustic echo canceling Systems and methods are provided for acoustic echo canceling. In one embodiment, a system for canceling acoustic echoes comprises one or more microphones configured to pick up sound generated by a sound source and transferred from the sound source to the one or more microphones via one or more unknown transfer paths having one or more unknown transfer functions, and to provide one or more electrical microphone signals therefrom, one or more adaptive filters for approximating the one or more unknown transfer functions with one or more estimated transfer functions and filtering one or more electrical signals representative of the sound generated by the sound source with the one or more estimated transfer functions to provide one or more estimated signals therefrom, and a microphone calibration block configured to individually attenuate or amplify the one or more electrical microphone signals dependent on the one or more estimated transfer functions.
US11081122B2	Method for coding by random acoustic signals and associated transmission method The invention relates to a method for coding information symbols of an alphabet into random acoustic signals. The coding dictionary is constructed in a heuristic manner by acquiring a set of random signals, by filtering same by way of the equivalent filter of the transmission channel, by selecting subsets of these signals, and, for each subset, by calculating the correlation matrix of the selected signals, the coding dictionary being constituted by the subset for which the correlation matrix most closely resembles a diagonal matrix. The invention also relates to a method for transmitting and receiving information symbols by way of acoustic signals.
US11081121B2	Signal processing method and device A signal processing method and device includes obtaining spectral coefficients of a current frame of an audio signal, in which N sub-bands of the current frame comprises at least one of the spectral coefficients. A total energy of M successive sub-bands of the N sub-bands, a total energy of K successive sub-bands of the N sub-bands, and an energy of a first sub-band are obtained to determine whether to modify original envelope values of the M sub-bands. When the original envelope values of the M sub-bands are modified, encoding bits are allocated to each of the N sub-bands according to the modified envelope values of the M sub-bands.
US11081119B2	Enhancement of spatial audio signals by modulated decorrelation Some methods involve receiving an input audio signal that includes N input audio channels, the input audio signal representing a first soundfield format having a first soundfield format resolution, N being an integer ≥2. A first decorrelation process may be applied to two or more of the input audio channels to produce a first set of decorrelated channels, the first decorrelation process maintaining an inter-channel correlation of the set of input audio channels. A first modulation process may be applied to the first set of decorrelated channels to produce a first set of decorrelated and modulated output channels. The first set of decorrelated and modulated output channels may be combined with two or more undecorrelated output channels to produce an output audio signal that includes O output audio channels representing a second and relatively higher-resolution soundfield format than the first soundfield format, O being an integer ≥3.
US11081116B2	Embedding enhanced audio transports in backward compatible audio bitstreams In general, techniques are described by which to embed enhanced audio transports in backward compatible bitstreams. A device comprising a memory and one or more processors may be configured to perform the techniques. The memory may store the backward compatible bitstream, which conforms to a legacy transport format. The processor(s) may obtain, from the backward compatible bitstream, legacy audio data that conforms to a legacy audio format, and obtain, from the backward compatible bitstream, extended audio data that enhances the legacy audio data. The processor(s) may also obtain, based on the legacy audio data and the extended audio data, enhanced audio data that conforms to an enhanced audio format, and output the enhanced audio data to one or more speakers.
US11081115B2	Speaker recognition A biometric is formed for at least one enrolled speaker by: obtaining a sample of speech of the enrolled speaker; obtaining a measure of a fundamental frequency of the speech of the enrolled speaker in each of a plurality of speech frames; and forming a first distribution function of the fundamental frequency of the speech of the enrolled speaker. Subsequently, for a speaker to be recognised, a sample of speech of the speaker to be recognised is obtained. Then, a measure of a fundamental frequency of the speech of the speaker to be recognised is obtained in each of a plurality of speech frames. A second distribution function of the fundamental frequency of the speech of the speaker to be recognised is formed, the second distribution function and the first distribution function are compared, and it is determined whether the speaker to be recognised is the enrolled speaker based on a result of comparing the second distribution function and the first distribution function.
US11081113B2	Idea scoring for creativity tool selection An intelligence-driven virtual assistant for automated documentation of new ideas is provided. During a brainstorming session, one or more user participants may discuss and identify one or more ideas. Such ideas may be tracked, catalogued, analyzed, developed, and further expanded upon through use of an intelligence-driven virtual assistant. Such virtual assistant may capture user input data embodying one or more new ideas and intelligently process the same in accordance with creativity tool workflows. Such workflows may further stimulate creativity for capturing ideas, while continuing to document, analyze, and identify further aspects to develop and expand.
US11081110B2	Dialogue processing system using speech act control and operation method thereof Disclosed is a dialogue processing system using speech act control, the dialogue processing system comprising: a main speech act unit which processes a free speech act and performs speech act control such that the free speech act returns to a main speech act, thereby processing a multi-turn dialogue in a consistent manner, and which processes a purposed utterance having a set purpose, for reaching a final dialogue objective; and a free speech act unit which processes a free utterance deviating from the purposed utterance and performs control such that the free utterance returns to the main speech act unit by searching for a node capable of returning to the purposed utterance.
US11081109B2	Speech processing method using artificial intelligence device Provided is a speech processing method using an AI device. The speech processing method using an AI device according to an embodiment of the present invention includes receiving a speech command of a speaker, determining a recipient of the speech command by performing a speech recognition operation on the speech command, checking whether the recipient receives feedback corresponding to the speech command, selecting a second AI device which is closest to the recipient based on pre-stored positional information of a plurality of AI devices in a specific space and positional information of the recipient by obtaining the positional information of the recipient if there is no feedback, and transmitting a notification message notifying the speech command to the second AI device. As a result, the speech command of the speaker can be successfully transmitted to a recipient when the recipient does not receive the speech command of the speaker.According to the present invention, at least one of an autonomous vehicle, a user terminal, and a server may be linked with an artificial intelligence module, a drone (unmanned aerial vehicle (UAV)), a robot, an augmented reality (AR) device, a virtual reality (VR) device, devices related to 5G services and the like.
US11081106B2	Contextual spoken language understanding in a spoken dialogue system A spoken dialogue system includes a spoken language understanding apparatus. The spoken language understanding apparatus can include an intent apparatus and a selection apparatus. The intent apparatus is configured to determine if a query comprises a global command, to determine if an intent associated with a query is or is not included in a domain that is supported by the spoken dialogue system, to determine if a query comprises a confirmation type, to tag one or more entities in a query, and to determine an intent probability distribution and a domain probability distribution that is associated with a query. When the query includes an entity that is included in two or more possible entities, the selection apparatus is configured to provide a score for each of the two or more possible entities.
US11081104B1	Contextual natural language processing A natural language understanding system that can determine an overall score for a natural language hypothesis using hypothesis-specific component scores from different aspects of NLU processing as well as context data describing the context surrounding the utterance corresponding to the natural language hypotheses. The individual component scores may be input into a feature vector at a location corresponding to a type of a device captured by the utterance. Other locations in the feature vector corresponding to other device types may be populated with zero values. The feature vector may also be populated with other values represent other context data. The feature vector may then be multiplied by a weight vector comprising trained weights corresponding to the feature vector positions to determine a new overall score for each hypothesis, where the overall score incorporates the impact of the context data. Natural language hypotheses can be ranked using their respective new overall scores.
US11081103B2	Speech recognition method, apparatus, and computer readable storage medium Disclosed are a speech recognition method, apparatus, computer device and storage medium. The method includes: performing a framing and an acoustic feature extraction of a speech-information-to-be-tested according to a default rule to obtain a frame-level speech feature sequence; dividing the frame-level speech feature sequence into n blocks sequentially; inputting all blocks into a preset bidirectional LSTM-RNN model parallelly to obtain an output result of the corresponding neuron in an output layer of the preset bidirectional LSTM-RNN model corresponding to the forward recognition result and backward recognition result of each block to obtain a speech recognition result of the speech-information-to-be-tested. The present application can improve the speech recognition effect significantly and reduce the time delay of the speech decoding effectively.
US11081101B1	Real time popularity based audible content acquisition A personalized news service provides personalized news programs for its users by generating personalized combinations of audible versions of news stories derived from text-based based versions of the news stories. The audible versions may be generated from the text-based version by a text-to-speech system, or may by recording a person reading aloud the text-based version. To acquire recordings, the personalized news service can make a determination that a particular news story has a threshold extent of popularity. The news service can then transmit a request to a remote recording station for a recording of a verbal reading of the particular news story. The news service can then receive the requested recording from the remote recording station.
US11081093B1	Music notation system An improved music notation system. The music notation system broadly uses numbers for notes, colors for octaves or scales, and bars and symbols for note duration. The system is easy to team and use and can be adapted for use by any instrument, e.g., a keyboard instrument.
US11081086B2	Display method and apparatus One example display method includes in response to receiving a display request from a target display device, determining a first display device and a second display device that support display of a target service, when a first distance between the first display device and a user is less than a second distance between the second display device and the user, obtaining current first display data of the target service from the target display device and sending the current first display data to the first display device, and when that the first distance reported by the first display device is greater than the second distance reported by the second display device is subsequently obtained, obtaining current second display data of the target service from the target display device and sending the current second display data to the first display device and the second display device.
US11081081B2	Color gamut conversion method, color gamut converter, display device, image signal conversion method, computer device and non-transitory storage medium A color gamut conversion method, a color gamut converter, a display device, an image signal conversion method, a computer device and a non-transitory storage medium are disclosed. The method includes: acquiring RGB signals and a preset grayscale value of a white subpixel in each pixel of a converted image according to grayscale values of monochromatic subpixels in each pixel of an original image corresponding to the RGB signals, the converted image is obtained by converting the original image from an RGB gamut to an RGBW gamut; and acquiring a target grayscale value of the white subpixel at least according to a first maximum grayscale of the white subpixels and the preset grayscale. As for a first saturation color patch in the original image, a first maximum grayscale of a white subpixel corresponding to each pixel in the first saturation color patch is equal to a grayscale threshold.
US11081078B2	Common voltage compensation circuit unit, display panel, display device, and common voltage compensation method for display panel A common voltage compensation circuit unit including a trigger signal terminal, a common voltage output terminal, a design common voltage signal terminal, a power signal terminal, a compensation common voltage signal terminal, a reset signal terminal, a clock signal terminal, a trigger signal input sub-circuit, a first output sub-circuit, a control sub-circuit, a second output sub-circuit, and a reset sub-circuit. The present disclosure further provides a display panel, a display device, and a common voltage compensation method for a display panel.
US11081076B2	Display device controlling an output timing of a data signal A display device includes a signal controller configured to provide data and a frame control signal, a display panel including first to m-th data line groups, and a data driver configured to receive the data and the frame control signal, and output a data signal corresponding to the data to the first to m-th data line groups. The data driver includes first to m-th data driving circuit units electrically connected to the first to m-th data line groups in one-to-one correspondence, Each of the first to m-th data driving circuit units includes a clock adjustment unit configured to generate a second clock signal using a first clock signal and the frame control signal. The second clock signal controls an output timing of the data signal to be transmitted to a first channel among a plurality of channels of each of the first to m-th data line groups.
US11081074B2	Driving circuit and display driving device Provided are a driving circuit and a display driving device, comprising: when a signal processing module acts on any control signal, only the path of the display signal outputting to the sources of transistors in a portion of the corresponding sub-pixels is turned on, enabling this portion to complete the display of sub-pixels. At the same time, the reference voltage is connected to the reference voltage terminal of the other portion of the corresponding sub-pixels, so that the pixel electrode of the other portion is charged to the reference voltage. On such basis, before each control signal is inverted, a portion of the sub-pixels is in operation, and the other portion is precharged to the reference voltage, thereby improving the charging efficiency of the pixel electrodes, and ensuring that the voltage on the pixel electrodes can be switched to a target voltage.
US11081069B2	Data rendering and driving of electronic device displays Aspects of the subject technology relate to displays for electronic devices and methods of operating the displays. The display may include an array of display pixels arranged in rows and columns. A v-drive operation in which rows are alternatingly operated about a center of each of two halves of the display is provided. Data rendering operations are provided that generate a virtual frame rate boost.
US11081068B2	Liquid crystal display device and video signal processing method A liquid crystal display device that displays an input video signal according to a present disclosure comprises: a first liquid crystal display panel and a second liquid crystal display panel disposed to be laminated; a first video signal generator that generates a first video signal for the first liquid crystal display panel by performing stereoscopic vision suppression processing of suppressing stereoscopic vision due to parallax on the video signal; and a second video signal generator that generates a second video signal for the second liquid crystal display panel using the first video signal, wherein when the video signal indicates a black spot, the first video signal generator performs the stereoscopic vision suppression processing with intensity different from that in a case where the video signal indicates a bright spot.
US11081067B2	Display substrate of electronic ink screen and display device thereof A display substrate of an electronic ink screen and a display device thereof are disclosed. The display substrate of the electronic ink screen includes: a base substrate having a display region and a non-display region; a display structure disposed in the display region of the base substrate; and a photoelectric conversion device disposed in the non-display region of the base substrate, wherein the photoelectric conversion device is connected to a driving circuit of the electronic ink screen and is configured to convert an optical signal of ambient light of the electronic ink screen to an electrical signal so as to supply power to the driving circuit.
US11081063B2	Organic light emitting display device and method of testing the same An organic light emitting display device includes scan lines arranged in horizontal lines, data lines intersecting the scan lines, a pixel array including pixels coupled to the scan lines and the data lines, the pixels including at least first color pixels, a panel tester including switching elements coupled to first ends of the data lines, the switching elements including at least first and second switching elements, and a first line coupled to the first switching elements and a second line coupled to the second switching elements. Data lines of K-th to (K+L)-th (where K and L are natural numbers) first color pixels arranged in a predetermined horizontal line are coupled to the first line through the first switching elements, and data lines of at least a part of remaining first color pixels arranged in the predetermined horizontal line are coupled to the second line through the second switching elements.
US11081060B2	Display device and method for driving the same A display device includes: a display panel including a plurality of pixels each coupled to a scan line and a data line; a scan driver for supplying a scan signal having at least one scan pulse to the scan line; and a pulse controller for adjusting a number of the scan pulses supplied during one frame, based on an image variation between a previous frame and a current frame.
US11081055B2	Active matrix-based electronic apparatus including a light emitting device that may be non-foward biased to sense light, and method of driving the same Disclosed are an active matrix-based electronic apparatus and a method of driving the same. More particularly, a pixel circuit of an electronic apparatus according to an embodiment of the present disclosure may include a light-emitting driver configured to apply a forward bias to a light-emitting device in an emission mode to control light to be emitted through the light-emitting device; a sensing driver configured to apply a non-forward bias to the light-emitting device in a sensing mode to control an electrical signal corresponding to light incident on the light-emitting device to be generated; and a reader configured to read intensity of light corresponding to the generated electrical signal.
US11081051B2	Pixel compensation circuit Provided is a pixel compensation circuit, which includes a signal amplification circuit, a signal storage circuit, a comparison calculation circuit and a signal compensation circuit. The signal amplification circuit collects an anode potential of an organic light emitting element and a driving current, such that the signal storage circuit can determine a threshold voltage of the driving transistor and a preset gray-scale voltage based on the anode potential and the driving current. The comparison calculation circuit calculates a compensation voltage required for the pixel while actually operating based on the threshold voltage, the anode potential and the preset gray-scale voltage. Thus, when a display gray-scale voltage is inputted, it can be compensated using the compensation voltage and then outputted to a gate of the driving transistor, such that the driving transistor can drive the organic light emitting element to emit light.
US11081049B2	Pixel and display device having the same A pixel in a display device includes a light emitting element, a first transistor for controlling an amount of current flowing from a first power source to a second power source via the light emitting element corresponding to a voltage applied to a first node, and second and third transistors coupled in series between a holding power source and a second node coupled to one electrode of the first transistor, wherein the second transistor includes a gate electrode coupled to an emission control line, and wherein the third transistor includes a gate electrode coupled to a scan line.
US11081042B2	Gate driving unit, driving method thereof, gate driving circuit and display device A gate driving unit includes a shift register including a forward input sub-circuit and a backward input sub-circuit, and a forward-backward scanning controller. The forward-backward scanning controller transmits a first clock signal provided by the first clock signal terminal to the forward input sub-circuit and the backward input sub-circuit for forward scanning, and transmits a second clock signal provided by the second clock signal terminal to the forward input sub-circuit and the backward input sub-circuit for backward scanning. The forward input sub-circuit transmits a signal provided by the forward-backward scanning controller to the pull-up node under control of an enabling signal provided by the forward scanning input terminal, and the backward input sub-circuit transmits the signal provided by the forward-backward scanning controller to the pull-up node under control of an enabling signal provided by the backward scanning input terminal.
US11081036B1	Slew rate enhancement circuit The disclosure provides a slew rate enhancement apparatus that is connected to an operational amplifier that receives an input signal and generates an output signal according to the input signal for driving a pixel. The slew rate enhancement apparatus comprises a signal edge detector, a comparator, an adjustment unit. The signal edge detector is coupled to the operational amplifier and configured to detect a signal edge and outputting a difference signal corresponding to a difference between the input and output signals. The comparator is coupled to the signal edge detector to receive the difference signal and configured to generate a control signal according to the difference signal. The adjustment unit is coupled to the comparator to receive the control signal, and configured to couple a compensation signal generated by a current source to the operational amplifier according to the control signal to enhance a slew rate of the operation amplifier.
US11081032B2	Display circuitry and method to utilize segmented resistors for optimizing front of screen performance Aspects of the subject technology relate to control circuitry for displays. A display control circuitry includes a plurality of amplifiers to drive gamma signals for a pixel array having a plurality of pixels of a display and a segmented resistor string coupled to the plurality of amplifiers. The resistor string includes a plurality of resistor segments with a resistor segment being designed with a modified resistance to modify display performance parameters including at least one of a settling time of an associated gamma signal, a power supply rejection ratio (PSRR) of an amplifier of the plurality of amplifiers, or an output voltage offset of an amplifier of the plurality of amplifiers.
US11081029B2	Method for evaluating brightness measurement accuracy of Demura equipment The invention discloses a method for evaluating a brightness measurement accuracy of a Demura equipment by generating a noise-added image by adding a random number to an original grayscale image and obtaining a measurement value corresponding to the added random number via the noise-added image displayed by the Demura equipment. The brightness measurement accuracy of the Demura equipment is evaluated based on a correlation between the measured value and the originally added random number to measure a brightness extraction performance of the Demura equipment. The method provided by the invention provides a quantitative and measurable determining method that may better reflect the actual performance of the Demura equipment.
US11081028B2	Light-emitting device assembly, method of producing the same, and display apparatus A light-emitting device assembly includes a light-emitting device including a light-emitting layer, a first electrode, and a second electrode, and a first connecting portion and a second connecting portion provided on a base, in which the first connecting portion and the second connecting portion are separated from each other by a separation portion, the base is exposed from the separation portion, a wide portion is on a first connecting portion side of the separation portion, the first electrode includes a first portion and a second portion, the second portion of the first electrode is connected to the first connecting portion, the first portion of the first electrode extends from the second portion of the first electrode, and an orthographic projection image of the first portion of the first electrode with respect to the base and the wide portion of the separation portion overlap with each other at least in part.
US11081024B2	Secure computation system, secure computation device, secure computation method, and program Fisher's exact test is efficiently computed through secure computation. It is assumed that a, b, c and d are frequencies of a 2×2 contingency table, [a], [b], [c] and [d] are secure texts of the respective frequencies a, b, c and d, and N is an upper bound satisfying a+b+c+dN. A reference frequency computation part computes a secure text ([a0], [b0], [c0], [d0]) of a combination of reference frequencies (a0, b0, c0, d0) which are integers satisfying a0+b0=a+b, c0+d0=c+d, a0+c0=a+c, and b0+d0=b+d. A number-of-patterns determination part determines integers h0 and h1 satisfying h0≤h1. A pattern computation part computes [ai]=[a0]+i, [bi]=[b0]−i, [ci]=[c0]−i and [di]=[d0]+i for i=h0, . . . , h1, and obtains a set S={([ai], [bi], [ci], [di])}i of secure texts of combinations of frequencies (ai, bi, ci, di).
US11081022B2	Instructional board for knitting A knitting board is provided. The instruction board includes a front side and a back side, each hinged attached to a spine. The hinge attachments will allow the front side and the back side to open into an A-frame. The front side has a window therethrough. The front side has a plurality of connectors at least located above the window. The connectors can moveably secure a plurality of instruction cards thereto. The instruction cards can display a desired topics such as the steps for various knitting techniques, thereon. A card marker located as part of the plurality of instruction cards can mark a place on the instruction card, such as the last place a user was at when they stopped the Instructional board for knitting.
US11081019B2	Analyzing or emulating a vocal performance using audiovisual dynamic point referencing The systems and methods taught herein are generally directed to a dynamic point referencing of an audiovisual performance for an accurate and precise selection and controlled cycling of portions of the performance. The dynamic point referencing can be used by a learning artist, for example, in analyzing or performing a portion of the work through an accurate and precise digital audio/video instructional method having the controlled cycling feature. Such systems and methods will be appreciated, for example, by musicians, dancers, and other enthusiasts of the performing arts.
US11081018B2	Personalized learning system and method for the automated generation of structured learning assets based on user data Learning systems and methods of the present disclosure include generating a text document based on a digital file, tokenizing the text document, generating a semantic model based on the tokenized text document using an unsupervised machine learning algorithm, assigning a plurality of passage scores to a corresponding plurality of passages of the tokenized text document, selecting one or more candidate knowledge items from the tokenized text document based on the plurality of passage scores, filtering the one or more candidate knowledge items based on user data, generating one or more structured learning assets based on the one or more filtered candidate knowledge items, generating an interaction based at least on the one or more structured learning assets, and transmitting the interaction to a user device. Each passage score is assigned based on a relationship between a corresponding passage and the semantic model.
US11081016B2	Personalized syllabus generation using sub-concept sequences One embodiment provides a method, including: receiving input identifying a goal of a student, wherein the goal indicates (i) a target concept to be learned by the student and (ii) a desired expertise corresponding to the target concept; receiving input indicating constraints comprising (i) a time budget and (ii) an effort budget; and generating a syllabus for the student to reach the goal, wherein the syllabus comprises a sequence of sub-concepts to be learned for reaching the goal, by: producing a plurality of alternative sequences of sub-concepts for reaching the identified goal, each sequence of sub-concepts having both a determined, corresponding (i) effort cost and (ii) time cost, wherein determining the corresponding effort cost and time cost comprises identifying relationships between sub-concepts; and determining, from the plurality of alternative sequences, a particular one of the sequences that reaches the target concept at the desired expertise and fulfills the indicated constraints.
US11081015B2	Training device, training method, and program A training device, which is used to cause a user to be trained to operate an extra part based on a measurement result of user's brain activity, notifies the user of information indicating a degree of activation of a brain area corresponding to the extra part, as information indicating the state of the brain activity of the user who imagines trying to operate the extra part.
US11081010B2	Automatically pairing GPS data to planned travel routes of mobile objects GPS data is paired with planned travel routes for mobile objects including vehicles. A system obtains GPS data from a mobile object and compares the GPS data to planned travel routes. The comparison includes comparing GPS coordinates of the mobile object to the planned travel routes to determine if a specified level of GPS coordinates are within a specified distance or buffer distance from a planned travel route within a specified period of time, the mobile object is travelling in the same direction of a planned travel route, and the planned travel route is unique. If such conditions are met, the mobile object is assigned or matched to a planned travel route.
US11081006B2	System and method for high accuracy location determination and parking The various systems and methods disclosed herein provide for a secure, cost effective, and high accuracy location detection. In some embodiments of the system and method for high accuracy location detection, a mobile location device obtains and calculates location data from a plurality of sources without requiring expensive and power inefficient processors. In some embodiments, such secure, cost effective, and high accuracy location detection by the mobile location device is used in improved parking and payment management systems and methods. In some such embodiments, the location device communicates with remote geomapping servers and payment systems to provide automated parking and payment.
US11081005B2	Distributed remote sensing system gateway A distributed remote sensing system including a group of gateways and a sensing device group associated with each gateway in the group of gateways wherein the sensing device group associated with one gateway is different than another sensing device group associated with a different gateway.
US11081003B2	Map-providing server and map-providing method A map-providing server includes: a travel information database creation unit that receives position information of a vehicle and vehicle brake application information; a place of residence estimation unit that estimates the position of the place of residence of a vehicle; a sudden braking location identification unit that identifies a location of the occurrence of vehicle sudden braking from information from the travel information database creation unit; a unit for determining the cause of sudden braking, which determines whether the location where sudden braking has occurred locally, at a position within a predetermined range from the position of the place of residence of the user of the vehicle; and a unit for recording sudden braking information that records, on map information, the location where sudden braking has occurred, in association with information indicating whether the vehicle user is a local resident.
US11081000B2	Method and system for generating heading information of vehicles A method, system, and computer program product is provided, for example, for generating heading information. The method comprises receiving a coordinate information for a gantry. The method further comprises receiving an identification information for a link associated with the gantry. Additionally, the method comprises extracting information related to one or more shape points associated with the link based on the identification information. Further, the method comprises matching the coordinate information for the gantry with at least two consecutive shape points from the one or more shape points, wherein the at least two consecutive shape points are closest from the gantry. Also, the method comprises calculating, by a processor, a heading value for the gantry based on the matching. The heading value for the gantry may be used to identify direction information for the gantry, which may further be used for updates.
US11080999B2	Traffic application instance processing method and traffic control unit An example method includes obtaining, by a first local traffic control unit (TCU), a traffic application type and first traffic information. The first local TCU can then determine an interaction coverage area based on the traffic application type and the first traffic information. The first local TCU can then determine a first area and send the traffic application type and the first traffic information to a global TCU, where a second local TCU is a local TCU adjacent to the first local TCU, where the first area is at least one overlapping area between a management area of a third local TCU and the interaction coverage area, and where the third local TCU is a local TCU not adjacent to the first local TCU.
US11080991B1	Dynamic gauges for displaying present and predicted machine status A facility creates a dynamic gauge for indicating the status of equipment. The facility causes a gauge to be displayed with an initial satisfactory range and an initial unsatisfactory range. The facility accesses historical data describing the status of a sensor attached to equipment. The facility determines a new satisfactory range and a new unsatisfactory range, and alters the gauge to visually indicate the new satisfactory range and the new unsatisfactory range.
US11080989B2	Method for assigning a smoke detector to be registered and a corresponding smoke detector management system A method for assigning a smoke detector (2) to be registered to a user profile (11) of a smoke detector management system (1), comprising the steps: establishing a data connection between the smoke detector (2) and a server (3) and transmitting first identification data (6) of the smoke detector (2) to the server (3); establishing a data connection between a mobile device (4) and the server (3); logging into the user profile (11) by means of the mobile device (4) using the user identification data (5); transmitting second identification data (7) of the smoke detector (2) to be registered to the mobile device (4); transmitting the second identification data (7) and/or the user identification data (5) to the server (3) by means of the mobile device (4); and identifying the smoke detector (2) by means of the first and/or second identification data (6; 7) and assigning the smoke detector (2) to the logged in user profile (11) or the user profile (11) corresponding to the user identification data (5).
US11080986B1	Firefighter accountability assembly A firefighter accountability assembly includes a master board that is mounted on a vertical support surface thereby facilitating the master board to be visible to a user. A plurality of panels is included and each of the panels is assigned to a respective one of a plurality of emergency vehicles. A plurality of tumbler units is provided and each of the tumbler units is rotatably coupled to a respective one of the panels. Each of the tumbler units has a plurality of numbers printed thereon and each is assigned to an emergency responder. Each of the tumbler units is manipulated by the assigned emergency responder to display a pre-determined numerical code that has been assigned to the assigned emergency responder. In this way each of the tumbler units on each of the panels displays the emergency responders that are assigned to and are on board each of the emergency vehicles.
US11080982B1	Leakage detection and location system in an irrigation network A system and method for determining a location of a leak within an irrigation network. The irrigation network is monitored for an indication that a leak has occurred, and then can evaluate the severity of the leak. At least one mobile sensing unit is selected to deploy across the irrigation network in response to the indication of a leak. Instructions are generated and sent to the at least one mobile sensing unit including information as to where in the irrigation network the at least one mobile sensing unit is to go. The mobile sensing unit is deployed into the irrigation network. A location of the leak within the irrigation network is determined based at least upon data gathered by the mobile sensing units while it is deployed in the irrigation network. An alert about the leak is sent in response to determining the location of the leak.
US11080976B2	Real time bypass detection in scanner A terminal includes an item scanner. The item scanner determines whether an item that passes within a field of view of the scanner during a transaction has a properly noted barcode recorded for the transaction. When the item fails to have a properly noted barcode an alert is raised in real time for assistance and/or investigation of the transaction.
US11080975B2	Theft proof techniques for autonomous driving vehicles used for transporting goods Various techniques for theft proofing autonomous driving vehicles (ADV) for transporting goods are described. In one embodiment, sensor data of a moving object representing a person within a predetermined proximity of an ADV are captured for real-time analysis by a theft detection module, to determine a moving behavior of the moving object based on the sensor data in view of a set of known moving behaviors. The theft detection module further determines whether an intention of the person is likely to remove at least some of the goods from the ADV using a process derived from historical image set, and sends an alarm to a predetermined destination in response to determining such an intention of the person. Other sensor data, for example, real time movements and weights of the ADV, can be used in conjunction with the process derived from historical image sets to determine the intention of the person.
US11080973B2	Burglary alarm assembly A burglary alarm assembly for alerting emergency responders to a forced entry includes a window that is positionable in a window opening in a building. A sensing sheet is integrated into the window and the sensing sheet is comprised of a translucent material to pass light therethrough. The sensing sheet is comprised of a brittle material thereby facilitating the sensing sheet to be broken when the window is damaged. An alarm unit is in electrical communication with the sensing sheet. The alarm unit receives an alarm input when the sensing sheet is broken to detect when the window has been damaged by a potential intruder. Moreover, the alarm unit communicates a distress call to emergency responders to alert the emergency responders to the potential of a forced entry at the building.
US11080972B2	Notification and alert method for wearable and/or other devices Systems and methods for delivering alerts, notifications and messages, to and, if configured, responses from one to many users wearing technology designed for single and/or multiple media types, utilizing one to many non-primary communication pathways enabled are contemplated in which (a) a primary communication channel pathway, (b) a primary or non-primary control channel(s) is established, by wireless receiver and/or wired connection to a group of users, that (b) then allows an activation method type to provide an alert/notification/message method to one-to-many persons (i.e., users) and/or, one-to-many devices in an addressable manner that establishes a non-primary communication channel path that is parallel and unknown to the primary communication channel path. The overall method consists of a router function and media delivery routing technology) that are actively listening on a primary communication/control pathway or a non-primary control channel. If an activation method is utilized over the communication pathway or non-primary control channel and an activation is designated for specific device(s) assigned within a specific non-primary communication channel pathway, then a delivery method for that device(s) is invoked that processes and delivers the non-primary media (audio, visual, and sensory) based on the command type, any local settings and the media type transmitted. In addition, the wearable device may also include connection to a specialized, logical audio router that manages non-primary communication channels and ‘cut-ins’ or ‘super-imposition’ functions for the delivery of alerts, notifications, and messages as an overlay on the primary communications channel that all users present may then hear, see, feel and/or respond via available methods through the appropriate primary and/or non-primary communications channel.
US11080967B2	Back-betting using a mobile device or other computing device The present disclosure relates generally to gaming systems and, in particular, to back-betting within a gaming system. As an example, a back-betting system is disclosed to include a first communication interface that facilitates machine-to-machine communications with an Electronic Gaming Machine (EGM) of a gaming system, where the first communication interface is used to exchange state-of-play information with the EGM. The system is also disclosed to include a second communication interface that facilitates machine-to-machine communications with a mobile device, where the second communication interface is used to exchange back-bet wager information and deliver an indication of an outcome of a back-bet placed during a back-betting session established with the mobile device. The system may still further include a processor and a computer-readable storage medium with processor-executable instructions that limit a duration of the back-betting session based on an association existing between the EGM and the mobile device.
US11080965B2	Systems and methods for incrementally increasing a tiered plurality of progressive jackpots An electronic gaming system includes a progressive system server configured to establish a tiered plurality of progressive jackpots that includes a first jackpot increasable a first cap value, a second jackpot increasable to a second cap value greater than the first cap value, and at least one intermediate jackpot increasable to at least one intermediate cap value greater than the first cap value and less than the second cap value. The progressive system server is further configured to allocate portions of player wagers to one of i) the first jackpot, ii) the at least one intermediate jackpot, and iii) the second jackpot, whereby the first jackpot is initially incrementally increased to the first cap value, the at least one intermediate jackpot is next incrementally increased to the at least one intermediate cap value, and the second jackpot is next incrementally increased to the second cap value.
US11080958B2	Vehicle window assembly with integrated touch/proximity sensor A vehicular window assembly includes a laminated glass window panel comprising an inner glass sheet and an outer glass sheet that are laminated together. A sensing device is disposed between the inner and outer glass sheets and includes a plurality of sensors and a plurality of illumination sources. With the laminated glass window panel disposed at a vehicle and when one or more of said illumination sources are activated, a person viewing the laminated glass window panel from exterior of the vehicle views one or more of a plurality of icons or alphanumeric characters illuminated by light emitted by the activated respective one or more of the illumination sources. With the laminated glass window panel disposed at the vehicle and when the illumination sources are not activated, the sensing device is not readily visible to the person viewing the laminated glass window panel from exterior of the vehicle.
US11080956B1	Disarming surveillance systems for authorized persons Deactivating one or more components of a surveillance system in response to authenticating an authorized person is disclosed and described. A method includes authenticating a user as an authorized person with permission to enter a property and, in response to authenticating the user, causing a compartment of a lockbox to open. The method includes providing a notification to a surveillance system indicating the user has been authenticated and accessed the compartment of the lockbox.
US11080955B2	Device, system and method for controlling a passage barrier mechanism A device, system and method for controlling a passage barrier mechanism is provided. While failing to detect, via a biometric imaging system in communication with a passage barrier mechanism, unauthorized users in a first area of interest of the biometric imaging system, a device: maintains the passage barrier mechanism in a multiple entry state in which multiple users at a time authenticate, via the biometric imaging system, and enter therethrough. Responsive to detecting, via the biometric imaging system, an unauthorized user in the first area of interest, the device: transitions the passage barrier mechanism from the multiple entry state to a single entry state in which only a single user at a time authenticates, via the biometric imaging system, and enters therethrough; and changes a biometric authentication range of the biometric imaging system from the first area of interest to a smaller second area of interest.
US11080952B2	System and method for providing hands free operation of at least one vehicle door A system and method for providing hands free operation of at least one vehicle door that include determining if a portable device is located within at least one local area polling zone of a vehicle. The system and method also include determining if the portable device is stationary for a predetermined period of time within the at least one local area polling zone of the vehicle and determining if the portable device is located outside of at least one door area zone of the vehicle, wherein the at least one door area zone of the vehicle includes a space that is occupied by the at least one vehicle door. The system and method supplying an amount of power to a motor associated with the at least one vehicle door to open or close the at least one vehicle door.
US11080951B2	Contactless electronic access control system An embodiment of an electronic access control system includes an electronic access apparatus, an electronic lock, and an access control administration program. The electronic access apparatus provides a wireless power signal and a wireless digital data signal to the electronic lock. The wireless power signal can be the only source of power used by the electronic lock to actuate an electronic lock mechanism. In some embodiments, the lock mechanism includes a piezoelectric latch.
US11080942B2	Assistance method for assisting performance of a task on a product, comprising displaying a highlighting image highlighting a monitored part of the product This assistance method is intended for assisting an operator in performing a task on a product (12). To that end, the method comprises a step of displaying, superimposed on a view of a scene including a monitored part of the product (12) on which a subtask of the task has to be performed, at least one assistance image (100, 136) intended to assist the operator in performing this subtask. Said at least one assistance image (100, 136) includes at least one highlighting image (100, 102) highlighting the monitored part.
US11080939B1	Generating test cases for augmented reality (AR) application testing Generating test cases for augmented reality (AR) application testing is disclosed. In one embodiment, an AR computing device constructs a virtual object hierarchy comprising a plurality of nodes corresponding to a plurality of virtual objects of a test AR environment. The AR computing device next generates an event-flow graph based on the virtual object hierarchy, wherein the event-flow graph comprises a directed graph comprising a plurality of vertices, wherein each vertex corresponds to an event supported by a virtual object of the plurality of virtual objects, and a plurality of edges, wherein each edge connects two (2) vertices of the plurality of vertices. The AR computing device then identifies a plurality of paths based on the event-flow graph, wherein each path comprises one or more edges of the plurality of edges. The paths are then stored as a plurality of test cases (e.g., for use as input during subsequent testing).
US11080936B2	First-person perspective-mediated reality An apparatus comprising means for: enabling user-selection of a first sub-set of available mediated reality content based on a current point of view of a user; throughout a first period of time, causing rendering of the selected first sub-set of available mediated reality content to the user as it is selected; throughout the first period of time, storing a second sub-set of the available mediated reality content for potential future rendering, wherein the second sub-set is different to the first sub-set being rendered to the user and is not being rendered to the user during the first period of time; during at least a latter portion of the first period of time, determining whether or not to augment the user-selected first sub-set of available mediated reality content to include an alert concerning the second sub-set of available mediated reality content.
US11080934B2	Mixed reality system integrated with surgical navigation system The present invention relates to a mixed reality system integrated with a surgical navigation system including a group of moveable position markers configured on a surgical instrument; a position sensor sensing the group of moveable position markers to acquire an instrument coordinate for the surgical instrument; a registered positioning marker configured in proximity to a surgical area to acquire a surgical area coordinate for the surgical area; a plurality of mixed reality sensors detecting the registered positioning marker and a plurality of mixed reality information; a computing unit module configured to receive the instrument coordinate, the surgical area coordinate, the plurality of mixed reality information, and a digital model of the surgical area, to render the digital model corresponded to the surgical area, and to add a digital instrument object into the digital model in accordance with the instrument coordinate; and a mixed reality display providing for a user to view and showing the digital model and the digital instrument object to the user upon the receipt thereof.
US11080931B2	Virtual x-ray vision in a process control environment In a method of providing virtual enhanced vision to a user of an augmented reality (AR) mobile device, it is determined that a first node associated with a map of a process control environment corresponds to a first real-world object currently within a field of view of a camera of the AR mobile device. A relationship between the first node and one or more other nodes is determined, with the relationship indicating that one or more other objects corresponding to other nodes are at least partially obscured by the first object. At least partially in response to determining the relationship, one or more digital models or images depicting the other object(s) is/are retrieved from memory. A display of the AR mobile device is caused to present the retrieved digital models or images to the user while the first object is in the field of view of the camera.
US11080930B2	Virtual reality control system According to one aspect of the present disclosure, a virtual reality control system includes at least one controller configured to control at least one of the first display and the second display, the controller is configured to acquire first position data related to the first user and second position data related to the second user, and output an image including a first area and a second area to the first display on the basis of the first position data, if the first user has a first authority, the second user has a second authority and the first authority is a higher authority than the second authority, the first image is output to the first display when the first position data is located in the first area, and a notification image is output to the second display when the second position data is located in the first area.
US11080929B2	Computer-implemented method and a system for generating a 3D path to a landing location for an aerial vehicle A system and a method for generating a 3D path from a source to a destination for an aerial vehicle is disclosed. An example system includes a managing unit to select a group of altitude layers including source and destination and generate a 2D horizontal scenario by identifying constraints to avoid at each altitude layer. The example system includes a path computing unit to determine common constraints for the altitude layers of the 2D horizontal scenario and compute a 2D lateral path avoiding the common constraints. The managing unit generates a 2D vertical scenario based on a projection of the previously computed 2D lateral path onto the constraints at the altitude layers. The path computing unit computes a 2D vertical path avoiding constraints of the 2D vertical scenario. The managing unit composes 3D waypoints of a conflict-free 3D path according to the 2D lateral path and 2D vertical path.
US11080926B2	Using tiling depth information in hidden surface removal in a graphics processing system A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitives, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will subsequently be hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.
US11080925B2	Hierarchical depth buffer back annotation Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.
US11080924B2	Optimized computation of perspective interpolants A graphics pipeline may reduce the number of times when reciprocal, multiply or add computations are used for interpolation computations when though the GPU hardware has been programmed or set to perform a linear-perspective interpolation by determining whether a homogeneous coordinate of each vertex of the primitive is within a predetermined threshold of 1 when a linear-perspective interpolation technique has been specified in a shader program, and determining one or more attributes of the element using a linear interpolation technique based on the homogeneous coordinate of each vertex of the primitive being within a predetermined threshold of 1.
US11080921B2	Three-dimensional object data generation apparatus, three-dimensional object forming apparatus, and non-transitory computer readable medium A three-dimensional object data generation apparatus includes an obtaining unit that obtains three-dimensional object data representing a three-dimensional object with plural voxels, for each of which a physical property value is set, a setting unit that sets a three-dimensional threshold matrix in which thresholds are arranged in a three-dimensional space in accordance with a predetermined basic shape, and a calculation unit that calculates whether to form each of the plural voxels on a basis of the physical property value of the voxel and the three-dimensional threshold matrix.
US11080920B2	Method of displaying an object The technical result obtained herein is providing the ability to display an output image having the actual texture of the photo or video image, simplifying the implementation by eliminating the need to store a database of reference textures of objects, enabling texturizing of a 3D model areas invisible on the 2D object. A feature-based ORB-SLAM algorithm can be used for image processing using sparse point cloud. An advantageous solution is provided that allows to improve the efficiency of the texturizing process and therefore allows to use the ORB-SLAM algorithm on mobile devices by reducing computational intensity of the overall process. In order to achieve these advantages, a system of preliminary image processing is implemented. Said preliminary image processing allows to identify the most promising areas for detecting object features on the images coming from the camera.
US11080918B2	Method and system for predicting garment attributes using deep learning There is provided a computer implemented method for predicting garment or accessory attributes using deep learning techniques, comprising the steps of: (i) receiving and storing one or more digital image datasets including images of garments or accessories; (ii) training a deep model for garment or accessory attribute identification, using the stored one or more digital image datasets, by configuring a deep neural network model to predict (a) multiple-class discrete attributes; (b) binary discrete attributes, and (c) continuous attributes, (iii) receiving one or more digital images of a garment or an accessory, and (iv) extracting attributes of the garment or the accessory from the one or more received digital images using the trained deep model for garment or accessory attribute identification. A related system is also provided.
US11080912B2	System and method for digital markups of custom products Techniques for generating and using digital markups on digital images are presented. In an embodiment, a method comprises receiving, at an electronic device, a digital layout image that represents a form of a product for manufacturing a reference product; generating a digital markup layout by overlaying the digital markup image over the digital layout image; based on the digital markup layout, generating one or more manufacturing files comprising digital data for manufacturing the reference product; receiving a digital reference image of the reference product manufactured based on the one or more manufacturing files; identifying one or more found markup regions in the digital reference image; based on the found markup regions, generating a geometry map and an interactive asset image; based on, at least in part, the geometry map, generating a customized product image by applying a user pattern to the interactive asset image.
US11080909B2	Image layer processing method and computing device An image processing method to reduce access pressure of each image in an image set, where the image processing method includes obtaining a quantity of times each image layer in an image set is accessed, determining one or more first image layers, where a quantity of times the first image layer in the image set is accessed is greater than a first threshold, and the first image layer has at least two child image layers, generating a copy of the first image layer, and modifying some child image layers of the first image layer to child image layers of the copy of the first image layer.
US11080908B2	Synchronized display of street view map and video stream Approaches presented herein enable displaying of a street view or map in the context of a video stream object. Specifically, captured video is analyzed for a plurality of geo-coordinate and direction metadata associated with frames of the video. The video may also be analyzed for visual indicia of location or direction. A user watching the video selects an object therein, which may be then identified by its coordinates and labeled for the user. A map or street view corresponding to the selected object is shown synchronized to the video (e.g., in a side-by-side view), based on the geo-coordinate and direction metadata associated with the video frames. The synchronized video and map speed may be manipulated. The video may also be broken up by frames, and the user permitted to navigate beyond the bounds of the video, where frames are played when the user navigates to areas within the video.
US11080905B1	System and method of image analysis of user-illustrated process flow to automate generation of executable code instructions An information handling system operating an image analysis integration flow creation system may comprise a network interface device receiving a captured image of an illustrated integration process flow chart connecting process step illustrations in a user-specified pattern, and a processor determining a process flow plot connecting visual element placeholders corresponding to the process step illustrations according to the user-specified pattern. The processor may identify an image shape within each process step illustration and image shape-identifying parameters for that image shape, apply a neural network to determine a type of integration process visual element represented by each process step illustration, based on the image shape-identifying parameters, and generate an integration process flow model displayed in a GUI by inserting the type of integration process visual element represented by each process step illustration into the visual element placeholder corresponding to that process step illustration.
US11080904B2	Computerized systems and methods for graph data modeling Systems, methods, and computer-readable media are provided for graph data modeling. In accordance with one implementation, a method is provided that includes operations performed by at least one processor. The operations of the method include receiving raw data and determining a model for the raw data, wherein the model defines the graph structure for the raw data. The method also includes converting the raw data to fit the model, and generating at least a portion of a graph based on the raw data and the model, wherein the graph produces modeled data. The method also includes archiving the graph.
US11080897B2	Systems and methods for a PET image reconstruction device Methods, devices and apparatus for reconstructing a PET image are provided. According to an example of the method, a PET initial image may be reconstructed from PET data obtained by scanning on a target object with a PET device, and an MRI image may be reconstructed from MRI data obtained by scanning on the target object with a MRI device, a fusion image retaining only a boundary of the target object is generated based on the PET initial image and the MRI image, and a PET reconstructed image is obtained by combining the PET initial image with the fusion image, where the definition of the boundary of the target object in the PET reconstructed image is higher than that in the PET initial image.
US11080896B2	Systems and methods for computed tomography image reconstruction The present disclosure provides a method for computed tomography (CT) image reconstruction. The method may include obtaining a plurality of projection images of a subject. The plurality of projection images may be generated according to scan data acquired by a CT scanner at a plurality of gantry angles, each of the plurality of projection images corresponding to one of the plurality of gantry angles. The method may also include determining attenuation information of the plurality of projection images. The method may further include reconstructing a CT image of the subject by simultaneously solving correction coefficients of the plurality of projection images such that a difference between estimated attenuation information of the plurality of projection images and the attenuation information of the plurality of projection images is minimized.
US11080894B2	Skin color detection method, skin color detection apparatus, and storage medium A skin color detection method comprises: determining chrominance signal values in a luminance chrominance YUV domain of a pixel value corresponding to each pixel point in a target image under skin color detection; searching for a skin color probability corresponding to the chrominance signal values in a stored skin color index matrix based on the chrominance signal values in the YUV domain of the pixel value corresponding to the pixel point, wherein the skin color index matrix is generated through processing skin color images under various illumination conditions, and the skin color probability is a probability that the pixel point is a skin color point; and performing skin color detection based on the skin color probability corresponding to the chrominance signal values of each pixel point in the target image. A skin color detection apparatus and a storage medium are further provided.
US11080891B2	Method and system for detecting dangerous situation A method of detecting a dangerous situation includes obtaining a first image including a first object capable of generating a movement, by using a dynamic vision sensor (DVS); detecting, from the first image, a second image including the first object in a predefined pose; and determining whether a situation of the first object is the dangerous situation by analyzing the second image.
US11080889B2	Methods and systems for providing guidance for adjusting an object based on similarity Methods and systems for providing guidance for adjusting a target. For example, a computer-implemented method for providing guidance for adjusting a target includes: receiving, by a neural network, a reference image; receiving, by the neural network, the target image, the target image being related to a position of a target; determining a similarity metric based at least in part on information associated with the reference image and information associated with the target image by the neural network; generating a target attention map corresponding to the target image based at least in part on the similarity metric; outputting the target image and the target attention map; and providing a guidance for adjusting the position of the target based at least in part on the target image and the target attention map.
US11080887B2	Method and device for recognising distance in real time A device for recognizing distance in real time includes first, second, and cameras. The third camera arranged nearer the first camera than the second camera. The first, second and third cameras acquire simultaneously first, second and third images, respectively, and an electronic circuit of the device estimates the distance of an object as a function of a stereoscopic correspondence established between first and second elements representative of the object. The first and second elements belong to the first and second images, respectively. The stereoscopic correspondence is established by a relationship between the first elements and corresponding third elements belonging to the third image.
US11080884B2	Point tracking using a trained network A trained network for point tracking includes an input layer configured to receive an encoding of an image. The image is of a locale or object on which the network has been trained. The network also includes a set of internal weights which encode information associated with the locale or object, and a tracked point therein or thereon. The network also includes an output layer configured to provide an output based on the image as received at the input layer and the set of internal weights. The output layer includes a point tracking node that tracks the tracked point in the image. The point tracking node can track the point by generating coordinates for the tracked point in an input image of the locale or object. Methods of specifying and training the network using a three-dimensional model of the locale or object are also disclosed.
US11080874B1	Apparatuses, systems, and methods for high-sensitivity active illumination imaging A disclosed imaging device may include an image sensor, a lens system, and an aperture filter. The aperture filter may include a first concentric region that passes light of a first wavelength range and that blocks light of a second wavelength range and a second concentric region that passes light of the first wavelength range and light of the second wavelength range. The lens system may direct received light through the aperture filter toward the image sensor. The lens system and the aperture filter may provide a first depth-of-field associated with the first wavelength range and a second depth-of-field associated with the second wavelength range. Associated systems and methods are also disclosed.
US11080856B1	Methods for digital imaging of living tissue Methods of providing digital images of living tissue that may include: obtaining data of a propagating wavefield through living tissue; obtaining a reference digital image of the living tissue; selecting a holographic computational method of wavefield imaging; selecting a wavefield based on one or more parameters; calculating a sampling ratio by dividing a number of data samples in the data subset by a number of image samples in the data subset; decimating the data subset; generating a new digital image based on the selected holographic computational method of imaging, the decimated data subset, and parameters corresponding to the data subset; and determining a quantitative difference measure between the reference digital image and the new digital image based on the changing of one or more parameters selected from the group consisting of field sampling, imaging sampling, and image quality.
US11080854B2	Augmented surgical reality environment The present disclosure is directed to an augmented reality surgical system for viewing an augmented image of a region of interest during a surgical procedure. The system includes an image capture device that captures an image of the region of interest. A controller receives the image and applies at least one image processing filter to the image. The image processing filter includes a spatial decomposition filter that decomposes the image into spatial frequency bands. A temporal filter is applied to the spatial frequency bands to generate temporally filtered bands. An adder adds each band spatial frequency band to a corresponding temporally filtered band to generate augmented bands. A reconstruction filter generates an augmented image by collapsing the augmented bands. A display displays the augmented image to a user.
US11080853B2	Calculating an image matrix size An embodiment of the invention relates to a method for calculating an image matrix size N for reconstructing image data of an examination subject from projection data. The method includes acquiring projection data obtained during a relative rotational movement between a radiation source of a computed tomography system and the examination subject; calculating the image matrix size N as a function of an extent of an axial field of view of the computed tomography system and a sharpness value in the image data to be reconstructed; and making the calculated image matrix size available to a reconstruction unit to reconstruct the image data from the projection data acquired.
US11080852B2	Method and system of analyzing medical images The present invention seeks to provide a method of analyzing medical image, the method comprises receiving a medical image; applying a model stored in a memory; analyzing the medical image based on the model; determining the medical image including a presence of fracture; and, transmitting an indication indicative of the determination.
US11080851B2	Method, apparatus, and computer-readable medium for assessing quality of images produced by scanning system for eye examination A method, apparatus, and computer-readable medium, for assessing image quality of an image produced by a scanning imaging system. The method comprises acquiring (S10) image data of an image produced by the scanning imaging system and calculating (S20 to S40), for each section of the image: a respective first value measuring at least one of sharpness or contrast of at least a part of the section, the measuring depending on noise, a respective second value measuring noise in at least a part of the section, and a respective third value indicating image quality, by combining the first and second values. The combining is such that calculated third values have a weaker dependency on the noise than the first values. The method further comprises determining (S50) a quality score that is indicative of image quality of the image based on a variation of the calculated third values among the sections.
US11080850B2	Glaucoma diagnosis method using fundus image and apparatus for the same Disclosed herein are a glaucoma diagnosis method using a fundus image and an apparatus for the same. The glaucoma diagnosis method includes performing data amplification of generating multiple transformed images for an original fundus image based on a preprocessed image of the original fundus image, allowing multiple individual learning models of different types to be learned based on the multiple transformed images and generating a glaucoma determination model based on respective outputs of the learned multiple individual learning models, and diagnosing a class of glaucoma for the original fundus image based on the glaucoma determination model.
US11080849B2	Systems and methods for deep learning based automated spine registration and label propagation Methods and systems are provided for whole-body spine labeling. In one embodiment, a method comprises acquiring a non-functional image volume of a spine, acquiring a functional image volume of the spine, automatically labeling the non-functional image volume with spine labels, automatically correcting the geometric misalignments and registering the functional image volume, and propagating the spine labels to the functional image volume. In this way, the anatomical details of non-functional imaging volumes may be leveraged to improve clinical diagnoses based on functional imaging, such as diffusion weighted imaging (DWI).
US11080848B2	Image-based disease diagnostics using a mobile device A diagnostic system performs disease diagnostic tests using at least an optical property modifying device and a mobile device. A user provides a biological sample from a patient to the optical property modifying device that reacts with a reagent in one or more reaction chambers of the device. The user captures one or more images of the one or more reaction chambers using an optical sensor of the mobile device. The diagnostic system can determine a quality level of the images based on factors such as skew, scale, focusing, shadowing, or white-balancing. Based on an analysis of the captured image, the diagnostic system can determine a test result of a disease diagnostic test for the patient. The diagnostic system may communicate the test result, as well as instructions for the disease diagnostic test, to the user via the mobile device.
US11080846B2	Hybrid cloud-based measurement automation in medical imagery Measurement of medical images as a hybrid cloud service is provided. In various embodiments, pre-trained parameters are received at a client from a remote server. A local cognitive system is instantiated using the pre-trained parameters. The cognitive system is applied to evaluate a medical image. A result is sent to the remote server for training of a remote cognitive system.
US11080841B1	Systems and methods for machine-assisted vehicle inspection One or more processing elements may be trained to identify vehicle damages or vehicle damages based upon training data. A remotely-controlled (RC) and/or autonomously operated inspection device, such as a ground vehicle or drone, may capture one or more sets of imaging data indicative of at least a portion of an automotive vehicle, such as all or a portion of the undercarriage. The one or more sets of imaging data may be analyzed using the trained processing elements to identify a damage to the vehicle or defect of the vehicle.
US11080839B2	System and method for training a damage identification model A system is provided for identifying damages of a vehicle. During operation, the system can obtain a set of digital images associated with a set of tagged digital images as training data. Each tagged digital image in the set of tagged digital images may include at least one damage object. The system can train a damage identification model based on the training data. When training the damage identification model, the system may identify at least a damage object in the training data based on a target detection technique. The system may also generate a set of feature vectors for the training data. The system can use the set of feature vectors to optimize a set of parameters associated with the damage identification model to obtain a trained damage identification model. The system can then apply the trained damage identification model to obtain a damage category prediction result.
US11080838B1	Systems and methods for image labeling using artificial intelligence An image analysis (“IA”) computer system for analyzing images of hail damage includes at least one processor in communication with at least one memory device. The at least one processor is programmed to: (i) store a damage prediction model associated with a rooftop, wherein the damage prediction model utilizes an artificial intelligence algorithm; (ii) display, to a user, an image of a rooftop; (iii) receive, from the user, a request to analyze damage to the rooftop; (iv) apply, by the at least one processor, the damage prediction model to the image, the damage prediction model outputting a plurality of damage prediction locations of the rooftop in relation to the image; and/or (v) display, by the at least one processor, an overlay box at each of the plurality of damage prediction locations, the overlay box being a virtual object overlaid onto the image for labeling the damage prediction locations.
US11080837B2	Architecture for improved machine learning operation Discussed herein are architectures and techniques for improving execution or training of machine learning techniques. A method can include receiving a request for image data, the request indicating an analysis task to be performed using the requested image data, determining a minimum image quality score for performing the analysis task, issuing a request for image data associated with an image quality at last equal to, or greater than, the determined minimum image quality score, receiving, in response to the request, image data with an image quality score greater than, or equal to, the determined minimum image quality score, and providing the received image data to (a) a machine learning (ML) model executor to perform the image analysis task or (b) an ML model trainer that trains the ML model to perform the image analysis task.
US11080835B2	Pixel error detection system A process receives, with a processor, video content. Further, the process splices, with the processor, the video content into a plurality of video frames. In addition, the process splices, with the processor, at least one of the plurality of video frames into a plurality of image patches. Moreover, the process performs, with a neural network, an image reconstruction of at least one of the plurality of image patches to generate a reconstructed image patch. The process also compares, with the processor, the reconstructed image patch with the at least one of the plurality of image patches. Finally, the process determines, with the processor, a pixel error within the at least one of the plurality of image patches based on a discrepancy between the reconstructed image patch and the at least one of the plurality of image patches.
US11080834B2	Image processing method and electronic device An image processing method and an electronic device are provided, the method extracts a first object mask of a texture image and a second object mask of a to-be-optimized image. An image recognition model is used to obtain a first content matrix, a first texture matrix, a second content matrix, a second texture matrix, a first mask matrix, and a second mask matrix. A total loss of the to-be-optimized image is determined, and the total loss is minimized by adjusting a value of each pixel of the to-be-optimized image, thereby an optimized image is obtained. By utilizing the image processing method, quality of final image is improved.

1 2 3 4 5 6 7 8 9 10