| Document | Document Title |
|---|---|
| US10869179B1 |
Systems, methods and techniques for interoperable emergency communication
An emergency communication server is provided for collaboration of an emergency response. The server comprises a processing system including a processor. The processing system is configured to receive an input from an electronic device, the electronic device being operated by a member from an originating communication group, upon receipt of the input from the electronic device, generate a notification based on the received input and send the generated notification to at least one member in the originating communication group, determine one or more receiving communication groups for the received input, send the notification to at least one member in each of the determined one or more receiving communication groups, and enable the at least one member in each of the determined one or more receiving communication groups to communicate with one or more members of the originating communication group. |
| US10869178B1 |
Emergency location service
An emergency location server may receive push location messages from a handset as the handset initiates a call to a public safety answering point (PSAP). The PSAP may request the location information from the location server by identifying the MSISDN of the handset. If the push message does not contain an MSISDN, the location server may send a message, e.g. SRI-SM message, to the home network of the handset to retrieve the MSISDN and associate the MSISDN with the location information in the push location message. This enables the location server to provide location responses to the PSAP even when the handset is unaware of its MSISDN. |
| US10869177B2 |
Methods and systems for establishing and maintaining presence information of neighboring bluetooth devices
A communication device and method can include one or more processors operatively coupled to memory, a sensor and an output device, where the one or more processors to perform operations of discovering neighboring short range communication enabled devices such as Bluetooth LE devices, creating presence lists from the discovered devices, and transferring biometric and personal data at least to or from the communication device or at least to or from one of the discovered devices. Other embodiments are disclosed. |
| US10869176B1 |
Near field communication (NFC) enhanced computing systems
Technologies are disclosed herein for utilizing near field communication (“NFC”) to improve the security, performance, and configuration of computing systems. In particular, NFC can be utilized to power an NFC-equipped server computer on or off, to log directly into an operating system executing on the NFC-equipped server computer, to stream firmware debugging data from an NFC-equipped server computer to an NFC-equipped mobile device, to initiate the update or recovery of firmware, to provide hardware inventory data, or to pair hardware devices. Firmware debugging data can also be streamed from a firmware to an NFC-equipped mobile device. NFC can also be utilized to disable functionality provided by a mobile device while the device is in motion, such as when a user of the mobile device is operating a motor vehicle. |
| US10869164B2 |
Athlete attend class monitoring system
A system and method for monitoring and verifying athlete attendance in a classroom is disclosed. An exemplary embodiment defines a GPS-based fence in association with a classroom as well as defines a class start time and a class end time. GPS coordinates associated with a portable computing device (“PCD”) associated with a given athlete are received and determined to be within a range of coordinates associated with the fence. Also, a time associated with the receiving of the GPS coordinates is determined to be within a window of time comprising the class start time. Subsequently, a picture of a user is captured with a camera of the PCD. Next, from the picture the user is verified to be the given athlete. Finally, the given athlete is marked as “present” within the class. |
| US10869163B2 |
Techniques for providing location-based health alerts based on biological indicators
Certain aspects of the present disclosure generally relate to providing location-based health alerts based on biological indicators. In some aspects, a server may receive information that identifies a location associated with a mobile device. The server may determine a venue associated with the location. The server may identify health information associated with the venue. The health information may be based on data previously received in association with the venue. The server may provide a health alert based on the health information. |
| US10869159B1 |
Apparatus for battlefield management, target location and target tagging
Embodiments of an apparatus configured for attachment to a firearm are described herein. In some embodiments, processing circuitry may be configured to process outputs of one or more accelerometers to identify a firearm discharge event, capture firearm orientation data provided by an attitude sensor and a geolocation of the firearm at a time of the firearm discharge event, and encode a firearm discharge message comprising the firearm orientation data, the geolocation, and the time, for transmission via a communication interface. In some embodiments, the apparatus may be configured for target tagging. Some embodiments are directed to a battlefield information node configured to decode a plurality of firearm discharge messages received, via a communication interface, from one or more other battlefield information nodes. Each firearm discharge message may comprise firearm orientation data, a geolocation, and a time associated with a firearm discharge event. The data from the plurality of firearm discharge messages may be aggregated using a sliding time-window to identify target locations in a hostile zone. |
| US10869155B2 |
Gain control in spatial audio systems
Apparatus including a processor configured to: provide a position for at least one sound source relative to a reference position; analyse at least one input audio signal associated with the at least one sound source to determine at least one gain value based on the at least one input audio signal and the position for the at least one sound source relative to the reference position; and synthesize at least two output channels based on the at least one input audio signal, a directional transfer function pair, the at least one gain value and the position for the at least one sound source relative to the reference position. |
| US10869147B2 |
Sound device and assembling method therefor
The present disclosure provides a sound device, comprising a housing and a sound unit received in the housing, wherein, the housing comprises an upper cover plate with a receiving space, the upper cover plate is made of 3D glass, and the upper cover plate and the sound unit are fixed to each other by laser welding. The sound device provided by the present disclosure replacing the housing with a 3D glass housing, and thus enhances the strength of the housing, and the sealing and fixing is implemented by laser welding due to the transparent property of the 3D glass, which effectively prevents overflowing caused by gluing and ultrasonic welding, meanwhile the maximum cavity is ensured and the usage of the antenna will not be affected. |
| US10869145B2 |
Electronic device charging via an audio jack
An electronic device may comprise audio processing circuitry and a universal serial bus (USB) connector having a first contact and a second contact. In a first mode of operation, the audio processing circuitry is configured to output one or more audio signals carrying music and/or voice via the first contact and the second contact. In a second mode of operation, the audio processing circuitry is configured to output a signal for delivering supply current via the first contact and the second contact. While the electronic device is in the first mode of operation, a gain and/or volume limit of the audio processing circuitry may be set to a first level, and while the electronic device is in the second mode of operation, the gain and/or volume limit of the audio processing circuitry may be set to a second level that is higher than the first level. |
| US10869142B2 |
Hearing aid with spatial signal enhancement
A new binaural hearing aid system is provided with a hearing aid in which signals that are received from external devices, such as a spouse microphone, a media player, a hearing loop system, a teleconference system, a radio, a TV, a telephone, a device with an alarm, etc., are filtered with binaural filters in such a way that a user perceives the signals to be emitted by respective sound sources positioned in different spatial positions in the sound environment of the user, whereby improved spatial separation of the different sound sources is facilitated. |
| US10869141B2 |
Audio device with valve state management
Methods and apparatus determine the actual state of one or more acoustic valves e.g., whether an acoustic valve is open or closed, in a hearing device. A sensor in the hearing device is configured to generate an output signal indicative of a state of the acoustic valve. An electrical circuit actuates the acoustic valve if the actual state is different than a desired state. The determination of the state of the acoustic valve can be done on the hearing device or on a remote device. |
| US10869139B2 |
Hearing aid device having a microphone and neckband to detect the direction of source of sound
A hearing aid device is provided. The hearing aid device at least includes a neckband and a first microphone. The neckband is worn on a neck of a user. The neckband defines a virtual datum plane and a first virtual plane parallel to each other, wherein the virtual datum plane overlaps a coronal plane of the user when the neckband is worn by the user, and a skin portion, furthest from the virtual datum plane, of a throat of the user is located on the first virtual plane. The first virtual plane is distant from the virtual datum plane by the first distance. The first microphone is disposed on the neckband, and is distant from the virtual datum plane by the second distance, wherein the second distance is less than the first distance. |
| US10869137B2 |
Acoustic speaker having a one-piece plastic shell
An acoustic speaker (1) including: a metal armature (7), a plastic shell (9) fastened on the armature, the shell defining at least two openings (11A, 11B), and at these two loudspeakers (13A, 13B) arranged head to tail along a transverse axis (T), the two loudspeakers respectively extending through the two openings. The shell is in one piece, and the shell and an outer part (19) of the armature are suitable for nesting in one another along a longitudinal axis (L), the outer part and the shell at least partially defining an inner volume (23) of the acoustic speaker. |
| US10869134B2 |
Speaker includes two symmetrical voice coils disposed in parallel and integrally wound molded
The present disclosure provides a speaker, comprising a basin frame with a receiving space, a vibration system disposed at the basin frame, and a magnetic circuit system configured for driving the vibration system to generate sounds by vibration, the vibration system comprises a diaphragm with an outer edge fixedly held by the basin frame and a voice coil configured for driving the diaphragm to vibrate, the voice coil includes a first voice and a second voice coil fixedly connected to the first voice coil, the first and second voice coils are disposed in parallel and symmetrically, the first and second voice coils are integrally wound molded and the winding direction of the first voice coil is opposite to that of the second voice coil. The speaker provided by the present disclosure could improve utilization of magnetic field, provide better vibration effect and reduce resonance frequency. |
| US10869132B2 |
Speaker
The present disclosure provides a speaker, including a vibration unit, a magnetic circuit unit for driving the vibration unit to vibrate and emit sound, and a holder for fixing the magnetic circuit unit. The magnetic circuit unit includes a magnetic frame fixed in the holder and a magnet received in the magnetic frame. the magnetic frame includes a bottom wall connected to the magnet, a sidewall extending from the bottom wall while being bent towards the vibration unit, a positioning boss that is formed by die molding from the sidewall, protrudes out of the sidewall and is close to the holder, and a recess formed by recessing from a surface of the sidewall facing the magnet in a direction facing away from the magnet. The recess corresponds to the positioning boss. A size of the recess gradually decreases along a direction facing away from the magnet. |
| US10869131B2 |
Magnet assembly for a loudspeaker and loudspeaker with such a magnet assembly
An example magnet assembly for a loudspeaker includes a first permanent magnet with a cuboid shape, the first magnet encompassing a central opening, and a second permanent magnet with a cuboid shape, the second magnet positioned coaxially within the opening of the first magnet and forming a rectangular-ring shaped first gap therebetween, the first and second magnets being axially poled in opposed directions. The assembly further includes a soft-magnetic base plate connected across one side of the first and second magnets, a soft-magnetic first pole piece having a first face and positioned on the first magnet, and a soft-magnetic second pole piece having a second face and positioned on the second magnet. The first pole piece and the second pole piece form a rectangular-ring shaped second gap between the first and second faces such that magnetic flux is focused in the second gap. |
| US10869130B2 |
Diaphragm and loudspeaker
Disclosed are a diaphragm and a loudspeaker using the diaphragm. The diaphragm comprises an edge, a fixing section formed by the edge's outer edge extending outward, and an intermediate section formed by the edge's inner edge extending inward, wherein the edge is disposed with a plurality of stiffeners extending from the edge and across the edge's inner edge to the intermediate section. The loudspeaker includes the diaphragm. The stiffeners disposed on the edge extend to the intermediate section, which increases strength of the inner of the edge, especially of the curved sections. In this way, strength of the edge and stability and pure tone matters of the diaphragm during practical applications may be improved. |
| US10869127B2 |
Amplifier interface and amplification methods for ultrasound devices
Amplifier architecture that allows low-cost class-D audio amplifiers to be compatible with ultrasonic signals, as well as loads presented by thin-film ultrasonic transducers. The amplifier architecture replaces the traditional capacitor used as an output filter in the class-D amplifier with the natural capacitance of the ultrasonic transducer load, and employs relative impedance magnitudes to create an under-damped low-pass filter that boosts voltage in the ultrasonic frequency band of interest. The amplifier architecture includes a secondary feedback loop to ensure that correct output voltage levels are provided. |
| US10869124B2 |
Information processing apparatus, control method, and recording medium
Provided is an information processing apparatus that is used by being adhered to the body of a user. The information processing apparatus includes a sound pickup sensor that has a sound pickup function, a communicating part that wirelessly transmits audio data picked up by the sound pickup sensor to the outside, a control part that controls the sound pickup sensor and the communicating part, a power source part that supplies a power source to at least one of the sound pickup sensor, the communicating part, or the control part, a housing part that accommodates therein at least one of the sound pickup sensor, the communicating part, the control part, or the power source part, and an adhering part that fixes the housing part to the user. The sound pickup part picks up a sound of the user using, for example, flesh conduction or bone conduction. |
| US10869114B2 |
Mobile music store assembly
A mobile music store assembly includes a housing base; a first housing member that is selectively movable relative to the housing base between a first position wherein the mobile music store assembly is in a closed configuration, and a second position wherein the mobile music store assembly is in an open configuration; and a second housing member that is selectively movable relative to the first housing member and the housing base between a first position wherein the mobile music store assembly is in the closed configuration, and a second position wherein the mobile music store assembly is in the open configuration. The mobile music store assembly can further include a music player that is positioned substantially within the housing assembly. The music player is only accessible when the mobile music store assembly is in the open configuration. |
| US10869111B2 |
Wireless communication protocol with peripheral devices
In some embodiments, a transceiver is configured to wirelessly transfer data between a host computing device and a plurality of peripheral devices over a communication path using a communication data construct sent by the transceiver comprising a plurality of packet structures forming a communication protocol for communicating peripheral device data (HID or audio data) between the host device and the plurality of peripheral devices. Each of the packet structures of the plurality of packet structures can include a single destination address configured to identify which of the plurality of peripheral devices will receive peripheral device data from the host computing device in the present packet structure and which of the plurality of computer peripheral devices will not receive peripheral device data from the host computing device in a present packet structure; and a data field configured to contain peripheral operational data for each of the plurality of peripheral devices. |
| US10869101B2 |
Display apparatus and control method thereof
A display apparatus includes: a display unit; a signal processor which is configured to process an image signal to be displayed as an image on the display unit; a communicator which is configured to communicate with an external network; and a controller which is configured to perform an initial setup service provide a user with a plurality of setup stages for adjusting a plurality of functions of the display apparatus, deduce an installation region of the display apparatus based on network information when the network information for the communicator to communicate with the external network is setup in execution of the initial setup service, and automatically perform at least part of the setup stages based on information on the deduced installation region. |
| US10869099B2 |
Transmission device, transmission method, reception device, and reception method
A technique capable of allowing a reception side to easily select components is provided. A transport stream in which a first transport packet including predetermined components and a second transport packet including signaling information related to the predetermined components are time-division multiplexed is transmitted via a predetermined transport path. Component selection information is inserted in the second transport packet. The component selection information includes information on a selective layer in which static selection is performed, information on a composite layer in which composition is performed, and information on an adaptive layer in which dynamic switching is performed, and these layers being arranged in that order from top to bottom. The acquisition destination information of a component which is a target of adaptive switching among the components selectable in the adaptive layer is information that designates specific information location of a metafile having data stream acquisition information for adaptive streaming. |
| US10869097B2 |
Television board card, television system and television system configuration method
A television board card, a television system and a television system configuration method are disclosed. The television board card includes a storage unit configured to store a configuration file, the configuration file comprising a country code form in which a plurality of country codes are preconfigured and system configuration information corresponding to each of the plurality of country codes. The television board card further includes a receiving unit configured to receive a configuration command, and a processing unit configured to analyze the configuration file and select the corresponding system configuration information for configuration according to the configuration command. |
| US10869095B2 |
Method and system for presenting additional content at a media system
A media system, receives a received sequence of media content, for presentation at the media system and generates a comparison fingerprint of the received sequence of media content. The comparison fingerprint is for comparison with a plurality of reference fingerprints so as to identify the received sequence of media content. The media system sends a request for identification of additional content to a server system. The request is based at least in part on the comparison fingerprint. The media system receives a response to the request, including information enabling additional content to be selected for display at the media system based at least in part on the identification of the received sequence of media content, and presents a displayed sequence of media content that includes at least a portion of the received sequence of media content and at least a portion of the additional content. |
| US10869089B1 |
Systems and methods for preventing display of blocked content
The disclosed computer-implemented method for preventing display of blocked content may include (i) displaying, by the computing device, content to a user, (ii) receiving, from a user, an indication to block the content, (iii) adding the content to a block list, (iv) receiving, at a later time, the content to display to the user, (v) determining the content is on the block list, and (vi) in response to determining the content is on the block list, performing a security action to prevent display of the content. Various other methods, systems, and computer-readable media are also disclosed. |
| US10869088B2 |
Video quality assessment method and device
A video quality assessment method includes obtaining a video quality assessment parameter of a to-be-assessed video, where the video quality assessment parameter of the to-be-assessed video includes an average packet loss gap of the to-be-assessed video, determining packet loss dispersion of the to-be-assessed video based on the video quality assessment parameter of the to-be-assessed video, and determining quality of the to-be-assessed video based on a packet loss rate of the to-be-assessed video, an average consecutive packet loss length of the to-be-assessed video, the packet loss dispersion of the to-be-assessed video, and attribute information of the to-be-assessed video. Therefore, during video quality assessment, impact of packet loss distribution indicated by the packet loss dispersion on the video quality is considered. |
| US10869086B2 |
Dynamic video overlays
A client device accesses a video input stream from an intermediate device for display. The client device analyzes the video input stream to determine that the video input stream matches a template indicating a change of speed. In some example embodiments, the analysis is performed while the client device is generating a video output stream that replaces video content received from a content source via the intermediate device. Based on the video input stream matching the template, the client device modifies the video output stream to show the change of speed. For example, commercials transmitted from a national content provider to a smart TV via a set-top box may be replaced with targeted commercials. During the replacement, fast-forwarding of the commercial may be detected by matching a template with the video input stream. While the video input stream is being fast-forwarded, the smart TV fast-forwards the targeted commercial. |
| US10869074B2 |
Systems and methods for optimizing content viewing using digital rights of multiple users
Systems and methods are disclosed herein for enabling multiple users' digital rights to be applied as needed to access media while those users are present to consume media. In particular, a media guidance application may receive a selection of a media asset and determine that the user equipment device does not allow access to the media asset. In response, the media guidance application may identify all the users consuming content from that user equipment device and retrieve digital rights for each user. The media guidance application may compare the digital rights of each user with digital rights required to access the media asset. The media guidance application may, based on the comparison, identify a set of digital rights (e.g., for another user present) that enable access to the media asset, and use those digital rights to access the media asset for consumption. |
| US10869071B2 |
Tracking and visualizing video utilization
A client process and a server process interact to allow the utilization of a video to be visualized during playback. When a video is played on a user device, the client process can detect state changes in the video player and report these state changes to the server process to allow the server process to maintain records of the video segments that were played. The server process can then use these records to calculate video utilization metrics for a particular video and report these metrics to the client process when the particular video is played on the user device. The client process in turn can generate a user interface element to represent the metrics and display the user interface element while the video is played. |
| US10869065B2 |
Method and apparatus encoding/decoding with quad and binary tree partitioning
A method for decoding a video according to the present invention may comprise: determining whether to divide a current block with quad tree partitioning, determining whether to divide the current block with binary tree partitioning when the current block is not divided with the quad tree partitioning, determining a binary tree partition type for the current block when it is determined to divide the current block with the binary tree partitioning, and dividing the current block into two partitions according to the determined binary tree partition type. |
| US10869061B2 |
Image processing apparatus and method
There is provided an image processing apparatus and method that make it possible to suppress degradation of the encoding efficiency. In the case where primary transform that is a transform process for a prediction residual that is a difference between an image and a prediction image of the image is to be skipped, also secondary transform, which is a transform process for a primary transform coefficient obtained by the primary transform of the prediction residual, is skipped. The present disclosure can be applied, for example, to an image processing apparatus, an image encoding apparatus, an image decoding apparatus and so forth. |
| US10869059B2 |
Point cloud geometry compression
A system comprises an encoder configured to compress a point cloud comprising a plurality of points each point comprising spatial information for the point. The encoder is configured to sub-sample the points and determine subdivision locations for the subsampled points. Also, the encoder is configured to determine, for respective subdivision location, if a point is to be included, not included, or relocated relative to the subdivision location. The encoder encodes spatial information for the sub-sampled points and encodes subdivision location point inclusion/relocation information to generate a compressed point cloud. A decoder recreates an original or near replica of an original point cloud based on the spatial information and the subdivision location inclusion/relocation information included in the compressed point cloud. |
| US10869055B2 |
Image encoding method, image decoding method, image encoding device, image decoding device, and image encoding/decoding device
An image encoding method includes: determining whether a current picture is a TSA picture or a trailing picture; and encoding a plurality of pictures according to whether the current picture is the TSA picture or a trailing picture. The determining includes: determining the current picture to be the TSA picture when the current picture does not belong to the highest layer and corresponds to a first field, and determining the current picture to be the trailing picture when the current picture belongs to the highest layer or corresponds to a second field. |
| US10869054B2 |
Video bitstream coding
A method of decoding JVET video includes receiving a bitstream indicating how a coding tree unit was partitioned into coding units, and parsing said bitstream to generate at least one predictor based on an intra prediction mode signaled in the bitstream. The predictor may be generated by interpolating neighboring pixels for each pixel within a coding block. The computation may be more accurate by deriving a value for a bottom right neighboring pixel. |
| US10869049B2 |
Image encoding/decoding method and device, and recording medium in which bitstream is stored
The present invention relates to an image encoding/decoding method and device. The image decoding method according to the present invention comprises the steps of: decoding a prediction mode index; determining whether the prediction mode index indicates function-based intra prediction; inducing a parameter (s) for generating a function, when the prediction mode index indicates the function-based intra prediction; generating the function on the basis of the induced parameter (s); and performing intra prediction by using the generated function. |
| US10869048B2 |
Method, device and system for transmitting and receiving pictures using a hybrid resolution encoding framework
Embodiments of this application disclose a picture transmission method performed at a computer device. After obtaining a picture, the computer device generates a video sequence by replicating the picture N times, and N being a positive integer. Next the computer device obtains a resolution setting sequence and encodes the N to-be-encoded pictures in the video sequence according to the resolution setting sequence to generate N encoded pictures, each encoded picture having an associated resolution setting. Finally, the computer device sends the N encoded pictures to a decoding computer device. The decoding computer device then decodes and displays the N encoded pictures according to their respective resolution settings from low to high. |
| US10869043B2 |
Method and apparatus for block vector signaling and derivation in intra picture block compensation
A method includes acquiring a current picture from a coded video bitstream. A determination is made as to whether a current block in the current picture is coded in an intra block copy mode. In response to a determination that the current block is coded in the intra block copy mode, a reference block in the current picture is selected based on a block vector type of the current block and the current block is decoded based on at least one characteristic of the selected reference block. |
| US10869039B2 |
Methods and systems for encoding pictures associated with video data
Several methods and systems for encoding pictures associated with video data are disclosed. In an embodiment, a method includes determining by a processing module, whether a picture is to be encoded based on at least one of a skip assessment associated with the picture and an encoding status of a pre-selected number of pictures preceding the picture in an encoding sequence. The method further includes encoding by the processing module, a plurality of rows of video data associated with the picture upon determining that the picture is to be encoded, wherein the plurality of rows are encoded based on a pre-selected maximum encoded picture size. |
| US10869037B2 |
Data encoding system, data encoding device, data encoding control device, data encoding method, data encoding control method, and program recording medium
To provide a data encoding system that can control compression parameters when compressing sensing data in a flying object without setting a compression method in advance. The data encoding control device installed in a ground station detects a position on earth sensed by the sensor, determines information about a compression parameter of sensing data acquired through sensing performed by the sensor, based on the detected position, and notifies, to the data encoding device, the information about the determined compression parameter. The data encoding device acquires the information about compression parameter notified from the data encoding control device, and compresses sensing data acquired through sensing performed by the sensor, according to the acquired information about the compression parameter. |
| US10869033B2 |
Picture coding device, picture coding method, picture coding program
In a case where a partition mode in which luma signals are partitioned horizontally and vertically is set when an intra prediction of a picture signal is made in units of minimal coding blocks set in advance, an intra prediction unit is configured to make an intra prediction of a chroma signal in units of prediction blocks of the intra prediction of chroma signals within the minimal coding block set in accordance with a chroma format. A second bitstream constructing unit constructs a bitstream of information relating to a luma intra prediction mode of a prediction block of luma signals and information relating to a chroma intra prediction mode of a prediction block of chroma signals. |
| US10869032B1 |
Enhanced encoding and decoding of video reference frames
Methods of video streaming are generally described. In some examples, the methods may be performed by a server device and may include generating first intra-coded frame (I-frame) data and a plurality of enhancement layer data corresponding to the first I-frame data. The methods may further include sending the first I-frame data to a client device. The methods may further include transmitting first enhancement layer data to the client device. The methods may include sending first inter-coded frame data to the client device. In some examples, the first inter-coded frame data can be decoded by referencing first reference frame data generated by combining the first I-frame data and the first enhancement layer data. |
| US10869030B2 |
Method of coding and decoding images, a coding and decoding device, and corresponding computer programs
A method is provided for coding at least one current image. The method includes: determining at least one parameter of a predetermining function, the function being able to transform a first subset of a set of previously decoded reference images into an approximation of a second subset of images of the set of reference images; applying the function according to the parameter determined to a third subset of the set of reference images, the third subset being different from the first subset, so as to obtain another set of previously decoded reference images; and coding the current image on the basis of the obtained set of reference images. |
| US10869024B2 |
Augmented reality displays with active alignment and corresponding methods
Binocular augmented reality display devices and corresponding methods allow alignment calibration to be performed by an end user. According to one approach, a camera is positioned to have a field of view which includes simultaneously part of a projected image from the left-eye display and part of a projected image from the right-eye display. By projecting via each display at least part of a calibration image and identifying within the camera-sampled image right-field and left-field alignment features, an alignment correction can be derived. Alternative approaches employ correlation of images sampled by forward-looking cameras rigidly associated with the respective right-eye and left-eye display units, or require a user to input a manual adjustment for aligning transversely-swapped camera images with the real world view. |
| US10869014B2 |
Vehicle display device
Disclosed is a display apparatus for vehicle including: a display unit configured to include a barrier unit and an image output unit; and a processor configured to output a parallax barrier 3D image to the display unit by implementing a parallax barrier in the barrier unit and outputting a disparity image to the image output unit, and to adjust an open slit ratio of the barrier unit based on an average luminance value of the disparity image. |
| US10869005B2 |
Electronic doorbell system with reduced latency
A system for electronic monitoring includes a doorbell configured to immediately call a user following the occurrence of a trigger event, such as a doorbell button push or detection of motion or sound. The system reduces latency by omitting push notifications to the user, which require the user to open an application program on a device, and instead proceeds to immediately call the user's device following the trigger event. The call can be a telephone call enabled by a wirelessly connected base station or hub making a Voice over Internet Protocol (VoIP) call to the user's mobile device. In one aspect, a video stream captured by a camera positioned separately from the doorbell (for providing an optimum viewing angle of a visitor) can be synchronized by the base station with an audio stream captured by a microphone of the doorbell for communicating a synchronized media stream near instantaneously to the user while the user returns an audio stream to the doorbell during a phone call. |
| US10869004B2 |
Shooting method controlling movement of unmanned aerial robot in unmanned aerial system and apparatus for supporting same
A unmanned aerial vehicle system which includes a unmanned aerial robot, a unmanned aerial robot station, and a base station to control a movement of the unmanned aerial robot is provided. The unmanned aerial robot photographs an area of a predetermined range using a camera in a state of being seated on the unmanned aerial robot station, photographs a set path while flying along the set path according to a preset condition, and transmits information on a photographed image to the base station. The base station transmits control information instructing a specific operation to the unmanned aerial robot based on the information on the photographed image, and the unmanned aerial robot station can charges a battery of the unmanned aerial robot through a charging pad when the unmanned aerial robot is seated on the unmanned aerial robot station. |
| US10869002B2 |
Vehicle camera device for capturing the surroundings of a motor vehicle and driver assistance device for detecting objects with such a vehicle camera device
The invention relates to a vehicle camera device for capturing the surroundings of a motor vehicle, having a first and a second optronic unit, wherein the first and second optronic units each comprise an optical device and an image sensor, wherein the first optronic unit is designed to capture a first detection area and the second optronic unit is designed to capture a second detection area of the surroundings, wherein the first and second optronic units have different image angles with an overlapping section of the detection areas, wherein the overlapping section which is captured by the first optronic unit has a different angular resolution from the rest of the first detection area. |
| US10868999B2 |
Eye gaze angle feedback in a remote meeting
A method of providing feedback to a presenter in a remote meeting includes capturing images of remote participants in the remote meeting using cameras associated with computing devices that display content presented by the presenter. Eye gaze angle information for at least one of the remote participants is determined based on the captured images. At least one region of interest in the displayed content is identified based on the eye gaze angle information. Feedback is provided to the presenter including an indication of the identified at least one region of interest. |
| US10868990B2 |
Active pixel sensor and driving method thereof, imager and electronic device
An active pixel sensor, a driving method thereof, an imager and an electronic device are disclosed. The active pixel sensor includes: a photosensitive element, configured to convert a received light signal into an electrical signal; a follower circuit, connected with the photosensitive element and configured to convert the electrical signal into an output voltage, the follower circuit including a source follower transistor; and an adjustment circuit, connected with the follower circuit and configured to collect the output voltage of the follower circuit and to adjust a bias current of the source follower transistor according to the output voltage, so as to adjust the output voltage to a preset range. |
| US10868982B2 |
Photoelectric conversion apparatus, photoelectric conversion system, moving object
A photoelectric conversion apparatus includes first and second photoelectric conversion elements, first and second counters, first and second reset units, an adder, and a detection unit. The first counter is configured to perform a counting operation to change a count value based on a signal input from the first photoelectric conversion element. The second counter is configured to perform a counting operation to change a count value based on a signal input from the second photoelectric conversion element. The count value of the first counter and the count value of the second counter are input to the adder. The detection unit is configured to detect an event that the count value of the first counter exceeds a threshold value. |
| US10868981B2 |
Shooting control apparatus, shooting control method, and shooting apparatus
There is provided a shooting control apparatus, a shooting control method for controlling operations of a shooting part mounted on a mobile object such as automobile, and a shooting apparatus mounted on a mobile object for use. A center region includes fine pixels, for high-resolution shooting. On the other hand, peripheral regions includes large-size pixels or are at a high sensitivity by pixel addition, thereby reducing blur or focal plane distortion by shortening the exposure time when fast driving or shooting a moving object. Further, while traveling during the nighttime or in a dark place, the peripheral regions not irradiated by the headlamps can be shot in a long exposure time and at a sufficient sensitivity. |
| US10868979B1 |
Bolometer pixel readout integrated circuit including trigger sense circuit
A thermal imaging system includes a pixel array having a plurality of pixel groups. Each pixel group including a plurality of pixel rows and a trigger sense circuit including a pixel group input line in signal communication with the plurality of bolometer pixels pixel row containing a plurality of bolometer pixels. The pixel group further includes a selector switch that selectively establishes an electrical connection between the pixel group and the trigger sense circuit. The selector switch operates in a first state to disconnect the pixel group from the pixel group input line while connecting the pixel group to the integration unit such that the integration unit generates the image, and a second state to disconnect the pixel group from the integration unit while connecting the pixel group to the pixel group input line such that the trigger sense circuit monitors the pixel group for a high temperature bolometer. |
| US10868978B2 |
Image processing device and image processing method
Provided is an image processing device including an adjustment unit that adjusts any one of a background image which is a far-infrared image showing a background that does not include an object and a target image which is a far-infrared image showing the object, on the basis of a time change model of an observation pixel value, and an extraction unit that extracts a target region including the object in the target image on the basis of a result of comparison between the background image and the target image after the adjustment is performed. |
| US10868975B2 |
Image processing system for acquiring an image picked up by a camera provided in a vehicle an image processing method executed by a computer and a non-transitory storage medium storing an image processing program executed by a computer
An image processing system includes: an image acquiring unit that acquires an image picked up by a camera, the camera being provided in a vehicle; and a quality changing unit that performs a quality changing process of decreasing a quality of the image to equal to or lower than a predetermined standard, based on at least one of a vehicle position at a time when the image is picked up, a vehicle position at a time when the image is output to an external device or a display device, and requestor information that indicates a requestor of an output request of the image. |
| US10868974B2 |
Method for determining alignment of vehicular cameras
A method for determining alignment of cameras at a vehicle includes mounting first and second cameras at a vehicle and providing an image processor at the vehicle. While the vehicle is moving along the road, first image data captured via the first camera is processed to determine movement of a road feature and second image data captured by the second camera is processed to determine movement of the road feature when the road feature is present in the second image data. The determined movement of the road feature in first image data is compared to the determined movement of the road feature in second image data, and an offset of the second camera relative to the first camera is determined, with the offset caused by a rotational or translational change in position of the first or second camera relative to the other. |
| US10868970B2 |
Image processing apparatus outputting display environment, image processing method, and storage medium
An image processing apparatus includes a processing unit, a setting acquisition unit, an environment acquisition unit, and an output unit. The processing unit is configured to perform image processing on an input image. The setting acquisition unit is configured to acquire information indicating a setting of the image processing on an image with a predetermined dynamic range. The environment acquisition unit is configured to acquire information indicating a display environment in which the image is displayed during the image processing. The output unit is configured to output at least the information indicating the setting and the information indicating the display environment in association with the image having undergone the image processing. The processing unit, the setting acquisition unit, the environment acquisition unit, and the output unit are implemented via at least one processor. |
| US10868969B1 |
Method and apparatus for accelerated tonemapping and display
According to some embodiments, a camera captures video images at a high dynamic range. These images are then tonemapped into images of a lower dynamic range with enhanced contrast. The contrast enhancement for a given pixel depends on the image's local contrast at a variety of different scales. The tonemapped images are then shown on a display. Calculation of this contrast is accelerated by the camera creating a plurality of low-pass filtered versions of the original image at progressively stronger low-pass filtering; these images may be stored at increasingly lower resolutions in a mipmap. Calculations are enhanced by use of a massively parallel processor and a texture mapping unit for hardware-accelerated sampling of blended averages of several pixels. Other embodiments are shown and discussed. |
| US10868965B1 |
Digital camera zoom control facility
A camera system with a body including an imager, a zoom lens having a variable focal length and a zoom control operable to adjust the focal length. The body may include a controller connected to the lens and configured to detect the focal length of the lens, and operable based on the focal length of the lens to establish a digital zoom factor. The digital zooming may occur in a limited portion of the zoom range, and this may be the upper end of the zoom range. |
| US10868964B2 |
Optical observation system and method for operating an optical observation system
An optical observation system (1) according to the invention comprises an optical observation apparatus, more particularly an endoscope or an exoscope (2), comprising an imaging optical unit and an electronic image recorder, wherein the imaging optical unit is embodied to image an object field (3) on the electronic image recorder with an alterable imaging scale and the electronic image recorder is embodied to produce recorded image data of the object field (3), an image display apparatus for presenting at least a section of the object field (3) and an image processing apparatus (20), which is configured to produce display image data by scaling the recorded image data with an alterable scaling factor and to actuate the image display apparatus with the display image data. According to the invention, the imaging scale is alterable over a plurality of levels and the scaling factor is continuously alterable, wherein the scaling factor is coupled to the optical imaging scale in such a way that the scaling factor is changed in the opposite sense when the optical imaging scale is altered. The invention also relates to a method for operating an optical observation system (1). |
| US10868960B2 |
Imaging apparatus
An imaging apparatus allows a user to register a setting of a predetermined function. The imaging apparatus includes a storage part configured to store setting information including a base setting which is a content of the setting registered by the user regarding the setting of the predetermined function; and a controller configured to change the setting information in accordance with an instruction by the user, and thereafter, to return a content of the changed setting information to the base setting at a predetermined timing. The controller sets a predetermined timing based on an instruction by the user. |
| US10868956B2 |
Picture-taking technique for self-photography using device having camera and device therefor
The present disclosure provides a method for supporting photograph in a device having a camera, the method comprising the operations of: recognizing the face of a subject within a photographing area of a camera when the camera is driven; determining a signal instructing to change the photographing area, on the basis of information about the recognized face; and outputting the signal instructing to change the photographing area, on the basis of the determination. |
| US10868953B2 |
Image processing device capable of notifying an effect of emphasizing a subject before performing imaging, control method thereof, and medium
An image processing device is provided that includes: an acquisition unit that acquires a plurality of viewpoint images which are captured at a plurality of different viewpoints by an imaging unit; a detection unit that detects viewpoint-relevant information between the plurality of viewpoint images; a determination unit that determines a second imaging condition in which image change between before and after predetermined image processing is greater than that in a first imaging condition in which the plurality of viewpoint images are captured on the basis of the first imaging condition and the viewpoint-relevant information; and an output unit that outputs the second imaging condition determined by the determination unit. |
| US10868950B2 |
Systems and methods for operating video medical scopes using a virtual camera control unit
A method of operating video scopes using graphics processing unit (GPU) resources of a virtual camera control unit (CCU) server connected to a network includes determining an available amount of GPU resources; providing a primary scope to connect to the network, the primary scope including a primary scope setting adjustable within a range from a minimum level that requires a minimum amount of GPU resources to a maximum level that requires a maximum amount of GPU resources; configuring the primary scope setting to a primary scope first level; determining a first desired amount of GPU resources based on the primary scope first level; and comparing the first desired amount of GPU resources with the available amount of GPU resources. |
| US10868947B2 |
Dual form factor devices having operative and complementary aligning components
Embodiments relate to mobile devices and systems having an operative component integrated into a first housing and a complementary component within an opening of a second housing moveably coupled to the first housing such that, in a particular configuration of the device or system, the operative component is aligned with the complementary component to enhance performance of the operative component. |
| US10868936B2 |
Image reading apparatus and image forming apparatus
An image reading apparatus includes an illumination unit that illuminates light on an image surface of a sheet, and a photoelectric conversion element that converts reflected light from the sheet illuminated by the illumination unit into an electric signal. The illumination unit includes a circuit board including a light emitting element, and a light guide that guides light, emitted from the light emitting element, to a sheet read surface. In the image reading apparatus, the light guide includes a positioning surface that abuts against a first surface of the circuit board and that performs positioning of the light guide and the circuit board, and a pressing portion that abuts against a second surface of the circuit board on an opposite side of the first surface and that presses the circuit board against the positioning surface. |
| US10868935B2 |
Information processing device, information processing method, non-transitory recording medium, and image forming system
An information processing device includes a memory and a processor. The memory stores a first application. The first application is executable on the information processing device that operates in a first operating environment or a second operating environment and is capable of communicating with a second application. The processor obtains communication connection information on a communication connection with a communication target device currently communicated with the information processing device, based on a determination that the information processing device operates in the first operating environment. The communication connection information has been acquired by the second application that controls the communication connection established between the information processing device and the communication target device. The processor further executes the first application to transmit, to the communication target device, a function execution request for executing a function of the communication target device, based on the communication connection information that is obtained. |
| US10868934B2 |
Information processing system, server apparatus, and non-transitory computer readable recording medium
A server apparatus is configured to receive, from the one client apparatus, a user identifier and a client identifier, determine whether or not the one client apparatus is a high-probability client apparatus, if it is determined that the one client apparatus is not the high-probability client apparatus, determine a high-probability function, determine whether or not differential operation information is present, the differential operation information being information indicating an operation different from an operation to be input in an operation device of the high-probability client apparatus when the high-probability client apparatus executes the high-probability function, out of an operation to be input in an operation device of the one client apparatus when the one client apparatus executes the high-probability function, and if it is determined that the differential operation information is present, send the differential operation information to the one client apparatus. |
| US10868932B2 |
Image reading device
An image reading device includes: a first reading unit that is provided at an intermediate position of a transport path and that reads an image of a document transported on the transport path; and a transport unit that is disposed on the transport path further upstream than the first reading unit and that transports the document to the first reading unit. The transport unit includes a third driving roller and third driven rollers that hold the document between the third driving roller and the third driven rollers. The third driving roller is provided on a frame main body, and the third driven rollers are provided on a holder member. When a cover is displaced from a closed position to an open position, the holder member is moved so as to separate the third driven rollers from the third driving roller. |
| US10868931B2 |
Bias members
In an example, a scanning system includes a scanner device, a first bias member, and a second bias member. The example first bias member is able to apply pressure on a medium towards a scan surface of the scanner device (e.g., apply pressure at a scan zone defined by the boundaries of the scanner device) and the example second bias member is able to orient the medium towards the scan surface before the medium reaches the first bias member. |
| US10868928B2 |
Switch operation erroneous-detection avoidance device and multifunctional machine, and switch operation erroneous-detection avoidance method
A switch operation erroneous-detection avoidance device includes: an execution control unit that if a prescribed device executes a prescribed process with a portable object when an operation switch transits from a pressed state to an unpressed state, prohibits execution of a process associated with the operation switch and if the prescribed device does not execute the prescribed process with the portable object when the operation switch transits from the pressed state to the unpressed state, permits the execution of the process associated with the operation switch. |
| US10868923B2 |
Communication management system, communication system, communication control method, and recording medium
A communication management system, a communication system, a communication control method, and a recording medium. The communication management system manages sharing of data between a plurality of communication terminals and transmits storage location information indicating a storage location of image data, the storage location information to be received by a first communication terminal of the plurality of communication terminals, receives a notice indicating a start of uploading of the image data to the storage location indicated by the storage location information, the notice transmitted by the first communication terminal, transmits the notice indicating the start of uploading of the image data, the notice to be received by a second communication terminal of the plurality of communication terminals, receives stroke data for reproducing a stroke image, the stroke data transmitted by the first communication terminal, and transmits the stroke data, the stroked data to be received by the second communication terminal. |
| US10868922B2 |
Image processing apparatus, method, and computer-readable medium for providing appropriate log image data
An image processing apparatus includes an scanner, a print engine, and a controller configured to control the scanner to scan images of one or more document sheets, thereby generating scanned image data, generate print data based on the scanned image data, control the print engine to print, on sheets, the images based on the print data, generate first log image data through reducing a data size of image data associated with the scanned image data, determine whether the first log image data includes a particular type of page, and when determining that the first log image data includes the particular type of page, generate second log image data having higher image quality than the first log image data. |
| US10868921B2 |
Information processing device, imaging device, and system
An information processing device 30 configured to transmit a file stored in a memory medium 120 to a terminal. The information processing device includes: a specifying information creating unit 34 configured to create specifying information for specifying files stored in the memory medium, by using a file name and information about the memory medium; a transmitting unit 35 configured to transmit the specifying information to the terminal; and a file transmitting unit 37 configured to transmit to the terminal one of the files specified by the terminal in accordance with the specifying information. |
| US10868917B2 |
Phone systems and methods of communication
Phone systems, phone devices (including hardware, software and firmware), and methods of operating a phone. Described herein are dissociated phone systems including one or a plurality of local client phones with basic call handling capability that communicate though a remote phone server but are locally controlled by a controller gateway that manages the local network including the local client phones. |
| US10868915B2 |
System and methods for routing communication requests to dedicated agents
A method is presented for linking a requestor to an agent of an entity. The method includes receiving a request to connect to an agent of an entity from a given requestor, retrieving a pool of agents from a data store, and determining a first subset of agents from the pool of agents, where agents in the first subset of agents have highest rating amongst agents in the pool of agents. The method also includes determining a second subset of agents from the pool of agents, where the agents in the second subset of agents have lowest number of assigned customers amongst the agents in the pool of agents. The method also includes identifying an intersection between the first subset and second subset, and assigning a dedicated agent to the given requestor from the intersection. The method also includes establishing a communication link between the given requestor and the dedicated agent. |
| US10868905B2 |
Text message playing method, terminal and computer-readable storage medium
Provided is a text message playing method. When a text message is received, an incoming call interface is displayed, where the incoming call interface includes a control function region which is used for controlling whether to play the text message. A first operation instruction to the control function region is received, and the text message is played in a preset playing mode, where the first operation instruction is used for instructing to play the text message. In this way, a humanized and diversified text message playing style is gained, and user experience is improved through a simple and convenient operation. Further provided are a terminal and a computer-readable storage medium. |
| US10868902B2 |
System and method for using a secondary device to access information stored remotely
A system and method allows for access to the contacts of one person on a second person's device, without affecting the content on the second person's device. The contact information, and other information that is stored on a first person's device, can be temporarily downloaded onto a second person's device for making calls or accessing the other information, thereby allowing for contact with someone. Upon logging out of the system on the second device, the information from the first person is deleted. This allows the first person to contact others when the first person's phone is not available for some reason. The system also allows for the downloading of more content and virtual access to the lost/stolen telephone to be able to locate the phone, control the phone or destroy the information on the phone. |
| US10868901B2 |
Electronic device providing contact destination and method for operating same
An electronic device according to an embodiment of the present invention comprises: a communication module; an input module; a display, and a processor, wherein the processor may select at least one contact destination of a plurality of contact destinations on the basis of a response inputted through the input module for each of a plurality of events generated through the communication module, and display the same on the display. |
| US10868899B2 |
Film for applying compressive stress to ceramic materials
A method to provide compressive stress to substrates includes depositing a film on a ceramic substrate at a deposition temperature (Td) to form an article, the film having a difference relative to the ceramic substrate at Td in a coefficient thermal expansion (CTE) of at least 1.0×10−6/K and a difference in a refractive index >0.10. At least a portion of the thickness the film is converted in at least one of composition, phase and microstructure by lowering or raising the temperature from Td to reach a changed temperature (Tc) that is at least 100° C. different from Td. The film converting conditions result in the converted film portion providing a difference in refractive index at the Tc between the converted film and the ceramic substrate of ≤|0.10|. The temperature of the article is then lowered to room temperature. |
| US10868898B2 |
Wireless charging device applying antenna module
A wireless charging device adapted for being applied in and installed to a mobile communication device. The wireless charging device is matched with the mobile communication device. The wireless charging device includes a charging module for charging the mobile communication device, and an antenna module mounted to and fastened to a rear face of the charging module. The charging module covers a rear of the mobile communication device. The antenna module opens a plurality of narrow slots. The plurality of the narrow slots are of arc shapes. |
| US10868893B2 |
Network interface device
A network interface device has in input. The input receives packets in accordance with a protocol and has at least one protocol header. The network interface has hardware which applies an artificial intelligence process to at least one of the protocol headers. This is used to provide an output which may, for example, indicate a risk associated with a packet. |
| US10868892B1 |
Replacement code implementing full-duplex communication channel protocol for message interception
Code implementing a full-duplex communication channel protocol within web browser software on a client computing device is replaced with replacement code. The replacement code intercepts incoming and outgoing messages on a channel opened at the web browser software between the client computing device and a server computing device running a web application. Responsive to the channel being opened at the web browser software, the replacement code intercepts and stores the incoming and outgoing messages. |
| US10868890B2 |
3D modeling system distributed between a client device web browser and a server
A system and method for implementing the functions of a web-based 3D modeling system partially as a script interpretable by a client browser application and partially as a component executing on a server modeling engine. A client-side script component may execute lightweight modeling system commands while the server-side modeling engine may execute computationally expensive 3D modeling system commands. For example, the script component may be accessed by the client device upon visiting a web page of the modeling service hosted by the web server. The script may include Javascript® instructions for viewing a 3D model in a browser window without installing a browser plug-in or a standalone application on the client device. However, to edit the model, the script component may forward commands and requests to the server via the network and also receive modified model data from the server. |
| US10868889B2 |
System for providing game play video by using cloud computer
Provided is a system for providing a game play video by using a cloud computer, and more particularly, to a system for providing a game play video to a user by rendering the game play video by using a cloud computer connected to a user terminal.According to the system for providing a game play video by using a cloud computer, a game play video may also be watched using a low-specification terminal, and there is no need to install a game on a terminal.According to the system for providing a game play video by using a cloud computer, a user may intervene, in real time, in a game that is being played, and watch a game play video using various methods. |
| US10868887B2 |
Systems and methods for isolating applications associated with multiple tenants within a computing platform
Systems and methods for isolating applications associated with multiple tenants within a computing platform receive a request from a client associated with a tenant for running an application on a computing platform. Hosts connected to the platform are associated with a network address and configured to run applications associated with multiple tenants. A host is identified based at least in part on the request. One or more broadcast domain(s) including the identified hosts are generated. The broadcast domains are isolated in the network at a data link layer. A unique tenant identification number corresponding to the tenant is assigned to the broadcast domains. In response to launching the application on the host: the unique tenant identification number is assigned to the launched application and is added to the network address of the host; and the network address of the host is sent to the client associated with the tenant. |
| US10868886B2 |
Communication device scheduling communication processing, communication method, and computer program product
According to an embodiment, a communication device includes an arrangement unit, a communication control unit, and a processing control unit. The arrangement unit is configure to arrange a schedule of a communication processing that transmits and receives a message with time division multiplex communication and one of more schedules of one or more pieces of application processing that are different from the communication processing. The communication control unit is configured to transmit and receive a message according to the arranged schedule. The processing control unit is configured to control execution of an application according to the arranged schedule. |
| US10868881B1 |
Loading web resources using remote resource pushing
This specification describes systems, methods, devices, and other techniques for transmitting electronic resources to a client device. In some implementations, a computing system includes a client proxy system and a push server system. The client proxy system is configured to obtain requests issued from a client device and responses to requests issued by a surrogate browser of a push server system. The client proxy system matches responses from the push server system with requests from the client device to determine responses to the requests from the client device. |
| US10868879B2 |
Systems and methods for web to mobile app correlation
The present application is directed to systems and methods for associating cookies of a linking system to a device identifier of the computing device. A server of a linking system can receive, from a browser of a computing device, a first request to access content via an encoded uniform resource locator (URL) link generated by the server and linked to a web page of the linking system. The server can redirect the browser of the computing device to the web page of the linking system. The server can receive a request to associate a cookie passed to a mobile application installed on the computing device with a device identifier of the computing device. The server can then associate the cookie with the device identifier. |
| US10868876B2 |
Authenticated service discovery using a secure ledger
In one embodiment, a service configured to execute on trusted participant devices authenticates network service devices each having identifying information and one or more offered services, and creates an entry into a secure digital ledger for each authenticated network service device and associated offered services, each entry based on the identifying information and the one or more offered services for a corresponding network service device. Upon receiving an advertisement for an advertised service from an advertising device attached to a given trusted participant device, the service then requests and may receive an authentic ledger entry from the secure digital ledger for the advertised service. In response to either validating or failing to validate authenticity of the advertised service based on the authentic ledger entry, registration at the given trusted participant device of the advertised service for the received advertisement from the advertising device may either be permitted or denied, respectively. |
| US10868874B2 |
Publish-subscribe messaging in a content network
A plurality of subscribers are registered to receive, from a publisher component, at client devices, via a broker component, at least one of messages and content pertaining to a first topic. Each of the subscribers is caused to generate one of N random numbers. A different one of the N random numbers is generated by each of the subscribers. Each of the subscribers is instructed to listen only for the messages and content pertaining to the first topic and corresponding to the corresponding one of the N random numbers. The at least one of messages and content pertaining to the first topic are published to those of the subscribers associated with each one of the N random numbers, number by number, until the at least one of messages and content pertaining to the first topic has been published to all of the plurality of subscribers. |
| US10868873B2 |
Communication session log analysis device, method and recording medium
In order to provide a communication session log analysis device allowing integration of communication session logs that makes it p to provide web session time with which quality of user experience can be evaluated with high precision, a communication session log analysis device according to the present invention that updates information relating to a web session includes: a web session integration means for integrating, when time elapsed from a start time of a reference communication session to a start time of one communication session is equal to or less than a threshold value, the one communication session into the same web session as the reference communication session, a threshold value setting means for setting the threshold value, based on a predetermined probability distribution, and a filtering means for extracting the web session determined as valid by statistical testing based on statistical information relating to a configuration of the web site. |
| US10868867B2 |
System and method for server based control
A system and method in a building or vehicle for an actuator operation in response to a sensor according to a control logic, the system comprising a router or a gateway communicating with a device associated with the sensor and a device associated with the actuator over in-building or in-vehicle networks, and an external Internet-connected control server associated with the control logic implementing a PID closed linear control loop and communicating with the router over external network for controlling the in-building or in-vehicle phenomenon. The sensor may be a microphone or a camera, and the system may include voice or image processing as part of the control logic. A redundancy is used by using multiple sensors or actuators, or by using multiple data paths over the building or vehicle internal or external communication. The networks may be wired or wireless, and may be BAN, PAN, LAN, WAN, or home networks. |
| US10868863B1 |
System and method for designating a leader using a consensus protocol within a database management system
A networked database management system (DBMS) is disclosed. In particular, the disclosed DBMS includes a plurality of nodes, one of which is elected as a designated leader. The designated leader is elected using a consensus algorithm, such as tabulated random votes, RAFT or PAXOS. The designated leader is responsible for managing open coding lines, and determining when to close an open coding line. |
| US10868855B2 |
File containerization and management
This disclosure is directed to embodiments of systems and methods for containerizing files and managing policy data applied to the resulting containers. In some of the disclosed embodiments, a computing system determines that a file stored in storage medium is to be included in a container to be sent to at least one computing component associated with a device including a user interface. The computing system determines that the file is of a particular type and also determines code that can be used to access files of the particular type. The computing system combines the file and the code into the container such that container is configured to be executed by the at least one computing component so as to cause content of the file to be presented by the user interface. The computing system then sends the container to the at least one computing component. In some implementations, the container may further include policy information defining at least one of whether, how, where, when, or by whom the file can be accessed using the code. A communication link may be established between the computing system and the container at the at least one computing component and an instruction may be sent via the communication link that causes a change to the policy information. |
| US10868854B2 |
Automatic population of a network accessible content collection
A system, computer-readable storage medium storing at least one program, and computer-implemented method for automatically posting content to a network accessible content collection are described. User activity over a communication network from a client device is tracked and a triggering event is detected. In response to detecting the triggering event, a content item is automatically posted to a network accessible collection of content items viewable by additional users. |
| US10868846B2 |
Delivering tailored audio segments within live audio streams
An online system tailors audio segments for users accessing a live audio stream such that the audio segments can be presented to users during a break of the live audio stream. The audio segment can include interactive content as well as one or both of an audio clip and a standard message, each of which serves as a type of introduction to the interactive content. For each user, the online system analyzes characteristics of the user to determine whether to include the standard message in addition to the audio clip, or to withhold the standard message from the audio segment. Therefore, different users accessing the live audio stream can be appropriately introduced to the interactive content which can improve the likelihood that the users interact with the interactive content. |
| US10868841B1 |
Voice over internet protocol (VoIP) call quality
A method for improving Voice over Internet Protocol (VoIP) call quality is disclosed. The method includes detecting, at a first computing device, a delay in receiving content data during a first media exchange. The first media exchange uses a first port. The method further includes automatically selecting a second port. The method also includes sending a port change notification featuring a port number of the second port to a second computing device. In some embodiments, the method further includes initiating a second media exchange using the second port. |
| US10868840B1 |
Multiple-master DNS system
In some particular embodiments, DNS servers are operated to maintain consistency of DNS records between the multiple master servers in response to certain types of communication situations. Each master DNS server monitors network connectivity by periodically testing or checking network connections of the master server (e.g., to another server). In one such exemplary context and particular embodiment, a first DNS master server operates by maintaining consistency of DNS records with at least one other DNS server. In this manner DNS records are updated using communications over a network and between the servers. Network isolation is detected and, after other related steps, restoration of connections to the at least one second DNS server is detected, and then queued DNS update requests are sent to the second DNS server. This approach is used to establish consistency of the DNS records between the DNS servers. |
| US10868839B2 |
Method and system for upload optimization
A technique for manipulating one mobile device (MD) from a plurality of MDs to maintain the transmitting rate of packets of an upload session to one Internet Protocol (IP) server from a plurality of IP servers is disclosed. The technique may utilize an upload-rate-controlling server that is communicatively coupled between the plurality of MDs and the plurality of IP servers and is configured to respond to missing one or more packets by using SACK and DSACK messages. Other embodiments may estimate the delay of the uploaded packets and adapt the value of a new-receiving window such that the delay of the uploaded packets is smaller than the value of the time threshold used by intermediate nodes for dropping packets. |
| US10868835B2 |
Method for managing data traffic within a network
A method manages data traffic within a network having controllers that each control a part of the network having a forwarding element (FE), the controllers being connected to a reference monitor (RM) for enforcing a security policy. The method includes: receiving a rule request by a controller and transmitting it its RM; the RM checking the rule request for policy compliance and authorizing a poly compliant part of the rule request. When the rule request has an outside modification: the controller contacts controllers impacted by the outside modification for obtaining an authorization, and upon receipt of authorization, sending the controller sends the modifications and authorizations to the impacted controllers to implement the modification in their FE. |
| US10868834B2 |
Detecting targeted data exfiltration in encrypted traffic
In one embodiment, a service that monitors a network obtains file characteristic data of a file stored on a first endpoint in the network. The service infers characteristics of encrypted content within encrypted traffic in the network between the first endpoint and a second endpoint, by applying a machine learning-based classifier to traffic data regarding the encrypted traffic session. The service compares the file characteristic data of the file to the inferred content characteristics of the encrypted content within the encrypted traffic, to detect the file within the encrypted traffic. The service enforces a network policy in the network, based on the detection of the file within the encrypted traffic. |
| US10868833B2 |
DNS or network metadata policy for network control
Techniques for configuring a network based on a Domain Name System (DNS) or network metadata policy for network control are disclosed. In some embodiments, a system, process, and/or computer program product for a DNS or network metadata policy for network control includes receiving a DNS or network metadata update at a DNS server (e.g., an authoritative or recursive DNS server) or an IP Address Management (IPAM) server, in which the DNS or network metadata update is determined to be relevant to the DNS or network metadata policy for network control; and sending the DNS or network metadata update to a network controller for a network, in which the network controller configures a plurality of network devices on the network based on the DNS or network metadata policy for network control. |
| US10868825B1 |
Cybersecurity and threat assessment platform for computing environments
An example network security and threat assessment system is configured to determine, based on one or more events that have occurred during execution of one or more applications, a potential security vulnerability of a target computing system, where the one or more events correspond to a node represented in the hierarchical risk model. The system is further configured to identify, based on a mapping of the node represented in the hierarchical risk model to a node represented in a hierarchical game tree model, one or more actions that are associated with the potential security vulnerability and that correspond to the node represented in the hierarchical game tree model, and to output, for display in a graphical user interface, a graphical representation of the potential security vulnerability and the one or more actions associated with the potential security vulnerability. |
| US10868823B2 |
Systems and methods for discriminating between human and non-human interactions with computing devices on a computer network
Humans as well as non-human actors may interact with computer devices on a computer network. As described herein, it is possible to train and apply human vs. non-human detection models to provide an indication of the probability that a human or a non-human actor was interacting with a computer device during a particular time period. The probability that a human or non-human was interacting with computers during a particular time may be used to improve various actions, including selecting one or more different threat detection models to apply during the particular time, selecting data to use with threat detection models during the time, or selecting data from the particular time to store. |
| US10868820B2 |
Systems and methods for determining individual and group risk scores
Embodiments disclosed herein describe a server, for example a security awareness server or an artificial intelligence machine learning system that establishes a risk score or vulnerable for a user of a security awareness system, or for a group of users of a security awareness system. The server may create a frequency score for a user, which predicts the frequency at which the user is to be hit with a malicious attack. The frequency score may be based on at least a job score, which may be represented by a value that is based on the type of job the user has, and a breach score that may be represented by a value that is based on the user's level of exposure to email. |
| US10868818B1 |
Systems and methods for generation of signature generation using interactive infection visualizations
According to one embodiment, a malware detection and visualization system includes one or more processors; and a storage module communicatively coupled to the one or more processors, the storage module comprises logic, upon execution by the one or more processors, that accesses a first set of information that comprises (i) information directed to a plurality of observed events and (ii) information directed to one or more relationships that identify an association between different observed events of the plurality of observed events; and generates a reference model based on the first set of information, the reference model comprises at least a first event of the plurality of observed events, a second event of the plurality of observed events, and a first relationship that identifies that the second event is based on the first event, wherein at least one of (i) the plurality of observed events or (ii) the one or more relationships constitutes an anomalous behavior is provided. |
| US10868816B2 |
Communities on a security information sharing platform
Examples disclosed herein relate to generating communities on a security information sharing platform. Some examples may enable identifying a set of community attributes to be used to generate a community on the security information sharing platform that enables sharing of security information among a plurality of communities. Some examples may enable authorizing a first user to access community-based security information of the community where the first user is associated a set of user attributes that satisfy the set of community attributes. A security indicator may be obtained from the first user of the community. Information related to the security indicator may be obtained from a second user of the community. Some examples may enable including the security indicator and the information related to the security indicator in the community-based security information of the community. |
| US10868814B2 |
System and method for flow-based architecture
A method for flow-based authorization includes receiving, at an electronic device, an input from an input agent and passing the input through a path of components to determine one or more action agents. Further, the method includes determining a flow for the input, wherein the flow comprises a representation of all possible paths between the input agent and the one or more action agents and providing a common language permission statement based on the flow. |
| US10868811B2 |
Secure user credential access system
A proxy server mitigates security risks of user credentials sent across a network in clear text. The proxy server encrypts user credentials within a client application request destined for an application server. The proxy server forwards the client application request to the application server. The application server sends the encrypted user credentials to the proxy server where the proxy server decrypts the user credentials and authenticates the user credentials with an authentication server. |
| US10868809B2 |
Analyzing facial recognition data and social network data for user authentication
Tools, strategies, and techniques are provided for evaluating the identities of different entities to protect business enterprises, consumers, and other entities from fraud by combining biometric activity data with facial recognition data for end users. Risks associated with various entities can be analyzed and assessed based on a combination of user liveliness check data, facial image data, social network data, and/or professional network data, among other data sources. In various embodiments, the risk assessment may include calculating an authorization score or authenticity score based on different portions or combinations of the collected and processed data. |
| US10868808B1 |
Server application access authentication based on SIM
A mobile communication device. The mobile communication device comprises a processor, a non-transitory memory, a subscriber identity module (SIM), wherein the SIM stores an encryption key, and a client application stored in the non-transitory memory. When executed by the processor, the client application transmits a server application authentication token request comprising an identity of the SIM, receives a message comprising a value, requests the SIM to encrypt the value using the encryption key stored by the SIM, receives an encrypted value from the SIM, transmits the encrypted value in a message, receives a server application authentication token, stores the server application authentication token in the non-transitory memory, transmits a server application access request comprising the server application authentication token, and conducts a communication session with the server application. |
| US10868806B2 |
Secure communication network
Secure network communications are described. In one aspect, a secure network can include a passbuilder that provides policy information related to performance characteristics of the secure network. A sender can receive the policy information and transmit packets to a receiver if the policy information is complied with by the potential packet transmission. |
| US10868804B2 |
Application package inspection method, inspection device and computer-readable storage medium
An application package inspection method is provided. The method includes: obtaining a to-be-inspected application installation package; and extracting an inherent attribute identifier and a certificate of the to-be-inspected application package from the to-be-inspected application package. Further, an authentication certificate corresponding to the inherent attribute identifier of the to-be-inspected application package is obtained from an information library storing correspondence relationships between inherent attribute identifiers and authentication certificates. The method also includes comparing the certificate of the to-be-inspected application package with the authentication certificate to obtain an inspection result of the to-be-inspected application package. |
| US10868801B2 |
Method and system for establishing connection
Establishing a connection is disclosed including acquiring an authentication code, sending data including the authentication code to a management server, receiving parameter information sent back by the management server after the management server performed a successful authentication using the data including the authentication code, and establishing, using the parameter information, a channel to a connection server. |
| US10868800B2 |
Secure communications system and device
A secure communication system includes a wearable secure communication device which may receive and transmit information via a network. A wearable secure communication device may include a noise generator. The wearable secure communication device further includes a power input connection. Additionally, the wearable secure communication device may include a communication processor. The secure communication system and the wearable secure communication device may provide access to a secure information exchange system. |
| US10868798B2 |
System and method of coupling a home area network with the cloud creating a highly secure and scalable private topology
A device, system and method, according to various embodiments, can include, for example, a hybrid cloud network, one or more personal cloud virtual LANs, and a home area network. The hybrid cloud network can be configured to provide public access and private access. The one or more personal cloud virtual LANs are provided at an overlapping segment of the hybrid cloud network to provide privacy within the hybrid cloud network. The home area network can include a single purpose computer configured as a gateway for the hybrid cloud network and configured to establish a site-to-site secure connection with the one or more personal cloud virtual LANs. |
| US10868794B2 |
Image processing apparatus, control method therefor, and storage medium
In a case where the name of the address book to be imported is a default name, the name of a stored address book is set as the name of the address book to be imported. A control method for an image processing apparatus includes storing, in a storage, an address book, importing an address book from an external apparatus, determining whether a name of an address book imported by the importing is a default name or not, and in a case where the name of the address book imported by the importing is a default name, setting a name of an address book stored in the storage as the name of the address book to be imported by the importing. |
| US10868790B2 |
Facilitating integration of collaborative communication platform and document collaboration tool
Disclosed are some implementations of systems, apparatus, methods and computer program products for integrating a collaborative communication system and a document collaboration system. A document within the document collaboration system may be linked to an object within the collaborative communication system. A user post may be received in association with the object or the document. A first feed configured to be rendered in association with the object is synchronized with a second feed configured to be rendered in association with the document such that both the first feed and the second feed each includes the user post. |
| US10868784B2 |
Comment thread navigation in a mobile document interface
A collaborative content item includes an ordered set of comment threads that each correspond to a portion of the collaborative content item. When a user requests that a first new comment be displayed, a first comment thread including the first new comment is displayed within a comment interface. When the user interacts with a new comment interface element, a second comment thread including a second new comment is displayed within the comment interface and a count of remaining new comments displayed within the new comment interface element is decremented. The user can also navigate between comment threads by interacting with the comment interface in a first direction (e.g., swiping, scrolling, selecting an interface element) and can navigate within a comment thread by interacting with the comment interface in a second direction. |
| US10868781B2 |
Video mail through peer to peer network
Illustrated is a system and method to record video mail using a peer to peer network. In some embodiments, a first computer system is operatively coupled to a second computer system, wherein the first and second computer systems are in a peer-to-peer configuration, a receiver resides on the second computer system to receive a video mail message, and a storage device resides on the second computer system to store the video mail message. In some embodiments, also illustrated is a method including configuring a first computer system and a second computer system into a peer-to-peer configuration, receiving a video mail message at the second computer system, and storing the video mail message on the second computer system. The method may further include receiving an audio signal on the first computer system, receiving a video signal on the first computer system, and transmitting the video signal using the first computer system. |
| US10868779B2 |
Indication of communication across applications
In a device including a processor and a memory, the memory includes executable instructions causing the processor to control the device to perform functions of displaying, via a GUI of a first communication application, content of a first communication session associated with a first communication application; detecting an activity related to a second communication session associated with a second communication application; displaying, as a part of the GUI of the first communication application, an indication of the detected activity and a first control element that, when activated, causes a user of the device to join the second communication session; receiving a first user input to activate the first control element; responsive to the received first user input, causing the user of the device to join and participate, via the GUI of the first communication application, the second communication session concurrently with the first communication session. |
| US10868778B1 |
Contextual feedback, with expiration indicator, to a natural understanding system in a chat bot
A chat bot computing system includes a bot controller and a natural language processor. The natural language processor receives a first textual input and identifies concepts represented by the first textual input. An indication of the concepts is output to the bot controller which generates a response to the first textual input. The concepts output by the natural language processor are also fed back into the input to the natural language processor, as context information, along with an expiration indicator when a second textual input is received. The natural language processor then identifies concepts represented in the second textual input, based on the second natural language, textual input and unexpired context information. |
| US10868775B2 |
Upgradable, high data transfer speed, multichannel transmission system
A local area network system that includes modular, multi-frequency, multi-channel, upgradable transmission nodes. The transmission nodes may include one or more independent RF modules and may be configured to include, for example, 802.11ac and may evolve to LTE and other technologies and frequency bands. |
| US10868773B2 |
Distributed multi-tenant network real-time model for cloud based enterprise resource planning solutions
Some embodiments are associated with multi-tenant software defined data center network traffic management. A data center computing system may calculate a first value for a first traffic flow, associated with a first user, using a dynamic, distributed, and substantially real-time model. The system may calculate a second value for to a second traffic flow, associated with a second user, using the dynamic, distributed, and substantially real-time model. The system may then dynamically allocate network resources to the first and second traffic flows based on the first and second priorities. Some embodiments may establish a plurality of network device queues and perform queue selection for optimization. According to some embodiments, the first user may be categorized as a premium user while the second user is categorized as an enterprise user. |
| US10868772B2 |
Control signaling of beam failure detection
Systems, apparatuses, and methods for control signaling of beam failure detection are disclosed. A beam pair link may be comprised of multiple bandwidth parts (BWPs) or component carriers (CCs). In one embodiment, a beam failure detection reference signal (BFD RS) may be configured, with subsequent BFD RS instances defining a BFD RS periodicity. A BFD periodicity for monitoring the BFD RS may be configured to be less than, or equal or greater than the BFD RS periodicity. A beam failure may be declared if a minimum number of BFD RS instances, either within the BFD periodicity, or nearest the BFD periodicity if no instances fall within the BFD periodicity, fall below a predetermined threshold. The BFD periodicity and BFD RS may be configured for all BWPs/CCs, a subset of BWPs/CCs, or each individual BWP/CC. |
| US10868771B2 |
Methods and systems for creating and managing network groups
The embodiments are directed to methods and devices for creating one or more network groups. The methods and devices can define a network group with one or more properties. The methods and devices can identify a plurality of isolated networks, and can assign the plurality of isolated networks to the defined network group. The methods and devices can assign machines to at least one of the plurality of isolated networks, wherein the network group enables unrestricted routing. |
| US10868770B2 |
System for early system resource constraint detection and recovery
A system for optimizing network traffic is described. The system includes a quality of service (QoS) engine configured to acquire information regarding a plurality of data packets comprising a plurality of data packet flows operating over a plurality of links. The QoS engine can be further configured to determine a flow priority to the plurality of data packets flows, and to determine TCP characteristics for the plurality of data packet flows. The system further includes a TCP controller configured to acquire the flow priority to the plurality of data packets from the QoS engine. The TCP controller can be configured to obtain queue information associated with the plurality of data packets, and adjust a receive window size based on the flow priority and the queue information. |
| US10868769B1 |
Read instruction queues in a network device
To more efficiently utilize buffer resources, schedulers within a traffic manager may generate and queue read instructions for reading buffered portions of data units that are ready to be sent to the egress blocks. The traffic manager may be configured to select a read instruction for a given buffer bank from the read instruction queues based on a scoring mechanism or other selection logic. To avoid sending too much data to an egress block during a given time slot, once a data unit portion has been read from the buffer, it may be temporarily stored in a shallow read data cache. Alternatively, a single, non-bank specific controller may determine all of the read instructions and write operations that should be executed in a given time slot. The read instruction queue architecture may be duplicated for link memories and other memories in addition to the buffer memory. |
| US10868767B2 |
Data transmission method and apparatus in optoelectronic hybrid network
The present disclosure relates to a data transmission method and apparatus in an optoelectronic hybrid network. The method is: receiving an RDMA transmission request, and determining an RDMA transmission type and a to-be-transmitted data volume for data transmission according to the RDMA transmission request; determining a preset encapsulation format corresponding to the RDMA transmission type for data transmission and the to-be-transmitted data volume for data transmission; receiving to-be-transmitted data and encapsulating the to-be-transmitted data into a to-be-transmitted data packet of the determined preset encapsulation format; selecting a switching link for data transmission from an optical switching link and an electrical switching link according to a size of the to-be-transmitted data packet; and sending the to-be-transmitted data packet to a peer end based on the selected switching link for data transmission. Therefore, a proper switching link can be selected each time RDMA transmission for data transmission is performed. |
| US10868765B2 |
Shaping traffic on PLCA-enabled 10SPE networks
A 10SPE network node includes a processor, a memory, instructions in the memory configured to cause the processor to generate data to be sent to other nodes, and a network stack. The network stack includes circuitry configured to delay transmission of data in a sending slot in a transmission cycle on a 10SPE network based upon a bandwidth sharing scheme. |
| US10868762B2 |
Systems and methods for mobility management in a distributed software defined network packet core system
A distributed software defined network (SDN) packet core system includes a plurality of interconnected local mobility domains (LMDs). Each LMD includes a plurality of radio access technology (RAT) specific front-end modules associated with at least one RAT and a mobility manager. Each RAT-specific front-end module is configured to handle intra-RAT and intra-LMD mobility events that involve switching connectivity of client devices between two radio access points coupled to the LMD and associated with a first common RAT that is also associated with that RAT-specific front-end module. The mobility manager is coupled to the front-end modules and is configured to handle intra-RAT and inter-LMD mobility events. The mobility manager can also be configured to handle inter-RAT and intra-LMD mobility events if the SDN packet core system supports more than one RAT. |
| US10868754B2 |
High availability input/output management nodes
Disclosed herein are enhancements for operating an input/output (I/O) management cluster with end I/O devices. In one implementation, a method of operating an I/O cluster includes, in a first I/O management node of the I/O management cluster, executing a first application to manage data for an I/O device communicatively coupled via at least one switch to the first I/O management node. The method further provides identifying a failure in the first I/O management node related to processing the data for the I/O device and, in response to the failure, configuring the at least one switch to communicate the data for the I/O device with a second I/O management node of the I/O management cluster. The method also includes, in the second I/O management node and after configuring the at least one switch, executing a second application to manage the data for the I/O device. |
| US10868752B2 |
Intelligent adaptive transport layer to enhance performance using multiple channels
A set of connections is established, continuously evaluated and maintained between two endpoints of a computer network for use in transmitting information flows in a more efficient and controlled manner. New connections are established and existing connections are terminated in a continual search for connections with better and/or different performance characteristics. Each connection may utilize the same or a different path through the network and may have performance characteristics that change over time. Several paths can be used simultaneously for a given information flow to improve network metrics including: throughput, transaction time, data consistency, latency and packet loss. Flows of information can be broken into one or more sub-flows and sub-flows can be assigned to one or more active connections. Furthermore, dynamic decisions regarding how flows are broken up and how they are assigned to connections can be made in response to network conditions. Through the use of these connections, a reduced cost can be offered and application QoS/QoE can be guaranteed, allowing existing networks such as the public Internet to provide an enterprise class connection, which can be used to accelerate enterprise cloud adoption without modifying the present Internet infrastructure. |
| US10868751B2 |
Configurable system for resolving requests received from multiple client devices in a network system
A system, a method, and a computer program for generating a dynamically configurable resolution route for transmitting a request object to one or more nodes in a network, comprising receiving a trigger signal from a first node, determining one or more destination nodes based on a resolution process, schema or scenario, determining a pathway to the one or more destination nodes, generating a resolution route for transmitting the request object in the network, iteratively transmitting the request object to the one or more destination nodes based on the resolution route, receiving a request object resolution signal from a final destination node, and transmitting the request object resolution signal to the first node based on the request object resolution signal. |
| US10868746B2 |
System and method for using subnet prefix values in global route header (GRH) for linear forwarding table (LFT) lookup in a high performance computing environment
System and method for supporting intra- and inter-subnet address resolution in a network environment using the same linear forwarding tale (LFT) for both the intra- and inter-subnet forwarding. Subnet prefix values in global route headers (GRHs) are used for linear forwarding table (LFT) lookup in a high performance computing environments. An exemplary can provide for use of an Inter Subnet Route Number (ISRN) embedded in the subnet prefix values in the GRHs for LFT lookup in a network switch environment in a high performance computing environment such as a network having an InfiniBand (IB) architecture. A method can provide, at a computer environment, including a network fabric, one or more subnets, each of which subnets are associated with one or more network switches or hosts. The system and method is compatible with legacy switches and nodes that are not conversant with the ISRNs. |
| US10868745B2 |
Device and network to reliably communicate in a network
A self-checking network device (201) for communication in a real-time network, wherein the self-checking network device (201) includes at least four modules (S-COM, P-COM, P-MON, S-MON), wherein the network device (201) and/or each of the four modules is configured such that a first module (S-COM) of the at least four modules receives both regular data and protocol data from said communication links (110) on a first input (COM-IN), and said first module (S-COM) forwards protocol data on a second input (P-COM-IN) to a second module (P-COM) of the at least four modules, wherein said second module (P-COM) executes a first function (C-PU) as part of the one or the more of the network protocols using protocol data received on said second input (P-COM-IN) and produces protocol data as output on a first output (P-COM-OUT). |
| US10868743B2 |
System and method for providing fast platform telemetry data
In one embodiment, a request for telemetry data measured by a plurality of components of a computing platform is received from a computing device. Contextual information associated with the requested telemetry data is provided in a first communication, wherein the contextual information comprises information describing the plurality of components. An instance of the requested telemetry data is provided to the computing device, wherein the telemetry data is provided in a second communication that omits at least a portion of the contextual information describing the plurality of components. |
| US10868742B2 |
Multi-cluster dashboard for distributed virtualization infrastructure element monitoring and policy control
This disclosure describes techniques for monitoring, scheduling, and performance management for virtualization infrastructures within networks. In one example, a computing system includes a plurality of different cloud-based compute clusters (e.g., different cloud projects), each comprising a set of compute nodes. Policy agents execute on the compute nodes to monitor performance and usage metrics relating to resources of the compute nodes. Policy controllers within each cluster deploy policies to the policy agents and evaluate performance and usage metrics from the policy agents by application of one or more rulesets for infrastructure elements of the compute cluster. Each of the policy controllers outputs data to a multi-cluster dashboard software system indicative of a current health status for the infrastructure elements based on the evaluation of the performance and usage metrics for the cluster. The multi-cluster dashboard software system data outputs, as single user interface screen, the current health status for each of the cloud-based compute clusters. |
| US10868741B2 |
Anchor shortening across streaming nodes
A method for facilitating anchor shortening across streaming nodes in an event stream processing system may include receiving a full anchor at an upstream marshaller. The full anchor may be associated with a data batch that corresponds to one or more event streams. The full anchor may include an indication of an input point for the one or more event streams. The full anchor may be received from an upstream compute processor. The method may also include mapping the full anchor to an index anchor and passing the index anchor to a downstream marshaller. |
| US10868737B2 |
Security policy analysis framework for distributed software defined networking (SDN) based cloud environments
Embodiments are disclosed that relate generally to software defined networking (SDN), and more particularly, but not by way of limitation, to devices, systems, and methods for a security policy analysis framework for distributed SDN-based cloud computing environments. The ease of programmability in SDN makes it a great platform implementation of various initiatives that involve application deployment, dynamic topology changes, and decentralized network management in a multi-tenant data center environment. However, implementing security solutions in such an environment is fraught with policy conflicts and consistency issues with the hardness of this problem being affected by the distribution scheme for the SDN controllers. In the embodiments disclosed herein, a security policy analysis framework is implemented on an OpenDaylight SDN controller that has comprehensive conflict detection and resolution modules to ensure that no two flow rules in a distributed SDN-based cloud environment have conflicts at any layer. This assures consistent conflict-free security policy implementation and preventing information leakage. In the embodiments disclosed herein, techniques are described for global prioritization of flow rules in a decentralized environment, for extending firewall rule conflict classification from a traditional environment to SDN flow rule conflicts by recognizing and classifying conflicts stemming from cross-layer conflicts, and providing strategies for unassisted resolution of these conflicts. Alternately, if administrator input is desired to resolve conflicts, a visualization scheme is implemented to help the administrators view the conflicts graphically. |
| US10868734B2 |
Service function chain detection path method and device
Provided are a service function chain detection path method and device. The method comprises: sealing a sending service function chain path identifier and a returning service function chain path identifier in a message header, and obtaining a service function chain detection message, the sending service function chain path identifier being used for indicating a path of the service function chain detection message, the returning service function chain path identifier being used for indicating a path of a service function chain detection reply message corresponding to the service function chain detection message; sending the service function chain detection message; receiving the service function chain detection reply message, the service function chain detection reply message comprising returning path information, the returning path information being used for indicating a service function chain path of the service function chain detection message during sending. |
| US10868725B2 |
Extensible plug-n-play policy decision framework for network devices using ahead of time compilation
A policy server may include a policy parser that is communicably coupled to a configuration database. The policy parser may identify a policy data model in the configuration database associated with a policy. The policy data model may include a policy object expressed in a human-readable format. The policy server may include a policy engine for constructing a dynamic acyclic graph (DAG) representing the policy data model. The policy engine may include a code generation engine for parsing the DAG to generate code in a high-level language. The policy engine may include a compiler for compiling the generated code to generate binaries for implementing the policy. The policy server may include a policy dispatcher for generating a notification to a policy client to dispatch the binaries to at least one subscriber of the policy following the code being compiled. The policy server may asynchronously update the policy for the subscribers. |
| US10868716B1 |
Hierarchical resource groups for providing segregated management access to a distributed switch
In one embodiment, an apparatus includes a network management module configured to execute at a network device operatively coupled to a switch fabric. The network management module is configured to receive a first set of configuration information associated with a subset of network resources from a set of network resources, the set of network resources being included in a virtual local area network from a plurality of virtual local area networks, the plurality of virtual local area networks being defined within the switch fabric. The first set of configuration information dynamically includes at least a second set of configuration information associated with the set of network resources. |
| US10868712B1 |
Cooperative monitoring networks
An electronic monitoring system is described that receives data from a particular monitoring system, receives data from multiple other monitoring systems, analyzes data received from the particular monitoring system irrespective of data received from the multiple other monitoring systems, based on the analysis, determines whether one or more events occur at the particular environment, and in response to determining that a particular event occurs at the particular environment, evaluates the particular event against a set of rules, selects, based on the evaluation results, a particular subset of the multiple other monitoring systems to serve as a cooperative monitoring network, assesses data received from the particular monitoring system with data received from the particular subset of the multiple other monitoring systems, based on the assessment, tracks, in connection with the particular event, events detected by the particular subset of the multiple other monitoring systems, and handles the particular event based on the tracked events detected by the particular subset of the multiple other monitoring systems. |
| US10868711B2 |
Actionable alert messaging network for automated incident resolution
Machine data reflecting operation of a monitored system is ingested and made available for search by a data intake and query system (DIQS). A monitoring function may search the data ingested by the DIQS to determine instances of notable events in regards to the monitored system and may further determine a defined invokable action message (IAM) associated with a notable event instance. Processing ensues to send an IAM to a communications device used by support personnel. The IAM includes information about an action invocation message (AIM) suitable to cause the performance of an action that possibly remedies or improves an operational condition represented by the notable event. Support personnel engages a user interface representation corresponding to the AIM and the AIM is sent to a remedial node where performance of the action is invoked. |
| US10868704B2 |
Method and device for transmitting wakeup packet in wireless LAN system
Proposed are a method and a device for transmitting a wakeup packet in a wireless LAN system. Specifically, a transmission device configures a wakeup packet and transmits the wakeup packet to a reception device. The wakeup packet, to which an OOK scheme is applied, includes a sequence comprising first information and second information. The first information comprises an on-signal, and the second information comprises an off-signal. The on-signal is transferred through a first symbol generated by applying a first sequence to K continuous subcarriers in a 20 MHz band and performing 64-point IFFT thereon. In the K subcarriers to which the first sequence is applied, coefficients of subcarriers are set to 1 or −1 by a unit of m subcarriers, and coefficients of the remaining subcarriers are set to 0. |
| US10868702B2 |
Method and apparatus for configuring and detecting cyclic prefix length in cell supporting multiple subcarrier spacings
The present embodiments relate to a method for configuring a cyclic prefix for a next generation/5G radio access network (referred to as new radio (NR)) about which 3GPP has begun discussions. According to the present embodiments, a base station configures cyclic prefix (CP) lengths for secondary numerology except for reference numerology and sets, through RRC signaling, the values of the CP lengths configured for the secondary numerology, thereby enabling a terminal to detect the CP lengths for the secondary numerology in a cell supporting mixed numerology. |
| US10868699B2 |
Method for generating forwarding information, controller, and service forwarding entity
A method for generating forwarding information includes determining, by a controller, a first service forwarding entity (SFE) and a second SFE forwarding a service stream, where the first SFE and the second SFE are on a service function chain corresponding to the service stream, generating, by the controller, first forwarding information for the first SFE and second forwarding information for the second SFE, and sending, by the controller, the first forwarding information to the first SFE and sending the second forwarding information to the second SFE. Hence, the controller generates forwarding information for the SFE such that a service chaining technology can be applied to a service environment in which a large quantity of services and a large quantity of service processing function units exist. |
| US10868697B2 |
Packet processing method, device, and packet processing system
A packet processing method, a device, and a packet processing system are provided. The method includes: generating, by a VTEP device at one end of a VXLAN tunnel, a PPP over VXLAN packet that carries control information, and transmitting the PPP over VXLAN packet to a VTEP device at the other end of the VXLAN tunnel by using the VXLAN tunnel. The VTEP device at the other end of the VXLAN tunnel may perform, based on the control information in the PPP over VXLAN packet, a function defined in PPP. In this way, a VXLAN control plane is implemented by using the PPP, and overheads and complexity of implementing the VXLAN control plane are reduced. |
| US10868694B2 |
Systems and methods for communication between devices and remote systems with a power cord
Systems and methods for remote control of an electronic device using a power cord are disclosed. A power cord that provides electric power to the device includes a module configured to receive wireless control signals originating from and/or transmit wireless signals to a remote device. The power cord includes one or more control wires for communicating signals between the module and the device. The module may be configured to translate information or signals received from the communications protocol of the remote device to the communications protocol of the device, and vice versa. The control wire(s) may extend along or within the power cord. Methods for wirelessly controlling a device comprise transmitting a command from a remote device to a module connected to the device's power cord, the module wirelessly receiving the command and transmitting the command to the appliance via control wires extending from the module to the device. |
| US10868692B2 |
Monitoring device using automation network
The disclosure is related to monitoring a legacy device using at least one smart device. A gateway of an automation system may monitor an operation status of a target legacy device located in a service area of an automation system using at least one of smart devices participating in the automation system. In order to monitor, a monitoring request may be received for monitoring the target legacy device from user equipment associated with a user. At least one of monitoring smart devices may be controlled for monitoring the target legacy device. Monitoring results may be received from the at least one of monitoring smart devices. The received monitoring results may be provided to the user through the user equipment using at least one of outputting monitoring smart devices. |
| US10868690B1 |
Programmable logic switch and system
A programmable logic switch (1) for controlling electrical utilities (3), has multiple control devices (2) of the electrical utilities (3), a serial interface (5) for connecting the switch (1) to an electrical bus (6) to which other switches (1) can be connected. The serial interface (5) is configured for receiving input signals (7) from other switches (1) and transmitting output signals (8) towards other switches (1). The switch (1) comprises an output device (12) having output channels (13) connectable to the electrical utilities (3) and separate with respect to the serial interface (5), and being configured for generating control signals (14) of the electrical utilities (3) as a function of any combination of signals chosen among control signals (4), programming signals (10) and input signals (7), so to control the electrical utilities (3) as a function of a command operated by a user and programming data. |
| US10868688B2 |
Method for setting functional parameters of a controller of a refrigeration apparatus
A method for setting functional parameters of a refrigeration apparatus controller is disclosed. A controller is prepared to operate a refrigeration apparatus having a unique identifier. The controller has a set of settable functional parameters having a plurality of subsets, each associated with an identifier. A setting device is provided to set each functional parameter of the set. A step of preparing a plurality of secondary applications is also included wherein each secondary application has a specific identifier and interacts with the primary application to limit the functional parameters which can be set by the primary application to the functional parameters belonging a specific subset. An assignment step for recording an identifier in the controller; a detection step during which the setting device is connected to the controller to receive the identifier; and an adaptation step for downloading the secondary application associated with the identifier received from an archive are also provided. |
| US10868686B2 |
System and method to provide default multicast group (MCG) for announcements and discovery as extended port information in a high performance computing environment
Systems and methods to provide default multicast group (MCG) for announcements and discovery as extended port information in a high performance computing environment. In accordance with an embodiment, hence, in order to enable IB multicast operations in a well-defined way without depending on SA access, there should be at least one IB multicast group (MCG) defined by the Subnet Manager and communicated to the IB clients via extended SMA attributes. |
| US10868683B2 |
Method and conference server for initializing scheduled conferences
Conference participants are selected via a network element in a network, the geographical area locations, for example, buildings of an enterprise, of the conference participants are determined and depending on the determined locations a geographical conference area, for example a conference room is determined for each conference participant. The conference area together with the conference information is communicated to the conference participants. The availability of the conference participants can be checked for the communication. |
| US10868680B2 |
Power over ethernet using shielded single twisted wire pair
A PoE system includes a PSE connected via a shielded twisted wire pair to a PD, where differential data is transmitted over only the wire pair, and where DC power is transmitted via the wires in the wire pair conducting a DC voltage in parallel while using the shield conductor as ground. A low power handshaking routine is performed by a PSE controller and a PD controller by conducting a source current through the wires in parallel and a return current through the shield conductor. Center tap auto-transformers are used to connect the two wires to the PSE and PD controllers and to a DC voltage source in the PSE. After a successful handshaking routine, the PSE couples the DC voltage source between the wire pair and the shield conductor by closing a first power switch. The PD controller then closes a second power switch to power a load. |
| US10868677B2 |
Method and system for reduced V2X receiver processing load using certificates
A method at a computing device within an Intelligent Transportation System, the method comprising: determining, at the computing device, whether a short-term certificate is available to sign a message; if the short-term certificate is available, signing the message with a private key associated with the short-term certificate; if the short-term certificate is not available, signing the message with a private key associated with a long-term certificate; and sending the message to a recipient. |
| US10868673B2 |
Network access control based on distributed ledger
Example embodiments for controlling access in a network system based on a distributed ledger are presented. In an example embodiment, a plurality of nodes of a computer network capture information describing requested data transactions in the computer network. At least some of the nodes construct transaction blocks for a distributed ledger, with each of the transaction blocks including information describing one or more of the requested data transactions. The nodes publish the transaction blocks to other nodes. The nodes receiving the transaction blocks add those of the transaction blocks that do not include a disallowable requested data transaction to copies of the distributed ledger. One or more arbitrator nodes approve those of the requested data transactions represented in transaction blocks added to the copies of the distributed ledger by a consensus of the nodes. |
| US10868666B2 |
Fully homomorphic encryption method based on modular operation
A fully homomorphic encryption method based on modular operation, the method including: acquiring a plaintext of any numerical value data type in an encryption process and converting the plaintext to a corresponding plaintext system plaintext according to an encryption requirement; performing an encryption operation on each number in the system plaintext, and combining ciphertexts acquired by the encryption operation to obtain a corresponding ciphertext combination; performing a ciphertext operation on the ciphertext combination using a ciphertext source code, a ciphertext radix-minus-one complement, and a ciphertext complement code based on modular encryption; and using modular division to decrypt a result of the ciphertext operation to obtain a decrypted plaintext. |
| US10868661B2 |
Systems and methods for efficiently-transformed digital self-interference cancellation
An efficiently-transformed digital self-interference canceller, preferably including an FD transformer, a TD transformer, a channel estimator, a composer, and a controller. The canceller can optionally include a channel memory, a predictor, and/or an extender. A method for digital self-interference cancellation, preferably including receiving inputs, transforming the inputs, generating outputs based on the transformed inputs, transforming the outputs, and/or generating a cancellation signal based on the outputs. |
| US10868660B2 |
Full-duplex activation in a wireless communication system
At least one condition associated with radio communication of a radio device (10-A, 10-B-, 10-C, 100) with a further radio device (10-A, 10-B-, 10-C, 100) is monitored. In response to the at least one condition being met, full-duplex operation is activated for the radio communication of the radio device (10-A, 10-B-, 10-C, 100) with the further radio device (10-A, 10-B-, 10-C, 100). The full-duplex operation comprises transmission of a first signal on a carrier frequency from the radio device (10-A, 10-B-, 10-C, 100) to the further radio device (10-A, 10-B-, 10-C, 100) and simultaneous transmission of a second signal on the same carrier frequency from the further radio device (10-A, 10-B-, 10-C, 100) to the radio device (10-A, 10-B-, 10-C, 100). |
| US10868657B2 |
Wireless network configured to provide mixed services
Systems, procedures, and instrumentalities are disclosed providing mixed data services such as mixed URLLC and eMBB services. In one example implementation, hierarchical modulation is dynamically configured and/or applied to provide the mixed services. The dynamic configuration and application of hierarchical modulation may be based on the respective priorities of the services and a condition of the concerned wireless network. The provision of the mixed services may utilize polar coding techniques. Control information may be mixed with data associated with the services. |
| US10868656B1 |
Channel state information computation delay determination for layer 1 signal to interference plus noise ratio reporting
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a channel state information (CSI) reporting configuration for a CSI report, wherein the CSI reporting configuration indicates that the CSI report is to include a layer 1 signal to interference plus noise ratio (L1-SINR); and determine a CSI computation delay requirement for processing the CSI report that is to include the L1-SINR. Numerous other aspects are provided. |
| US10868655B2 |
System and method for pipelining HARQ retransmissions for small cell backhaul
A system and method for reducing latency in a N/ACK system is described. The present system and method reduces latency in a N/ACK system by pre-generating one or more unsolicited backhaul grants to prepare one or more backhaul elements for the receipt and transmission of wireless data. In an embodiment, the present system and method additionally generates backhaul NACK holds for delaying the transmission of a NACK such that a NACK arrive at the UE at a predesignated time, such as at the subframe 12 after the original transmission at the subframe 0. |
| US10868643B2 |
Method and system for orthogonal multi-protocol transmissions
Methods and systems for multi-protocol transmissions in shared spectrum are disclosed where an OFDM transmitter is configured to generate transmissions associated with one OFDM technology or protocol using subcarriers of another OFDM technology. Generally, an OFDM transmitter may be configured to map or assign the different OFDM signals to different subsets of the available OFDM subcarriers such that the data contained therein can be transmitted at the same or during an overlapping time interval. In one application, an LTE transmitter is configured to generate and/or transmit LTE information using LTE subcarriers located in unused portion(s) of the Wi-Fi system bandwidth independently of or in addition to transmitting Wi-Fi or LTE information using LTE subcarriers located in portions of the Wi-Fi system bandwidth normally occupied by Wi-Fi subcarriers. |
| US10868639B2 |
Communication method, apparatus and system for multiple access points
Embodiments of the present invention provide a communication method, apparatus and system for multiple access points, which relate to a field of communication and support error recovery when multiple sending terminals and multiple receiving terminals transmit data together, so as to guarantee reliability of data transmission and improve throughput of system. The method includes: simultaneously sending, by a primary sending terminal and a secondary sending terminal, data corresponding to each receiving terminal to each receiving terminal through a shared channel; sending, by the primary sending terminal, BAR corresponding to the data to each receiving terminal; receiving, by the primary sending terminal, BA corresponding to the BAR and sent by each receiving terminal; and if the BA indicates that the data are correctly received by each receiving terminal, clearing the data cached in the primary sending terminal, and if the BA indicates that the data is not correctly received by each receiving terminal, retransmitting data which is not correctly received, and clearing correctly received data cached in the primary sending terminal. |
| US10868631B2 |
Construction method of mode-division multiplexing fiber-optic communication system and a constructed fiber-optic communication system
The present invention relates to a construction method of a mode-division multiplexing fiber-optic communication system, which includes following contents: converting multiple-input optical signals into optical propagation modes supported by a graded-index ring-core optical fiber at a transmitting end, after being multiplexed by a mode multiplexer, injecting the optical signals into the graded-index ring-core optical fiber for transmission; using a mode de-multiplexer to separate optical signals of different mode groups at a receiving end firstly; and for the separation of internal modes of the same mode group, adopting a multi-channel reception and a digital signal processing method based on a multiple-input multiple-output equalization for processing: for the separation of modes in a base mode group and a high-order mode group, using a digital signal processing algorithm including a 2×2 multiple-input multiple-output equalization and a digital signal processing algorithm including a 4×4 multiple-input multiple-output equalization for recovery processing, respectively. The method according to the present invention only needs to add an optical receiver and a digital signal processing module based on the 4×4 multiple-input multiple-output equalization repeatedly while adding the mode group to expand communication capacity. Compared with the prior art, the present invention has the characteristics of low complexity, high scalability and easy upgrading. |
| US10868627B2 |
Device and method of configurable synchronization signal and channel design
Devices and methods of using xSS are generally disclosed. A UE receives an xPSS with (Nrep) symbols each with a subcarrier spacing of K x a PSS subcarrier spacing and a duration of a PSS symbol/K. PSD subcarriers surround the xPSS and the ZC sequence is punctured to avoid transmission on a DC subcarrier. Guard subcarriers separate the xPSS and PSD when the ZC sequence is less than the occupied BW of the xPSS and at least one element in the ZC sequence is punctured for xPSS symbol generation otherwise. One or more xSSSs and xS-SCHs may follow the xPSS. The xSS may be omnidirectional, each having a same xPSS and different xSSS or xS-SCH or a different xPSS and same xSSS or xS-SCH or beamformed, each having different xPSSs and xSSSs or xS-SCHs or a same xPSS and different xSSS or xS-SCH. |
| US10868623B2 |
Airframe timestamping technique for point-to-point radio links
An example system comprising a first transceiver configured to receive a request airframe from a second transceiver over a wireless link, the request airframe including a first time indication indicating a first time TS1, a second time indication indicating a second time TS2 that the request airframe was received, generate a respond airframe and including a third time indication indicating a third time TS3 that the respond airframe is transmitted to the second transceiver, transmit the respond airframe to the second transceiver, provide a timestamp information request to second transceiver, receive a timestamp information response, the timestamp information response including a fourth time indication indicating a fourth time TS4, calculate a counter offset using the first time, second time, third time and fourth time as follows: counter offset = ( TS 1 + TS 4 - TS 3 - TS 2 ) 2 , calculate a phase offset based on the counter offset, and correct a phase of the first transceiver. |
| US10868622B2 |
Control and data multiplexing
Embodiments of the present disclosure may relate to an apparatus with a first component and a second component coupled with the first component by a plurality of signal wires. A first wire of the plurality of signal wires may be to carry a command byte of a packet and a first data byte of the packet from the first component to the second component. A second wire of the plurality of signal wires may be to carry a second data byte of the packet from the first component to the second component when the first signal wire carries the command byte of the packet and carry a third data byte of the packet from the first component to the second component when the first signal wire carries the first data byte of the packet. Other embodiments may be described or claimed. |
| US10868619B2 |
Method and user equipment for performing measurement, and method and base station for configuring measurement
A received signal strength indicator (RSSI) measurement time resource is provided to a user equipment. RSSI measurement symbol information indicating OFDM symbols from which the UE measures RSSI in a time resource unit for RSSI measurement (hereinafter, an RSSI measurement time resource unit) is provided to the user equipment. The user equipment measures RSSI from the OFDM symbols indicated by the RSSI measurement symbol information in RSSI measurement time resource unit(s). |
| US10868618B2 |
Device and method for providing a synchronized pattern sequence on multiple devices
A synchronized pattern sequence system including a processor and a timing receiver configured to receive a time reference signal to set a time of the electronic device. The system further includes sequence receiver configured to receive a sequence pattern and a timing for presenting the sequence pattern and a pattern indicator configured to present the sequence pattern. The system also has a memory and machine-readable code stored in the memory. The machine-readable code is configured to cause the processor to direct the pattern indicator to present the sequence pattern as a recognizable pattern according to the received timing in synchronization with the sequence pattern presented on at least one other electronic device. |
| US10868616B2 |
Method and apparatus for alignment of a line-of-sight communications link
Techniques are disclosed for aligning an optical transmitter with an optical receiver for a line-of-sight communications link, wherein the optical transmitter comprises a laser array emitter, the laser array emitter comprising a plurality of laser emitting regions, wherein each of a plurality of the laser emitting regions is configured to emit laser light in a different direction such that the laser array emitter is capable of emitting laser light in a plurality of different directions. The system can run produce emissions from different laser emitting regions until a laser emitting region that is in alignment with the optical receiver is found. This aligned laser emitting region can then be selected for use to optically communicate data from the optical transmitter to the optical receiver. |
| US10868615B1 |
Method of communication link acquisition using search pattern
Aspects of the disclosure provide for a method of forming a communication link between two communication devices using a primary search pattern and a secondary search pattern. A misalignment between a first optical system of a first communication device and a second optical system of a second communication device is detected. The first optical system is rotated according to the primary search pattern, and the second optical system according to the secondary search pattern. At the second communication device, a set of frames is captured. Then, it is determined whether a beacon beam transmitted from the first communication device is detected in the one or more of the captured frames. When it is determined that the beacon beam is detected, the communication link is formed between the first communication device and the second communication device. |
| US10868609B1 |
Diversity polarization modulation
A method includes transmitting a digital code from a transmitter to a receiver. Information is transmitted via electromagnetic waves from the transmitter to the receiver. The transmission of the information includes transmitting a first portion of the information using electromagnetic waves with a first polarization in response to a first value of the digital code, and transmitting a second portion of the information using electromagnetic waves of a second polarization in response to a second value of the digital code. The first information may include a first navigational code and the second information may include a second navigational code. |
| US10868608B2 |
Method and apparatus for beam association between downlink/uplink
The disclosure relates to a communication scheme and system for the convergence of a 5G communication system for supporting a higher a data transfer rate after the 4G system with the IoT technology. The disclosure may be applied to intelligence services (e.g., a smart home, a smart building, a smart city, a smart car or connected car, healthcare, digital education, retail business, security and safety-related services) based on the 5G communication technology and IoT-related technology. The disclosure discloses a method and apparatus for a beam association between DL/UL. |
| US10868604B2 |
Method and apparatus for reference signal for measurements
Methods and apparatuses for a reference signal for measurements. A method for operating a user equipment (UE), includes receiving, from a base station, a channel state information-reference signal (CSI-RS) trigger and an aperiodic CSI (A-CSI) request and decoding the CSI-RS trigger and the A-CSI request. The method includes measuring a CSI-RS associated with the CSI-RS trigger; and calculating, based on the measured CSI-RS, an A-CSI report associated with the A-CSI request. The method includes transmitting, to the base station, the A-CSI report. The CSI-RS includes two signal components for channel and interference measurement, respectively. Additional embodiments include base station and UE apparatuses and a method for operating a base station. |
| US10868600B2 |
Method for reporting and receiving channel state information, and device
Embodiments of the present invention provide a method for reporting and receiving channel state information (CSI), and a device. The reporting method includes: acquiring reference signal resource configuration information, where antenna port configuration information in the reference signal resource configuration information is used to indicate an antenna port structure; receiving, according to the reference signal resource configuration information, a reference signal sent by a base station; selecting a precoding matrix from a codebook based on the received reference signal, where a structure of the precoding matrix corresponds to the antenna port structure indicated by the antenna port configuration information; and reporting, to the base station, a PMI used to indicate the selected precoding matrix. According to the technical solutions of the present invention, a problem of reporting CSI in an AAS base station scenario is resolved, and precision of CSI reporting is improved. |
| US10868597B2 |
Method and apparatus for transmitting channel state information in wireless communication system
A method for receiving channel state information (CSI) by a base station, includes transmitting configuration information indicating whether to use a 4 antenna ports codebook, wherein a first codebook index for a first precoding matrix indicator (PMI) and a second codebook index for a second PMI for a specific CSI report mode with 4 antenna ports are determined when the UE is configured to use the 4 antenna ports codebook; and receiving the CSI indicating the first codebook index and the second codebook index, wherein a value of the first codebook index is determined as follows: when a rank indicator (RI) is 1, the value of the first codebook index is determined based on a value of the first PMI multiplied by 4, and when the RI is 2, the value of the first codebook index is determined based on the value of the first PMI multiplied by 4. |
| US10868594B2 |
UE-RS-based open-loop and semi-open-loop MIMO
Design of precoding and feedback for user equipment (UE)—specific reference signals (UE-RS)—based open-loop and semi-open-loop multiple input, multiple output (MIMO) systems is discussed. Aspects of the present disclosure provide for sub-resource block (RB) random precoding that allows for greater diversity gain in a lower bandwidth. In addition, the precoding may be performed using resource element (RE)—level layer shifting that provides for a number of precoders to be assigned to a number of layers for every such continuous subcarrier. As such, two codewords may experience the same effective channel quality with channel quality indicators (CQI) being averaged across all of the layers. |
| US10868591B2 |
Spatial and frequency diversity design for machine type communications (MTC)
Certain aspects of the present disclosure generally relate to wireless communications, and more specifically to increased diversity for devices with limited communications resources. An example method generally includes transmitting data as a bundled transmission to a device with limited communications resources, the bundled transmission comprising multiple bursts wherein each burst spans a plurality of transmission time intervals (TTIs) and the same data is transmitted in each burst, and taking action to increase diversity (e.g., at least one of spatial diversity, time diversity, frequency diversity, etc.) for the bundled transmission. |
| US10868589B2 |
Hybrid MU-MIMO spatial mapping using both explicit sounding and crosstalk tracking in a wireless local area network
Systems and methods for a wireless station supporting wireless communications with an associated wireless access point (WAP) on a wireless local area network (WLAN) where the wireless station can include hardware processing circuitry to perform hybrid spatial mapping feedback operations for multi-user (MU) multiple-input multiple-output (MIMO) downlinks from the WAP to a group of associated stations. An exemplary implementation includes a channel estimation circuit to determine a communication channel responsive to an explicit sounding from the WAP, and to transmit channel sounding feedback to the WAP indicating the determined communication channel; and a crosstalk tracking circuit to determine an amount of crosstalk from portions of a downlink MU-MIMO communication packet targeted for other stations in the group of associated stations, and to transmit crosstalk feedback to the WAP as to the determined amount of crosstalk. |
| US10868588B2 |
Conditional reference signal transmission and measurement
A user equipment apparatus determines whether a transmission is received from a base station within a time window and skips measurement of a reference signal during a subsequent period, when a transmission is received from the base station within the time window. A base station apparatus configures a UE to monitor one or more reference signals associated with a beam pair link and transmits a first signal in a transmission to the UE. The base station determines whether the transmission is received at the UE within a time window and determines whether to transmit a reference signal, based on whether the transmission is received at the UE within the time window. Upon determining that the transmission was received at the UE, the base station may skip transmission of the reference signal or modify a time, a frequency, a power, and/or a reference signal offset for the reference signal. |
| US10868585B2 |
Method for preventing abnormality during wireless charging
Disclosed is a control method of a wireless power transmitter, including transmitting power to a plurality of wireless power receivers based on a first power value required by a first wireless power receiver from among the plurality of wireless power receivers, selecting, before reaching a threshold condition in which a system error occurs in the wireless power transmitter, a second wireless power receiver from among the plurality of wireless power receivers, and in response to the second wireless power receiver being selected, transmitting power to the plurality of wireless power receivers based on a second power value required by the second wireless power receiver, wherein the system error comprises at least one of an over-temperature error, an over-current error, and an over-voltage error. |
| US10868583B2 |
Communication apparatus, communication method, and program
A communication device includes a first processing unit that sends a first command to start an activation processing. The communication device also includes a second processing unit that receives the first command from the first processing unit. In addition, the communication device includes an interface between the first processing unit and the second processing unit. The first processing unit activates the interface at a predetermined interface level from among a plurality of interface levels. The second processing unit starts an application in accordance with the activated interface level. The first processing unit and the second processing unit exchange data by the activated application. The first processing unit and the second processing unit perform a deactivation processing of the activated interface. |
| US10868581B2 |
Data center management using device identification over power-line
In one embodiment, a first device (e.g., a host device or power distribution unit) stores identification information of the first device, and determines, over a power connection, when the first device is in powered connectivity with a second device (e.g., a power distribution unit or host device, respectively). The first device may then communicate, with the second device over the power connection, identification information of at least one of either the first or second device, where the communicated identification information is accessible to a third device (e.g., a server) via a data network due to the communicating over the power connection. In another embodiment, a server may determine, based on the identification information, a physical location of a power distribution unit, and may deduce, based on the physical location of the power distribution unit, that a host device is physically located at the physical location of the power distribution unit. |
| US10868579B2 |
Device for controlling receiver to receive wireless signal
According to one embodiment, a wireless device includes a plurality of transmission/reception units and a controller. The each of the plurality of transmission/reception units includes an antenna and is configured to transmit/receive a wireless signal by the antenna. The controller individually controls a frequency of the wireless signal transmitted/received by each of the plurality of transmission/reception units. |
| US10868576B2 |
Frequency independence for synthesis within programmable non-reciprocal network circuit
An apparatus includes parallel delay lines, each exhibiting a delay; a first set of switches for each port of a first set of ports, each of which is to selectively couple a port of the first set of ports to first ends of the delay lines; a second set of switches for each port of a second set of ports, each of which to selectively couple a port of the second set of ports to second ends of the delay lines. A signal source generates a series of clock signals that are sequentially time delayed between the first set of switches and the second set of switches, where an input signal at one of the first or second sets of ports travels from the one of the first or second sets of ports to an output port of opposite set of ports over the delay lines. |
| US10868567B2 |
Methods and systems for encoding and decoding for LDPC codes
Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices. The Methods and devices use a LDPC matrix Hn of lifting factor Z. The LDPC matrix Hn comprises a plurality of submatrices, each submatrix having a size of Z×Z, and at least one submatrix has m1 diagonals of “1” m1 is an integer>=2. |
| US10868566B2 |
Error correction device, operating method of error correction device, and controller including error correction device
An error correction device includes a low density parity check (LDPC) decoder and an adaptive decoding controller. The LDPC decoder iteratively performs LDPC decoding on data by using a decoding parameter. The adaptive decoding controller calculates an error rate depending on a result of the LDPC decoding and adjusts the decoding parameter depending on the error rate. |
| US10868564B1 |
Methods and apparatus for a delta-sigma analog-to-digital converter
Various embodiments of the present technology may provide methods and apparatus for a delta-sigma analog-to-digital converter. The delta-sigma ADC may provide a sample-and-hold circuit defined by a first switch, a second switch, a capacitor, and an amplifier, and an integrator defined by the first capacitor, a second capacitor, and the amplifier, wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier. |
| US10868560B2 |
Low distortion successive approximation register (SAR) analog-to-digital converters (ADCs) and associated methods
An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage Vref=M*VDD, where M<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where Vref=M*VDD, where M<1, wherein the first capacitor having a capacitive value that is equal to (1−M)times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (VIN) signal as the second input to the comparator. |
| US10868559B1 |
Readout method, readout circuit and sensing apparatus with wide dynamic range
A readout circuit that includes an amplifier circuitry, an analog-to-digital converter, a feedback circuit and a control logic is introduced. The amplifier circuitry may receive and amplify a differential signal that is obtained according to an input signal and a feedback signal to generate an amplified signal. The analog-to-digital converter is configured to convert the amplified signal to generate a n-bit digital code, wherein n is a positive integer. The feedback circuit is configured to search and generate a m-bit digital code based on a value of the n-bit digital code and convert the m-bit digital code to generate the feedback signal, wherein m is a positive integer. The control logic is coupled to the analog-to-digital converter and the feedback circuit, and configured to control the analog-to-digital converter and the feedback circuit. A multi-bit digital output of the readout circuit is generated according to the n-bit digital code and the m-bit digital code. |
| US10868556B2 |
Apparatus for calibrating a time-interleaved analog-to-digital converter
An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes a clock generation circuit configured to generate a plurality of phase shifted clock signals for the plurality of time-interleaved analog-to-digital converter circuits and a reference clock signal. Further, the apparatus includes a reference signal generation circuit configured to generate a reference signal based on the reference clock signal. The reference signal is a square wave signal. The apparatus additionally includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the reference signal generation circuit or to a signal node capable of providing an analog signal for digitization. |
| US10868555B2 |
Successive approximation register (SAR) analog-to-digital converter (ADC), radar unit and method for improving harmonic distortion performance
A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: a track and hold circuit (414) configured to sample an analog input signal (410); a comparator (416) coupled to the track and hold circuit and configured to compare the sampled analog input signal (410) with a DAC (444) output voltage; and a feedback path (422) that comprises a digital-to-analog converter, DAC, (444) configured to generate the reference voltage that approximates the input analog signal (410). The SAR ADC (400) further includes a dither circuit (468) coupled to or located in the feedback path (422) and arranged to add a dither signal at an input of the DAC (444) in a first time period and subtract the dither signal from the output digital signal routed via the feedback path (422) and input of the DAC (444) in a second time period during a conversion phase of the SAR ADC (400). |
| US10868553B2 |
Atomic oscillator
An atomic oscillator includes an atom cell that accommodates an alkali metal atom, a heating device that heats the atom cell, a container that includes a first magnetism shielding member that is disposed between the heating device and the atom cell and a second magnetism shielding member that is disposed on the side opposite the atom cell with respect to the heating device to shield the atom cell from magnetism produced by the heating device, and a thermally insulating member disposed between the first member and the second member. |
| US10868552B2 |
Frequency divider circuit, demultiplexer circuit, and semiconductor integrated circuit
A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit. |
| US10868544B2 |
Digitally reconfigurable ultra-high precision internal oscillator
A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results. |
| US10868540B2 |
Superconducting non-destructive readout circuits
Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates. |
| US10868538B1 |
Logic cell structure and integrated circuit with the logic cell structure
A logic cell structure includes: a first portion, with a first height, arranged to be a first layout of a first semiconductor element; a second portion, with the first height, arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion; and a third portion arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. |
| US10868537B1 |
Supply voltage and temperature independent receiver
Embodiments relate to a circuitry for digital data communication. The circuitry includes an inverter circuit connected between an input node and an output node. The inverter circuit has core circuits each of which includes a complementary metal-oxide-semiconductor (CMOS) transistor of a first type and a CMOS transistor of a second type having a first common gate node connected to the input node and a first common drain node connected to the output node. The circuitry further includes another inverter circuit of a switching threshold voltage different than that of the inverter circuit and connected between the input node and the output node. The other inverter circuit has core circuits each of which includes a CMOS transistor of a third type and a CMOS transistor of a fourth type having a second common gate node connected to the input node and a second common drain node connected to the output node. |
| US10868534B2 |
Adiabatic logic-in-memory architecture
An adiabatic logic-in-memory based complementary metal-oxide-semiconductor/magnetic-tunnel-junction (ALiM CMOS/MTJ) circuit utilizes an adiabatic logic based pre-charged sense amplifier (PCSA) to recover energy from its output load capacitors. The ALiM CMOS/MTJ includes a non-volatile magnetic-tunnel-junction (MTJ) based memory. The ALiM CMOS/MTJ also includes a dual rail complementary metal-oxide-semiconductor (CMOS) logic that performs logic operations in association with the MTJ, and thereby generates logic outputs based on logic inputs. The ALiM CMOS/MTJ also includes the adiabatic PCSA, which is operatively coupled to the dual rail CMOS logic. The adiabatic logic based PCSA includes PCSA circuitry for which an input is a multi-phase power clock, and a charge recovery circuit having the output load capacitors. The charge recovery circuit is operatively coupled to the PCSA circuitry such that the ALiM CMOS/MTJ circuit uses the power clock to recover energy from the output load capacitors. |
| US10868528B2 |
Signal output device
Provided is a signal output device capable of appropriately outputting a signal even when a received signal amount is low. A signal output device is provided with: a high-side comparator; a low-side comparator; a high-side AC coupling unit which is connected to one end of the input terminal of the high-side comparator, and removes a DC component from either a high signal or a low signal; a low-side AC coupling unit which is connected to one end of the input terminal of the low-side comparator, and removes a DC component from either a high signal or a low signal; and a threshold output unit which outputs high-side threshold DC voltage to be combined with the output of the high-side AC coupling unit, and also outputs low-side threshold DC voltage to be combined with the output of the low-side AC coupling unit. |
| US10868525B2 |
Power transmission through a single conductive element
A circuit for power transmission through a single conductive element. The circuit includes an oscillator, a single conductive element, and a load. The oscillator is configured to generate a periodic voltage. The single conductive element is connected in series with the oscillator. The load is connected in series with the single conductive element. The load includes a first diode, a first resistor, and a first inductor. The first diode is connected in series with the single conductive element. The first resistor is connected in series with the first diode. The first inductor is connected between the first diode and the single conductive element. The first inductor is connected in series with the first resistor. |
| US10868524B2 |
Semiconductor circuit and semiconductor circuit layout system
A semiconductor circuit and a semiconductor circuit layout system are provided. The semiconductor circuit includes a clock inverter which inverts a clock signal and outputs an inverted clock signal where the clock inverter is laid out between a second master latch main circuit configured to latch signals of a first node and a fourth node based on the clock signal and the inverted clock signal, respectively, and a second slave latch main circuit configured to latch signals of a second node and a fifth node based on the clock signal and the inverted clock signal, respectively. |
| US10868520B2 |
Control buffer circuit and radio frequency switch device
A radio frequency switch includes a control buffer circuit to generate a first gate voltage and a first body voltage; and a switching circuit to switch at least one signal path in response to the first gate voltage and the first body voltage. The control buffer circuit includes an off voltage detection circuit to detect whether the off voltage is a negative voltage or a ground voltage and output a voltage detection signal, a first gate buffer circuit to output a first gate voltage having a voltage level based on the voltage detection signal and the band selection signal, and a first body buffer circuit to output a first body voltage having a voltage level based on the voltage detection signal, the band selection signal, and the mode signal. |
| US10868514B2 |
Method for manufacturing resonance apparatus
A resonance apparatus that processes an electrical loss using a conductive material and a method of manufacturing the resonance apparatus are provided. The resonance apparatus includes a lower electrode formed at a predetermined distance from a substrate, and a piezoelectric layer formed on the lower electrode. The resonance apparatus further includes an upper electrode formed on the piezoelectric layer, and a conductive layer formed on the upper electrode or the lower electrode. |
| US10868513B2 |
Transversely-excited film bulk acoustic filters with symmetric layout
There are disclosed acoustic resonators and radio frequency filter devices. An acoustic resonator includes a piezoelectric plate having a front surface. A conductor pattern is formed on the front surface, the conductor pattern including interdigital transducers (IDTs) of one or more pairs of sub-resonators, each pair consisting of two sub-resonators. The two sub-resonators of each pair of sub-resonators are positioned symmetrically about a central axis. |
| US10868507B2 |
Biasing circuits for voltage controlled or output circuits
A number of biasing circuits for amplifiers including voltage controlled amplifier is presented. Also a number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits. |
| US10868505B1 |
CMOS input stage circuits and related methods
Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage. |
| US10868496B1 |
Oscillator circuits and methods for realignment of an oscillator circuit
Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator. |
| US10868495B2 |
Auto-compensation for control voltage range of VCO at low power supply
Some aspects of the present disclosure relate to an apparatus, a PLL and an electronic device. The apparatus comprises a voltage-to-current (V2I) converter, a current controlled oscillator and a compensation current. The V2I converter is operable to receive a first voltage and generate a first current based on the first voltage. The current controlled oscillator is coupled to the V2I converter and operable to generate an oscillation signal based on a second current from or to the V2I converter. The compensation circuit is coupled to the V2I converter and operable to receive a third current from or to the V2I converter. The second and third currents vary in response to at least one of temperature variation and supply voltage variation of the apparatus. Variation direction of the third current is opposite to variation direction of the second current and different frequencies may be provided for a low supply voltage domain. |
| US10868486B2 |
Low power adaptive linear resonant actuator driver using accelerometer
An accelerometer and a linear resonant actuator (LRA) are mechanically coupled, such as by being mounted to the same circuit board. The output of the accelerometer is evaluated in order to select a drive frequency for the LRA. For example, the drive frequency may be varied while measuring the magnitude of acceleration induced by the LRA. The output of the accelerometer may further be used to perform a fitness tracking function, such as counting steps or detecting an activity level. |
| US10868483B1 |
DC generator system
A system including a variable frequency generator (VFG) including a generator configured to conduct alternating current to a first rectifier configured to convert alternating current from the VFG to direct current and drive it to an HVDC Bus Network, a variable frequency second generator including a second generator configured to conduct alternating current to a second rectifier configured to convert alternating current from the second generator to direct current and conduct it to the HVDC Bus Network, a speed correcting gearbox operatively connected to the VFG configured to align generator frequency to the second generator frequency, and a VFG control unit operatively connected to the generator configured to control the VFG, and a second generator control unit operatively connected to the second generator and the HVDC Bus Network configured to control the second generator. |
| US10868480B2 |
Motor driving apparatus, motor system including the same, imaging apparatus, and motor driving method
An apparatus includes at least one processor or circuit programmed to function as a detection unit that detects a rotational position of a rotor, and a generation unit that generates a driving waveform for a motor based on the detected rotational position. The generation unit includes a phase difference setting unit that sets a phase difference between the rotational position and the driving waveform, a changing time setting unit that sets a changing time, which is a time required for changing the phase difference from a phase difference before the change to a phase difference after the change, in a case where the set phase difference is changed, and a determination unit that determines a phase of the driving waveform based on the phase difference before the change, the phase difference after the change, and the changing time. |
| US10868479B2 |
Inverse electrowetting and magnetic energy harvesting and scavenging methods, circuits and systems
A harvesting and scavenging circuit includes an inverse electrowetting harvesting and scavenging circuit including a moveable mass with a moveable electrode that is moveable in three-dimensions relative to a second electrode having a first insulating layer covering a surface of the second electrode. A conductive fluid positioned between the first insulating layer and the moveable electrode. A magnetic energy harvesting and scavenging circuit includes at least one permanent magnetic segment on the movable mass and at least one energy harvesting and scavenging coil positioned proximate the moveable mass. Energy harvesting and scavenging circuitry is electrically coupled to the moveable electrode and the second electrode and is coupled to the at least one energy harvesting and scavenging coil. The energy harvesting and scavenging circuitry provides electrical energy generated through reverse electrowetting and magnetic energy stored in the at least one energy harvesting and scavenging coil. |
| US10868476B2 |
Power converting apparatus, and photovoltaic module including the same
Disclosed are a power converting apparatus and a photovoltaic module including the same. The photovoltaic module includes: a converter configured to convert a level of DC power; an inverter configured to convert a half sine wave voltage from the converter into an AC voltage; and a controller configured to control the converter and the inverter based on an output current and an output voltage of the inverter, wherein a plurality of switching elements in the inverter is respectively turned on once in each cycle, and wherein the controller is configured to, based on a difference between a grid voltage and an output current of the inverter, control a bidirectional current to flow to the converter. Accordingly, the power converting apparatus including the unfolding inverter is able to control a power factor. |
| US10868472B2 |
Power conversion circuit with switching modes, and control method thereof
A power conversion circuit includes a switching circuit, a resonant circuit, a rectifying circuit, a controller and a transformer including a primary winding and a secondary winding. The resonant circuit is electrically coupled to the switching circuit and the primary winding. The rectifying circuit is electrically coupled to the secondary winding. The controller is electrically coupled to the switching circuit and the rectifying circuit and configured to selectively output one of a frequency modulation signal and a pulse width modulation signal as a second control signal according to a working frequency of a first control signal. |
| US10868471B2 |
Adaptive voltage modification (AVM) controller for mitigating power interruptions at radio frequency (RF) antennas
This disclosure describes techniques to identify and mitigate an effect of a power interruption that impacts the operation of Radio Frequency (RF) antennas associated with a telecommunications network. More specifically, an Adaptive Voltage Modification (AVM) controller is described that is configured to monitor and detect a change in voltage that occurs during a power transmission from a Direct Current (DC) power source to a Remote Radio Unit (RRU). A power interruption may include a power disruption or a power surge. The AVM controller may be configured to cause a potential transformer that is coupled between the DC power source and the RRU to incrementally step-up or step-down the voltage of a power transmission from the DC power source. In this way, the AVM controller may preemptively mitigate an impact of a power interruption on Quality of Service (QoS) parameters associated with signal data transmitted by the RF antennas. |
| US10868468B1 |
DC-DC converter for current controlled solenoid drive
Provided are embodiments for a circuit including a DC-DC converter for current controlled solenoid drive, the circuit includes a constant current source; a charge pump circuit comprising a plurality of stages. Each stage includes a capacitor configured to be charged to a predetermined voltage; a current source operable to charge the capacitor; a switch; and a controller that is configured to control switching of the switch for each of the plurality of stages based at least in part on an output current of the charge pump. Also, provided are embodiments of a method for operating a DC-DC converter for current controlled solenoid drive. |
| US10868464B2 |
Linear vibration motor
Disclosed is a linear vibration motor, including an housing, a driving unit, a vibration unit, and an elastic component. The vibration unit includes a mass block having a through hole, and a permanent magnet and a pole core that are disposed in the through hole, the driving unit includes an iron core fixed on the housing and running through the through hole and a coil wound around the iron core, the pole core is disposed at one side of the permanent magnet close to the coil, the iron core includes an iron core body portion running through the through hole and two iron core abutting portions, the coil is wound around the iron core body portion, two different sides of the permanent magnet have different magnetic polarities, and after the coil is powered on, the two iron core abutting portions have opposite magnetic polarities. |
| US10868463B2 |
Vibration motor and mobile communication device using same
The present disclosure provides a vibration motor and a mobile communication device using same. The vibration motor includes an housing, a vibrator accommodated in the housing, a driving apparatus driving the vibrator to vibrate, and an elastic part elastically supporting the vibrator, where the driving apparatus is a secondary coil accommodated in the housing, the vibrator is provided with a magnet steel corresponding to the coil, the vibration motor further includes a primary coil, disposed outside the housing, corresponding to the secondary coil, and spaced apart from the secondary coil, and the primary coil is electrically connected to the outside to generate an alternating electromagnetic field, to cause the secondary coil to generate an induced electromotive force, and cause relative vibration between the vibrator and the secondary coil. |
| US10868459B2 |
Electromechanical actuator comprising a redundant electronic sub-system
An electromechanical actuator for rack-and-pinion steering includes a stator, rotor, and electronic system. The electronic system includes at least one first electronic sub-system and a second electronic subsystem, each operatively connected to the stator and the rotor. The at least one first electronic sub-system is arranged at least on a first circuit carrier plane and a second circuit carrier plane, and includes a first power output stage, a first control unit, and a first rotor position sensor arrangement. The second electronic sub-system is arranged at least on the first circuit carrier plane and a third circuit carrier plane, and includes a second power output stage, a second control unit, and a second rotor position sensor arrangement. The first, second and third circuit carrier planes are arranged perpendicular to an axis of rotation of the rotor, and are spaced apart from each other along the axis of rotation. |
| US10868456B2 |
False tooth assembly for generator stator core
A false tooth assembly for a generator stator core is presented. The false tooth assembly has a tapered shape including multiple tapered false tooth pieces. The multiple tapered false tooth pieces are installed into a damaged area in a tooth of a lamination of the stator core such that a wide end of the false tooth assembly is disposed into a wide opening of the damaged area and a narrow end of the false tooth assembly is flushed with a narrow opening of the damaged area at a tip of the tooth. The tapered shape of the false tooth assembly enables the false tooth assembly to fill the entire damaged area and to lock the false tooth assembly into the damaged area. The false tooth assembly can be used to repair stator core in any region of the stator core including step iron region without being dislodged during generator operation. |
| US10868452B2 |
Motor
A motor includes a rotor to rotate about a motor axis, and a stator radially outside of the rotor. The rotor includes a shaft extending along the motor axis, and including a collar portion and a screw portion located along an axial direction on an outer circumferential surface thereof, a rotor core surrounding the shaft from radially outside, a rotor magnet fixed to the rotor core, a pair of plate-shaped end plates on both axial sides of the rotor core, and a nut screwed onto the screw portion. The rotor core and the pair of end plates are held between the collar portion and the nut. Each end plate includes a first surface opposite to an axial end surface of the rotor core, and a second surface facing away from the first surface. The first surface includes a slanting surface that slants toward the rotor core and extends radially outward, and is in contact with the axial end surface of the rotor core. |
| US10868451B2 |
Electric machine comprising a rotor and a stator
The invention relates to an electric machine comprising a rotor (10) and a stator (20). The rotor (10) has magnet pockets for receiving permanent magnets (55, 56, 85, 86), and the magnet pockets comprise at least one first pair of magnet pockets (50, 51) and a second pair of magnet pockets (80, 11). The second pair (80, 81) is arranged further inwards than the first pair (50, 51) when viewed in a radial direction with respect to a rotational axis, and the magnet pockets of each pair of magnet pockets (50, 51, 80, 81) are arranged symmetrically to one another with respect to an axis of symmetry (45), wherein the axis of symmetry (45) runs in the radial direction and through the center of the rotor (10). The magnet pockets of each pair of magnet pockets (50, 51, 80, 81) are arranged such that the distance of each magnet pocket to the axis of symmetry (45) increases as the distance to the circumferential edge (110) of the rotor (10) decreases. The magnet pockets of the first pair (50, 51) are arranged at a first mechanical angle to one another, and the magnet pockets of the second pair (80, 81) are arranged at a second mechanical angle to one another. The invention is characterized in that the first angle ranges from ca. 100° to ca. 140°, in particular from ca. 120° to ca. 140°, and the second angle ranges from ca. 65° to ca. 112°, in particular from ca. 88° to ca. 112°. |
| US10868450B2 |
Rotor of rotary electric machine
A rotor of a rotary electric machine includes a rotor core having a slot in an outer circumferential portion thereof, a permanent magnet inserted in the slot, and a resin injected into the slot to fix the permanent magnet in the slot, wherein an injection fixing space into which the resin is injected to fix the permanent magnet in the slot, and a non-injection space into which the resin is not injected are provided in a space within the slot, the non-injection space is disposed at a position adjacent to an outer side of the rotor core in a radial direction with respect to the injection fixing space, and an edge of the non-injection space includes a surface of the resin injected into the injection fixing space, and a first region on an inner surface of the slot which continues to the surface of the resin. |
| US10868447B2 |
Fast method for identifying coil misalignment/mutualcoupling in wireless charging systems
Methods and apparatus for determining the misalignment and mutual coupling between the transmitter coil and receiver coil, with or without an intermediate relay resonator coil, of a wireless power charging system are provided. The determination can be made without using any direct measurement from the receiver circuit. The technic involves exciting the transmitter coil of the wireless power charging system at several frequencies with equal or different input voltage/current, such that the number of equivalent circuit equations is at least equal to the number of unknown terms in the equations. The methods use the knowledge of only the input voltage and the input current of the transmitter coil. This means that the mutual inductance or magnetic coupling coefficient between the transmitter and receiver coils can be determined based on the information obtained from the transmitter circuit and there is no need for any wireless communication from or direct measurements of the receiver circuit. |
| US10868445B2 |
Magnetic sheet and wireless power reception device comprising same
A magnetic sheet according to an embodiment comprises: a first magnetic sheet part comprising a first surface; a second magnetic sheet part comprising a second surface facing the first surface; and an adhesion part disposed between the first surface and the second surface, wherein the adhesion part comprises a plurality of magnetic particles, and the plurality of magnetic particles may have a concentration gradient in the thickness direction of the adhesion part. |
| US10868444B2 |
Method of operating a system having a substrate configured to facilitate through-metal energy transfer via near field magnetic coupling
An electrically conductive material configured having at least one opening of various unlimited geometries extending through its thickness is provided. The opening is designed to modify eddy currents that form within the surface of the material from interaction with magnetic fields that allow for wireless energy transfer therethrough. The opening may be configured as a cut-out, a slit or combination thereof that extends through the thickness of the electrically conductive material. The electrically conductive material is configured with the cut-out and/or slit pattern positioned adjacent to an antenna configured to receive or transmit electrical energy wirelessly through near-field magnetic coupling (NFMC). A magnetic field shielding material, such as a ferrite, may also be positioned adjacent to the antenna. Such magnetic shielding materials may be used to strategically block eddy currents from electrical components and circuitry located within a device. |
| US10868443B2 |
Selectable coil array
An inductive wireless power system using an array of coils with the ability to dynamically select which coils are energized. The coil array can determine the position of and provide power to one or more portable electronic devices positioned on the charging surface. The coils in the array may be connected with series resonant capacitors so that regardless of the number of coils selected, the resonance point is generally maintained. The coil array can provide spatial freedom, decrease power delivered to parasitic loads, and increase power transfer efficiency to the portable electronic devices. |
| US10868442B2 |
Wireless power transfer pad with ferrite chimney
A wireless power transfer (“WPT”) pad with a ferrite chimney is disclosed. The WPT pad includes a winding with a conductor where the conductor is wound in a planar configuration. The winding includes a center section about which the winding is wound. The WPT pad includes a ferrite structure with a parallel section located on a side of the winding with at least a portion in parallel with the winding, and a chimney section in magnetic contact with the parallel section and located in the center section of the winding, the chimney section extending perpendicular to the parallel section. |
| US10868440B2 |
Compressed air energy storage generator
A compressed air energy storage generator includes a motor, a compressor, a pressure accumulator, an expander, a generator, an electric-motor inverter, a generator inverter, a feed command receiver, a discharge command receiver, and a controller. The controller includes a feed determination unit, a discharge determination unit, and an input and output adjustment unit, the feed determination unit being configured to determine whether a feed command value is smaller than minimum charge power, the discharge determination unit being configured to determine whether a discharge command value is smaller than minimum discharge power, the input and output adjustment unit being configured to control, when the feed determination unit determines that the feed command value is smaller than the minimum charge power or when the discharge determination unit determines that the discharge command value is smaller than the minimum discharge power, the inverters to simultaneously drive the motor and the generator. |
| US10868435B2 |
Charging station mounted on a powered driveable machine
A mower having a supplemental battery charging station mounted thereon is provided. The mower utilizes a flywheel/alternator arrangement to output a selected voltage. The voltage is directed to the supplement battery charging station. The supplemental batteries are thereby charged at the charging station as the mower is driven forward or in another direction. The lawn mower also includes a rack (which may be in the form of a hook) to carry a battery powered supplemental lawn maintenance tool, such as a weed trimmer, hedger, edger, or leaf blower, amongst others. |
| US10868427B2 |
Method for feeding electrical power into an electrical supply network
A method for supplying electric power to an electrical supply grid that has a grid rated voltage and is operated at a grid voltage, wherein the supplied electric power has a reactive power component that is prescribed by a phase angle describing an angle between a current and a voltage of the supplied electric power, wherein the phase angle is set by means of phase angle control that has a delay function characterized by at least one time constant. |
| US10868426B1 |
Exploitation of electrical power produced by a household photovoltaic system to electrically power remotely electronically-controllable electric household appliances
An electronic control system to control exploitation of electrical power produced by a household photovoltaic system to electrically power remotely electronically-controllable electric household appliances. The household photovoltaic system is electrically connected to a public electrical power mains and to a household electric system via an electronic electrical power meter configured to measure the electrical power produced by the household photovoltaic system and the electrical power absorbed from or supplied to the public electrical power mains as a result of an electrical power underproduction or overproduction of the household photovoltaic system compared to the electric power consumption of the household electric system. The electronic control system comprises an electronic control unit provided with a user programming interface and configured to communicate with the electronic electrical power meter to determine an excess of electrical power produced by the photovoltaic system over the electric power consumption of the household electric system. |
| US10868424B2 |
Method for controlling current amount flowing into circuit module and associated chip
The present invention provides a chip comprising a circuit module, a power switch and a detection and control circuit. The power switch is coupled between a supply voltage and the circuit module, and is used to selectively connect the supply voltage to the circuit module, and control a current amount flowing into the circuit module according to at least a control signal. The detection and control circuit is coupled to the power switch, and is used to detect a first signal generated by a first circuit positioned surrounding the circuit module, and compare the first signal with a second signal in a real-time manner to generate the control signal to adjust the current amount flowing into the circuit module. |
| US10868420B2 |
Input protection circuit
An input protection circuit includes a current detection circuit, a voltage detection circuit, a latch circuit and an output circuit. The current detection circuit receives a power input, and when an input current exceeds a threshold current, the current detection circuit outputs a control current. The voltage detection circuit is coupled to the current detection circuit, and when the input voltage exceeds a threshold voltage, the voltage detection circuit outputs a control voltage. The latch circuit is coupled to the current detection circuit and the voltage detection circuit. When the latch circuit receives the control voltage or the control current, a switching voltage outputted by the latch circuit is equal to a reference voltage. The output circuit is coupled to the current detection circuit, the voltage detection circuit and the latch circuit. When the switching voltage is equal to the reference voltage, the output circuit stops outputting a power output. |
| US10868418B2 |
Electronic switch for electronic fuse
In accordance with one example, the electronic switch has a load current path operably coupled to a load via a wire; the electronic switch is configured to connect or disconnect a load current supply node and the load via the wire dependent on a drive signal. Further, the electronic fuse circuit includes a monitoring circuit configured to receive a current sense signal representing the load current passing through the wire and to determine a first protection signal based on the current sense signal and at least one wire parameter. The first protection signal is indicative of whether to disconnect the load current supply node from the load. Moreover, the electronic fuse circuit includes a logic circuit configured to receive at least one selection signal and to set the at least one wire parameter based on the at least one selection signal. |
| US10868414B2 |
Mounting system for sensors on electrical power lines
A system for monitoring current and voltage from a power source or load at the tap wire connected to an overhead distribution power line, the distribution power line being spaced apart from the ground is provided. The system includes a current clamp sensor coupled to the tap wire and spaced apart from the distribution power line. A sensor is insulated body coupled to the current clamp, the sensor body being configured to simultaneously measure voltage on the overhead distribution power line and current of the tap wire prior to the distribution power line. A mounting assembly is provided that suspends the sensor from the distribution power line, the mounting assembly being coupled between the distribution power line and the current clamp. |
| US10868413B1 |
Depth-adjusting electrical box
The depth-adjusting electrical box comprises an electrical box and one or more mounting brackets. The electrical box may be mounted to a stud via an individual mounting bracket selected from the one or more mounting brackets. The electrical box may be mounted at a mounting depth that is selected from a plurality of mounting depths. The mounting depth may be established by the selection of the individual mounting bracket, by the orientation of the individual mounting bracket, by the selection of which of a plurality of mounting apertures on the electrical box are used to couple the electrical box to the individual mounting bracket, or by combinations thereof. The mounting depth may be selected to compensate for the thickness of coverings placed over the studs. |
| US10868409B2 |
Spark plug
Disclosed is a spark plug in which a first electrode has a tip joined to an electrode base through a fusion zone. In a cross section of the first electrode taken along a center axis, an interface of the fusion zone and a tip includes a first region, a second region and a base point present on at least one side of the cross section. The base point is a point connection of the first and second regions and is located farthest away from the imaginary straight line in the direction parallel to the center axis. The base point is positioned so as to satisfy a condition of 0.1≤X/W≤0.4 where W is a length of the interface in a direction perpendicular to the center axis; and X is a distance between the base point and the center axis. |
| US10868400B1 |
Clamping light bulb
A light bulb having a tapering base with a circumferential clip providing the electrical and mechanical attachment to a conventional socket. The clip includes a circumferential band and a pair of diametrically opposing spring clips that, when simultaneously pressed inward, serve to compress the circumferential band, thereby enabling removal of the light bulb from the socket. |
| US10868399B2 |
Adapter
Disclosed herein is an adapter having a plug removably coupled to an adapter body. The adapter includes an adapter body including an adapter pin, a mounting portion provided in the adapter body and including a first mounting portion provided on one side of the adapter body on which the adapter pin is disposed, and a second mounting portion provided on another side of the adapter body, and a plug configured to be removably coupled to the first mounting portion and the second mounting portion wherein a plug terminal provided on one side surface of the plug is electrically connected to the adapter pin provided on the one side of the first mounting portion regardless of an orientation of the plug with respect to the mounting portion. |
| US10868395B2 |
Ethernet transmission line
An Ethernet transmission line includes two RJ45 connectors and a thin connection line. Each RJ45 connector has a connection terminal group, and the connection terminal group includes a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal that are sequentially arranged. The thin connection line is connected between the two RJ45 connectors and the thin connection line includes a first flexible printed circuit board layer, a second flexible printed circuit board layer, and a spacing layer. The first flexible printed circuit board layer is provided with two first transmission lines respectively electrically connected to the third terminal and the sixth terminal. The second flexible printed circuit board layer is provided with two second transmission lines respectively electrically connected to the fourth terminal and the fifth terminal. |
| US10868389B2 |
Electrical contact device with interlock
An electrical connector assembly includes a first electrical contact device and a second electrical contact device. The first electrical contact device includes at least one first electrical contact and an actuator movable between a first position and a second position. The second electrical contact device includes at least one second electrical contact device and an interlock feature to engage the actuator when the actuator is in the first position. The actuator is in the first position when the first electrical contact is in electrical communication with a power source, and the actuator is in the second position when the electrical communication between the first electrical contact and the power source is disconnected. When the actuator is in the first position and the second electrical contact engage the first electrical contact, the interlock feature engages the actuator, thereby securing the first electrical contact device and the second electrical contact device against disconnection. |
| US10868387B2 |
High speed wire end connector and manufacturing method thereof
A high speed wire end connector manufacturing method includes the following steps. First, a cable is soldered to a printed circuit board, and then an inner film is formed to cover a portion of the cable and a portion of the printed circuit board by an insert molding process. Another portion of the printed circuit board is passed through a guide hole of an outer casing, and a molded bonding layer is formed by an outer molding process to bond to the outer casing and the inner film. In addition, a metal spring latch is fixed on the outer casing. In addition, a high speed wire end connector is also disclosed herein. |
| US10868383B2 |
Surface-treated plated material, connector terminal, connector, FFC terminal, FFC, FPC and electronic part
A surface-treated plated material is provided. The surface-treated plated material can suppress generation of whiskers, maintain good solderability and low contact resistance even when exposed to an elevated temperature environment, and have lower insertion force for terminals/connectors. The surface-treated plated material comprises a substrate provided with an upper layer, and the upper layer comprises a plated material containing Sn or In. A surface of the plated material contains at least one compound represented by a certain general formula and at least one compound represented by a certain general formula. One or more compounds selected from a group D of constituent compounds represented by certain general formulae are further applied onto a surface on the upper layer side. |
| US10868378B2 |
Receptacle connector and connector assembly including the same
A receptacle connector having a stable contact point structure and a rigid structure, and a connector assembly including the same, is provided. The receptacle connector includes a receptacle housing, a plurality of receptacle terminals which are retained and supported in the receptacle housing in a first direction, and one pair of receptacle metal members which are provided on both ends of the receptacle housing in the first direction. |
| US10868377B2 |
Electrical spring contact with integrated extending carrier portion
An electrical spring contact is provided. The electrical spring contact includes a connection portion configured to couple the electrical spring contact to a printed circuit board, a bulge portion, a bend portion having a substantially U-shaped configuration, and an inclined portion extending from the bend portion at an angle relative to a plane that is substantially parallel to the connection portion. The connection portion, the bulge portion, the bend portion, and the inclined portion are formed from a single conductive contact material. |
| US10868374B2 |
Electric connector for circuit board, and producing method for electric connector for circuit board
An electric connector for a circuit board includes a housing including a reception part, a plurality of metal members, and a movable member that is movable relative to the housing. The movable member includes a movement restricted part. The metal members include a rolled surface that is parallel to a connector width direction and an exposed part that is exposed from the housing. The rolled surface of the exposed part faces the movement restricted part and the exposed part includes a movement restricting part that restricts movement of the movement restricted part. The connector includes a housing part for housing the movement restricted part and the movement restricting part. |
| US10868369B2 |
Antenna module
A base part (110) has one main surface (111) that is spherically curved so as to protrude outward and another main surface (112) that is flat. A plurality of antenna elements (130) are provided along the one main surface (111) inside the base part (110). A plurality of connection wiring lines (150) connect the plurality of connection terminals (120) and the plurality of antenna elements (130) to each other. A part of each of the plurality of connection wiring lines (150) disposed in a region where a ground wiring line (140) is provided extends in a direction perpendicular to the other main surface (112) when viewed in a direction perpendicular to the other main surface (112). |
| US10868353B2 |
Electronic device and manufacturing method thereof
An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface. |
| US10868347B2 |
Battery module including a cooling plate with embedded cooling tubes
A battery module includes a plurality of secondary battery cells; one or more cooling tubes formed of a metal material; and a cooling plate formed of casted aluminum, the cooling plate being cast around the one or more cooling tubes, the one or more cooling tubes being molded within the cooling plate. |
| US10868345B2 |
Battery module and use of such a battery module
A battery module comprising at least one battery cell (2), in particular a lithium-ion battery cell, and a cooling plate (3) thermally conductively connected to the at least one battery cell (2), a thermal compensation layer (4) configured in order to increase the thermal conductivity between the at least one battery cell (2) and the cooling plate (3) furthermore being arranged between the at least one battery cell (2) and the cooling plate (3), wherein the thermal compensation layer (4) is formed from a base material (5), and furthermore comprises at least one bimetallic actuator (6), which has a conversion temperature above a temperature of 20° C. |
| US10868344B2 |
Entropy driven thermal and electrical management
A capacitor is configured to be in thermal contact with an electrical load. A controller is configured to charge and discharge the capacitor to change a temperature of the capacitor. The controller is configured to selectively discharge the capacitor at a discharge current at which entropic cooling of the capacitor is greater than Joule heating of the capacitor to provide cooling for the electrical load. |
| US10868342B2 |
Charge and discharge control device, charge and discharge control method, battery pack, electronic equipment, electric vehicle, power tool and power storage system
A charge and discharge control device is provide. The charge and discharge control device includes a determination circuitry configured to determine an ion diffusion rate associated with electric conduction in a secondary battery, and determine a time integrated value of an overcharged amount of an active material based on the ion diffusion rate and a charge condition; an evaluation circuitry configured to evaluate the charge condition of the secondary battery based on a determination result obtained by the determination circuitry; and a charge and discharge controller configured to control state of current application and voltage application to the secondary battery at a time of charging or discharging the secondary battery based on an evaluation result obtained by the evaluation circuitry. |
| US10868339B2 |
Aqueous electrolytes with bis(fluorosulfonyl)imide salt electrolyte and ionic liquid system and batteries using the electrolyte system
An aqueous electrolyte composition suitable for a lithium secondary battery is provided. The aqueous electrolyte composition contains water; lithium bis(fluorosulfonyl) imide (LiFSI); and an ionic liquid comprising an organic cation and a bis(fluorosulfonyl) imide anion (FSI); wherein the ionic liquid is a liquid at 20° C. A lithium secondary battery containing the aqueous electrolyte and a vehicle at least partially powered by the battery are also provided. |
| US10868333B2 |
Electrolytes for lithium batteries
An electrochemical cell includes a cathode active material, lithium metal, a separator, and an electrolyte including a lithium salt and a fluorinated glycol ether. |
| US10868332B2 |
Modified ionic liquids containing phosphorus
The present disclosure is directed to a phosphorus-modified ionic liquid compound, the synthesis thereof and an electrochemical cell electrolyte containing the phosphorus-modified ionic liquid compound. |
| US10868329B2 |
All solid state secondary battery, solid electrolyte composition used therefor, electrode sheet for battery using the same, and method for manufacturing electrode sheet for battery and all solid state secondary battery
To provide an all solid state secondary battery capable of realizing favorable bonding properties and a favorable ion conductivity.Provided is an all solid state secondary battery having a structure in which an electrode layer is located between a collector and an inorganic solid electrolyte layer, in which the electrode layer contains an inorganic solid electrolyte having a conductivity of ions of metals belonging to Group I or II of the periodic table, an active material, and a specific polymer described below,specific polymer: a polymer having at least one specific functional group selected from acidic functional groups, amide groups, or hydroxyl groups. |
| US10868327B2 |
Negative electrode for secondary battery, secondary battery, battery pack, electric vehicle, power storage system, power tool, and electronic device
A secondary battery includes a negative electrode including a plurality of first negative electrode active material particles, second negative electrode active material particles, and a negative electrode binder. The first negative electrode active material particles include a carbon material, and the second negative electrode active material particles include a silicon material. The negative electrode binder includes polyvinylidene fluoride and at least a part of the negative electrode binder is provided on a part of the surface of each of the second negative electrode active material particles. A ratio M2/M1 of an abundance M2 of the negative electrode binder on the surface and in proximity to each of the second negative electrode active material particles to an abundance M1 of the negative electrode binder on the surface and in proximity to each of the first negative electrode active material particles is larger than 1. |
| US10868316B2 |
Fuel cell system and method of controlling the same
When the fuel cell stack is operated in a state in which the air stoichiometric ratio is smaller than the predetermined value, the controller calculates the amount of retained water that has been retained in the cathode flow path of the fuel battery cell per fixed time in such a way that the calculated amount includes an extra amount therein, integrates the amount of retained water per fixed time that has been calculated in such a way that the calculated amount includes the extra amount therein, and executes air blow in the cathode flow path of the fuel battery cell when the integrated value of the amount of retained water becomes equal to or larger than the threshold. |
| US10868315B2 |
System for measuring high pressure of in-tank regulator
A system for measuring pressure of an in-tank regulator includes a direct-pipe flow path which directly communicates with an inside of a high-pressure container, a high-pressure sensor, of which a portion is movable into the direct-pipe flow path, fastened to and separated from the direct-pipe flow path, and a shut-off valve disposed on the direct-pipe flow path between the high-pressure container and the high-pressure sensor, wherein when the high-pressure sensor is separated from the direct-pipe flow path, the direct-pie flow path is sealed by the shut-off valve. |
| US10868313B2 |
Separator plate for an electrochemical system
A separator plate for an electrochemical system is described. The separator plate may have a first individual plate and a second individual plate which is connected to the first individual plate. The first individual plate may have two first channels for leading media, the first channels running next to one another, being shaped in the first individual plate and being separated from one another at least in sections by a web which is formed between the first channels. The second individual plate may have a second channel which is for leading media and is shaped in the second individual plate. The web which is formed between the first channels and the second channel which is shaped in the second individual plate are designed and arranged in a manner such that a projection of the second channel onto the first individual plate perpendicularly to the planar surface plane of the first individual plate crosses the web along a crossing region of the web. |
| US10868308B2 |
Cathode slurry for lithium ion battery
Provided herein is a lithium-ion battery cathode slurry, comprising: a cathode active material, a conductive agent, a binder material, and a solvent, wherein the cathode active material has a particle size D50 in the range from about 10 μm to about 50 μm, and wherein the slurry coated onto a current collector having a wet film thickness of about 100 μm has a drying time of about 5 minutes or less under an environment having a temperature of about 60° C. to about 90° C. and a relative humidity of about 25% to about 40%. The cathode slurry disclosed herein has homogeneous ingredient dispersion and quick drying capability for making a lithium-ion battery with high quality and consistent performance. In addition, these properties of the cathode slurry increase productivity and reduce the cost of manufacturing lithium-ion batteries. |
| US10868304B2 |
Battery having a low output voltage
An electrochemical battery cell comprising an anode having a primary anode active material, a cathode, and an ion-conducting electrolyte, wherein the cell has an initial output voltage, Vi, measured at 10% depth of discharge (DoD), selected from a range from 0.3 volts to 0.8 volts, and a final output voltage Vf measured at a DoD no greater than 90%, wherein a voltage variation, (Vi−Vf)/Vi, is no greater than ±10% and the specific capacity between Vi and Vf is no less than 100 mAh/g or 200 mAh/cm3 based on the cathode active material weight or volume, and wherein the primary anode active material is selected from lithium (Li), sodium (Na), potassium (K), magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), manganese (Mn), iron (Fe), vanadium (V), cobalt (Co), nickel (Ni), a mixture thereof, an alloy thereof, or a combination thereof. |
| US10868302B2 |
Lithium secondary battery
Disclosed is a lithium secondary battery capable of preventing the battery life from being reduced. The lithium secondary battery includes a cathode, an anode including silicon, a separator positioned between the cathode and the anode, and an electrolyte including flouoroethylene carbonate (FEC), wherein a weight ratio of the silicon to the FEC is about 0.4 to about 0.8. |
| US10868301B2 |
Rechargeable electrochemical cell
A rechargeable electrochemical battery cell with a housing, a positive electrode, a negative electrode and an electrolyte which contains SO2 and a conducting salt of the active metal of the cell, whereby at least one of the electrodes contains a binder chosen from the group: Binder A, which consists of a polymer, which is made of monomeric structural units of a conjugated carboxylic acid or of the alkali salt, earth alkali salt or ammonium salt of this conjugated carboxylic acid or a combination thereof or binder B which consists of a polymer based on monomeric styrene structural units or butadiene structural units or a mixture of binder A and B. |
| US10868298B2 |
Porous carbon nanotube microsphere and preparation method and use thereof, lithium metal-skeleton carbon composite and preparation method thereof, negative electrode, and battery
Disclosed is a porous carbon nanotube microsphere material and the preparation method and use thereof, a lithium metal-skeleton carbon composite and the preparation method thereof, a negative electrode of a secondary battery, a secondary battery, and a metal-skeleton carbon composite. The porous carbon nanotube microsphere material is spherical or spheroidal particles composed of carbon nanotubes. The spherical or spheroidal particles have an average diameter of 1 μm to 100 μm. A large number of nanoscale pores are composed of interlaced nanotubes inside the particle, and the pore size is 1 nm to 200 nm. The preparation method thereof comprises: mixing and dispersing carbon nanotubes and a solvent, and performing spray drying, to obtain the carbon nanotube microspheres. The lithium metal-skeleton carbon composite is obtained by uniformly mixing lithium metal in a melted state with a porous carbon material carrier and cooling. |
| US10868294B2 |
Positive electrode for lithium secondary battery and lithium secondary battery including same
A positive electrode for a lithium secondary battery includes a positive electrode current collector, a positive electrode active material layer, and a primer layer formed between the positive electrode current collector and the positive electrode active material layer. The primer layer includes lithium carbonate (Li2CO3) particles having two or more different particle diameters, a binder polymer, and a conductive material. The lithium secondary battery attains the overcharge cutoff voltage rapidly by virtue of the gas generated between the positive electrode current collector and the positive electrode active material layer, in an overcharged state. Thus, it is possible to ensure the safety of the lithium secondary battery. |
| US10868290B2 |
Lithium-metal batteries having improved dimensional stability and methods of manufacture
Lithium-metal batteries with improved dimensional stability are presented along with methods of manufacture. The lithium-metal batteries incorporate an anode cell that reduces dimensional changes during charging and discharging. The anode cell includes a container having a first portion and a second portion to form an enclosed cavity. The first portion is electrically-conductive and chemically-stable to lithium metal. The second portion is permeable to lithium ions and chemically-stable to lithium metal. The anode cell also includes an anode comprising lithium metal and disposed within the cavity. The anode is in contact with the first portion and the second portion. The cavity is configured such that volumetric expansion and contraction of the anode during charging and discharging is accommodated entirely therein. |
| US10868284B2 |
Safely ingestible batteries and methods
A battery for use in electronic devices and which is safely ingested into a body and a related method of making the battery. The battery includes an anode, a cathode and a quantum tunneling composite coating. The quantum tunneling composite coating covers at least a portion of at least one of the anode or the cathode and provides pressure sensitive conductive properties to the battery including a compressive stress threshold for conduction. The compressive stress threshold may be greater than a pre-determined applied stress in a digestive tract of the body in order to prevent harm if the battery is ingested. The battery may include a waterproof seal that extends between the quantum tunneling composite coating and a gasket separating the anode and cathode to inhibit the battery from short circuiting in a conductive fluid below the compressive stress threshold. |
| US10868282B2 |
Apparatus of separating flexible panel from glass substrate and method thereof
An apparatus of separating a flexible panel from a glass substrate is provided. The apparatus includes a console, a movable object fixing table, a position catcher, a lifting platform, and a suction separator. The console respectively drives the movable object fixing table and the lifting platform to move to a first position and a second position according to a real-time position of a fixed object captured by the position catcher, and an adhesive element of the suction separator tightly attaches to the flexible panel of the fixed object, drives the lifting platform to move to a direction away from the movable object fixing table, and drives the movable object fixing table to move to a direction away from the suction separator to separate the flexible panel from the glass substrate of the fixed object and fix the flexible panel on the adhesive element. |
| US10868275B2 |
Display panel and preparation method thereof
The present disclosure relates to a display panel. The display panel may include an OILED device and a package structure on the OLED device. The package structure may include a first water-oxygen absorbing layer comprising a first water-oxygen absorbing material. The first water-oxygen absorbing material may include first transition metal nanoparticles and a first metal organic framework coated on a surface of the first transition metal nanoparticles. |
| US10868272B2 |
Display device and manufacturing method thereof
A display device includes a substrate, a thin film encapsulation layer, a cover layer, and a touch unit. The substrate includes a display area including pixels, and a non-display area disposed outside the display area. The thin film encapsulation layer is disposed on the substrate. The cover layer overlaps an edge of the thin film encapsulation layer such that the cover layer is disposed on an edge of the display area and in the non-display area. The touch unit is disposed on the thin film encapsulation layer and the cover layer. The cover layer includes a light blocking material. |
| US10868266B2 |
Semiconductor thin-film and manufacturing method thereof, thin-film transistor, and display apparatus
A method for manufacturing a semiconductor thin film includes sequentially forming a first semiconductor layer, an intermediate layer, and a second semiconductor layer over a substrate. The first semiconductor layer and the second semiconductor layer can be one and another of an n-type semiconductor layer and a p-type semiconductor layer. At least one of the first semiconductor layer, the intermediate layer, or the second semiconductor layer is formed via a solution process. The n-type semiconductor layer can include indium oxide. The intermediate layer can include a self-assembly material. The p-type semiconductor layer can include a p-type organic semiconductor material, and can be pentacene. On the basis, a semiconductor thin film manufactured thereby, a semiconductor thin film transistor, and a display apparatus, are also disclosed. |
| US10868264B2 |
Electronic device with movable flexible display and operating method thereof
An electronic device is provided. The electronic device includes a flexible touchscreen layer movable between an open state and a closed state and having a periphery located at a first distance from a first sidewall in the closed state, and located at a second distance longer than the first distance from the first sidewall in the open state. When the flexible touchscreen layer is moved from the open state to the closed state, at least part of the bendable portion may be led out from a recess to construct substantially a plane. When the flexible touchscreen layer is moved from the closed state to the open state, at least part of the bendable portion may be led into the recess to expose at least one of an inner structure having various modules disposed thereon or electronic component for access and/or use. |
| US10868256B2 |
Light-emitting element, display device, electronic device, and lighting device
A light-emitting element containing a light-emitting material and having high light emission efficiency is provided. The light-emitting element includes a host material and a guest material. The host material includes at least a first molecule and a second molecule having the same molecular structure. The guest material has a function of exhibiting fluorescence or converting triplet excitation energy into light emission. The first molecule and the second molecule each include a first skeleton, a second skeleton, and a third skeleton, and the first skeleton and the second skeleton are bonded to each other through the third skeleton. The first skeleton includes at least one of a π-electron rich heteroaromatic skeleton and an aromatic amine skeleton and the second skeleton includes a π-electron deficient heteroaromatic skeleton. The first molecule and the second molecule have a function of forming an excited complex. |
| US10868254B2 |
Phosphorescent OLED and hole transporting materials for phosphorescent OLEDS
The present invention relates to phosphorescent organic light-emitting diodes (OLEDs) including a hole-transporting or a hole-transporting and an electron-blocking layer including an N,N,N′,N′-tetraaryl-phenylene-3,5-diamine or an N,N,N′,N′-tetraaryl-1,1′-biphenyl-3,3′-diamine matrix compound and to new N,N,N′,N′-tetraarylsubstituted m-arylene diamine compounds useful as hole-transporting and electron-blocking layer matrices in phosphorescent OLEDs. |
| US10868253B2 |
Process for making an organic charge transporting film
A single phase liquid formulation useful for producing an organic charge transporting film; said formulation comprising: (a) a first polymer resin having Mw less than 5,000; (b) a second polymer resin having Mw at least 7,000; (c) a first solvent having a boiling point from 50 to 165° C.; and (d) a second solvent having a boiling point from 180 to 300° C. |
| US10868251B2 |
Method for fabricating organic light emitting diode display
A method for fabricating an organic light emitting diode (OLED) display is provided. The fabricating method includes: forming a switch array layer on a base substrate; forming an organic light emitting display layer on the switch array layer; forming a thin film package layer on the organic light emitting display layer; and forming a superhydrophobic thin film on the thin film package layer using plasma chemical vapor deposition. The superhydrophobic thin film has a thickness smaller than a predetermined thickness. |
| US10868248B2 |
Tapered memory cell profiles
Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode. |
| US10868244B2 |
Multiple hard mask patterning to fabricate 20nm and below MRAM devices
A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size. |
| US10868242B2 |
Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode
A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug. |
| US10868235B2 |
Minimal thickness synthetic antiferromagnetic (SAF) structure with perpendicular magnetic anisotropy for STT-MRAM
A synthetic antiferromagnetic structure for a spintronic device is disclosed and has an FL2/Co or Co alloy/antiferromagnetic coupling/Co or Co alloy/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. Antiferromagnetic coupling is improved by inserting a Co or Co alloy dusting layer on top and bottom surfaces of the antiferromagnetic coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)n laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the synthetic antiferromagnetic structure. |
| US10868232B2 |
Piezoelectric material, manufacturing method for piezoelectric material, piezoelectric element, vibration wave motor, optical equipment, and electronic device
A piezoelectric material includes a metal oxide containing at least Ba, Ca, Ti, Zr, and Mn, in which the piezoelectric material has a perovskite structure, in which: x, which represents a ratio of a content (mol) of Ca to A (mol) representing a total content of Ba and Ca, falls within a range of 0.10≤x≤0.18; y, which represents a ratio of a content (mol) of Zr to B (mol) representing a total content of Ti, Zr, and Mn, falls within a range of 0.055≤y≤0.085; and z, which represents a ratio of a content (mol) of Mn to the B (mol), falls within a range of 0.003≤z≤0.012, and in which the piezoelectric material satisfies a relationship of 0≤(|d31(−20u)−d31(−20d)|)/|d31(−20u)|≤0.08, and has a value of 130 pm/V or more for each of |d31(−20u)| and |d31(−20d)|. |
| US10868230B2 |
Thermoelectric conversion module and manufacturing method thereof
Provided is a thermoelectric conversion module having a high heat resistance. The thermoelectric conversion module includes a first substrate, a second substrate, a thermoelectric element, and a bonding layer. The first substrate includes a first metalized layer. The second substrate includes a second metalized layer which faces the first metalized layer. The thermoelectric element includes a chip formed from a thermoelectric material and is arranged between the first metalized layer and the second metalized layer. The bonding layer is composed of a sintered body of a metallic material of which the average crystal particle diameter is no greater than 20 μm and bonds the first metalized layer and the second metalized layer with the thermoelectric element. |
| US10868226B2 |
LED light bulb having filament with conductor pratly overlapping with LED chip
An LED light bulb, consisting of: a lamp housing; a bulb base connected to the lamp housing; a stem connected to the bulb base and located in the lamp housing, the stem comprises a stand extending to the center of the lamp housing; a single LED filament, disposed in the lamp housing, the LED filament comprising: a plurality of LED sections, each of the LED sections includes at least two LED chips that are electrically connected to each other by a wire; a plurality of conductive sections, each of the conductive sections is located between the two adjacent LED sections and configured to electrically connect the two adjacent LED sections, each of the conductive section includes a conductor connecting the LED sections, and length of the wire being less than that of the conductor, the conductor comprises joint region and transition regions, the joint region is located between the transition regions and configured to connect the transition regions, wherein taking the central point of the LED chip as the center, the shortest distance from the center to the closest boundary of the joint region is set to r1, and the shortest distance from the center to the closest boundary of the transition region is set to r2, where the distance r1 is greater than or equal to the distance r2; two conductive supports, a driving circuit, electrically connected with both the two conductive supports and the bulb base; and a plurality of supporting arms. |
| US10868224B2 |
Wavelength converted light emitting device
Embodiments of the invention include a semiconductor structure comprising a light emitting layer. The semiconductor structure is attached to a support such that the semiconductor structure and the support are mechanically self-supporting. A wavelength converting material extends over the sides of the semiconductor structure and the support, wherein the wavelength converting material has a substantially uniform thickness over the top and sides of the semiconductor structure and the support. |
| US10868223B2 |
Optoelectronic component
An optoelectronic component includes a semiconductor chip that emits primary radiation from the blue spectral region, a conversion element including at least three phosphors each converting the primary radiation into secondary radiation, wherein the first phosphor emits secondary radiation from the green spectral region, the second phosphor emits secondary radiation from the red spectral region, the third phosphor is a potassium-silicon-fluoride phosphor that emits secondary radiation from the red spectral region, and the component has an Ra value of at least 80 and an R9 value of at least 75, and emits white mixed radiation. |
| US10868222B2 |
Method of manufacturing gallium nitride quantum dots
Provided is a method of manufacturing gallium nitride quantum dots. The method includes the steps of: preparing a gallium precursor solution by heating a mixture prepared by dissolving a gallium halide and an organic ligand in a solvent; heating the gallium precursor solution to obtain a heated gallium precursor solution; hot-injecting a nitrogen precursor into the heated gallium precursor solution at a heating temperature to produce gallium nitride; growing the gallium nitride while maintaining the heating temperature, thereby producing a growth-completed gallium nitride; and cooling a solution including the growth-completed gallium nitride to produce gallium nitride quantum dots in a colloid state. |
| US10868220B2 |
Multiple LED light source lens design in an integrated package
Light emitting diode (LED) packages and LED displays utilizing the LED packages are disclosed. LED packages can have a plurality of cavities with each having one or more LEDs. The LEDs can be individually controllable so that the LED package emits the desired color combination of light from the package. The LED packages are arranged with an encapsulant over the cavities that shape the LED package emission to a wide angle or pitch. Some of the LED packages can have three cavities, while others can have four or more cavities. The packages can comprise an encapsulant that forms lenses over the cavities and continues beyond the cavities to cover surfaces of the LED package body. The body can include different anchoring features to improve package reliability by anchoring the encapsulant to the body. One embodiment of an LED display according to the present invention comprises a plurality of LED packages, at least some having a plurality of cavities. Each of the packages comprises a lens over each cavity to produce an emission of the LEDs that has a wider angle compared to the emission without the lens. A potting material can be included between adjacent ones of the LED packages and overlaps the package encapsulant to further improve reliability. |
| US10868215B2 |
Ultraviolet light emitting diode
An ultraviolet light-emitting diode includes: a substrate; an n-type semiconductor layer located on the substrate; a mesa arranged on the n-type semiconductor layer and including an active layer and a p-type semiconductor layer; an n-ohmic contact layer coming in contact with the n-type semiconductor layer; a p-ohmic contact layer coming in contact with the p-type semiconductor layer; an n-bump electrically connected to the n-ohmic contact layer; and a p-bump electrically connected to the p-ohmic contact layer, wherein the mesa includes a main branch and a plurality of sub branches extending from the main branch, the n-ohmic contact layer encompasses the mesa and is interposed in an area between the sub branches, and the n-bump and the p-bump respectively cover the upper part and sides of the mesa. Therefore, an optical output can be increased by reducing light loss, and a forward voltage can be lowered. |
| US10868212B2 |
Epitaxial formation structures and associated methods of manufacturing solid state lighting devices
Epitaxial formation structures and associated methods of manufacturing solid state lighting (“SSL”) devices with target thermal expansion characteristics are disclosed herein. In one embodiment, an SSL device includes a composite structure having a composite CTE temperature dependency, a formation structure on the composite structure, and an SSL structure on the formation structure. The SSL structure has an SSL temperature dependency, and a difference between the composite CTE and SSL temperature dependencies is below 3 ppm/° C. over the temperature range. |
| US10868207B1 |
Photodetector systems with low-power time-to-digital converter architectures to determine an arrival time of photon at a photodetector based on event detection time window
An exemplary photodetector system includes a photodetector and a time-to-digital converter (TDC) coupled to the photodetector. The TDC is configured to receive, during a predetermined event detection time window that commences in response to an application of a light pulse to a target, a signal triggered by an event in which the photodetector detects a photon of the light pulse after the light pulse reflects from the target. The TDC is further configured to enable, in response to the receiving the signal, a gated ring oscillator (GRO) of the TDC, measure, using the GRO, a time interval between when the event occurred and an end of the predetermined event detection time window, and determine, based on the time interval and the predetermined event detection time window, an arrival time of the photon at the photodetector. |
| US10868201B1 |
Front-side conductive paste for crystalline silicon solar cell, preparation method therefor, and solar cell
A front-side conductive paste for a crystalline silicon solar cell is provided. The front-side conductive paste for a crystalline silicon solar cell includes, in parts by weight, 80.0-93.0 parts of a metal powder, 6.0-15.0 parts of an organic carrier, and 1.0-5.0 parts of an oxide etching agent, where based on 100% by mole of the oxide etching agent, the oxide etching agent includes 15-30% of PbO; 25-40% of TeO2; 8.0-15.0% of Li2O; 9.0-20.0% of SiO2; 5.0-15.0% of Bi2O3; 0.5-10.0% of ZnO; and either one or both of 0.1-10.0% of MgO and 0.1-10.0% of CaO; and no more than 5.0% of an oxide of additional metal elements. The metal powder forms good ohmic contact with crystalline silicon substrate during the sintering process of the front-side conductive paste applied overlying an insulation film on the substrate. Finally, a front-side electrode of low contact resistance, good electrical conductivity, and strong adhesion is obtained. |
| US10868199B2 |
Standard integrated cell with capacitive decoupling structure
A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes a capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor. |
| US10868189B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, at least one active region, at least one gate structure, and an insulating structure. The active region is present at least partially in the substrate. The gate structure is present on the active region. The gate structure has at least one end sidewall and a top surface intersecting to form a top interior angle. The top interior angle is an acute angle. The insulating structure is present adjacent to the end sidewall of the gate structure and on the substrate. |
| US10868188B2 |
Semiconductor device and method
A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure. |
| US10868187B2 |
Method of forming embedded source or drain region of transistor with laterally extended portion
In some embodiments, in a method, a body structure with a gate structure configured thereon is provided. The gate structure comprises a gate side wall traversing the body structure. A spacer is formed over the gate side wall. A first recess is formed in the body structure. The first recess is formed beside the spacer and extending laterally under the spacer. A recess extension is formed under the first recess to extend a vertical depth of the first recess. Stressor material with a lattice constant different from that of the body structure is grown such that the extended first recess is filled. |
| US10868181B2 |
Semiconductor structure with blocking layer and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure. |
| US10868176B2 |
Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process
A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences. |
| US10868175B2 |
Method for manufacturing semiconductor structure
Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure. The method includes forming a recess in a substrate and forming an epitaxy region, comprising a multilayer structure with a substance having a first lattice constant larger than a second lattice constant of the substrate. Forming the epitaxy region further includes forming a first layer in proximity to an interface between the epitaxy region and the substrate with an average concentration of the substance from about 20 to about 32 percent by an in situ growth, and forming a second layer over the first layer, a bottom portion of the second layer having a concentration of the substance from about 27 percent to about 37 percent by an in situ growth operation. |
| US10868171B2 |
Semiconductor device structure with gate dielectric layer and method for forming the same
A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer over an inner wall and a bottom of the trench. The method includes forming a mask layer over the gate dielectric layer over the bottom. The method includes removing the gate dielectric layer over the inner wall. The method includes removing the mask layer. The method includes forming a gate electrode in the trench. |
| US10868170B2 |
Layout for needle cell trench MOSFET
A power semiconductor die conducts a load current between front and back side load terminals. The die includes an active region with a plurality of columnar trench cells. Each columnar trench cell includes: a section of a drift zone, a section of a channel zone and a section of a source zone, the channel zone section being electrically connected to the front side load terminal and isolating the source zone section from the drift zone section; and a control section with at least one control electrode in a control trench. An edge termination region between the die edge and the active region includes a front side zone configured to have an electrical potential different from an electrical potential of the front side load terminal. An isolating trench structure is arranged between the front side zone and the channel zone which is electrically connected to the front side load terminal. |
| US10868168B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a gate insulating film, and a gate electrode. A threshold voltage of the semiconductor device is higher than forward voltage of a built-in PN diode constituted by the second semiconductor layer, the semiconductor substrate, and the first semiconductor layer. Thus, when high electric potential is applied to a source electrode and the built-in PN diode is driven, the generation of crystal effects may be suppressed. |
| US10868167B2 |
Semiconductor device
A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire. |
| US10868163B2 |
Semiconductor device
A semiconductor device includes first and second nitride semiconductor layers, a first electrode electrically connected to the first nitride semiconductor layer, a second electrode electrically connected to the first nitride semiconductor layer, a gate electrode between the first and second electrodes, a first field plate electrode electrically connected to the first electrode, a second field plate electrode between the gate electrode and the second electrode and electrically connected to the first electrode, a first conductive layer on the gate electrode, and a second conductive layer on the first conductive layer. A distance between the gate electrode and the second field plate electrode in a lateral direction is shorter than a distance between the first conductive layer and the second field plate electrode in the lateral direction, and is equal to or shorter than a distance between the second conductive layer and the second field plate electrode. |
| US10868162B1 |
Self-aligned gallium nitride FinFET and method of fabricating the same
A self-aligned GaN FinFET device and a method of fabricating the same are disclosed. This self-aligned process helps to fabricate GaN FinFET devices in a scalable manner. This work transforms the T-gate process to incorporate fins to further improve pinch-off and decrease leakage currents on highly scaled GaN HEMT structures. The GaN FinFET structure will also allow for integration of normally-off devices with normally-on devices by varying the fin width. The FinFET improvement combines the fin structure consisting of various fin pitches and widths, gate dielectric, self-aligned gate design, ultra-low ohmic contacts, and vertically scaled epitaxy into a single scalable process. |
| US10868161B2 |
Low resistance source/drain regions in III-V transistors
Low resistance source/drain regions in III-V transistors are disclosed. More particularly, a source and a drain are formed from heavily doped III-V materials that have lower resistances than a barrier layer and/or a cap layer under the drain. In an exemplary aspect, the barrier and cap layers are formed over a mobility channel layer and then etched to form source and drain recesses. A source and a drain are then epitaxially grown in the recesses. The source and the drain may include one or more layers, with the top layer having the lowest bandgap, thus helping to lower contact resistance. By lowering the resistance of the source and the drain, the overall resistance of the transistor may be lowered to allow for operation at higher frequencies. |
| US10868160B2 |
Neuromorphic devices and circuits
Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively. |
| US10868158B2 |
Charge storage and sensing devices and methods
Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode. |
| US10868156B2 |
Method of forming epitaxial silicon layer and semiconductor device thereof
A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, wherein a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer having a first sidewall adjacent to the gate structures and a first central portion; and, in the chamber, shaping the epitaxial silicon-rich layer to form a second sidewall adjacent to the gate structures and a second central portion, wherein a first height difference between the first sidewall and the first central portion is greater than a second height difference between the second sidewall and the second central portion. |
| US10868155B2 |
Compound semiconductor device
A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening. |
| US10868152B2 |
Semiconductor device and semiconductor device manufacturing method
A semiconductor device including a memory cell, the semiconductor device including: a floating gate provided at a semiconductor substrate with a first insulation film inbetween, and including a pointed portion having a pointed end at one end side; a spacer provided at the floating gate; a second insulation film provided between the floating gate and the spacer and that covers a side surface of the spacer at the one end side; and a control gate that contacts a side surface of the floating gate at the one end side via a third insulation film and that contacts the side surface of the spacer at the one end side via the second insulation film and the third insulation film. |
| US10868141B2 |
Spacer structure and manufacturing method thereof
A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure. |
| US10868134B2 |
Method of making transistor having metal diffusion barrier
A channel layer is grown over a substrate, and an active layer is grown over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A dielectric layer is deposited over the active layer, and the dielectric layer is patterned to expose a portion of the active layer. A metal diffusion barrier is formed over the exposed portion of the active layer, and a gate is deposited over the metal diffusion barrier. |
| US10868131B2 |
Gaseous spacer and methods of forming same
A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack. |
| US10868130B2 |
Semiconductor device and method of manufacture
A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening. |
| US10868128B2 |
Ohmic contact structure, semiconductor device including an ohmic contact structure, and method for forming the same
Semiconductor contact structures, a semiconductor device including the semiconductor contact structures, and a method for forming the same are disclosed. In an embodiment, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, the interface layer including titanium (Ti), the interface layer contacting the channel layer; and a contact metal layer over the interface layer, the contact metal layer including aluminum silicon copper alloy (AlSiCu). |
| US10868120B1 |
Method for making a varactor with hyper-abrupt junction region including a superlattice
A method for making a semiconductor device may include forming a hyper-abrupt junction region on a substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a first contact coupled to the hyper-abrupt junction regions, and forming a second contact coupled to the substrate to define a varactor. |
| US10868114B2 |
Isolation structures of semiconductor devices
The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages. |
| US10868112B2 |
Circuit device including guard ring and method of forming guard ring
A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance. |
| US10868100B2 |
Display panel and display device
A display panel and a display device are provided. The display panel comprises a display area including a first display area and a second display area arranged in a row direction, and the first display area includes at least one notch; and a non-display area surrounding the display area. The non-display area includes a first non-display area and a second non-display area, and along the row direction, the first non-display area and the second non-display area are respectively disposed at two opposite sides of the display area. The first non-display area include a first driving circuit, which includes a plurality of cascaded first shift registers, and the second non-display area includes a second driving circuit, which includes a plurality of cascaded second shift registers. The display panel includes a first driving unit and a second driving unit. |
| US10868096B2 |
Display device
A display device includes: a substrate; an inorganic insulating layer arranged in a display region, the inorganic insulating layer having a lower valley as an opening or a groove arranged in a region between a first pixel circuit and a second pixel circuit adjacent to each other; a first organic planarization layer arranged over entire regions of the first pixel circuit and the second pixel circuit, the first organic planarization layer filling the lower valley; and a connection wire arranged on the first organic planarization layer, the connection wire connecting the first pixel circuit to the second pixel circuit. |
| US10868094B2 |
Display device
A display device includes a substrate, a plurality of pixel electrode over the substrate, a bank covering an end portion of the pixel electrode and exposing a part of the pixel electrode, an organic layer over the pixel electrode and the bank, and a common electrode over the organic layer. The bank includes an inclined surface in a portion covering the end portion of the pixel electrode. An angle between the inclined surface of the bank and an upper surface of the pixel electrode is equal to or larger than 85 degrees. A thickness of the organic layer disposed on the inclined surface of the bank in a direction perpendicular to the inclined surface of the bank is equal to or smaller than 1/10 of a thickness of the organic layer disposed on the pixel electrode in a direction perpendicular to the upper surface of the pixel electrode. |
| US10868092B2 |
Display device having dummy and reflective regions
A display device includes a substrate, a thin film transistor on the substrate, an interlayer insulating layer on the thin film transistor, an electrode on the interlayer insulating layer, the electrode including an emission region, a contact region overlapping the thin film transistor, and a dummy region protruding from the emission region in a direction different from the contact region, and an emission layer on the electrode, the emission region of the electrode overlapping the emission layer. |
| US10868088B2 |
Display device
A display device is provided. The display device includes a substrate including an active region in which a plurality of pixels are arranged; a first electrode layer disposed on the substrate and including a first electrode disposed in each pixel and an auxiliary electrode spaced apart from the first electrode and disposed along a boundary of each pixel; an intermediate layer disposed on the first electrode and including a light emitting layer; and a second electrode disposed on the intermediate layer, disposed in each pixel, and electrically connected to the auxiliary electrode; wherein a plurality of unit pixel groups, each including one or more pixels, are defined on the substrate, the respective second electrodes of the pixels belonging to each unit pixel group are electrically connected to each other by the auxiliary electrode, and the auxiliary electrodes belonging to different unit pixel groups are electrically separated from each other. |
| US10868087B2 |
Method for manufacturing a cathode isolation retaining wall, a display panel and manufacturing method thereof
The disclosure provides a method for manufacturing cathode isolation retaining walls, display panel and manufacturing method thereof. A method for manufacturing a cathode isolation retaining wall, including exposing a first photoresist layer formed on an anode layer to obtain a first isolation retaining wall portion. The method includes forming a second photoresist layer on a side of the first photoresist layer away from the anode layer. After exposing the second photoresist layer, a second isolation retaining wall portion at least partially stacked with the first isolation retaining wall portion is obtained. The method includes developing the first photoresist layer and the second photoresist layer to obtain a cathode isolation retaining wall composed of the first isolation retaining wall portion and the second isolation retaining wall portion. |
| US10868084B2 |
Foldable display panel
A foldable display panel is provided. The foldable display panel includes a foldable area and two non-foldable areas. The foldable display panel further includes at least two pixel units. Each of the pixel units includes three sub-pixels. A pattern of the sub-pixel in the foldable area is elliptical or is curved quadrilateral. A pattern of the sub-pixel in the non-foldable area is a rhombus. An ability of the sub-pixels located in the foldable area 100 to withstand stress during a bending process is enhanced. Detachment of an electroluminescent layer or a thin film encapsulation layer located in the foldable area is prevented, thereby a reliability of a display device is ensured and a quality of the product is improved. |
| US10868083B2 |
Anti-reflective optical film and bendable display apparatus including the optical film
A display apparatus includes a display panel configured to display an image. The display panel has a folding axis extending in a first direction. An optical film is disposed over the display panel. The optical film includes a circular polarizer including at least two phase retarders and one polarizer. Slow axes of each of the at least two phase retarders are located in the same quadrant of four quadrants of the optical film. |
| US10868077B2 |
Thermoelectric apparatus and applications thereof
In some embodiments, thermoelectric apparatus and various applications of thermoelectric apparatus are described herein. In some embodiments, a thermoelectric apparatus described herein comprises at least one p-type layer coupled to at least one n-type layer to provide a pn junction, and an insulating layer at least partially disposed between the p-type layer and the n-type layer, the p-type layer comprising a plurality of carbon nanoparticles and the n-type layer comprising a plurality of n-doped carbon nanoparticles. |
| US10868074B2 |
Detector module, detector, imaging apparatus and method of manufacturing a detector module
The present invention relates to a detector module comprising a direct conversion crystal (10) for converting incident photons into electrical signals, said direct conversion crystal having a cathode metallization (100) deposited on a first surface and an anode metallization (101) deposited on a second surface, an integrated circuit (12) in electrical communication with said direct conversion crystal, said integrated circuit having a smaller width than said direct conversion crystal thus forming a recess (120) in width direction at a side surface of the integrated circuit, an interposer (11, 11a) arranged between said direct conversion crystal and said integrated circuit for providing electrical communication there between, wherein said interposer is made as separate element that is glued, soldered or bonded with the anode metallization (101) of said direct conversion crystal facing said integrated circuit, and a multi-lead flex cable (13, 13a, 13b, 13c, 13d) providing a plurality of output paths, said multi-lead flex cable having a first portion (131, 131a, 131b, 131c, 13 Id) connected with one surface to said direct conversion crystal and with the opposite surface to said integrated circuit (12) and a second portion (132), which is bent with respect to the first portion and is arranged in said recess. |
| US10868072B2 |
Semiconductor structure and image sensor
A semiconductor structure includes a substrate having a front surface and a back surface. The semiconductor structure further includes a first isolation structure extending from the front surface into the substrate, the first isolation structure having a depth D1 from the front surface. The semiconductor structure further includes a second isolation structure extending from the front surface into the substrate, the second isolation structure having a depth D2 from the front surface. The semiconductor structure further includes a first etching stop feature in the substrate and contacting the first isolation structure. The semiconductor structure further includes a second etching stop feature in the substrate and contacting the second isolation structure. |
| US10868071B2 |
Method for forming semiconductor image sensor
A method for forming a semiconductor image sensor includes: providing a first substrate including a first front side and a first back side opposite to the first front side, and the first substrate including a plurality of first sensing devices; bonding the first substrate to a second substrate including a second front side and a second back side opposite to the second front side with the first front side of the first substrate facing the second front side of the second substrate; disposing an insulating structure over the first back side of the first substrate, wherein the insulating structure includes a plurality of dielectric grating patterns; and bonding the first substrate to a third substrate including a third front side and a third back opposite to the third front side, and the third substrate including a plurality of second sensing devices. |
| US10868063B2 |
Surface treatment for BSI image sensors
A method comprises forming an image sensor adjacent to a first side of a substrate, thinning a second side of the substrate, performing a halogen treatment on the second side of the substrate and forming a backside illumination layer on the second side of the substrate. |
| US10868061B2 |
Packaging structure for a sensor having a sealing layer
According to an aspect, a sensor packaging structure includes a sensor die having a first surface and a second surface opposite the first surface, where the sensor die defines a sensor edge disposed between the first surface and the second surface. The sensor packaging structure includes a bonding material having a first surface and a second surface opposite the second surface, where the bonding material defines a bonding material edge disposed between the first surface of the bonding material and the second surface of the bonding material. The sensor packaging structure includes a transparent material, where the bonding material couples the sensor die to the transparent material. The sealing material is disposed on an interface between the sensor die and the bonding material, and at least one of a portion of the sensor edge or a portion of the bonding material edge. |
| US10868060B2 |
Photoelectric detection substrate, method for fabricating the same, and photoelectric detection device
A photoelectric detection substrate, a method for fabricating the same, and a photoelectric detection device are disclosed. The photoelectric detection substrate includes a thin film transistor and a photodiode coplanar with the thin film transistor. The thin film transistor has a vertical channel structure and includes a gate electrode, an active layer, a first electrode and a second electrode. The photodiode includes a first doped layer, an absorption layer and a second doped layer disposed in this order. The active layer and the absorption layer are disposed in a same layer and formed by a same patterning process. By forming a photodiode coplanar with a thin film transistor of a vertical channel structure, the overall thickness of the photoelectric detection substrate is effectively reduced, deformation of the substrate caused by stress is reduced, and damage caused by deformation of the substrate is avoided, and thereby the yield is improved. |
| US10868059B2 |
Image sensors for distance measurement
An image sensor includes a semiconductor substrate including a first surface and a second surface and further includes a well region and a first floating diffusion region that are each adjacent to the first surface. The image sensor includes a first vertical transmission gate and a second vertical transmission gate isolated from direct contact with each other and each extend from the first surface of the semiconductor substrate and in a thickness direction of the semiconductor substrate through at least a portion of the well region. The image sensor includes a first storage gate between the first vertical transmission gate and the first floating diffusion region and on the first surface of the semiconductor substrate. The image sensor includes a first tap transmission gate between the first storage gate and the first floating diffusion region and on the first surface of the semiconductor substrate. |
| US10868045B2 |
Transistor, semiconductor device, and electronic device
To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device. By covering a side surface of an oxide semiconductor layer in which a channel is formed with an oxide semiconductor layer, diffusion of impurities into the inside from the side surface of the oxide semiconductor layer is prevented. By forming a gate electrode in a damascene process, miniaturization and high density of a transistor are achieved. By providing a protective layer covering a gate electrode over the gate electrode, the reliability of the transistor is increased. |
| US10868044B2 |
Active layer, thin-film transistor array substrate comprising the same, and display device comprising the same
Carbon allotropes, a thin-film transistor array substrate comprising the same, and a display device comprising the same are disclosed. The thin-film transistor array substrate comprising a substrate, a gate electrode on the substrate, a gate insulating film on the gate electrode, an active layer positioned on the gate insulating film and comprising a semiconductor material and a plurality of carbon allotropes, and a source electrode and a drain electrode that make contact with the active layer. |
| US10868042B1 |
Ferroelectric memory device containing word lines and pass gates and method of forming the same
A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines. |
| US10868041B2 |
3D semiconductor devices including a supporter and methods of forming the same
A semiconductor device comprises a lower conductive layer on a substrate. A conductive line is on the lower conductive layer. A buried trench in the conductive line is provided. A supporter which is on the conductive line and extends in the buried trench is provided. A stack structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked is on the supporter. A channel structure passing through the stack structure, the supporter, and the conductive line is provided. An isolation trench passing through the stack structure, the supporter, and the conductive line is provided. |
| US10868032B2 |
Dielectric extensions in stacked memory arrays
In an example of forming a stacked memory array, a stack of alternating first and second dielectrics is formed. A dielectric extension is formed through the stack such that a first portion of the dielectric extension is in a first region of the stack between a first group of semiconductor structures and a second group of semiconductor structures in a second region of the stack and a second portion of the dielectric extension extends into a third region of the stack that does not include the first and second semiconductor structures. An opening is formed through the first region, while the dielectric extension couples the alternating first and second dielectrics in the third region to the alternating first and second dielectrics in the second region. |
| US10868029B2 |
Staggered semiconductor memory device
According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction. |
| US10868024B2 |
Method of forming embedded nonvolatile memory
A method includes forming first and second gate stacks over a substrate. Each of the first and second gate stacks includes a tunneling dielectric layer, a floating gate over the tunneling dielectric layer, a middle dielectric layer over the floating gate, and a control gate over the middle dielectric layer. A conductive layer is formed over the first and second gate stacks. The conductive layer is etched to form a erase gate between the first and second gate stacks. Etching the conductive layer is performed such that a top surface of the erase gate is not higher than a top surface of the control gate and such that the top surface of the erase gate is at least partially curved inwards. |
| US10868023B2 |
Non-volatile memory array
A non-volatile memory array includes gate structures disposed on a substrate, each of the gate structures including a tunneling oxide layer positioned on the substrate, a floating gate positioned on the tunneling oxide layer and being arranged along a first direction on the tunneling oxide layer, sidewall gates disposed on sidewalls of the floating gate, extending in the first direction and being spaced apart from each other, and a gate dielectric layer interposed between the floating gate and the sidewall gates, bit lines disposed over the substrate, each extending in a second direction to intersect the sidewall gates, a drain region positioned in an upper portion of the substrate, the drain region overlapping, and being electrically connected to, the one of the bit lines, and a source line positioned between adjacent sidewall gates, the source line extending in the first direction and being buried in the substrate. |
| US10868019B2 |
Semiconductor device having strap cell
A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions. |
| US10868018B2 |
SRAM structure and connection
A semiconductor structure includes SRAM cells, bit-line edge cells, and word-line edge cells, wherein the SRAM cells are arranged in an array, bordered by the bit-line edge cells and the word-line edge cells, each of the SRAM cells including two inverters cross-coupled together and a pass gate coupled to the two inverters, and the pass gate includes a FET; a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to a drain feature of the FET; a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer; and a second bit-line of a third metal material, electrically connected to the first bit-line, and disposed in a third metal layer. The first metal material and the third metal material are different from each other in composition. |
| US10868016B2 |
Semiconductor memory device and method of fabricating the same
A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench. |
| US10868007B2 |
Semiconductor device
A semiconductor device is provided. The semiconductor device includes a field insulating film on a substrate, a first fin type pattern which is formed on the substrate and protrudes upward from an upper surface of the field insulating film, and a gate electrode which intersects with the first fin type pattern on the field insulating film and includes a first portion and a second portion, the first portion being located on one side of the first fin type pattern and including a first terminal end of the gate electrode, and the second portion being located on the other side of the first fin type pattern, wherein a height from the substrate to a lowest part of the first portion is different from a height from the substrate to a lowest part of the second portion. |
| US10868006B2 |
FinFET transistor with fin back biasing
A method of forming a semiconductor device includes forming a fin protruding from a substrate, the fin having a channel region, a source/drain (S/D) region, and a biasing region, wherein the channel region and the biasing region sandwich the S/D region. The method further includes trimming the biasing region to reduce a height of the biasing region and forming a gate structure engaging the channel region. The method also includes forming a conductive feature electrically coupling to the biasing region. |
| US10868000B2 |
Semiconductor device structure with epitaxial structure and method for forming the same
A method for forming a semiconductor device structure is provided. The method includes forming a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The method includes forming a dielectric layer over the first epitaxial structure, the second epitaxial structure, and the semiconductor substrate. The method includes forming a first mask layer over the dielectric layer and between the first epitaxial structure and the second epitaxial structure. The method includes forming a second mask layer over the dielectric layer and the first mask layer. The method includes partially removing the dielectric layer covering the first epitaxial structure and the second epitaxial structure. The method includes removing the first mask layer. The method includes forming a first conductive layer and a second conductive layer respectively in the first recess and the second recess. |
| US10867999B2 |
Semiconductor device and method of forming the same
A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first well and a first dummy cell region. The substrate has a plurality fins disposed therein, and the fins are extended along a first direction. The first well is disposed in the substrate, and a dummy cell region is disposed at a first boundary of the first well. The first dummy cell region includes a first isolation structure and a plurality of first gate structures. The first SDB is disposed in the substrate, along a second direction perpendicular to the first direction to penetrate through one of the fins, and the first gate structures are disposed over the first SDB. |
| US10867993B2 |
Touch sensing circuits and methods for detecting touch events
A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness. |
| US10867990B2 |
Series resistor over drain region in high voltage device
Some embodiments relate to a method. In the method, a semiconductor substrate is provided. Dopant impurities of a first dopant conductivity are implanted into the semiconductor substrate to form a body region. A gate dielectric and a field oxide region are formed over the semiconductor substrate. A polysilicon layer is formed over the gate dielectric and field oxide region. The polysilicon layer is patterned to concurrently form a conductive gate electrode over the gate dielectric and a resistor structure over the field oxide region. The resistor structure is perimeterally bounded by an inner edge of the conductive gate electrode. Dopant impurities of a second dopant conductivity, which is opposite the first dopant conductivity, are implanted into the semiconductor substrate to form a source region and a drain region. The drain region is perimeterally bounded by the inner edge of the conductive gate electrode. |
| US10867988B2 |
Integrated ESD enhancement circuit for SOI device
The present disclosure relates to an integrated circuit. The integrated circuit comprises a silicon on insulator (SOI) device separated from a SOI substrate by an insulation layer. The SOI device comprises a power supply terminal, a ground terminal, a first I/O terminal and a second I/O terminal. An electrostatic discharge (ESD) protection circuit is integrated with the SOI device. The ESD protection circuit is configured to shunt current between two terminals of the SOI device during an ESD surge event. An electrostatic discharge (ESD) enhancement circuit is integrated with the SOI device. The ESD enhancement circuit is configured to clamping the SOI substrate to a lower potential of the two terminals of the SOI device. |
| US10867984B2 |
Method of manufacturing a package-on-package type semiconductor package
A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof. |
| US10867983B2 |
Three-dimensional memory device and fabrication method thereof
Methods and structures of a three-dimensional memory device are disclosed. In an example, the method for forming a memory device includes the following operations. First, a plurality of first semiconductor channels can be formed over a first wafer with a peripheral device and a plurality of first via structures neighboring the plurality of first semiconductor channels. The plurality of first semiconductor channels can extend along a direction perpendicular to a surface of the first wafer. Further, a plurality of second semiconductor channels can be formed over a second wafer with a plurality of second via structures neighboring the plurality of second semiconductor channels. The plurality of second semiconductor channels can extend along a direction perpendicular to a surface of the second wafer and a peripheral via structure. |
| US10867980B2 |
Semiconductor equipment
Semiconductor equipment includes semiconductor modules sealed with a resin, each having first and second connection terminals exposed from the resin, a capacitor including third and fourth connection terminals, a cooler directly contacting the semiconductor modules and the capacitor, a busbar including a first busbar connecting the first connection terminal to the third connection terminal, a second busbar connecting the second connection terminal to the fourth connection terminal, and a first insulating layer sandwiched by the first and second busbars, main surfaces of the first and second busbars being parallel to each other, a control circuit board configured to control the semiconductor modules, and a heat transfer component including a main body connected to the cooler, and a second insulating layer arranged on the main body, the main body being in contact with the busbar and the control circuit via the second insulating layer. |
| US10867978B2 |
Integrated circuit module with integrated discrete devices
In at least one embodiment, an integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, and a discrete device disposed laterally with respect to the integrated circuit die and disposed above the redistribution layer. The integrated circuit product may include encapsulant mechanically coupling the redistribution layer, the integrated circuit die, and the discrete device. The integrated circuit product may include first conductive vias through the redistribution layer and second conductive vias through the redistribution layer. The first conductive vias may be electrically coupled to the integrated circuit die and the second conductive vias being electrically coupled to the discrete device. The discrete device may include a discrete capacitor device made from a ceramic material, electrolytic materials, or electrochemical materials. |
| US10867976B2 |
Semiconductor packages having dummy connectors and methods of forming same
An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package. |
| US10867975B2 |
Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a polymer material and a post passivation interconnect (PPI) pad disposed over the polymer material. A PPI line is disposed within an opening in the polymer material, the PPI line being coupled to the PPI pad. |
| US10867971B2 |
Light emitting diode panel
A light emitting diode panel including a first connecting wire, a first driving connection wire, a second driving connection wire, a first light emitting device, a second light emitting device and a spare electrode is provided. The driving signal transmitted by the first driving connection wire is independent of the driving signal transmitted by the second driving connection wire. The first light emitting device is connected to the first connecting wire and the first driving connection wire. The second light emitting device is connected to the first connecting wire and the second driving connection wire. The spare electrode is positioned between the first driving connection wire and the second driving connection wire. The spare electrode includes a first part and two second parts. The first part is positioned between two second parts. The first part extends in a first direction and each of the second parts extends in a second direction. An imaginary line extending from the first part along the first direction crosses over two second parts. |
| US10867970B2 |
Semiconductor package
A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer. |
| US10867969B2 |
Multi-wafer stacking structure and fabrication method thereof
A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate. |
| US10867966B2 |
Package structure, package-on-package structure and method of fabricating the same
A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts. |
| US10867963B2 |
Die stack structure and method of fabricating the same
A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer. The first bonding dielectric layer separates the second bonding dielectric layer from the dielectric material layer, and the first die and the second die are bonded through bonding the second bonding dielectric layer with the first bonding dielectric layer and bonding the conductive feature with the TSV. |
| US10867961B2 |
Single layer low cost wafer level packaging for SFF SiP
In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board. |
| US10867960B2 |
Device package including molding compound having non-planar top surface around a die and method of forming same
A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure. |
| US10867959B2 |
Integrated circuit packaging method and integrated packaged circuit
An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins. |
| US10867954B2 |
Interconnect chips
A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die. |
| US10867953B2 |
Manufacturing method of integrated fan-out package
A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts. |
| US10867952B2 |
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a top surface of the semiconductor substrate; a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively; a first bump disposed between the polymeric pad and the first pad; and a second bump disposed between the active pad and the second pad; wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad. Further, a method of manufacturing the semiconductor structure is disclosed. The method includes providing a circuit board; and forming a polymeric pad and an active pad on a surface of the circuit board, wherein a first thickness of the polymeric pad is substantially greater than a second thickness of the active pad. |
| US10867949B2 |
Substrate design for semiconductor packages and method of forming same
A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity. |
| US10867943B2 |
Die structure, die stack structure and method of fabricating the same
Provided is a die structure including a die, a bonding structure, and a protection structure. The die includes a substrate and a metal feature disposed over the substrate. The bonding structure is disposed over the die. The bonding structure includes a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer. The bonding metal layer is electrically connected to the metal feature of the die. The protection structure is disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer. A die stack structure and a method of fabricating the die structure are also provided. |
| US10867942B2 |
Chip packages and methods for forming the same
A chip package for optical sensing includes a substrate, and a semiconductor device positioned on the substrate and coupled to the substrate through a first conducting element. Two molding processes are applied, to form a first colloid body on the substrate so as to cover the semiconductor device and, on the first colloid body, to form a second colloid body which covers an optical device. The optical device is electrically connected to the substrate through a second conducting element. The light transmittance of the second colloid body exceeds that of the first colloid body. |
| US10867940B2 |
Package structure and manufacturing method thereof
A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element. |
| US10867939B2 |
Package structure and method of fabricating the same
A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer. |
| US10867931B2 |
MOS transistor embedded substrate and switching power supply using the same
Disclosed herein is a MOS transistor embedded substrate that includes first and second MOS transistors each having a source electrode formed on one surface and a drain electrode formed on other surface, and an insulation resin layer in which the first and second MOS transistors are embedded such that the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor face a same direction and that the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor face a same direction. |
| US10867925B2 |
Method for forming chip package structure
A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface. |
| US10867919B2 |
Electronic device and manufacturing method thereof
An electronic device and the manufacturing method thereof are provided. The electronic device includes a semiconductor die, a conductive structure electrically coupled to the semiconductor die, an insulating encapsulant encapsulating the semiconductor die and the conductive structure, and a redistribution structure disposed on the insulating encapsulant and the semiconductor die. The conductive structure includes a first conductor, a second conductor, and a diffusion barrier layer between the first conductor and the second conductor. The redistribution structure is electrically connected to the semiconductor die and the first conductor of the conductive structure. |
| US10867912B2 |
Dummy fill scheme for use with passive devices
Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions. |
| US10867903B2 |
Semiconductor package and method of forming the same
The present disclosure provides a semiconductor package, including at least two conductors and a first dielectric partially surrounding the at least two conductors, a capacitor substantially under the first dielectric, and a second dielectric over and lining along the first dielectric and top portions of the at least two conductors. The at least two conductors are respectively configured as an input/output (I/O) terminal of the semiconductor package. The capacitor includes a first electrode extending along a first direction and electrically connected with one of the at least two conductors, and a second electrode extending along a second direction opposite to the first direction and electrically connected to the other one of the at least two conductors. The second dielectric provides a compressive stress to the first dielectric. A method of forming the semiconductor package is also provided. |
| US10867902B2 |
Semiconductor module and method for producing the same
A power semiconductor module arrangement including two or more individual semiconductor devices each semiconductor device having a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. The power semiconductor module arrangement further includes a frame surrounding the two or more individual semiconductor devices, and a casting compound at least partly filling a capacity within the frame, thereby at least partly enclosing the two or more individual semiconductor devices. |
| US10867901B2 |
Semiconductor module and semiconductor device using the same
A semiconductor module includes: a sealing resin sealing an insulation circuit board so that a second metal layer is exposed to a rear plane and the rear plane is warped downward in a convex shape; and a cylindrical member including a center outer peripheral surface formed such that an upper portion is embedded in the sealing resin and including an unevenness and a lower outer peripheral surface provided below the center outer peripheral surface and smoother than the center outer peripheral surface and provided such that a bottom plane of a lower end of the lower outer peripheral surface is exposed from the rear plane of the sealing resin and the lower outer peripheral surface above the lower end of the lower outer peripheral surface is sealed by the sealing resin and is disposed near the end of the sealing resin in relation to the insulation circuit board. |
| US10867897B2 |
PoP device
A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate. |
| US10867894B2 |
Semiconductor element including encapsulated lead frames
To achieve the miniaturization of and the enhancement of the strength of a semiconductor element. In a semiconductor element (1) having a shape of a rectangular parallelepiped, on four sides forming one surface of the rectangular parallelepiped in plan view, portions of at least one of a first lead frame (11) and a second lead frame (12) are respectively in contact with the four sides and are exposed from a sealing portion (4) to serve as connection terminals (P12, P14, N11, N14), and in each of two pairs each composed of the two sides, facing each other, of the four sides, the portion of the first lead frame (11) is in contact with one of the two sides and is exposed as the connection terminal (P12, P14), the portion of the second lead frame (12) is in contact with the other of the two sides and is exposed as the connection terminal (N11, N14), and the connection terminal (P12, P14) formed by the first lead frame (11) and the connection terminal (N11, N14) formed by the second lead frame (12) are disposed at positions that are axially symmetric with each other. |
| US10867893B2 |
Semiconductor devices and methods for forming a semiconductor device
A semiconductor device includes an electrically conductive contact pad structure. Moreover, the semiconductor device includes a bond structure. The bond structure is in contact with the electrically conductive contact pad structure at least at an enclosed interface region. Additionally, the semiconductor device includes a degradation prevention structure laterally surrounding the enclosed interface region. The degradation prevention structure is vertically located between a portion of the bond structure and a portion of the electrically conductive contact pad structure. |
| US10867888B2 |
Component carrier comprising at least one heat pipe and method for producing said component carrier
The invention refers to a component carrier comprising at least one heat pipe, wherein the at least one heat pipe has at least a largely cylindrical heat pipe section with a largely cylindrical profile with an outer diameter. The at least one heat pipe is embedded within a recess of at least one inner layer or is surface-mounted on an outer layer of said component carrier, wherein at least the largely cylindrical heat pipe section of the heat pipe is thermoconductively coupled by means of at least one adapter means that directly contacts the heat pipe with at least one layer of the component carrier. Furthermore the invention refers to several methods for producing said component carrier. |
| US10867887B2 |
Enhanced flow boiling heat transfer in microchannels with structured surfaces
A two-phase microchannel heat sink can be a fluid channel including a bottom wall including a superhydrophilic surface with microstructures and a side wall including a surface that is hydrophobic relative to the superhydrophilic surface of the bottom wall. When heat flux is applied to the fluid channel, a liquid film on the bottom wall is maintained and nucleation of boiling occurs only on the side wall. |
| US10867880B2 |
Multi-die module with substrate cavity assembly
A multi-die module includes a first die with a first substrate and a first device formed over the first substrate, wherein the first substrate includes a cavity on a side opposite the first device. The multi-die module also includes a second die with a second substrate and a second device formed over the second substrate, wherein the second die is positioned at least partially in the cavity. The multi-die module also includes a coupler configured to convey signals between the first device and the second device. |
| US10867878B2 |
Dam for three-dimensional integrated circuit
An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure. |
| US10867877B2 |
Targeted recall of semiconductor devices based on manufacturing data
A system for providing a targeted recall includes a metrology sub-system for performing in-line measurements on semiconductor dies after one or more fabrication steps to generate in-line measurement profiles, a failure analysis sub-system for determining a manufacturing fingerprint of a failed die, and a controller. The metrology sub-system may further perform one or more measurements of the semiconductor dies after one or more packaging steps to generate package characterization profiles. The controller may generate manufacturing fingerprints for the semiconductor dies based on the in-line measurement profiles and the package characterization profiles, which are referenced to unique electronic chip identifiers. The controller may further identify at-risk dies by comparing the manufacturing fingerprints of the semiconductor dies with the manufacturing fingerprint of the failed die and direct a targeted recall for the one or more at-risk dies. |
| US10867871B2 |
Interconnect structure for fin-like field effect transistor
Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2. |
| US10867867B2 |
Methods of fabricating semiconductor devices with mixed threshold voltages boundary isolation of multiple gates and structures formed thereby
A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer. |
| US10867866B2 |
Semiconductor device and manufacturing method thereof
In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure. |
| US10867865B2 |
Method and structure for FinFET isolation
A semiconductor device includes a substrate and a fin protruding from the substrate, the fin having a first fin segment and a second fin segment discontinued from the first fin segment. The semiconductor device further includes an isolation feature disposed between the first and second fin segments and a spacer feature disposed on sidewalls of an upper portion of the isolation feature and surrounding the isolation feature from a top view. |
| US10867864B2 |
Semiconductor device and method of manufacture
Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill. |
| US10867861B2 |
Fin field-effect transistor device and method of forming the same
A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin adjacent to the gate structure; and forming a source/drain region in the recess, the source/drain region including a first layer, a second layer, and a third layer, where forming the source/drain region includes performing a first epitaxy process under first process conditions to form the first layer in the recess, the first layer extending along surfaces of the fin exposed by the recess; performing a second epitaxy process under second process conditions to form the second layer over the first layer; and performing a third epitaxy process under third process conditions to form the third layer over the second layer, the third layer filling the recess, where the first processing conditions, the second process conditions and the third process conditions are different. |
| US10867858B2 |
Simultaneous metal patterning for 3D interconnects
Processing methods may be performed to produce three-dimensional interconnects on a substrate. The methods may include forming a first metal interconnect layer over a semiconductor substrate. The methods may include forming a first dielectric layer over the first metal interconnect layer. The methods may include forming a second metal interconnect layer over the first dielectric layer. The methods may include forming a patterning mask overlying the second metal interconnect layer. The methods may also include simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer to expose the substrate to produce a multilayer interconnect structure in a first lateral direction. |
| US10867857B2 |
Method of cutting substrate and method of singulating semiconductor chips
A method of cutting a substrate including a device region and a scribe lane region includes selectively forming a passivation layer in the device region of the substrate, selectively forming a self-assembled monolayer on the passivation layer, and performing plasma cutting in the scribe lane region. |
| US10867855B2 |
Through silicon via fabrication
One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer. |
| US10867852B2 |
Semiconductor device and manufacturing method thereof
Provided is a semiconductor device including a substrate, a gate structure, a dielectric layer, an etch stop layer, and an adhesion layer. The gate structure is formed over the substrate. The dielectric layer is formed aside the gate structure. The adhesion layer overlays a top surface of the gate structure and extends to a first top surface of the dielectric layer. The etch stop layer is over the adhesion layer and in contact with a second top surface of the dielectric layer. |
| US10867849B2 |
Package-on-package structure
A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die. |
| US10867846B2 |
Fin field effect transistor (finFET) device structure with protection layer and method for forming the same
A method for forming a FinFET device structure is provided. The method includes forming a gate structure over a fin structure. The method also includes forming an S/D contact structure over a S/D structure and depositing a protection layer over the S/D contact structure. The protection layer and the S/D contact structure are made of different materials. The method further includes forming an etching stop layer over the protection layer and forming a dielectric layer over the etching stop layer. The method includes forming a first recess through the dielectric layer and the etching stop layer to expose the protection layer and forming an S/D conductive plug in the first recess. The S/D conductive plug includes a barrier layer directly on the protection layer, and the protection layer and the barrier layer are made of different materials. |
| US10867845B2 |
Semiconductor device and method
A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer. |
| US10867842B2 |
Method for shrinking openings in forming integrated circuits
A method includes forming a first hard mask layer and a second hard mask layer over the first hard mask layer, and forming a tri-layer including a bottom layer, a middle layer, and a patterned upper layer. The method further includes etching the middle layer to extend an opening in the patterned upper layer into the middle layer, wherein the opening has a first portion in the middle layer, and the first portion has a first top width and a first bottom width smaller than the first top width; etching the bottom layer to extend the opening into the bottom layer; and etching the second hard mask layer to extend the opening into the second hard mask layer. The opening has a second portion in the second hard mask layer, and the second portion has a second top width and a second bottom width smaller than the second top width. |
| US10867839B2 |
Patterning methods for semiconductor devices
Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask. |
| US10867834B2 |
Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer. |
| US10867832B2 |
Apparatus for holding semiconductor wafers
Apparatus for holding semiconductor wafers during semiconductor manufacturing processes are disclosed. In one embodiment, the apparatus comprises a heat-conductive layer disposed on a supporting base. The apparatus also comprises a plurality of holes formed through the heat-conductive layer and the supporting base. The apparatus further comprises a plurality of heat-conductive lift pins that extend through the holes over the heat-conductive layer at the top end, and make a direct contact with a wafer substrate. The heat-conductive layer and the lift pins are connected to a heating circuit. |
| US10867830B2 |
Room temperature debondable and thermally curable compositions
Embodiments in accordance with the present invention are directed to a method of fabricating a semiconductor device wherein a device wafer substrate is coated with a composition encompassing a surface energy modifier and a thermally stable polymer which is then bonded to a carrier wafer substrate coated with a composition encompassing a crosslinkable polymer composition. The polymer composition allows thinning of a device wafer before separating from the carrier wafer at room temperature. |
| US10867825B2 |
Wafer boat and treatment apparatus for wafers
A wafer boat is described for the plasma treatment of disc-shaped wafers, in particular semiconductor wafers for semiconductor or photovoltaic applications, which has a plurality of plates positioned parallel to each other made of an electrically conductive material, which have at least one carrier for a wafer on each side which faces another plate and define a receiving space for the wafers on the plates. The wafer boat also has a plurality of spacer elements, which are positioned between directly adjacent plates in order to position the plates parallel to each other, wherein the spacer elements are electrically conductive. Also a plasma treatment apparatus for wafers and a method for the plasma treatment of wafers is described. The apparatus has a process chamber for the reception of a wafer boat of the previously described type, means for controlling or regulating a process gas atmosphere in the process chamber and at least one voltage source, which is connectable to the plates of the wafer boat in a suitable manner, in order to apply an electrical voltage between directly adjacent plates of the wafer boat, wherein the at least one voltage source is suitable for applying at least one DC-voltage or at least one low-frequency AC-voltage and at least one high-frequency AC-voltage. In the method, during the heating phase a DC-voltage or a low-frequency AC-voltage is applied to the plates of the wafer boat in such a way that the spacer elements heat up by current flowing therethrough, and during a processing phase a high-frequency AC-voltage is applied to the plates of the wafer boat, in order to generate a plasma between the wafers inserted into them. |
| US10867812B2 |
Semiconductor manufacturing system and control method
A system includes a chamber, an inlet valve, and a control device. The chamber is configured to perform a semiconductor process. The inlet valve is coupled to the chamber and a facility water source. The control device is coupled to the inlet valve, and configured to at least partially close the inlet valve when the chamber is idle. |
| US10867801B2 |
Etching apparatus and etching method
According to one embodiment, an etching apparatus for etching a semiconductor with an aid of a noble metal catalyst, includes a reaction vessel configured to accommodate a semiconductor substrate provided with a catalyst layer including a noble metal, and a feeder configured to feed, to the reaction vessel, an oxidizer, hydrogen fluoride, an organic additive, and carbon dioxide in a supercritical or subcritical state. |
| US10867799B2 |
FinFET device and methods of forming same
A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer. |
| US10867797B2 |
Methods and apparatuses related to shaping wafers fabricated by ion implantation
The wafer fabrication technique uses an ion implantation process on the back side of the wafer to control the shape of the wafer. At least one first dopant is implanted into a front side of a wafer to dope the wafer. At least one second dopant is implanted into a back side of the wafer in a dopant profile to create a back side structure, where the back side structure controls a shape of the wafer. A blank wafer is provided that has an undoped front side and a form shaping back side structure on the back side. A doped wafer is provided that has a dopant implanted on the front side and a form shaping back side structure on the back side that least partially offsets the strain in the wafer induced by the front side dopant. |
| US10867794B2 |
Patterning method for semiconductor devices and structures resulting therefrom
A hard mask formed over a patterned photoresist layer in a tri-layer photoresist and a method for patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a photoresist layer over a first hard mask layer; patterning the photoresist layer to form a plurality of openings in the photoresist layer; depositing a second hard mask layer over the photoresist layer, the second hard mask layer filling the plurality of openings, the second hard mask layer having a first etch selectivity relative to the first hard mask layer, the photoresist layer having a second etch selectivity relative to the first hard mask layer, the first etch selectivity being greater than the second etch selectivity; planarizing the second hard mask layer; removing the photoresist layer; and etching the first hard mask layer using the second hard mask layer as a mask. |
| US10867791B2 |
Method for manufacturing epitaxial silicon wafer and epitaxial silicon wafer
A manufacturing method of an epitaxial silicon wafer uses a silicon wafer containing phosphorus, having a resistivity of less than 1.0 mΩ·cm. The silicon wafer has a main surface to which a (100) plane is inclined and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°5′ to 0°25′ with respect to an axis orthogonal to the main surface. The manufacturing method includes: annealing the silicon wafer at a temperature from 1200 degrees C. to 1220 degrees C. for 30 minutes or more under argon gas atmosphere (argon-annealing step); etching a surface of the silicon wafer (prebaking step); and growing the epitaxial film at a growth temperature ranging from 1100 degrees C. to 1165 degrees C. on the surface of the silicon wafer (epitaxial film growth step). |
| US10867789B2 |
Treatment to control deposition rate
A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials. |
| US10867786B2 |
Substrate processing method
A substrate processing method capable of uniformly maintaining damage to a pattern structure under a thin film formed on a substrate includes supplying a source material to a substrate on which a pattern structure that is reactive with a reactant is formed; and supplying the reactant through at least a central gas inlet of a supply unit in a plasma atmosphere, wherein, during the supplying of the reactant, a blocking material different from the reactant is supplied through an additional gas inlet that is spaced apart from the central gas inlet of the supply unit, and a flow of the blocking material at the edge of the substrate is increased, thereby increasing a radical density of the reactant near a center of the substrate. |
| US10867772B2 |
Electrostatic element having grooved exterior surface
Provided herein are approaches for increasing surface area of a conductive beam optic by providing grooves or surface features thereon. In one approach, the conductive beam optic may be part of an electrostatic filter having a plurality of conductive beam optics disposed along an ion beam-line, wherein at least one conductive beam optic includes a plurality of grooves formed in an exterior surface. In some approaches, a power supply may be provided in communication with the plurality of conductive beam optics, wherein the power supply is configured to supply a voltage and a current to the plurality of conductive beam optics. The plurality of grooves may be provided in a spiral pattern along a length of the conductive beam optic, and/or oriented parallel to a lengthwise axis of the conductive beam optic. |
| US10867771B2 |
Electron microscope and specimen tilt angle adjustment method
An electron microscope includes: an irradiation lens system that irradiates a specimen with an electron beam; an irradiation system deflector that deflects an electron beam incident on the specimen; a specimen tilting mechanism that tilts the specimen; an imaging lens system that forms an electron diffraction pattern or an electron microscope image by using an electron having passed through the specimen; an imaging device that acquires the electron diffraction pattern or the electron microscope image formed by the imaging lens system; and a controller that controls the irradiation system deflector and the specimen tilting mechanism. The controller performs: a process of acquiring a plurality of electron diffraction patters formed by using electron beams having different incidence angles to the specimen, the different incidence angles having been obtained by deflecting the electron beams incident on the specimen by using the irradiation system deflector; a process of calculating a tilt angle of the specimen based on the plurality of electron diffraction patterns; and a process of controlling the specimen tilting mechanism so that the specimen has the calculated tilt angle. |
| US10867766B2 |
Subsea fuse device
Example embodiments relate a subsea fuse device exposed to a high ambient pressure when deployed. The fuse device comprises a metallic fuse housing enclosing a low-pressure hollow space and a fuse arranged in the low-pressure hollow space, the fuse having two electrical connectors, wherein one of the electrical connectors of the fuse is electrically and thermoconductively coupled to the metallic fuse housing so as to provide an electrical connection between the fuse connector and the housing and to dissipate heat from the fuse. |
| US10867763B1 |
Shape-memory-based dead-facing mechanisms for severing electrical connections
An apparatus includes an electrical switch that includes (i) multiple first electrical contacts and (ii) a second electrical contact configured to bridge the first electrical contacts in order to form at least one electrical connection. The apparatus also includes a shape-memory actuator configured to move the second electrical contact in order to selectively open the electrical switch and break the at least one electrical connection. The shape-memory actuator may be configured to be returned to an original shape and the second electrical contact may be configured to be returned to a bridging position in order to reset the apparatus. The apparatus may further include a shutter member configured to be moved between the first electrical contacts in order to prevent re-bridging of the first electrical contacts and to extend an arc-gap between the first electrical contacts. |
| US10867762B2 |
Keyboard key having a haptic elastic piece abutting the return spring
A key structure is provided, including a key housing, a keycap, an elastic piece and a spring. The key housing comprises an interfering portion. The keycap is movably assembled to the key housing along a pressing axial direction. The elastic piece is movably assembled to the keycap along the pressing axial direction. The elastic piece comprises a protrusion, and the interfering portion is located on a movement path of the protrusion. The spring abuts between the keycap and the elastic piece. When in an initial position, the protrusion is stopped at the interfering portion. When an external force is applied to the keycap, in a pressing process, the keycap is moved relative to the key housing, and drives the protrusion to surmount and cross over the interfering portion. An elastic restoring force of the elastic piece causes the protrusion to hit the interfering portion to make a sound. |
| US10867760B2 |
Conducting switch mechanism
A conducting switch mechanism includes a housing, an operating stem is exposed from the housing, a fixed terminal set, a movable terminal module, a fulcrum bar, and an elastic member. The fixed terminal set is fixed on a base of the housing, and includes a pair of constant contact terminals, a pair of first pathway terminals, and a pair of second pathway terminals. The movable terminal module has a first movable terminal, a second movable terminal, and an insulating member. The insulating member partially clads the movable terminals. The structures of movable terminals are integrally stamped. One end of the movable terminals correspondingly abuts against the constant contact terminals, and another end of the movable terminals correspondingly contacts the first pathway terminal or the second pathway terminal. The elastic member is connected between the fulcrum bar and the movable terminal module. |
| US10867759B2 |
Keyswitch structure
A keyswitch structure includes a keycap, a base, and two supports pivotally connected to each other relative to a rotation axis and connected to and between the keycap and the base. One of the supports includes a first shaft recess, a first shaft portion, and a division slot formed therebetween; the other support includes a second shaft recess, a second shaft portion, and a division wall therebetween. The two supports are pivotally connected relative to the rotation axis by the first shaft portion and the second shaft portion rotatably disposed in the first shaft recess and the second shaft recess respectively. Therein, the division wall is inserted into the division slot. The keycap can move up and down relative to the base through the two supports. |
| US10867756B2 |
Contact in RF-switch
The present invention generally relates to a mechanism for making a MEMS switch that has a robust RF-contact by avoiding currents to run through a thin sidewall in a via from the RF-contact to the underlying RF-electrode. |
| US10867753B2 |
Solid electrolytic capacitor for use in a humid atmosphere
A capacitor that is capable of exhibiting good properties under humid conditions is provided. The ability to perform under such conditions is due in part to selective control over the particular nature of the solid electrolyte and cathode coating that overlies the solid electrolyte. For example, the solid electrolyte contains pre-polymerized conductive polymer particles, which can help act as a blocking layer for any silver ions migrating through the capacitor. Likewise, the cathode coating also contains conductive metal particles (e.g., silver particles) that are dispersed within a resinous matrix. The resinous matrix includes a polymer that absorbs only a small amount of water, if any, when placed in a humid atmosphere. |
| US10867749B2 |
Multilayer capacitor
A multilayer capacitor includes a capacitor body, a first external electrode, and a second external electrode. The capacitor body includes a plurality of first and second internal electrodes alternately stacked with dielectric layer interposed therebetween. The first and second external electrodes are electrically connected to the first and second internal electrodes, respectively. A first Schottky layer is Schottky-junctioned to an interface between the dielectric layer and the first internal electrode in the capacitor body. A second Schottky layer is Schottky-junctioned to an interface between the dielectric later and the second internal electrode in the capacitor body. The work function values of the first and second Schottky layers is higher than the work function values of the first and second internal electrodes. |
| US10867744B2 |
Coil component
A coil component includes a magnetic portion that includes metal particles and a resin material, a coil conductor embedded in the magnetic portion, and outer electrodes electrically connected to the coil conductor and disposed on the bottom surface of the coil component. The magnetic portion includes a magnetic base having a protrusion portion and a magnetic outer coating. The coil conductor is disposed on the magnetic base such that the protrusion portion is located in a core portion of the coil conductor. The magnetic outer coating is disposed so as to cover the coil conductor, and the height of the edge portion of the upper surface of the magnetic base is more than the height at the position at which the edge of the protrusion portion is located. |
| US10867739B2 |
Ceramic core, wire-wound electronic component, and method for producing ceramic core
A ceramic core, which is made of a ferrite material including Ni and Zn, includes an axial core extending in a length direction and a pair of flange portions disposed at both ends of the axial core in the length direction. The dimension L of the ceramic core in the length direction satisfies 0 mm |
| US10867732B2 |
Sintered body for forming rare-earth permanent magnet and rotary electric machine having rare-earth permanent magnet
This invention provides for a rotary electric machine that includes a rotor having a plurality of permanent magnets arranged in the circumferential direction, and in which the leakage of magnetic flux can be suppressed with a simple structure; and a rare-earth permanent magnet-forming sintered compact for forming rare-earth permanent magnets to be used in said rotary electric machine. |
| US10867731B2 |
Hybrid superconducting magnetic device
A hybrid superconductive device for stabilizing an electric grid comprises (a) a magnetic core arrangement at least partially carrying an AC winding the AC winding connectable to an AC circuit for a current to be limited in the event of a fault; (b) at least one superconductive coil configured for storing electromagnetic energy; the superconductive coil magnetically coupled with the core arrangement and saturating the magnetic core arrangement during use. The hybrid superconductive device further comprises a switch unit preprogrammed for switching electric current patterns corresponding to the following modes: at least partially charging the superconductive coil; a standby mode when the superconductive coil is looped back; and at least partially discharging the superconductive coil into the circuit. Optionally, hybrid superconductive device comprises at least one passage located within said magnetic flux. The passage conducts a material flow comprising components magnetically separable by said magnetic flux. |
| US10867729B2 |
Method for producing sintered body that forms rare-earth permanent magnet and has non-parallel easy magnetization axis orientation
Provided is a method for producing a sintered body that forms a rare-earth permanent magnet, has a single sintered structure and an arbitrary shape, and has easy magnetization axis orientations of different directions applied to the magnet material particles in a plurality of arbitrary regions. This method forms a three-dimensional first molded article from a composite material formed by mixing a resin material and magnet material particles containing a rare-earth substance. The first molded article is then subjected to a deforming force and a second molded article is formed in which the orientation direction of the easy magnetization axis of the magnet material particles in at least the one section of the horizontal cross-section is changed to a direction which differs from the orientation direction of the first molded article. The second molded article is heated to a sintering temperature and kept at the temperature for a period of time. |
| US10867727B2 |
Rare earth permanent magnet material and manufacturing method thereof
The present invention provides a rare earth permanent magnet material and manufacturing method thereof. The manufacturing method of the present invention comprises a multi-arc ion plating step and a infiltrating step, wherein multi-arc ion plating process is adopted to deposit a metal containing a heavy rare earth element on a surface of a sintered neodymium-iron-boron magnet which has a thickness of 10 mm or less in at least one direction; and then heat treatment is performed on the sintered neodymium-iron-boron after deposition. The sum of an intrinsic coercive force (Hcj, in unit of kOe) and a maximum magnetic energy product ((BH)max, in unit of MGOe) of the permanent magnet material of the present invention is 66.8 or more. Moreover, the manufacturing method of the present invention has high production efficiency and does not increase harmful substances, and the price of devices is relatively low. |
| US10867721B2 |
Wire harness
A wire harness includes a functional exterior component shaped into a sheet and an electric wire disposed to overlap with the functional exterior component in at least a part of a region along a longitudinal direction. At least a part of an overlap between the insulating covering of the electric wire and the functional exterior component is welded. |
| US10867719B2 |
Enhancing performance stability of electroactive polymers by vapor-deposited organic networks
Disclosed are compositions of electroactive polymers (EAPs) having improved performance stability. In the EAP compositions, a cross-linked polymer is deposited onto the surface of the EAP by vapor-deposition methods. Upon contact with an aqueous solution (e.g., an aqueous electrolyte solution), the vapor-deposited polymeric network becomes a hydrogel that encapsulates the EAPs. By modulating precursors and vapor deposition conditions, the mesh size of the resultant hydrogel coatings can be controlled to accommodate the key species that interact with the EAPs. |
| US10867718B2 |
Mechanically interlocked air-stable radicals
Provided herein are mechanically interlocked air-stable persistent organic radicals. The radical compositions may access a multiplicity of radical, cationic redox states as well as a fully cationic redox state. A composition comprises a first ring mechanically interlocked with a second ring or a salt thereof, wherein the first ring comprises a 4,4′-bipyridinium subunit or a derivative thereof and a diazapyrenium subunit or a derivative thereof and the second ring comprises a 4,4′-bipyridinium subunit or a derivative thereof. In some embodiments, the second ring further comprises a diazapyrenium subunit or a derivative thereof. Methods of preparing the compositions are also provided. |
| US10867712B2 |
Isolation condenser systems for nuclear reactor commercial electricity generation
Nuclear reactors include isolation condenser systems that can be selectively connected with the reactor to provide desired cooling and pressure relief. Isolation condensers are immersed in a separate chamber holding coolant to which the condenser can transfer heat from the nuclear reactor. The chamber may selectively connect to an adjacent coolant reservoir for multiple isolation condensers. A check valve may permit coolant to flow only from the reservoir to the isolation condenser. A passive switch can operate the check valve and other isolating components. Isolation condensers can be activated by opening an inlet and outlet to/from the reactor for coolant flow. Fluidic controls and/or a pressure pulse transmitter may monitor reactor conditions and selectively activate individual isolation condensers by opening such flows. Isolation condenser systems may be positioned outside of containment in an underground silo with the containment, which may not have any other coolant source. |
| US10867709B2 |
Emergency response device and system for service to individuals with diminishing dexterity and neurological physiological functionality
A method and system for providing care comprises: monitoring the status of multiple patients, and responding to the needs of the multiple patients by a response agent system, wherein the response agent system is configured to convey communications regarding patient needs to multiple response agents of the response agent system as they arise, such that an available response agent can quickly respond. |
| US10867707B2 |
Systems and methods for anatomical modeling using information obtained from a medical procedure
Systems and methods are disclosed herein for anatomical modeling using information obtained during a medical procedure, whereby an initial anatomical model is generated or obtained, a correspondence is determined between the initial model and additional data and/or measurements from an invasive or noninvasive procedure, and, if a discrepancy is found between the initial model and the additional data, the anatomical model is updated to incorporate the additional data and reduce the discrepancy. |
| US10867705B2 |
Predicting health outcomes
Described are methods for identification of likelihood of health outcomes such as the development of a medical condition using health histories from genetically related individuals. Embodiments include: receiving a first set of genetic data associated with the human subject; comparing the first set of genetic data to a plurality of sets of genetic data from a plurality of other individuals; identifying from the comparison a family network comprising individuals genetically related to the human subject as defined by identity by descent; receiving a set of health history data for each individual and each individual in the family network; analyzing the set of health history data to generate a health outcome score for the human subject, the health outcome score being a measure of risk for the human subject to develop a pre-defined health outcome that is associated with the health outcome score; and reporting the health outcome score. |
| US10867703B2 |
System and method for predicting health condition of a patient
According to embodiments illustrated herein, there is provided a system for predicting a health condition of a first patient. The system includes a document processor configured to extract one or more headings from one or more medical records of the first patient based on one or more predefined rules. The document processor is further configured to extract one or more words from one or more phrases written under each of the extracted one or more headings, wherein the one or more phrases correspond to documentation of the observation of the first patient by a medical attender. The system further includes one or more processors configured to predict the health condition of the first patient based on a count of the one or more words in historical medical records and the one or more medical records. |
| US10867699B2 |
Medication list generator
Methods, systems, and computer-readable media are provided for collecting information regarding the medication an individual is taking before an individual's healthcare visit. A patient medication list is generated using scanned barcode information or information from a photograph taken with the patient's mobile device. The pre-populated medication list is served to a clinician during the individual's healthcare visit without the need for manual entry of each medication the patient is currently taking to speed up the medication reconciliation process. |
| US10867692B2 |
Apparatuses and methods for latching redundancy repair addresses at a memory
Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block. |
| US10867690B2 |
Memory modules and methods of operating memory systems including the same
A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories. |
| US10867689B2 |
Test access port architecture to facilitate multiple testing modes
A system comprises a testing mode register, a set of pins, and a test access port controller. The test access port controller initiates a first testing mode by configuring the set of pins according to a first pin protocol. The test access port controller configures a first pin to receive first test pattern data based on a first convention and configures a second pin to output first test result data based on the first test pattern data. Based on detecting a register command stored in the testing mode register, the test access port controller initiates a second testing mode by configuring the set of pins according to a second pin protocol. The test access port controller configures the first pin to receive a second test pattern data generated based on a second convention and configures the second pin to output a second test result data based on the second test pattern data. |
| US10867682B2 |
Memory device and method of reading data
A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation. |
| US10867679B2 |
Semiconductor memory device
A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address. |
| US10867676B2 |
Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described. |
| US10867675B2 |
Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells
Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells are disclosed. The apparatus includes a first memory cell including first and second ferroelectric capacitors configured to store charges representing complementary logical values, a second memory cell including first and second dielectric capacitors configured to store charges representing complementary logical values, a first bit line selectably coupled to the first ferroelectric capacitor of the first memory cell and to the first dielectric capacitor of the second memory cell, a second bit line selectably coupled to the second ferroelectric capacitor of the first memory cell and to the second dielectric capacitor of the second memory cell, and a sense amplifier coupled to the first and second bit lines. |
| US10867672B2 |
Resistive memory device and programming method of the same
In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially. |
| US10867668B2 |
Area efficient write data path circuit for SRAM yield enhancement
A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance. |
| US10867666B2 |
Memory unit
There is provided a memory unit comprising an array of memory cells and a driver circuit configured to output an output address signal that addresses a portion/subset of the array of memory cells. The driver circuit comprises a logic gate that is configured to receive one or more input address signals and to provide an output address signal in dependence upon the one or more input address signals, and wherein the logic gate is configured to output a drive voltage provided by a first of the one or more input address signals as the output address signal when the output of the logic gate is true/high. |
| US10867665B1 |
Reset before write architecture and method
An SRAM bit-cell with independent write and read ports and an architecture utilizing a feedback loop from the read port to the write port of half-selected bit-cells. This guarantees absolute data retention of all SRAM bit-cells not fully selected for write operation across a wide range of supply voltage spanning from the nominal voltage of a process to a sub-threshold range. |
| US10867663B2 |
Control method for memory and non-transitory computer-readable media
A control method for a memory is provided. External data is received. An error correct code scheme is performed on the external data to generate first parity data. The number of logic values equal to a specific logic value in the external data and the first parity data is calculated to generate a calculation result. First reverse data is generated according to the calculation result and tendency data. The external data and the first parity data are inverted and the inverted external data, the inverted first parity data and the first reverse data are written into a cell array in response to the calculation result and the tendency data matching a predetermined condition. The external data, the first parity data and the first reverse data are written into the cell array in response to the calculation result and the tendency data not matching the predetermined condition. |
| US10867658B2 |
Address counting circuit, memory device and operating method thereof
An address counting circuit includes an address counter suitable for counting an address in response to a counting signal; and a counting control block suitable for controlling the address counter to skip the address of at least one predetermined value. |
| US10867656B2 |
Memory performing refresh operation and operation method of the same
A memory includes: first to Nth areas refreshed based on first to Nth refresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number. |
| US10867649B2 |
Magnetic memory device
According to one embodiment, a magnetic memory device includes a first conductive layer, a first stacked body, and a controller. The first conductive layer includes a first region, a second region, and a third region between the first region and the second region. The first stacked body includes a first magnetic layer, a second magnetic layer provided between the third region and the first magnetic layer in a first direction crossing a second direction, and a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The second direction is from the first region toward the second region. The controller electrically is connected to the first region, the second region, and the first magnetic layer. The controller performs at least first to third operations. In the operations, the controller sets the first stacked body to first to third resistance state. |
| US10867648B2 |
Memory system and operating method thereof
A memory system includes a memory and a controller for providing the memory with a data strobe signal; and data synchronized with an internal data strobe signal, wherein the controller includes a signal generator for generating the data strobe signal, an inverter for selectively outputting one between a non-inverted data strobe signal having the same phase as the data strobe signal and an inverted data strobe signal having an inverted phase to the phase of the data strobe signal based on an inversion signal, a delayer for delaying the inverted data strobe signal or the non-inverted data strobe signal based on a delay signal and outputting the internal data strobe signal, and a trainer for performing a verification operation on the synchronized data and generating the inversion signal and the delay signal based on the verification operation result. |
| US10867647B2 |
Marching memory and computer system
A marching memory includes an alternating periodic array of odd-numbered columns (U1, U2, . . . , Un−1, Un) and even-numbered columns (Ur1, Ur2, . . . , Urn−1, Urn). Each of the odd-numbered columns (U1, U2, . . . , Un−1, Un) has a sequence of front-stage cells aligned along a column direction so as to store a set of moving information of byte size or word size. And each of the even-numbered columns (Ur1, Ur2, . . . , Urn−1, Urn) has a sequence of rear-stage cells aligned along a column direction so as to store the set of moving information, so that the set of moving information can be transferred synchronously, step by step, along a direction orthogonal to the column direction. |
| US10867645B2 |
Memory device including plurality of latches and system on chip including the same
A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches. |
| US10867635B2 |
Method and system for generation of a variant video production from an edited video production
A method for generating a variant video production from an original video production is provided herein. The method may include the following steps: obtaining an original video production made of a plurality of visual assets being video cuts and/or images and at least one original audio track; automatically analyzing content of the original video production, to separate said visual assets; automatically detecting and storing editing operations applied on the visual assets during creation of the original video production; and automatically generating a variant video production based on at least some of the separated visual assets, wherein only some of the separated visual assets retain respective editing operations applied on the visual assets during the creation of the original video production. |
| US10867632B2 |
Shingled magnetic recording device capable of recording position error on non-volatile memory
According to one embodiment, a magnetic disk device includes a disk, a head that writes data to the disk and reads data from the disk, and a controller that overwrites a second track on a first track in a first track group, and records a maximum first positioning error in a first direction from the first track to the second track in the first track in a nonvolatile first recording area. |
| US10867627B1 |
Amplifying structure for microwave-assisted magnetic recording
An apparatus comprises a microwave-assisted magnetic recording slider body. The body includes a write pole, a trailing shield, a spin torque oscillator, and an amplifying structure. The write pole extends from the air bearing surface into the slider body for a first distance, and the trailing shield extends from the air bearing surface into the slider body for a second distance. The spin torque oscillator is disposed proximate and between the write pole and the trailing shield at the air bearing surface and extends into the slider body for a third distance that is less than the first and second distances. The amplifying structure comprises a stepped portion and a gap, is recessed from the air bearing surface and disposed proximate the spin torque oscillator. The gap has a first interface with the write pole and a second interface with the trailing shield, wherein at least one of the first and second interfaces forms the stepped portion. |
| US10867621B2 |
System and method for cluster-based audio event detection
Methods, systems, and apparatuses for audio event detection, where the determination of a type of sound data is made at the cluster level rather than at the frame level. The techniques provided are thus more robust to the local behavior of features of an audio signal or audio recording. The audio event detection is performed by using Gaussian mixture models (GMMs) to classify each cluster or by extracting an i-vector from each cluster. Each cluster may be classified based on an i-vector classification using a support vector machine or probabilistic linear discriminant analysis. The audio event detection significantly reduces potential smoothing error and avoids any dependency on accurate window-size tuning. Segmentation may be performed using a generalized likelihood ratio and a Bayesian information criterion, and the segments may be clustered using hierarchical agglomerative clustering. Audio frames may be clustered using K-means and GMMs. |
| US10867620B2 |
Sibilance detection and mitigation
The present disclosure relates to sibilance detection and mitigation in a voice signal. A method of sibilance detection and mitigation is described. In the method, a predetermined spectrum feature is extracted from a voice signal, the predetermined spectrum feature representing a distribution of signal energy over a voice frequency band. Sibilance is then identified based on the predetermined spectrum feature. Excessive sibilance is further identified from the identified sibilance based on a level of the identified sibilance. Then the voice signal is processed by decreasing a level of the excessive sibilance so as to suppress the excessive sibilance. Corresponding system and computer program products are described as well. |
| US10867619B1 |
User voice detection based on acoustic near field
Processing sound received by a device can include receiving a first signal from a first microphone of the device and a second signal from a second microphone of the device, where the first and second microphones capture sounds from a sound field. A ratio between the acoustic pressure and the particle velocity of the sound field can be calculated. In response to the ratio exceeding a threshold, speech signal processing is performed on one or more of the microphone signals. Other aspects are also described and claimed. |
| US10867616B2 |
Noise mitigation using machine learning
This disclosure relates to solutions for eliminating undesired audio artifacts, such as background noises, on an audio channel. A process for implementing the technology can include receiving a set of audio segments, analyzing the segments using a first ML model to identify a first probability of unwanted background noises in the segments, and if the first probability exceeds a threshold, analyzing the segments using a second ML model to determine a second probability that the one or more background features exist in the segments. In some aspects, the process can include attenuating audio artifacts in the segments, if the second probability exceeds a second threshold. In some implementations, dynamic time stretching and shrinking can be applied to the noise attenuation. Systems and machine-readable media are also provided. |
| US10867611B2 |
User programmable voice command recognition based on sparse features
A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sparse sound parameter information is extracted from the analog signal. The extracted sparse sound parameter information is processed using a speaker dependent sound signature database stored in the sound recognition sensor to identify sounds or speech contained in the analog signal. The sound signature database may include several user enrollments for a sound command each representing an entire word or multiword phrase. The extracted sparse sound parameter information may be compared to the multiple user enrolled signatures using cosine distance, Euclidean distance, correlation distance, etc., for example. |
| US10867607B2 |
Voice dialog device and voice dialog method
A voice dialog device includes a sight line detection unit configured to detect a sight line of a user, a voice acquiring unit configured to acquire voice pronounced by the user, and a processor. The processor is configured to perform a step of acquiring a result of recognizing the voice, a step of determining whether or not the user is driving, and a step of determining whether or not the voice dialog device has a dialog with the user. When the detected sight line of the user is in a certain direction, and a start keyword has been detected from the voice, the processor determines that the user has started a dialog. The processor switches the certain direction based on whether the user is driving. |
| US10867603B2 |
Audio-video reproduction device setup using interview-based voice control
An audio-video (AV) reproduction device that comprises at least one audio capturing device, at least one speaker, a memory, and circuitry. The memory stores setup information associated with first-time device setup of the audio-video reproduction device. The first-time device setup is associated with a plurality of configuration settings of the AV reproduction device. The circuitry controls the at least one speaker to output a message in the setup information, and controls the at least one audio capturing device to receive a user input based on the message. The circuitry compares the user input with at least one condition associated with the message. The circuitry configures a configuration setting from the plurality of configuration settings based on the comparison. The circuitry controls at least a function of the AV reproduction device based on the configured configuration setting. |
| US10867602B2 |
Method and apparatus for waking up via speech
The present disclosure provides a method and an apparatus for waking up via a speech. The method includes: obtaining a speech signal; decoding the speech signal according to a pre-generated searching space to obtain a speech recognition result, in which the searching space includes a path where an inversion model is located, the inversion model includes a first inversion model generated by training based on one or more word segmentation results of each of one or more wake-up phrases; when the first preset number of words of the speech recognition result is obtained, determining whether the preset number of words contains at least part of words in one of the one or more wake-up phrases; and determining cancellation of a wake-up operation directly if does not contain at least part of words in one of the one or more wake-up phrases, and ending the decoding of the speech signal. |
| US10867601B2 |
In-band voice-assistant/concierge for controlling online meetings
A computing device includes a hardware interface to be coupled to a microphone and speaker assembly, and a network interface to be coupled to a network for audio conferencing with remote audio conferencing devices and for accessing a voice assistant service that operates to assist with the audio conferencing. An audio interceptor is coupled between the hardware interface and the network interface to direct audio over a first voice channel while audio conferencing with the remote audio conferencing devices. The audio interceptor monitors for a user initiated trigger command signal during the audio conferencing, and directs audio from the first voice channel to a second voice channel upon detection of the user initiated trigger command signal. The second voice channel is used to access the voice assistant service. |
| US10867600B2 |
Recorded media hotword trigger suppression
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for hotword trigger suppression are disclosed. In one aspect, a method includes the actions of receiving, by a microphone of a computing device, audio corresponding to playback of an item of media content, the audio including an utterance of a predefined hotword that is associated with performing an operation on the computing device. The actions further include processing the audio. The actions further include in response to processing the audio, suppressing performance of the operation on the computing device. |
| US10867598B2 |
Semantic analysis method, semantic analysis system and non-transitory computer-readable medium
A semantic analysis method, semantic analysis and non-transitory computer-readable medium are provided in this disclosure. The semantic analysis method includes the following operations: inputting a voice and recognizing the voice to generate an input sentence, wherein the input sentence includes a plurality of vocabularies; selecting at least one key vocabulary from the vocabularies according to a word property corresponding to each vocabulary; establishing a parse tree according to the input sentence and finding a plurality of associated sub-sentences; calculating an associated feature vector between the associated sub-sentences; concatenating the associated feature vector and the vocabulary vector corresponding to each vocabulary to generate a vocabulary feature vector corresponding to each vocabulary; and analyzing the vocabulary feature vector to generate an analysis result by a semantic analysis model, wherein the analysis result includes a slot type corresponding to each vocabulary and an intent corresponding to the input sentence. |
| US10867597B2 |
Assignment of semantic labels to a sequence of words using neural network architectures
Technologies pertaining to slot filling are described herein. A deep neural network, a recurrent neural network, and/or a spatio-temporally deep neural network are configured to assign labels to words in a word sequence set forth in natural language. At least one label is a semantic label that is assigned to at least one word in the word sequence. |
| US10867595B2 |
Cold fusing sequence-to-sequence models with language models
Described herein are systems and methods for generating natural language sentences with Sequence-to-sequence (Seq2Seq) models with attention. The Seq2Seq models may be implemented in applications, such as machine translation, image captioning, and speech recognition. Performance has further been improved by leveraging unlabeled data, often in the form of a language models. Disclosed herein are “Cold Fusion” architecture embodiments that leverage a pre-trained language model during training. The Seq2Seq models with Cold Fusion embodiments are able to better utilize language information enjoying faster convergence, better generalization, and almost complete transfer to a new domain while using less labeled training data. |
| US10867592B2 |
Curtain providing a barrier against light, noise, heat, fire and electromagnetic radiation
The invention relates to a curtain providing a barrier against light, noise, heat, fire and electromagnetic radiations. The curtain comprises two textile layers, each having a combination of non-woven textile material and woven textile material, subjected to a fire-proofing treatment; an inner layer sandwiched between the textile layers and formed by sound insulation wool; and a cover layer adjacent to the outer side of one of the textile layers, formed by a metal selected from the group consisting of aluminum and copper. The curtain as a whole has a total thickness between 0.5 cm and 3 cm. |
| US10867591B1 |
Vehicle horn assembly and method
A vehicle horn assembly for installation in one of a first vehicle type and a second vehicle type different than the first vehicle type is provided. The vehicle horn assembly includes a housing common to each of the first vehicle type and the second vehicle type. The housing has a resonance tube provided with a sound outlet portion. A first cover separate from the housing has a first configuration. The first cover is configured to be releasably connected to the housing for covering the sound outlet portion when the housing is to be installed in the first vehicle type. A second cover separate from the housing has a second configuration different than the first configuration. The second cover is configured to be releasably connected to the housing for covering the sound outlet portion when the housing is to be installed in the second vehicle type. |
| US10867586B1 |
Virtual reality streaming media system and method of use
A virtual reality experience system includes an environment with a viewing area; a datastream to be implemented into the viewing area by a display device to display the datastream in a virtual reality fashion; a down sampler device to receive the datastream, the down sampler device having one or more adaptive learning algorithms contained thereon, the down sampler is to perform the steps of receiving the datastream; predicting visual movement of a user related to the viewing area; determining a likely direct viewing direction by the user; and manipulating the datastream such that a high resolution stream is displayed in the likely direct viewing direction and a low resolution image is displayed in a remainder of the viewing area; the down sampler reduces the overall bandwidth need for portraying a virtual reality experience to the user. |
| US10867585B2 |
Electronic apparatus and method for displaying a content screen on the electronic apparatus thereof
An electronic apparatus and a controlling method thereof. The electronic apparatus includes a display; an outer frame to house the display; an illuminance sensor which detects a sensing value used to determine at least one of illuminance and color temperature of an external light; a memory which stores a background image, which is an image of an area behind the electronic apparatus; and a processor, which generates a content screen comprising an object layer including at least one graphic object and a background image layer including the background image. The display displays the content screen and the processor may correct the background image or provide an image effect based on the sensed values. |
| US10867583B2 |
Beam scanning image processing within an improved graphics processor micro architecture
Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images. |
| US10867580B2 |
Three dimensional (3-D) look up table (LUT) used for gamut mapping in floating point format
A data segmenter is configured to determine indices using numbers of most significant bits (MSBs) of fractional values of floating-point representations of component values of an input color that are selected based on exponent values of the floating-point representations. The component values are defined according to a source gamut. The data segmenter is also configured to determine offsets associated with the indices using subsets of the fractional values. An interpolator configured to map the input color to an output color defined according to a destination gamut based on a location in a three-dimensional (3-D) look up table (LUT) indicated by the indices and offsets. |
| US10867579B2 |
Data processing method and device, driving method, display panel and storage medium
A data processing method, an image display driving method, a data processing device, a display panel and a computer-readable storage medium are provided. The data processing method includes: based on input RGB grayscale values, calculating a chromaticity coordinate of the input RGB grayscale values on a chromaticity diagram, in which the chromaticity diagram includes a white basic point; calculating to obtain intermediate grayscale values containing a white component, based on the input RGB grayscale values and according to a position relationship between the chromaticity coordinate and the white basic point; and adjusting the intermediate grayscale values to obtain output RGBW grayscale values. |
| US10867578B2 |
Ambient light adaptive displays with paper-like appearance
An electronic device may include a display having an array of display pixels and having display control circuitry that controls the operation of the display. The display control circuitry may operate the display in different modes. In a paper mode, display control circuitry may use stored spectral reflectance data to adjust display colors such that the colors appear as they would on a printed sheet of paper. In a low light mode when the ambient light level is below a threshold, the light emitted from the display may be adjusted to mimic the appearance of an incandescent light source. In a bright light mode when the ambient light level exceeds a threshold, the light emitted from the display may be adjusted to maximize readability in bright light. The target white point of the display may be adjusted based on which mode the display is operating in. |
| US10867577B2 |
Display device including data conversion circuit
Image processing in accordance with the shape of a display device is performed at high speed with low power consumption, without the use of a large frame memory or a high-throughput GPU. Used is a data conversion circuit including: a latch circuit that takes in data from input data in synchronization with a writing clock signal and stores the data as writing data; a memory circuit that stores the writing data and outputs the writing data to an external circuit as readout data in synchronization with a readout clock signal; and a clock selection control circuit. The writing clock signal is one of a plurality of clock signals with different frequencies and is output in accordance with control by the clock selection control circuit. |
| US10867576B2 |
Semiconductor device, and display device and electronic device utilizing the same
A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased. |
| US10867573B2 |
Common voltage control circuit and method, display panel and display device
Provided in the embodiments of the disclosure are a common voltage control circuit and method, a display panel and a display device. The control circuit includes a temperature sensing circuit and a voltage adjusting circuit. The temperature sensing circuit is configured to sense the ambient temperature. The voltage adjusting circuit is coupled to the temperature sensing circuit and the common electrode, and is configured to provide a corresponding common voltage to the common electrode based on a temperature signal from the temperature sensing circuit. According to the embodiments of the present disclosure, the common voltage may be changed according to the ambient temperature to improve the image sticking. |
| US10867570B2 |
Display device automatically setting gate shift amount and method of operating the display device
A display device includes a display panel including data lines, gate lines, and pixels connected to the data lines and the gate lines, a data driver configured to drive the data lines, a plurality of gate drivers, each configured to drive a corresponding portion of the gate lines, and a plurality of feedback lines connected to one of the data lines at a plurality of measurement positions corresponding to the plurality of gate drivers. The data driver applies a test voltage to the data line, receives the test voltage as a plurality of feedback voltages through the plurality of feedback lines, and determines gate shift amounts at the plurality of measurement positions corresponding to the plurality of gate drivers based on the plurality of feedback voltages. The gate drivers apply gate signals to the gate lines that are shifted by the determined gate shift amounts. |
| US10867568B2 |
Liquid crystal display device and driving method thereof comprising low refresh rate polarity inversion patterns
A liquid crystal display device comprises a memory configured to store polarities of the source outputs from a source driver with respect to a panel self-refresh operation and a normal refresh operation that is not the panel self-refresh operation as a first inversion pattern and to store the polarities of source outputs with respect to a low refresh rate operation as a second inversion pattern; and an LRR controller configured to control the polarities of the source outputs with the first inversion pattern in panel self-refresh frames before the low refresh rate operation is performed, to control the polarities of the source outputs with a third inversion pattern referring to the first inversion pattern in low refresh rate frames in which the low refresh rate operation is performed, and to control the polarities of the source outputs with a fourth inversion pattern referring to the second inversion pattern in normal refresh frames after the low refresh rate operation ends. |
| US10867565B2 |
Pixel array substrate
A pixel array substrate including a substrate, a first scan line, a first sub-pixel, a second scan line, a second sub-pixel, and a common electrode is provided. The substrate has a first region and a second region. A length of the first region is smaller than a length of the second region. Two opposite sides of the second region correspond to two opposite sides of the substrate respectively. At least one side of the first region does not correspond to one of the two opposite sides of the substrate. The first scan line is disposed on the first region. The first sub-pixel is electrically connected to the first scan line. The second scan line is disposed on the second region. The second sub-pixel is electrically connected to the second scan line. The common electrode is disposed on the substrate. A vertical distance between the common electrode and the first scan line is V11, a vertical distance between the common electrode and the second scan line is V2, and V2>V11. |
| US10867563B2 |
Display device
A display device includes a display panel; a frame at a rear of the display panel, the frame including a first and a second protrusions; a first substrate at a front surface of the frame, the first substrate elongated in a direction along a first side of the frame; a plurality of first light sources disposed on the first substrate at predetermined intervals in the direction. Further, the first protrusion is positioned at an end of the first substrate adjacent to the foremost light source in the first substrate, and the second protrusion is positioned at an end of the first substrate adjacent to the rearmost light source in the first substrate, at least one of the first and the second protrusions includes an inclined surface and the frame is pressed to form the first and the second protrusion such that the protrusions are formed on the front surface of the frame. |
| US10867560B2 |
Organic light emitting display device
An organic light emitting display device includes: a display panel including a plurality of pixel rows each including first pixel groups alternating with second pixel groups; a gate driver configured to provide a first group gate signal to the first pixel groups, and to provide a second group gate signal to the second pixel groups; a data driver configured to output data voltages to a plurality of output line groups; and a connection controller configured to connect the output line groups to a first data line group in response to a first connection control signal, and to connect the output line groups to a second data line group in response to a second connection control signal. |
| US10867557B2 |
Display device
There is provided an active matrix EL display device that can display a clear multi gray-scale color display to reduce the shift in the potential caused by the potential drop due to the wiring resistance of a power source supply line, in order to decrease the unevenness in a display region. A plurality of drawing out ports of the power source supply line are arranged. Further, in the wiring resistance between the external input terminal and the pixel portion power source supply line, potential compensation is performed by supplying potential to the power source supply line by a feedback amplifier. Further, in addition to above structure, the power source supply line may be arranged in a matrix. |